Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, with which it is possible to prevent uneven formation of Ni silicide and to reduce the contact resistance. In this method for manufacturing a silicon carbide semiconductor device, a silicide layer (18) is formed by: forming a film of Ni or a film of Ni and Ti; subjecting the film to a heat treatment at a temperature of 400°C or more and less than 600° C in an inert gas (group 18) atmosphere; removing the unreacted film; and subjecting the film to a heat treatment at a temperature of less than 1000°C in an inert gas (group 18) atmosphere.

Description

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices and methods of manufacturing silicon carbide semiconductor devices.

[0002] Conventionally, to form an ohmic junction in the source region, Ni silicide is formed on a high-concentration impurity region. To obtain good contact resistance, a semiconductor device has been proposed in which, after forming a contact hole, sacrificial oxidation and hydrogen etching at 1300 to 1500°C are performed to form a Ni film, and silicide is then formed in a nitrogen atmosphere at 500 to 900°C (see, for example, Patent Document 1 below).

[0003] Japanese Patent Application Laid-Open No. 2023-136280

[0004] However, in conventional semiconductor devices, Ni silicide is not formed uniformly, resulting in a problem of high contact resistance.

[0005] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can prevent uneven formation of Ni silicide and reduce contact resistance.

[0006] In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to the present disclosure has the following features: a drift layer of a first conductivity type made of silicon carbide, a source region of the first conductivity type made of silicon carbide provided on an upper surface side of the drift layer, a silicide layer provided on the source region, a barrier layer containing Ti provided in contact with the silicide layer, and a main electrode provided in contact with the barrier layer, wherein the barrier layer does not have a portion in contact with the source region.

[0007] According to the above disclosure, since the silicide layer is formed uniformly, no portion is formed where the silicon carbide layer and the barrier metal are in direct contact with each other, and the contact resistance can be reduced.

[0008] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present disclosure have the effect of preventing uneven formation of Ni silicide and reducing contact resistance.

[0009] FIG. 1 is a cross-sectional view showing an active structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a schematic diagram of a contact hole of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a flowchart showing a silicide layer formation method in a silicon carbide semiconductor device manufacturing method according to an embodiment. FIG. 4 is a graph showing the temperature dependence of sheet resistance after first silicidation annealing on the temperature of the first silicidation annealing. FIG. 5 is a graph showing the temperature dependence of sheet resistance after second silicidation annealing on the temperature of the first silicidation annealing. FIG. 6 is a graph showing the temperature dependence of sheet resistance after second silicidation annealing on the temperature of the second silicidation annealing. FIG. 7 is a graph showing Raman spectra after first silicidation annealing. FIG. 8 is a graph showing Raman spectra after first silicidation annealing. FIG. 9 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. FIG. 10 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. Fig. 11 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. Fig. 12 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. Fig. 13 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. Fig. 14 is a schematic diagram of a cross-sectional SEM image after second silicidation annealing. Fig. 15 shows a flowchart of conventional silicide film formation. Fig. 16 is a schematic diagram of a contact hole in a conventional silicon carbide semiconductor device.

[0010] <Outline of Embodiments of the Present Disclosure> In order to solve the above-described problems and achieve the object of the present disclosure, a silicon carbide semiconductor device according to the present disclosure has the following features: A first conductivity type drift layer made of silicon carbide, a first conductivity type source region made of silicon carbide provided on an upper surface side of the drift layer, a silicide layer provided on the source region, a Ti-containing barrier layer provided in contact with the silicide layer, and a main electrode provided in contact with the barrier layer, wherein the barrier layer does not have a portion in contact with the source region.

[0011] According to the above disclosure, since the silicide layer is formed uniformly, no portion is formed where the silicon carbide layer and the barrier metal are in direct contact with each other, and the contact resistance can be reduced.

[0012] In addition, in the silicon carbide semiconductor device disclosed above, the silicide layer has a height difference of 40 nm or less.

[0013] In order to solve the above-described problems and achieve the object of the present disclosure, a method for manufacturing a silicon carbide semiconductor device according to the present disclosure has the following features. First, a first step is performed to form a drift layer of a first conductivity type made of silicon carbide. Next, a second step is performed to form a source region of the first conductivity type made of silicon carbide on an upper surface side of the drift layer. Next, a third step is performed to form a silicide layer on the source region. Next, a fourth step is performed to form a barrier layer containing Ti in contact with the silicide layer. Next, a fifth step is performed to form a main electrode in contact with the barrier layer. The third step includes a sixth step of forming a Ni or Ni and Ti film, a seventh step of heat-treating the film in an inert gas (group 18) atmosphere at a temperature of 400°C or higher but lower than 600°C, an eighth step of removing the film that has not reacted in the seventh step, and a ninth step of heat-treating the film in an inert gas (group 18) atmosphere at a temperature lower than 1000°C.

[0014] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the ninth step comprises heat treatment at a temperature of 900°C or higher and lower than 1000°C.

[0015] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, when the film is a Ni film, the seventh step is characterized in that the heat treatment is performed at a temperature of 450°C or higher and lower than 600°C.

[0016] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, when the film is a Ni or Ti film, the seventh step is characterized in that the heat treatment is performed at a temperature of 400°C or higher and lower than 500°C.

[0017] In addition, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, the inert gas (group 18) is any one of He, Ne, Ar, Kr, and Xe.

[0018] <Findings underlying the present disclosure> First, the problems with conventional methods for manufacturing silicon carbide semiconductor devices will be described. Conventionally, to obtain good contact resistance, after forming contact holes, sacrificial oxidation and hydrogen etching at 1300 to 1500°C are performed, a Ni (nickel) film is formed, and silicide is formed in a nitrogen atmosphere at 500 to 900°C. FIG. 15 shows a flowchart of the conventional method for forming a silicide layer. As shown in FIG. 15, first, an interlayer insulating film is formed on the silicon carbide layer (step S101). Next, contact holes are formed in the interlayer insulating film (step S102). Next, sacrificial oxidation is performed on the silicon carbide layer to form a sacrificial oxide film (step S103). Sacrificial oxidation is thermal oxidation, and by forming the sacrificial oxide film, impurities and damage on the surface of the silicon carbide layer are removed.

[0019] Next, the surface of the silicon carbide layer is etched at a temperature of 1300 to 1500°C in an atmosphere containing hydrogen (H2) gas (Step S104). This reduces the amount of carbon vacancies in the silicon carbide layer. Next, a nickel film is formed in the contact hole (Step S105). Next, silicidation annealing is performed at a temperature of 500 to 900°C in an atmosphere containing nitrogen gas (Step S106). Finally, the unreacted nickel film is removed (Step S107).

[0020] In this way, impurities and damage on the surface of the silicon carbide layer are removed by sacrificial oxidation, and the amount of carbon vacancies is reduced by hydrogen etching, so that nickel diffuses to the target site, resulting in good contact resistance.

[0021] However, the process of forming Ni silicide is carried out after forming an interlayer insulating film made of NSG or BPSG, and after this, an electrode pad such as an Al electrode is formed, which functions as a contact electrode. However, after forming the interlayer insulating film, it is difficult to perform sacrificial oxidation or hydrogen etching, which affect the shape.

[0022] For this reason, it is conceivable to form Ni silicide by forming a nickel film, annealing it for silicidation (500°C, N2 atmosphere), removing the unreacted nickel film, and annealing it for silicidation (950°C, N2 atmosphere) without using sacrificial oxidation or hydrogen etching. Figure 16 is a schematic diagram of a contact hole in a conventional silicon carbide semiconductor device. As shown in Figure 16, a silicide layer 118, a barrier metal 115, and a source electrode 116 are stacked in this order on a silicon carbide layer 160.

[0023] When formed by this method, there are portions (T in the figure) where the silicide layer 118 is not formed by silicidation annealing, and the silicon carbide layer 160 is in direct contact with the barrier metal 115. Furthermore, the height difference h101 of the silicide layer 118 from the silicon carbide layer 160 is greater than 50 nm, and there are only one or two points at the same depth as the deepest point, meaning that the silicide layer 118 is not formed uniformly.

[0024] One of the reasons for high contact resistance in semiconductor chips is that Ni silicide is not formed uniformly, resulting in the formation of areas where the silicon carbide layer and electrode pad are in direct contact. For this reason, the establishment of a Ni silicide formation process that is less likely to cause variations within the wafer surface and between lots, without using sacrificial oxidation or hydrogen etching, has become a challenge.

[0025] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are given the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0026] (Embodiment) A semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: Insulated Gate Field Effect Transistor) as an example. Figure 1 is a cross-sectional view showing an active structure of a silicon carbide semiconductor device according to the embodiment.

[0027] A silicon carbide semiconductor device 70 according to an embodiment includes an active region 50 and an edge termination region (not shown) surrounding the active region 50 in a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))). The active region 50 is a region through which current flows in the on-state. The edge termination region is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage.

[0028] As shown in FIG. 1, the silicon carbide substrate is a n-type silicon carbide substrate. + Mold support substrate (n + On the front surface of the silicon carbide substrate 1, a n-type silicon carbide substrate made of silicon carbide is - a first conductivity type drift region (drift layer) 2; and - n-type drift region 2 + and a p-type base region 5 made of silicon carbide on the surface opposite to the n-type silicon carbide substrate 1 side. + The n-type silicon carbide substrate 1 functions as a drain region. - type drift region 2 and n + Between the silicon carbide substrate 1 and the n-type silicon carbide substrate 2, for example, + A buffer layer or the like may be provided to reduce the growth of crystal defects from silicon carbide substrate 1 .

[0029] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The n-type drift region 2 + The impurity concentration is lower than that of the n-type silicon carbide substrate 1. - The drift region 2 reaches the p-type base region 5 and is connected to the p-type base region 5 and the p-type base region 5 described later. +The gate insulating film 11 is in contact with the mold portion region 4, and extends in a direction parallel to the front surface of the semiconductor substrate to a trench 25 (described later). - The impurity concentration of the drift region 2 is, for example, 5×10 16 cm -3 Below, the thickness is 5.0 μm or more.

[0030] Also, n - An n-type high concentration region (not shown) may be provided between the n-type drift region 2 and the p-type base region 5. When an n-type high concentration region is provided, the n-type high concentration region is formed between adjacent p-type regions as described later. + The n-type high concentration region is in contact with these regions at the n-type partial region 4, extends in a direction parallel to the front surface of the semiconductor substrate, reaches the trench 25, and is in contact with the gate insulating film 11. The n-type high concentration region is in contact with the p-type base region 5 at its upper surface and with the n-type high concentration region at its lower surface. - The n-type high concentration region is in contact with the n-type drift region 2. + lower than that of the silicon carbide substrate 1 - It is higher than the type drift region 2.

[0031] n + A drain electrode 17 serving as a back surface electrode is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide base) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 17.

[0032] A trench structure is formed on the first main surface side (p-type base region 5 side) of the silicon carbide substrate. Specifically, the trench 25 is formed on the n-type + The n-type silicon carbide substrate 1 is connected to the surface of the silicon carbide substrate 1 opposite to the first main surface side through the p-type base region 5. - The n-type impurity reaches the n-type drift region 2 (or the n-type high concentration region, if provided).

[0033] A gate insulating film 11 is formed along the inner wall of the trench 25, on the bottom and side walls of the trench 25, and a gate electrode 13 is formed inside the gate insulating film 11 in the trench 25. The gate electrode 13 is formed by the gate insulating film 11. -The gate electrode 13 is insulated from the p-type drift region 2 and the p-type base region 5. A part of the gate electrode 13 may protrude from above the trench 25 (the side where the source electrode 16 described later is provided) toward the source electrode 16.

[0034] n - n-type drift region 2 + The surface layer on the side opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide substrate) is provided with an upper p + The mold part area 4a is provided. + The mold portion region 4a is provided between the trenches 25, for example. - In the drift region 2, an upper p + The lower part p that contacts the bottom of the mold part region 4a + The trench 25 has a bottom formed with a p + A p-type region 26 is provided in contact with the bottom of the trench 25. + The mold region 26 is provided at a position facing the bottom of the trench 25 in the depth direction (the direction from the source electrode 16 to the back surface electrode). + Mold part region 4a and lower part p + The mold part region 4b is p + This becomes the mold part region 4.

[0035] p + The width of the mold region 26 is equal to or wider than the width of the trench 25. + The width of the mold part region 4b is + The width of the trench 25 is equal to or wider than the width of the mold portion region 4a. + The p-type base region 5 and the p-type region 26 may be connected. + n sandwiched between mold regions 26 - It may be located within the mold drift region 2 .

[0036] Inside the p-type base region 5, an n-type ++ type source region (first conductivity type source region) 7 and p ++ A contact region 6 is selectively provided. ++ type source region 7 and p ++ The mold contact regions 6 abut each other.

[0037] The interlayer insulating film 14 is provided on the entire first main surface side of the silicon carbide substrate so as to cover the gate electrode 13 embedded in the trench 25. The interlayer insulating film 14 is made of NSG or BPSG. A contact hole is opened in the interlayer insulating film 14, and the bottom of the contact hole has an n-type SiO 2 film. ++ type source region 7 and p ++ A silicide layer 18 is provided in contact with the n-type contact region 6. The source electrode 16 is connected to the n-type contact region 6 via the silicide layer 18. ++ type source region 7 and p ++ The silicon carbide semiconductor device 70 has a surface that is in contact with the silicon carbide contact region 6. The source electrode (main electrode) 16 is electrically insulated from the gate electrode 13 by an interlayer insulating film 14. A source electrode pad (not shown) is provided on the source electrode 16. A barrier metal (barrier layer) 15 is provided between the source electrode 16 and the interlayer insulating film 14 to prevent, for example, diffusion of metal atoms from the source electrode 16 toward the gate electrode 13. A polyimide (not shown) that functions as a protective film is provided on the surface of the silicon carbide semiconductor device 70. Although FIG. 1 shows only two MOS gate structures (insulated gates made of metal-oxide-semiconductor) in the active region 50, more MOS gate structures may be arranged in parallel.

[0038] 2 is a schematic diagram of a contact hole of a silicon carbide semiconductor device according to an embodiment. In this embodiment, a silicide layer 18 is formed by a manufacturing method described later. Therefore, as shown in FIG. 2, the silicide layer 18 is formed uniformly. For example, there is no portion where the silicide layer 18 is not formed by silicidation annealing, and there is no portion where the silicon carbide layer 60 and the barrier metal 15 are in direct contact with each other. The silicon carbide layer 60 is, for example, n ++ type source region 7, p ++The silicide layer 18 is a region including the p-type contact region 6 and the p-type base region 5. Furthermore, the height difference h1 of the silicide layer 18 from the silicon carbide layer 60 is less than 40 nm, and there are three or more points at the same depth as the deepest point. The height difference h1 is the difference between the point closest to the silicon carbide layer 60 and the point farthest from the silicon carbide layer 60 on the surface of the silicide layer 18 facing the silicon carbide layer 60. The deepest point is the point closest to the silicon carbide layer 60 on the surface of the silicide layer 18 facing the silicon carbide layer 60. As described above, in the embodiment, the silicide layer 18 is formed uniformly, and no portion is formed where the silicon carbide layer 60 and the barrier metal 15 are in direct contact with each other, thereby reducing the contact resistance.

[0039] (Method for Manufacturing a Semiconductor Device According to an Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. For example, the semiconductor device is manufactured as follows. First, n + On the front surface of the silicon carbide substrate 1, - The mold drift region 2 is epitaxially grown (first step).

[0040] Next, n - The p-type base region 5 is epitaxially grown on the front surface of the n-type drift region 2. The p-type base region 5 may be formed by ion implantation. - An n-type high concentration region may be formed between the n-type drift region 2 and the p-type base region 5 .

[0041] Next, p-type regions (p + Mold partial region 4, p ++ Type contact region 6, p + and forming an n-type region 26) by photolithography and ion implantation of n-type impurities. ++ Next, the n-type source region 7 is formed (second step). - Then, a heat treatment is performed to activate the impurities ion-implanted into the p-type drift region 2 and the p-type base region 5. This heat treatment for impurity activation may be performed for each impurity ion implantation, or may be performed all at once. Next, a trench 25, a gate insulating film 11, and a gate electrode 13 are formed by a general method.

[0042] Next, the p-type base region 5, p ++ type contact region 6 and n ++ A silicide layer 18 is formed on the source region 7 (Step 3). A method for forming the silicide layer 18 will be described in detail below. FIG. 3 shows a flowchart of the silicide layer formation process in the method for manufacturing a silicon carbide semiconductor device according to the embodiment. As shown in FIG. 3, first, an interlayer insulating film 14 is formed on the silicon carbide layer 60 (Step S1). Next, contact holes are formed in the interlayer insulating film 14 (Step S2). Next, a nickel film is formed in the contact holes (Step S3, Step 6). Here, a nickel film is formed, but a nickel-titanium (Ti) laminated film or a mixture of Ni and Ti can also be used. Adding Ti allows for a lower temperature heat treatment (annealing). In the case of a Ni-Ti laminated film, Ti is formed on the silicon carbide layer 60 so as to form TiC.

[0043] Next, a first silicidation anneal is performed as a heat treatment in an inert gas (Group 18 elements (He, Ne, Ar, Kr, Xe)) atmosphere at a temperature of less than 600°C, for example, at a temperature of 400°C or higher but lower than 600°C (step S4, seventh process). In the case of Ni, the temperature is preferably 450°C or higher but lower than 600°C, and in the case of Ni and Ti, the temperature is more preferably 400°C or higher but lower than 500°C. Next, the unreacted nickel film is removed (step S5, eighth process). The removal is performed by, for example, wet etching. A phosphoric acid + nitric acid + acetic acid system is preferable for the wet etching.

[0044] Finally, a second silicidation anneal is performed again in an inert gas (group 18 elements (He, Ne, Ar, Kr, Xe)) atmosphere at a temperature lower than the BPSG reflow temperature (1000°C), for example, at a temperature of 900°C or higher but lower than 1000°C, as a heat treatment for silicidation by solid-phase reaction (step S6, ninth process). The second silicidation anneal promotes the silicidation reaction and forms an ohmic electrode.

[0045] Here, by heating at a temperature lower than the reflow temperature of BPSG, penetration of Ni into BPSG is prevented, the formation of an inhibitory layer is suppressed, and the region in which silicide layer 18 is formed can be defined. Furthermore, by performing heat treatment in an inert gas (group 18 elements (He, Ne, Ar, Kr, Xe)) atmosphere, the formation of a reaction inhibitory layer (SiN) in silicon carbide layer 60 is prevented, and uniform silicide formation is possible. Forming in this manner prevents formation unevenness and allows silicide layer 18 to be formed uniformly. Therefore, no portion is formed in direct contact between silicon carbide layer 60 and barrier metal 15, and contact resistance can be reduced.

[0046] Next, a Ti film is formed uniformly in the contact hole and on the surface of the interlayer insulating film 14 by sputtering. Next, a TiN film is formed on the surface of the Ti film by sputtering. This results in a barrier metal 15 being stacked on the interlayer insulating film 14 and in the contact hole (fourth step). Next, the Ti film on the bottom of the contact hole is silicified by heat treatment (annealing).

[0047] Next, an Al metal film that will become the source electrode 16 is formed by, for example, sputtering. The Al metal film may be formed of, for example, aluminum containing 1% silicon (Al-Si). Next, the Al metal film is patterned to form the source electrode 16 (step 5). Thereafter, a gate pad (not shown), a passivation film (surface protection film: not shown), and a drain electrode 17 are formed by a typical method. The portion of the source electrode 16 exposed in the opening of the passivation film becomes the source pad. The semiconductor wafer is then diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 70 of FIG. 1.

[0048] 4 is a graph showing the temperature dependence of the sheet resistance after the first silicidation annealing. In FIG. 4, the horizontal axis represents the processing temperature of the first silicidation annealing in ° C. The vertical axis represents the sheet resistance in Ω / □. FIG. 4 shows the sheet resistance after the first silicidation annealing when a Ni film or a Ni / Ti film is formed and the processing temperature of the first silicidation annealing is changed.

[0049] In the case of Ni films, the results are for films formed with a thickness of 50 to 100 nm using a sputtering device and then heat-treated in an argon atmosphere using a vertical heat treatment device.In the case of Ni / Ti films, the results are for films formed with a Ti thickness of 25 to 50 nm and a Ni thickness of 25 to 50 nm (1:1 thickness) using a sputtering device and then heat-treated in an argon atmosphere using a vertical heat treatment device.

[0050] As shown in FIG. 4, in the case of a Ni film, when the processing temperature of the first silicidation annealing is between 25° C. and 400° C., the sheet resistance is the same as that after the Ni film is formed, and the Ni film is unreacted and not silicided; at 450° C. to 800° C., the sheet resistance rises sharply, silicidation progresses, and a reaction layer is formed; and at 900° C. or higher, the sheet resistance decreases, and the Ni film is sufficiently silicided.

[0051] Furthermore, in the case of a Ni / Ti film, when the processing temperature of the first silicidation annealing is between 25°C and 350°C, the sheet resistance is the same as that after the Ni / Ti film is formed, and the Ni / Ti film is unreacted and not silicided; at 400°C to 800°C, the sheet resistance rises sharply, silicidation progresses, and a reaction layer is formed; and at 900°C or higher, the sheet resistance decreases, and the Ni / Ti film is sufficiently silicided.

[0052] 5 is a graph showing the temperature dependence of the sheet resistance after the second silicidation anneal on the temperature of the first silicidation anneal. In FIG. 5, the horizontal axis represents the processing temperature of the first silicidation anneal in °C. The vertical axis represents the sheet resistance in Ω / □. FIG. 5 shows the sheet resistance after the second silicidation anneal when a Ni film or Ni / Ti film is formed and the processing temperature of the first silicidation anneal is changed. The film formation conditions are the same as those in FIG. 4. The second silicidation anneal was performed at 975 °C.

[0053] As shown in FIG. 5, when the second silicidation annealing is performed at 975° C. in both the Ni film and the Ni / Ti film, the sheet resistance is low and the film is sufficiently silicided, regardless of the processing temperature of the first silicidation annealing.

[0054] 6 is a graph showing the temperature dependence of the sheet resistance after the second silicidation annealing. In FIG. 6, the horizontal axis represents the processing temperature of the second silicidation annealing in ° C. The vertical axis represents the sheet resistance in Ω / □. FIG. 6 shows the sheet resistance after the second silicidation annealing when a Ni film or Ni / Ti film is formed, the processing temperature of the first silicidation annealing is set to 500° C., and the processing temperature of the second silicidation annealing is changed.

[0055] In FIG. 6, the composition of BPSG is 3.7 wt % P (phosphorus), 8.1 wt % B (boron), 88.2 wt % Si (silicon), and the remainder is O (oxygen) (P2O5 2 mol %, B2O3 6.5 mol %).

[0056] 6, it can be seen that for both the Ni film and the Ni / Ti film, the sheet resistance is reduced and sufficient silicidation is achieved by setting the processing temperature of the second silicidation annealing to 900° C. or higher. Therefore, the lower limit of the second silicidation annealing is 900° C., and the upper limit is 1000° C. (the reflow temperature of BPSG).

[0057] 7 and 8 are graphs showing Raman spectra after the first silicidation annealing. Fig. 7 and Fig. 8 show Raman spectra when a Ni film is formed and the processing temperature of the first silicidation annealing is changed. In Fig. 7 and Fig. 8, the horizontal axis represents the Raman shift, and the unit is cm. -1 The vertical axis indicates the intensity of the spectrum, and the unit is arbitrary. In Fig. 7 and Fig. 8, the Raman shift of 100 cm -1 and 140 cm -1 indicates the spectrum of NiSi, and 211 cm -1 indicates the spectrum of NiSi, and 204 cm -1 7 and 8, it can be seen that silicide is formed by setting the processing temperature of the first silicidation annealing to 500° C. or higher.

[0058] 9 to 14 are schematic diagrams of cross-sectional SEM images after the second silicidation annealing, in which the sample is coated with platinum films 19 and 20, taken with a scanning electron microscope.

[0059] FIG. 9 shows the case where the processing temperature of the first silicidation annealing is 300° C. and the processing temperature of the second silicidation annealing is 975° C., and no silicide layer 18 (Ni silicide) is detected.

[0060] FIG. 10 shows the case where the processing temperature for the first silicidation annealing is 400° C. and the processing temperature for the second silicidation annealing is 975° C., and no silicide layer 18 (Ni silicide) is detected.

[0061] FIG. 11 shows the case where the processing temperature for the first silicidation annealing is 500° C. and the processing temperature for the second silicidation annealing is 975° C., and the silicide layer 18 (Ni silicide) is detected.

[0062] FIG. 12 shows the case where the processing temperature of the first silicidation annealing is 600° C. and the processing temperature of the second silicidation annealing is 975° C., and the silicide layer 18 (Ni silicide) is detected.

[0063] FIG. 13 shows the case where the processing temperature of the first silicidation annealing is 900° C. and the processing temperature of the second silicidation annealing is 975° C., and the silicide layer 18 (Ni silicide) is detected.

[0064] FIG. 14 shows the case where the silicidation annealing process was performed once at a temperature of 900° C., and the silicide layer 18 (Ni silicide) was detected.

[0065] As shown in FIGS. 9 to 14, when the processing temperature of the first silicidation annealing is 500° C. or higher and the processing temperature of the second silicidation annealing is 975° C., it is found that a silicide layer 18 (Ni silicide) is formed.

[0066] As described above, according to the embodiment, after forming the nickel film, the first silicidation annealing is performed in an inert gas (group 18) atmosphere at a temperature of less than 600°C, and after removing the unreacted nickel film, the second silicidation annealing is performed in an inert gas (group 18) atmosphere at a temperature of less than 1000°C. This prevents formation of uneven silicide layers and allows the silicide layer to be formed uniformly. Therefore, no portion is formed where the silicon carbide layer and the barrier metal are in direct contact with each other, and the contact resistance can be reduced.

[0067] As described above, the present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0068] INDUSTRIAL APPLICABILITY As described above, the semiconductor device and method for manufacturing a silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automotive igniters, and the like.

[0069] 1n + Silicon carbide substrate 2n - Type drift region 4p + Mold partial area 4a Upper p + Mold partial area 4b lower part p + Type partial region 5 p type base region 6 p ++ Type contact region 7 n ++ 11: Type source region 11: Gate insulating film 13: Gate electrode 14: Interlayer insulating film 15, 115: Barrier metal 16, 116: Source electrode 17: Drain electrode 18, 118: Silicide layer 19, 20: Platinum film 25: Trench 26: p + Mold region 50 Active region 60, 160 Silicon carbide layer 70 Silicon carbide semiconductor device

Claims

1. A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type made of silicon carbide; a source region of the first conductivity type made of silicon carbide provided on an upper surface of the drift layer; a silicide layer provided on the source region; a barrier layer containing Ti provided in contact with the silicide layer; and a main electrode provided in contact with the barrier layer, wherein the barrier layer does not have a portion in contact with the source region.

2. The silicon carbide semiconductor device according to claim 1, wherein the difference in height between the silicide layers is 40 nm or less.

3. A method for manufacturing a silicon carbide semiconductor device comprising: a first step of forming a drift layer of a first conductivity type made of silicon carbide; a second step of forming a source region of the first conductivity type made of silicon carbide on an upper surface of the drift layer; a third step of forming a silicide layer on the source region; a fourth step of forming a barrier layer containing Ti in contact with the silicide layer; and a fifth step of forming a main electrode in contact with the barrier layer, wherein the third step comprises: a sixth step of forming a film of Ni or Ni and Ti; a seventh step of heat-treating the film in an inert gas (group 18) atmosphere at a temperature of 400°C or higher and lower than 600°C; an eighth step of removing the film that has not reacted in the seventh step; and a ninth step of heat-treating the film in an inert gas (group 18) atmosphere at a temperature lower than 1000°C.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the ninth step comprises heat treatment at a temperature of 900°C or higher and lower than 1000°C.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein when the film is a Ni film, the seventh step comprises heat treatment at a temperature of 450°C or higher and lower than 600°C.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein when the film is a Ni or Ti film, the seventh step comprises heat treatment at a temperature of 400°C or higher and lower than 500°C.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the inert gas (group 18) is any one of He, Ne, Ar, Kr, and Xe.

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