Storage device

Abstract

The present invention enables detection of erroneous selection of a word line or a bit line based on address designation, while suppressing an increase in scale of a memory cell array.　This storage device comprises: a memory cell array in which memory cells are arranged in a matrix in a row direction and a column direction; a data memory in which data cells in which encoded data encoded on the basis of a row address are stored are arranged in the column direction; word lines connecting the memory cells and the data cells in the row direction; bit lines connecting the memory cells in the column direction; a word selection circuit for selecting a word line on the basis of a designation of a row address; a reading circuit for reading the encoded data stored in the data memory; and a computing unit for outputting a computation result of the encoded data and the row address read on the basis of the selection of the word line.

Description

storage device

[0001] The present technology relates to a memory device, and more particularly to a memory device capable of detecting erroneous selection of a memory cell based on addressing.

[0002] In a memory device, data may be read from an address different from the address specified by the address due to an erroneous selection of a word line or bit line by an address decoder. For example, a semiconductor memory device has been disclosed that compares input address information with address information read from a memory cell array in order to enable detection of a fault in the address decoder (see, for example, Patent Document 1).

[0003] JP 2016-71910 A

[0004] However, in the above-mentioned conventional technology, in order to enable detection of a fault in the address decoder, it is necessary to store address information in the memory cell array, which may lead to an increase in the scale of the memory cell array.

[0005] This technology was developed in light of these circumstances, and aims to make it possible to detect erroneous selection of word lines or bit lines based on addressing while suppressing an increase in the scale of memory cell arrays.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a storage device including: a memory cell array in which memory cells are arranged in a matrix in a row direction and a column direction; a data memory in which data cells, each row having coded data stored therein, are arranged; word lines connecting the memory cells and the data cells to each row; bit lines connecting the memory cells to each column; a word selection circuit that selects the word line based on the row address designation; a read circuit that reads the coded data stored in the data memory; and a calculation unit that outputs a result of a calculation between the coded data read based on the selection of the word line and the row address. This provides the effect of detecting erroneous word line selection based on row address designation while providing data cells for each row with a number of bits fewer than the number of bits used to designate the row address.

[0007] In the first aspect, the memory cell may further include a sub-bit line connected to the data cell, and the read circuit may input the encoded data to the operation unit based on a potential transmitted to the sub-bit line via the data cell, thereby simplifying the read circuit and enabling data to be read from the data cell.

[0008] In the first aspect, the data cell may include a transistor that is set to be open or shorted with respect to the read circuit or a memory element that is conductive or insulated with respect to the read circuit, thereby providing an effect that data is read from the data cell based on selection of a word line.

[0009] In the first aspect, the arithmetic unit may include a combinational circuit to which the row address and the encoded data are input, thereby providing an effect that erroneous selection of a word line based on row address specification is detected based on the current values ​​of the row address and the encoded data.

[0010] In the first aspect, the arithmetic unit may include an exclusive OR circuit to which the row address and the encoded data are input, thereby preventing the complication of the arithmetic based on the row address and the encoded data and detecting an erroneous word line selection based on the row address specification.

[0011] In the first aspect, the coded data may be a parity bit of a row address assigned to the word line, thereby providing an effect that erroneous selection of a word line based on row address specification is detected based on the row address and the parity bit.

[0012] In the first aspect, the data memory and the read circuit may be provided for a plurality of columns, thereby enabling detection and correction of erroneous word line selection based on row address specification, based on the row address and encoded data.

[0013] In the first aspect, the arithmetic unit may include an error correction code (ECC) circuit, which enables detection and correction of erroneous word line selection based on row address specification, based on the row address and encoded data.

[0014] In the first aspect, the memory cell may include a transistor having a gate connected to the word line and a storage element connected in series to the transistor, thereby enabling selection of the memory cell and storing data in the memory cell.

[0015] In addition, in the first aspect, the memory cell may further include a sense amplifier that determines data stored in the memory cell based on the potential of the bit line, and the read circuit may read the encoded data from the data memory based on a data read command input to the sense amplifier, thereby providing an effect that the read timing from the data memory is set based on the read timing from the memory cell.

[0016] In the first aspect, the read circuit may have the same configuration as the sense amplifier, thereby providing an effect that the encoded data is read from the data memory based on a data read command input to the sense amplifier.

[0017] In the first aspect, the word selection circuit may be caused to reselect the word line based on the calculation result by the calculation unit, thereby eliminating erroneous word line selection based on a row address based on the calculation result by the calculation unit.

[0018] According to a second aspect, there is provided a memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells, each column containing coded data coded based on a column address, are arranged; word lines connecting the memory cells to each row; bit lines connecting the memory cells to each column; sub-bit lines connecting the data cells to each column; a column selection circuit that selects the bit lines and the sub-bit lines based on the column address; a read circuit that reads the coded data stored in the data memory; and an arithmetic unit that outputs a result of an operation between the coded data read based on the selection of the sub-bit lines and the column address, thereby providing the effect of detecting erroneous bit line selection based on the column address.

[0019] In the second aspect, the data cell may include a data line that sets the sub-bit line to an open state or a short state, thereby providing an effect that data is stored in the data cell based on the wiring connected to the sub-bit line.

[0020] In the second aspect, the data memory may include the data cells for each row of the memory cell array, the number of which corresponds to the number of columns of the memory cell array, thereby providing an effect that a data cell is selected based on a row address and a column address.

[0021] In the second aspect, the column selection circuit may include a switch for each column that connects the selected sub-bit line to the read circuit, thereby providing an effect that the coded data stored in the data memory is read based on the column address specification.

[0022] In the second aspect, the column selection circuit may be caused to reselect the bit lines and the sub-bit lines based on the calculation result by the calculation unit, thereby eliminating erroneous selection of bit lines and sub-bit lines based on the column address based on the calculation result by the calculation unit.

[0023] A third aspect of the present invention is a memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells, each of which stores coded data coded based on an address, are arranged in rows and columns; word lines connecting the memory cells and the data cells to each row; bit lines connecting the memory cells to each column; sub-bit lines connecting the data cells to each column; a word selection circuit that selects the word lines based on a row address; a column selection circuit that selects the bit lines and the sub-bit lines based on a column address; a read circuit that reads the coded data stored in the data memory; and an arithmetic unit that outputs a result of an operation between the coded data read based on the selection of the word lines and the sub-bit lines and the address, thereby providing the effect of detecting erroneous selection of a memory cell based on address specification.

[0024] In the third aspect, the calculation unit may output a calculation result based on the row address and a calculation result based on the column address separately. This provides an advantage that erroneous selection of a memory cell based on addressing is detected. This provides an advantage that erroneous selection of a memory cell based on row addressing and erroneous selection of a memory cell based on column addressing are detected separately.

[0025] In the third aspect, the calculation unit may output a calculation result combining the row address and the column address, thereby providing an effect that erroneous selection of a memory cell based on addressing including a row address and a column address is detected.

[0026] 10 is a block diagram showing a configuration example of a storage device according to a first embodiment. FIG. 11 is a block diagram showing a configuration example of a row selection circuit according to the first embodiment. FIG. 12 is a circuit diagram showing a configuration example of a row selection circuit according to the first embodiment. FIG. 13 is a block diagram showing a configuration example of a storage device according to a second embodiment. FIG. 14 is a flowchart showing an example of a data determination process according to the second embodiment. FIG. 15 is a diagram showing an example of an XOR determination result in the data determination process according to the second embodiment. FIG. 16 is a diagram showing an example of a data determination sequence according to the second embodiment. FIG. 17 is a diagram showing another example of a data determination sequence according to the second embodiment. FIG. 18 is a block diagram showing a configuration example of a storage device according to a third embodiment. FIG. 19 is a flowchart showing an example of a data determination process according to the third embodiment. FIG. 19 is a diagram showing an example of a data determination sequence according to the third embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to a fourth embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to a fifth embodiment. FIG. 19 is a circuit diagram showing a configuration example of a column selection circuit according to the fifth embodiment. FIG. 19 is a flowchart showing an example of a data determination process according to the fifth embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to a sixth embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to a seventh embodiment. FIG. 19 is a flowchart showing an example of a data determination process according to the seventh embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to an eighth embodiment. FIG. 19 is a block diagram showing a configuration example of a storage device according to a ninth embodiment. FIG. 19 is a block diagram showing a configuration example of an imaging device according to a tenth embodiment. Fig. 16 is a block diagram showing an example of the configuration of a solid-state imaging device according to a tenth embodiment. Fig. 17 is a perspective view showing an example of stacking of a pixel array unit according to a tenth embodiment. Fig. 18 is a block diagram showing an example of the configuration of a distance measuring device according to an eleventh embodiment. Fig. 19 is a block diagram showing a schematic example of the configuration of a vehicle control system. Fig. 20 is an explanatory diagram showing an example of the installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be made in the following order: 1. First embodiment (an example in which an erroneous selection of a word line based on row addressing is detected based on a parity check) 2. Second embodiment (an example in which an erroneous selection of a word line based on row addressing is detected based on a parity check, and a row selection command is reissued based on the detection result) 3. Third embodiment (an example in which an erroneous selection of a word line based on row addressing is detected based on a parity check, and the detection result is output together with data read from a memory cell) 4. Fourth embodiment (an example in which a plurality of data memories used to detect an erroneous selection of a word line based on row addressing are provided for each row) 5. Fifth embodiment (an example in which only one row's worth of data cells for storing parity bits are provided, and an erroneous selection of a bit line based on column addressing is detected based on a parity check) 6. 6. Sixth Embodiment (an example in which data cells for storing parity bits are provided in the number of rows of memory cells, and erroneous selection of bit lines based on column addressing is detected based on a parity check with transistors of the data cells and sub-bit lines disconnected) 7. Seventh Embodiment (an example in which data cells for storing parity bits are provided in the number of rows of memory cells, and erroneous selection of bit lines based on column addressing is detected based on a parity check) 8. Eighth Embodiment (an example in which erroneous selection of word lines based on row addressing and erroneous selection of bit lines based on column addressing are detected) 9. Ninth Embodiment (an example in which erroneous selection of memory cells based on addressing combining row addresses and column addresses is detected) 10. Tenth Embodiment (an example in which a storage device provided with a data memory used to detect erroneous selection of word lines based on addressing is applied to an imaging device) 11. Eleventh Embodiment (an example in which a storage device provided with a data memory used to detect erroneous selection of word lines based on addressing is applied to a distance measuring device) 12. Application to a Mobile Object

[0028] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a storage device according to a first embodiment.

[0029] In the figure, this memory device is capable of detecting erroneous selection of a word line WL based on the specification of a row address RAD, and includes a memory cell array 101, a row selection circuit 102, a column selection circuit 103, a sense amplifier 104, a row address latch circuit 105, a row selection command issuing circuit 106, a column address latch circuit 107, and a data output command issuing circuit 108.

[0030] This storage device also includes a data memory 111, a read circuit 112, and a determination circuit 113. The data memory 111, the read circuit 112, and the determination circuit 113 can be used to detect erroneous selection of a word line WL based on the designation of a row address RAD.

[0031] Memory cells MC are arranged in a matrix in the row and column directions in the memory cell array 101. In the memory cell array 101, a word line WL is arranged for each row, and a bit line BL and a source line SL are arranged for each column.

[0032] Each memory cell MC includes a transistor TR and a storage element MD. The transistor TR and the storage element MD are connected in series. The transistor TR may be a field-effect transistor. In this case, the gate of the transistor TR is connected to a different word line WL for each row. The source of the transistor TR is connected to a different source line SL for each column. The drain of the transistor TR is connected to a different bit line BL for each column via the storage element MD.

[0033] Although the figure shows an example of a memory cell MC, the memory cell MC is not necessarily limited to the configuration shown in the figure, and may be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), or may be a ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or flash memory.

[0034] The row selection circuit 102 selects a row in the memory cell array 101 and the data memory 111 based on the row address RAD. At this time, the row selection circuit 102 can drive the word line WL based on the result of the selection of the row in the memory cell array 101 and the data memory 111.

[0035] Based on the column address CAD, the column selection circuit 103 selects a column of the memory cell array 101. At this time, the column selection circuit 103 can connect the bit line BL and the source line SL to the sense amplifier 104 based on the selection result of the column of the memory cell array 101.

[0036] The column selection circuit 103 includes switches 121 and 122. Each switch 121 and 122 is provided for each column. The source line SL is connected to the sense amplifier 104 for each column via the switch 121. The bit line BL is connected to the sense amplifier 104 for each column via the switch 122. Each switch 121 and 122 may be configured with a field effect transistor.

[0037] The sense amplifier 104 detects the data read from the memory cell MC. At this time, the sense amplifier 104 can determine the data stored in the memory cell MC based on the potential of the bit line BL.

[0038] The row address latch circuit 105 latches the row address RAD and outputs it to the row selection circuit 102 .

[0039] The row selection command issuing circuit 106 outputs a row selection command RSI to the row selection circuit 102. At this time, the row selection circuit 102 can decode the row address RAD based on the row selection command RSI and drive the word line WL.

[0040] The column address latch circuit 107 latches the column address CAD and outputs it to the column selection circuit 103 .

[0041] The data output command issuing circuit 108 outputs a column selection command CSI to the column selection circuit 103 and outputs a data output command DSI to the sense amplifier 104. At this time, the column selection circuit 103 can decode the column address CAD based on the column selection command CSI and switch the switches 121 and 122. Furthermore, the sense amplifier 104 can output data DA read from the memory cell MC based on the data output command DSI.

[0042] The data memory 111 stores coded data COD, which is coded based on a row address RAD, for each row. Data cells DC are arranged for each row in the data memory 111. Word lines WL are arranged for each row in the data memory 111. Furthermore, sub-bit lines PBL and sub-source lines PSL are arranged for each column in the data memory 111. Only one column's worth of data cells DC may be provided. In this case, one parity bit can be stored in each data cell DC as the coded data COD.

[0043] The data cell DC includes a transistor TR'. The transistor TR' may be configured similarly to the transistor TR. In this case, the gate of the transistor TR' is connected to a different word line WL for each row. The source of the transistor TR' is connected to a sub-source line PSL. The drain of the transistor TR' is connected to or disconnected from a sub-bit line PBL depending on the value of the parity bit. For example, when the value of the parity bit is 0, the transistor TR' can be connected to the sub-bit line PBL, and when the value of the parity bit is 1, the transistor TR' can be disconnected from the sub-bit line PBL. The sub-bit line PBL is connected to the read circuit 112. The sub-source line PSL is connected to ground potential.

[0044] The read circuit 112 reads out the coded data COD stored in the data memory 111 and outputs it to the decision circuit 113. At this time, when a 1 is stored in the data cell DC, the read circuit 112 can output a 1 to the decision circuit 113. When a 0 is stored in the data cell DC, the read circuit 112 can output a 0 to the decision circuit 113.

[0045] The read circuit 112 includes a resistor 123 and a buffer 124. The resistor 123 is connected to the sub-bit line PBL. The buffer 124 is connected to the sub-bit line PBL in parallel with the resistor 123. The output of the buffer 124 is connected to the determination circuit 113.

[0046] At this time, the sub-bit line PBL can be connected to the power supply potential via a resistor 123. When a word line WL is selected based on the row address RAD, the transistor TR' of the data cell DC connected to the selected word line WL is turned on. When the value of the parity bit stored in the data cell DC is 0, the sub-bit line PBL is connected to the sub-source line PSL via the transistor TR'. At this time, the potential of the sub-bit line PBL is pulled down and set to a low level. The low level set on the sub-bit line PBL is input to the decision circuit 113 via a buffer 124, and a parity bit value of 0 is input to the XOR circuit 125.

[0047] On the other hand, when the value of the parity bit stored in the data cell DC is 1, the sub-bit line PBL remains disconnected from the sub-source line PSL. At this time, the potential of the sub-bit line PBL remains pulled up via the resistor 123, and the potential of the sub-bit line PBL is set to a high level. The high level set on the sub-bit line PBL is then input to the decision circuit 113 via the buffer 124, and a parity bit value of 1 is input to the XOR circuit 125.

[0048] The determination circuit 113 determines whether a word line WL has been erroneously selected based on the row address RAD. At this time, the determination circuit 113 can determine whether a word line WL has been erroneously selected based on the row address RAD based on an XOR operation.

[0049] The decision circuit 113 may include a combinational circuit to which the row address RAD and the encoded data COD are input. The combinational circuit may be an XOR (exclusive OR) circuit 125. The XOR circuit 125 performs an XOR operation on the encoded data COD read from the data cell DC based on the selection of the word line WL and the row address RAD, and outputs the operation result DB. By using the combinational circuit to determine whether a word line WL has been selected based on the row address RAD, it is possible to detect whether a word line WL has been selected based on the row address RAD, based on the current values ​​of the row address RAD and the encoded data COD. This prevents the complexity of the detection sequence for the word line WL selection, and also prevents increases in the circuit size and power consumption of the decision circuit 113. The XOR circuit 125 is an example of an arithmetic unit described in the claims.

[0050] Here, when only one column's worth of data cells DC are provided, the determination circuit 113 can detect a one-bit error in the selection of a word line WL based on the decoded result of the row address RAD. For example, the parity bit of the encoded data COD can be determined for each row so that the XOR operation of the encoded data COD and the row address RAD results in 0, and a value corresponding to the determined parity bit can be stored in the data cells DC for each row. If there is no error in the selection of a word line WL based on the decoded result of the row address RAD, the XOR circuit 125 outputs 0 as the operation result DB. On the other hand, if there is a one-bit error in the selection of a word line WL based on the decoded result of the row address RAD, the XOR circuit 125 outputs 1 as the operation result DB. Therefore, it is possible to determine whether there is an error in the selection of a word line WL based on the decoded result of the row address RAD based on the operation result DB of the XOR circuit 125.

[0051] FIG. 2 is a block diagram showing an example of the configuration of the row selection circuit according to the first embodiment.

[0052] 1, the row selection circuit 102 includes a row pre-decoder 102A, a row decoder 102B, and a word line driver 102C. The row pre-decoder 102A is connected to the row decoder 102B, and the row decoder 102B is connected to the word line driver 102C.

[0053] The row predecoder 102A divides the word line WL into selection units. At this time, the row predecoder 102A can predecode the row address RAD based on the row selection command RSI and the row address RAD. At this time, the row predecoder 102A divides the word line WL into 1 / 2 ｍ (m is a positive integer) selection may be performed.

[0054] The row decoder 102B can decode the row address RAD based on the row selection command RSI and the predecoded address predecoded by the row predecoder 102A. At this time, the row decoder 102B can latch the decoded result of the row address RAD and output the decoded result to the word line driver 102C.

[0055] The word line driver 102C drives the word line WL based on the result of decoding by the row decoder 102B. At this time, the word line driver 102C can output a word line drive signal WD to the word line WL selected by the row decoder 102B.

[0056] 3 is a circuit diagram showing an example of the configuration of a row selection circuit according to the first embodiment, which shows an example of a row predecoder 102A, a row decoder 102B, and a word line driver 102C for two rows.

[0057] In the figure, the row predecoder 102A can operate as a 1 / 2 selection circuit. The row predecoder 102A includes an inverter 141 and AND circuits 142 and 143. The AND circuit 142 receives the row address XA<0> via the inverter 141 and also receives the row selection command RSI. The AND circuit 142 outputs an inverted value XRA<0> of the row address XA<0> based on the input of the row selection command RSI. The AND circuit 143 receives the row address XA<0> and the row selection command RSI. The AND circuit 143 outputs a non-inverted value XRA<1> of the row address XA<0> based on the input of the row selection command RSI. The row address XA<0> is the first bit of the row address RAD.

[0058] The row decoder 102B includes P-channel field effect transistors 151 and 153, N-channel field effect transistors 152 and 154, and latch circuits LA1 and LA2. The latch circuit LA1 includes inverters 155 and 156. The latch circuit LA2 includes inverters 157 and 158.

[0059] The P-channel field effect transistor 151 and the N-channel field effect transistor 152 are connected in series to each other. The P-channel field effect transistor 153 and the N-channel field effect transistor 154 are connected in series to each other. A row select command RSI is input to the gates of the P-channel field effect transistors 151 and 153. An inverted value XRA<0> of the row address XA<0> is input to the gate of the N-channel field effect transistor 152. A non-inverted value XRA<1> of the row address XA<0> is input to the gate of the N-channel field effect transistor 154.

[0060] The output of inverter 155 is connected to the input of inverter 156, and the output of inverter 156 is connected to the input of inverter 155. Furthermore, the input of inverter 155 is connected to the drain of N-channel field effect transistor 152, and the output of inverter 155 is connected to the input of inverter 161.

[0061] The output of inverter 157 is connected to the input of inverter 158, and the output of inverter 158 is connected to the input of inverter 157. Furthermore, the input of inverter 157 is connected to the drain of N-channel field effect transistor 154, and the output of inverter 157 is connected to the input of inverter 162.

[0062] If a latch error occurs in either of the latch circuits LA1 and LA2, a one-bit error occurs in the selection of the word line WL based on the decoded result of the row address RAD. The latch error in each of the latch circuits LA1 and LA2 can be caused by, for example, the influence of radiation, the influence of power supply noise, a data transmission error, or the like.

[0063] The word line driver 102C includes inverters 161 and 162. The inverters 161 and 162 invert the outputs of the latch circuits LA1 and LA2, respectively, and output the word line drive signals WD0 and WD1.

[0064] As described above, in the first embodiment, one column's worth of data cells DC for storing parity bits are provided for each row, and the word lines WL of the memory cell array 101 are connected to the data cells DC for each row. This makes it possible to detect erroneous selection of word lines WL based on the row address RAD while providing data cells DC for each row with a number of bits fewer than the number of bits used to specify the row address RAD. Therefore, it is possible to detect faults during row decoder operation while suppressing an increase in the size of the memory device and an increase in the amount of calculation, and it is possible to improve reliability while suppressing an increase in the packaging area and power consumption of the memory device.

[0065] 2. Second Embodiment In the first embodiment described above, an erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check. In this second embodiment, an erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check, and a row selection command RSI is reissued based on the detection result.

[0066] FIG. 4 is a block diagram illustrating an example of the configuration of a storage device according to the second embodiment.

[0067] In the figure, this memory device includes a row selection command issuing circuit 106' instead of the row selection command issuing circuit 106 of the first embodiment. Other configurations of the memory device of the second embodiment are similar to those of the memory device of the first embodiment.

[0068] The row selection command issuing circuit 106′ receives the operation result DB of the XOR circuit 125. At this time, if the operation result DB of the XOR circuit 125 is 1, the row selection command issuing circuit 106′ reissues the row selection command RSI to the row selection circuit 102. When the row selection command RSI is reissued, the row selection circuit 102 reselects the word line WL based on the previous row address RAD.

[0069] FIG. 5 is a flowchart illustrating an example of a data determination process according to the second embodiment.

[0070] In the figure, the row selection circuit 102 selects a word line WL based on the row selection command RSI and the row address RAD (S101).

[0071] Next, the read circuit 112 reads the coded data COD stored in the data cell DC based on the result of the selection of the word line WL (S102).

[0072] Next, the decision circuit 113 performs an XOR operation on the row address RAD and the encoded data COD read from the data cell DC, and determines whether the result is 0 or 1 (S103). If the result of the operation by the decision circuit 113 is 0, it determines that there is no erroneous selection of the word line WL based on the specification of the row address RAD, and proceeds to normal operation. In this normal operation, column selection is performed, and data DA can be read from the memory cell MC specified by the row address RAD and the column address CAD.

[0073] On the other hand, if the calculation result of the determination circuit 113 is 1, it is determined that there has been an erroneous selection of the word line WL based on the specification of the row address RAD, and the row selection circuit 102 is caused to input the row selection command RSI again. At this time, the row selection circuit 102 reselects the word line WL based on the row selection command RSI and the previous row address RAD (S101). By reselecting the word line WL, the latch error of the latch circuits LA1 and LA2 can be resolved, and the word line WL based on the specification of the row address RAD can be correctly selected.

[0074] 6 is a diagram showing an example of an XOR determination result in the data determination process according to the second embodiment. The diagram shows an example in which the row address RAD is composed of two bits. Also, in the diagram, "a" shows an example in which the erroneous selection of the word line WL is not included, and "b" shows an example in which the erroneous selection of the word line WL is included.

[0075] In the figure, at a, if the number of 0's included in the row address RAD is even, the parity bit is set to 0, and if the number of 0's included in the row address RAD is odd, the parity bit is set to 1. Here, word line WL0 can be assigned to row address RAD=00, word line WL1 can be assigned to row address RAD=01, word line WL2 can be assigned to row address RAD=10, and word line WL3 can be assigned to row address RAD=11. In this case, if there is no erroneous selection of the word line WL, the XOR judgment result will be 0.

[0076] At b in the figure, for example, it is assumed that word line WL2 is selected based on the row address RAD=11. When word line WL2 is selected, 1 is read as the parity bit. At this time, the XOR result of row address RAD=11 and parity bit=1 becomes 1, and an erroneous selection of word line WL can be detected.

[0077] 7 is a diagram showing an example of a data determination sequence according to the second embodiment, in which there is no erroneous selection of the word line WL.

[0078] In the figure, when an ACT command is issued (A1), a row selection command RSI rises and is input (A2) to a row selection circuit 102. When an address is specified (A5), a row address RAD is input (A6) to the row selection circuit 102. Then, the row selection circuit 102 selects a word line WL based on the row address RAD.

[0079] When a word line WL is selected, a parity bit is read from the data cell DC in accordance with the selection result of that word line WL (A3). Then, the decision circuit 113 determines whether the word line WL has been erroneously selected based on the row address RAD based on an XOR operation of the parity bit read from the data cell DC and the row address RAD (A4, A7). At this time, if there is no erroneous selection of the word line WL, the XOR decision result will be 0.

[0080] 8 is a diagram showing another example of the data determination sequence according to the second embodiment, in which a row selection command RSI is reissued based on an erroneous selection of a word line WL, thereby eliminating the erroneous selection of the word line WL.

[0081] In the figure, when an ACT command is issued (A1), a row selection command RSI rises and is input (A2) to a row selection circuit 102. When an address is specified (A5), a row address RAD is input (A6) to the row selection circuit 102. Then, the row selection circuit 102 selects a word line WL based on the row address RAD.

[0082] When a word line WL is selected, a parity bit is read from the data cell DC in accordance with the selection result of that word line WL (A3). Then, the decision circuit 113 determines whether the word line WL has been erroneously selected based on the row address RAD based on an XOR operation of the parity bit read from the data cell DC and the row address RAD (A4, A7). At this time, if there is an erroneous selection of the word line WL, the XOR decision result will be 1.

[0083] The XOR judgment result is input to the row selection command issuing circuit 106'. At this time, if the XOR judgment result is 1, the row selection command issuing circuit 106' reissues the row selection command RSI to the row selection circuit 102 (B1). When the row selection command RSI is reissued, the row selection command RSI rises and is input to the row selection circuit 102 (B2). In addition, the previous row address RAD is reinput to the row selection circuit 102 (B6). Then, the row selection circuit 102 reselects the word line WL based on the row address RAD.

[0084] When the word line WL is reselected, a parity bit is read from the data cell DC in accordance with the reselection result of the word line WL (B3). Then, the decision circuit 113 determines whether the word line WL was erroneously selected based on the row address RAD based on the XOR operation of the parity bit read from the data cell DC and the row address RAD (B4, B7). At this time, when the erroneous selection of the word line WL is resolved, the XOR decision result becomes 0.

[0085] In this way, in the second embodiment described above, erroneous selection of a word line WL based on the specification of the row address RAD is detected based on a parity check, and the row selection command RSI is reissued based on the detection result. This makes it possible to eliminate erroneous selection of a word line WL based on the specification of the row address RAD while providing data cells DC for each row with a number of bits fewer than the number of bits used to specify the row address RAD.

[0086] 3. Third Embodiment In the first embodiment described above, erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check, and the detection result is output. In this third embodiment, erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check, and the detection result is output together with read data from a memory cell MC.

[0087] FIG. 9 is a block diagram illustrating an example of the configuration of a storage device according to the third embodiment.

[0088] In the figure, this storage device includes a data memory 111' and a read circuit 112' instead of the data memory 111 and read circuit 112 of the first embodiment. Other configurations of the storage device of the third embodiment are similar to those of the storage device of the first embodiment described above.

[0089] The data memory 111' stores coded data COD, which is coded based on a row address RAD, for each row. Data cells DC' are arranged for each row in the data memory 111'. Word lines WL are arranged for each row in the data memory 111'. Furthermore, sub-bit lines PBL and sub-source lines PSL are arranged for each column in the data memory 111'. Only one column's worth of data cells DC' may be provided. In this case, one parity bit can be stored in each data cell DC' as the coded data COD.

[0090] The data cells DC' can be configured in the same manner as the memory cells MC. In this case, the gates of the transistors TR of the data cells DC' are connected to different word lines WL for each row. The sources of the transistors TR of the data cells DC' are connected to the sub-source lines PSL. The drains of the transistors TR of the data cells DC' are connected to the sub-bit lines PBL via the storage elements MD.

[0091] The memory element MD of the data cell DC' can store one parity bit as encoded data COD. For example, assume that the data cell DC' is a ReRAM. In this case, when a parity bit value of 0 is stored in the data cell DC', the memory element MD can be made to store a low resistance value, and when a parity bit value of 1 is stored in the data cell DC', the memory element MD can be made to store a high resistance value.

[0092] The read circuit 112' can be configured in the same manner as the sense amplifier 104. At this time, the read circuit 112' can determine the encoded data COD stored in the data cell DC' based on the potential of the sub-bit line PBL and output it to the decision circuit 113. Here, the read circuit 112' can output the encoded data COD to the decision circuit 113 based on the data output command DSI. At this time, the output timing of the read data DA from the sense amplifier 104 and the output timing of the encoded data COD from the read circuit 112' can be made to be equal to each other. Here, the decision circuit 113 can output the operation result DB of the XOR circuit 125 in accordance with the output of the read data DA from the sense amplifier 104.

[0093] FIG. 10 is a flowchart illustrating an example of a data determination process according to the third embodiment.

[0094] In the figure, the row selection circuit 102 selects a word line WL based on the row selection command RSI and the row address RAD (S101).

[0095] Next, the read circuit 112 reads the coded data COD stored in the data cell DC based on the result of the selection of the word line WL (S102).

[0096] Next, the decision circuit 113 performs an XOR operation on the row address RAD and the encoded data COD read from the data cell DC, and decides whether the result of the operation is 0 or 1 (S103).

[0097] On the other hand, the column selection circuit 103 selects a bit line BL and a source line SL based on the column selection command CSI and the column address CAD (S201).

[0098] Next, the sense amplifier 104 reads the data DA from the memory cell MC based on the selection result of the bit line BL and the source line SL (S202).

[0099] Next, the determination circuit 113 outputs its determination value in accordance with the output of the read data DA from the sense amplifier 104 (S104).

[0100] 11 is a diagram showing an example of a data determination sequence according to the third embodiment, in which there is no erroneous selection of the word line WL.

[0101] In the figure, the determination of erroneous selection of the word line WL based on the designation of the row address RAD is carried out in the same manner as in the memory device of the first embodiment (A1 to A7).

[0102] Next, when a READ command is issued (C1), a column selection command CSI rises and is input to the column selection circuit 103 (C2). When an address is specified (C5), a column address CAD is input to the column selection circuit 103 (C6). Then, the column selection circuit 103 selects a bit line BL and a source line SL based on the column address CAD.

[0103] Next, when the data output command DSI rises, the sense amplifier 104 outputs the read data DA (C7), and the decision circuit 113 outputs a decision value (C8).

[0104] In this way, in the third embodiment described above, erroneous selection of the word line WL based on the row address RAD is detected based on the parity check, and the detection result is output together with the read data DA from the memory cell MC, thereby making it possible to externally recognize whether the read data DA output from the memory device is the read data DA corresponding to the row address RAD.

[0105] In the above-described third embodiment, an example was shown in which the data memory 111' and the read circuit 112' are provided instead of the data memory 111 and the read circuit 112 of the first embodiment. However, the storage device of the above-described third embodiment may also be provided with the data memory 111 and the read circuit 112 of the above-described first embodiment instead of the data memory 111' and the read circuit 112'.

[0106] Furthermore, in the first and second embodiments described above, an example was shown in which the data memory 111 and the read circuit 112 were provided. However, in the first and second embodiments described above, the data memory 111' and the read circuit 112' of the third embodiment described above may be provided instead of the data memory 111 and the read circuit 112.

[0107] 4. Fourth Embodiment In the first embodiment described above, data cells DC for storing parity bits are provided for each row for one column. In this fourth embodiment, data cells DC for storing parity bits are provided for each row across multiple columns.

[0108] FIG. 12 is a block diagram illustrating an example of the configuration of a storage device according to the fourth embodiment.

[0109] In the figure, this storage device includes a plurality of data memories 111A, 111B, and a plurality of read circuits 112A, 112B, instead of the data memory 111 and read circuit 112 of the first embodiment described above. Also, this storage device includes a determination circuit 213 instead of the determination circuit 113 of the first embodiment described above. Other configurations of the storage device of the fourth embodiment are similar to those of the storage device of the first embodiment described above.

[0110] The data memories 111A, 111B... and the read circuits 112A, 112B... are provided for each column. Each of the data memories 111A, 111B... stores, for each row, coded data COD1, COD2... that is coded based on a row address RAD. Each of the data memories 111A, 111B... can be configured in the same manner as the data memory 111 of the first embodiment described above.

[0111] Each of the read circuits 112A, 112B, etc. reads out the coded data COD1, COD2, etc. stored in each of the data memories 111A, 111B, etc. for each column, and outputs the coded data to the determination circuit 213. Each of the read circuits 112A, 112B, etc. can be configured in the same manner as the read circuit 112 of the first embodiment described above.

[0112] The determination circuit 213 determines whether a word line WL has been erroneously selected based on the row address RAD. Based on the result of an operation between the row address RAD and the encoded data COD1, COD2, etc., the determination circuit 213 can determine whether multiple bits of the word line WL have been erroneously selected based on the row address RAD, and can perform error correction. The determination circuit 213 may include an ECC (Error Correction Code) circuit. The encoded data COD1, COD2, etc. may be, for example, a Hamming code.

[0113] In this way, in the fourth embodiment described above, data cells DC for storing parity bits are provided for each row across multiple columns, which makes it possible to detect erroneous selection of word lines WL due to garbled bits of two or more bits specified by the row address RAD.

[0114] In the fourth embodiment described above, an example was shown in which a plurality of data memories 111A, 111B... and a plurality of readout circuits 112A, 112B... were provided. However, in the fourth embodiment described above, a plurality of data memories 111A, 111B... and a plurality of readout circuits 112A, 112B... may be replaced with a plurality of data memories 111' and a plurality of readout circuits 112' of the third embodiment described above.

[0115] 5. Fifth Embodiment In the first embodiment described above, erroneous selection of a word line WL based on the row address RAD is detected based on a parity check. In this fifth embodiment, only one row of data cells for storing parity bits are provided, and erroneous selection of a bit line BL based on the column address CAD is detected based on a parity check.

[0116] FIG. 13 is a block diagram illustrating an example of the configuration of a storage device according to the fifth embodiment.

[0117] In the figure, this storage device includes a data memory 111A, a read circuit 112', and a judgment circuit 113' instead of the data memory 111, read circuit 112, and judgment circuit 113 of the first embodiment described above. Also, this storage device includes a column selection circuit 103', a column address latch circuit 107', and a data output command issuing circuit 108' instead of the column selection circuit 103, column address latch circuit 107, and data output command issuing circuit 108 of the first embodiment described above. Other configurations of the storage device of the fifth embodiment are the same as those of the storage device of the first embodiment described above.

[0118] The column address latch circuit 107' latches the column address CAD and outputs it to the column selection circuit 103'.

[0119] The data output command issuing circuit 108' outputs a column select command CSI to the column selection circuit 103' and outputs a data output command DSI to the sense amplifier 104. The operation result DB' of the XOR circuit 125' is input to the data output command issuing circuit 108'. At this time, if the operation result DB' of the XOR circuit 125' is 1, the data output command issuing circuit 108' reissues the column select command CSI to the column selection circuit 103'. When the column select command CSI is reissued, the column selection circuit 103' reselects the bit line BL based on the previous column address CAD. When the column select command CSI is reissued, the column selection circuit 103' reselects a column of the data memory 111A based on the specification of the column address CAD.

[0120] The data memory 111A stores coded data COD' for each column, which is coded based on a column address CAD. The data memory 111A has as many data cells DCA as there are columns in the memory cell array 101. The data memory 111A has sub-bit lines PBL' and sub-source lines PSL' for each column. One parity bit can be stored in each data cell DCA as the coded data COD'.

[0121] The data cell DCA includes a data line DL. The data line DL can set the sub-bit line PBL' and the sub-source line PSL' to a short state or an open state depending on the value of the parity bit. For example, when the value of the parity bit is 0, the data line DL can set the sub-bit line PBL' and the sub-source line PSL' to a short state, and when the value of the parity bit is 1, the data line DL can set the sub-bit line PBL' and the sub-source line PSL' to an open state. The sub-bit line PBL' is connected to a read circuit 112'. The sub-source line PSL' is connected to a ground potential.

[0122] In addition to the selection operation of the first embodiment described above, the column selection circuit 103' selects a column of the data memory 111A based on the specification of the column address CAD. At this time, the column selection circuit 103' can connect the sub-bit lines PBL' to the read circuit 112' for each column based on the column selection result of the memory cell array 101.

[0123] The column selection circuit 103' includes a switch 122' in addition to the configuration of the first embodiment described above. A switch 122' is provided for each column. The sub-bit line PBL' is connected to the read circuit 112' for each column via the switch 122'. The switch 122' may be configured with a field-effect transistor. After a column selection command CSI is issued, the switch 122' corresponding to the column selected based on the column address CAD is turned on, and the sub-bit line PBL' corresponding to that column is connected to the read circuit 112'.

[0124] The read circuit 112' reads out the coded data COD' stored in the data memory 111A and outputs it to the decision circuit 113'. At this time, if a 1 is stored in the data cell DCA, the read circuit 112' can output a 1 to the decision circuit 113'. If a 0 is stored in the data cell DCA, the read circuit 112' can output a 0 to the decision circuit 113'.

[0125] The read circuit 112' includes a resistor 123' and a buffer 124'. The resistor 123' is connected to the output of the selector 103E. The buffer 124' is connected to the output of the selector 103E in parallel with the resistor 123'. The output of the buffer 124' is connected to the determination circuit 113'.

[0126] At this time, the output of the selector 103E can be connected to the power supply potential via a resistor 123'. When a column address CAD is specified, a bit line BL is selected, and a switch 122' for the column corresponding to the column address CAD is turned on, connecting the sub-bit line PBL' for that column to the read circuit 112'. When the parity bit stored in the data cell DCA has a value of 0, the sub-bit line PBL' is connected to the sub-source line PSL' via the data line DL. At this time, the potential of the sub-bit line PBL' is pulled down and set to a low level. The low level set on the sub-bit line PBL' is input to the decision circuit 113' via a buffer 124', and a parity bit value of 0 is input to the XOR circuit 125'.

[0127] On the other hand, when the value of the parity bit stored in the data cell DCA is 1, the sub-bit line PBL' remains disconnected from the sub-source line PSL'. At this time, the potential of the sub-bit line PBL' remains pulled up via the resistor 123', and the potential of the sub-bit line PBL' is set to a high level. The high level set on the sub-bit line PBL' is then input to the decision circuit 113' via the buffer 124', and a parity bit value of 1 is input to the XOR circuit 125'.

[0128] The determination circuit 113' determines whether the bit line BL has been erroneously selected based on the column address CAD. At this time, the determination circuit 113' can determine whether the bit line BL has been erroneously selected based on the column address CAD based on the XOR operation.

[0129] The decision circuit 113' may include a combinational circuit to which the column address CAD and the coded data COD' are input. The combinational circuit may be an XOR circuit 125'. The XOR circuit 125' performs an XOR operation on the coded data COD' read from the data cell DCA based on the selection of the bit line BL and the column address CAD, and outputs the operation result DB'.

[0130] Here, when only one row of data cells DCA is provided, the decision circuit 113' can detect a one-bit error in the selection of the bit line BL based on the decoded result of the column address CAD. For example, a parity bit of the coded data COD' can be determined for each column so that the XOR operation of the coded data COD' and the column address CAD results in 0, and a value corresponding to the determined parity bit can be stored in the data cell DCA for each column. If there is no error in the selection of the bit line BL based on the decoded result of the column address CAD, the XOR circuit 125' outputs 0 as the operation result DB'. On the other hand, if there is a one-bit error in the selection of the bit line BL based on the decoded result of the column address CAD, the XOR circuit 125' outputs 1 as the operation result DB'. Therefore, the decision circuit 113' can determine whether there is an error in the selection of the bit line BL based on the decoded result of the column address CAD based on the operation result DB' of the XOR circuit 125'.

[0131] 14 is a circuit diagram showing an example of the configuration of a column selection circuit according to the fifth embodiment, which shows an example of a decoder 103B, a driver 103C, and selectors 103D and 103E for two columns.

[0132] In the figure, the column selection circuit 103' includes a latch circuit 103A, a decoder 103B, a driver 103C, and selectors 103D and 103E. The decoder 103B is connected to the rear of the latch circuit 103A, the driver 103C is connected to the rear of the decoder 103B, the selector 103D is connected to the rear of the driver 103C, and the selector 103E is connected to the rear of the selector 103D.

[0133] The latch circuit 103A latches the column select command CSI based on the column address YA<0>, which is the first bit of the column address CAD. The output of the latch circuit 103A is input to the decoder 103B.

[0134] Decoder 103B inputs the inverted and non-inverted values ​​of the output of latch circuit 103A to driver 103C. Decoder 103B includes an inverter 241. The output of inverter 241 is connected to the input of inverter 251, and the input of inverter 241 is connected to the output of latch circuit 103A and the input of inverter 252.

[0135] The driver 103C drives the selectors 103D and 103E. The driver 103C includes inverters 251 and 252. The inverter 251 generates a non-inverted value XCA<1> of the column address YA<0> and outputs it to the inverter 261. The inverter 252 generates an inverted value XCA<0> of the column address YA<0> and outputs it to the inverter 262.

[0136] The selector 103D includes inverters 261 and 262 and transmission gates 263 to 266. The transmission gates 263 and 265 can be used as the switches 121 for the source lines SL0 and SL1, respectively, and the transmission gates 264 and 266 can be used as the switches 122 for the bit lines BL0 and BL1, respectively. The non-inverting inputs of the transmission gates 263 and 264 are connected to the output of the inverter 252, and the inverting inputs of the transmission gates 263 and 264 are connected to the output of the inverter 262. The non-inverting inputs of the transmission gates 265 and 266 are connected to the output of the inverter 251, and the inverting inputs of the transmission gates 265 and 266 are connected to the output of the inverter 261.

[0137] The selector 103E includes transmission gates 271 and 272. The transmission gate 271 can be used as a switch 122' for each sub-bit line PBL'. The non-inverting input of the transmission gate 271 is connected to the output of the inverter 252, and the inverting input of the transmission gate 271 is connected to the output of the inverter 262. The non-inverting input of the transmission gate 272 is connected to the output of the inverter 251, and the inverting input of the transmission gate 272 is connected to the output of the inverter 261.

[0138] FIG. 15 is a flowchart illustrating an example of a data determination process according to the fifth embodiment.

[0139] In the figure, a column selection circuit 103' selects a bit line BL and a source line SL, and also selects a sub-bit line PBL', based on the specification of a column selection command CSI and a column address CAD (S301).

[0140] Next, the read circuit 112' reads the coded data COD' stored in the data cell DCA based on the selection result of the sub-bit line PBL' (S302).

[0141] Next, the determination circuit 113' performs an XOR operation on the column address CAD and the encoded data COD' read from the data cell DCA, and determines whether the result of the operation is 0 or 1 (S303). If the result of the operation by the determination circuit 113' is 0, it determines that there is no erroneous selection of the bit line BL based on the specification of the column address CAD, and proceeds to normal operation (S304).

[0142] On the other hand, if the calculation result of the decision circuit 113' is 1, it is determined that there has been an erroneous selection of the bit line BL based on the specification of the column address CAD, and the column selection circuit 103' is caused to input the column selection command CSI again. At this time, the column selection circuit 103' reselects the bit line BL and the sub-bit line PBL' based on the column selection command CSI and the previous column address CAD (S301). By reselecting the bit line BL and the sub-bit line PBL', the latch error of the latch circuit 103C can be eliminated, and the bit line BL and the sub-bit line PBL' based on the specification of the column address CAD can be correctly selected.

[0143] As described above, in the fifth embodiment, only one row of data cells for storing parity bits is provided, and erroneous selection of bit lines BL based on the specification of column addresses CAD is detected based on a parity check. This allows for detection of erroneous selection of bit lines BL based on the specification of column addresses CAD, while providing data cells DCA with a number of bits less than the number of bits used to specify column addresses CAD for each column. Therefore, it is possible to detect faults during operation of the column decoder while suppressing an increase in the size of the memory device and an increase in the amount of calculations, thereby enabling improved reliability while suppressing increases in the packaging area and power consumption of the memory device.

[0144] In the fifth embodiment, the data cells DCA for storing the parity bits are provided for one row per column. However, as in the fourth embodiment, the data cells DCA for storing the parity bits may be provided for each column across multiple rows in order to enable detection of bit errors of multiple bits in the column address CAD.

[0145] 6. Sixth Embodiment In the fifth embodiment described above, only one row of data cells DCA for storing parity bits are provided, and erroneous selection of bit lines BL based on the specification of column addresses CAD is detected based on a parity check. In this sixth embodiment, data cells for storing parity bits are provided in the same number as the number of rows of memory cells MC, and the transistors of the data cells are not connected to the sub-bit lines, so that erroneous selection of bit lines based on the specification of column addresses is detected based on a parity check.

[0146] FIG. 16 is a block diagram illustrating an example of the configuration of a storage device according to the sixth embodiment.

[0147] In the figure, this storage device includes a data memory 111B instead of the data memory 111A of the fifth embodiment. The other configuration of the storage device of the sixth embodiment is the same as that of the storage device of the first embodiment.

[0148] The data memory 111B includes data cells DCB. The data cells DCB are provided for each row, the number of which is equal to the number of columns in the memory cell array 101. Each data cell DCB includes a transistor TR'. In this case, the gate of the transistor TR' is connected to a different word line WL for each row. The source of the transistor TR' is connected to a sub-source line PSL'. The drain of the transistor TR' is left unconnected.

[0149] Furthermore, the sub-bit line PBL' and the sub-source line PSL' are connected to each other via the data line DL according to the column address CAD that designates each column. For example, when the value of the parity bit set in the column address CAD is 0, the sub-bit line PBL' and the sub-source line PSL' of that column can be connected via the data line DL. When the value of the parity bit set in the column address CAD is 1, the sub-bit line PBL' and the sub-source line PSL' of that column can be prevented from being connected via the data line DL.

[0150] As described above, in the sixth embodiment, data cells DCB for storing parity bits are provided for each row, the number of which is equal to the number of columns in the memory cell array 101, and the word lines WL of the memory cell array 101 are connected to the data cells DC for each row. At this time, a transistor TR' is provided in each data cell DCB. This makes it possible to uniformly arrange the memory cells MC and data cells DCB in a matrix in the row and column directions, while also making it possible to detect erroneous selection of a bit line BL based on the specification of a column address CAD.

[0151] 7. Seventh Embodiment In the sixth embodiment described above, data cells DCB each having a transistor TR' are provided for each row, the number of which corresponds to the number of columns in the memory cell array 101, and the parity bit set in the column address CAD is set via the data line DL. In this seventh embodiment, data cells DC each having a transistor TR' are provided for each row, the number of which corresponds to the number of columns in the memory cell array 101, and the parity bit set in the column address CAD is stored in the data cells DC.

[0152] FIG. 17 is a block diagram illustrating an example of the configuration of a storage device according to the seventh embodiment.

[0153] In the figure, this storage device includes a data memory 111' instead of the data memory 111B of the sixth embodiment. The other configuration of the storage device of the seventh embodiment is the same as that of the storage device of the sixth embodiment.

[0154] The data memory 111' includes data cells DC. The data cells DC are provided for each row, the number of which is equal to the number of columns in the memory cell array 101. In this case, the gate of the transistor TR' is connected to a different word line WL for each row. The source of the transistor TR' is connected to a sub-source line PSL'. The drain of the transistor TR' is connected to or disconnected from a sub-bit line PBL' depending on the value of the parity bit. For example, when the value of the parity bit is 0, the transistor TR' can be connected to the sub-bit line PBL', and when the value of the parity bit is 1, the transistor TR' can be disconnected from the sub-bit line PBL'. In this case, the same parity bit can be set in the data cells DC in the same column.

[0155] FIG. 18 is a flowchart illustrating an example of a data determination process according to the seventh embodiment.

[0156] In the figure, the row selection circuit 102 selects a word line WL based on the row selection command RSI and the row address RAD (S101).

[0157] On the other hand, the column selection circuit 103' selects the bit line BL and the source line SL, and also selects the sub-bit line PBL', based on the column selection command CSI and the column address CAD (S301).

[0158] Next, the read circuit 112' reads the coded data COD' stored in the data cell DC based on the selection result of the word line WL and the sub-bit line PBL' (S302).

[0159] Next, the determination circuit 113' performs an XOR operation on the column address CAD and the encoded data COD' read from the data cell DC, and determines whether the result of the operation is 0 or 1 (S303). If the result of the operation by the determination circuit 113' is 0, it determines that there is no erroneous selection of the bit line BL based on the specification of the column address CAD, and proceeds to normal operation (S304).

[0160] On the other hand, if the calculation result of the decision circuit 113' is 1, it is determined that there has been an erroneous selection of the bit line BL based on the specification of the column address CAD, and the column selection circuit 103' is caused to input the column selection command CSI again. At this time, the column selection circuit 103' reselects the bit line BL and the sub-bit line PBL' based on the column selection command CSI and the previous column address CAD (S301).

[0161] In this way, in the seventh embodiment described above, data cells DC each having a transistor TR' are provided for each row, the number of which is equal to the number of columns in the memory cell array 101, and the parity bit set in the column address CAD is stored in the data cells DC. This makes it possible to uniformly arrange the memory cells MC and the data cells DC in a matrix in the row and column directions, while also making it possible to detect erroneous selection of the bit line BL based on the specification of the column address CAD.

[0162] 8. Eighth Embodiment In the first embodiment described above, erroneous selection of a word line WL based on specification of a row address RAD is detected based on a parity check. In this eighth embodiment, erroneous selection of a word line WL based on specification of a row address RAD and erroneous selection of a bit line BL based on specification of a column address CAD are detected.

[0163] FIG. 19 is a block diagram illustrating an example of the configuration of a storage device according to the eighth embodiment.

[0164] In the figure, this storage device includes a column selection circuit 103', a column address latch circuit 107', and a data output command issuing circuit 108' instead of the column selection circuit 103, the column address latch circuit 107, and the data output command issuing circuit 108 of the second embodiment. Furthermore, this storage device is configured by adding the data memory 111', the read circuit 112', and the determination circuit 113' of the seventh embodiment to the storage device of the second embodiment. Other configurations of the storage device of the eighth embodiment are the same as those of the storage device of the second embodiment.

[0165] At this time, the determination circuit 113 determines whether a word line WL has been erroneously selected based on the row address RAD, and the determination circuit 113' determines whether a bit line BL has been erroneously selected based on the column address CAD. The determinations of these determination circuits 113 and 113' can be performed in parallel. When the determination circuit 113 determines whether a word line WL has been erroneously selected, the row selection command issuing circuit 106' reissues a row selection command RSI to the row selection circuit 102. When the determination circuit 113' determines whether a bit line BL has been erroneously selected, the data output command issuing circuit 108' reissues a column selection command CSI to the column selection circuit 103'.

[0166] In this way, in the eighth embodiment described above, erroneous selection of a word line WL based on the specification of a row address RAD and erroneous selection of a bit line BL based on the specification of a column address CAD are detected. This makes it possible to realize fault detection during operation of the row decoder and column decoder while suppressing an increase in the scale of the memory device and an increase in the amount of calculation, and makes it possible to improve reliability while suppressing an increase in the mounting area and power consumption of the memory device.

[0167] 9. Ninth Embodiment In the above-described eighth embodiment, erroneous selection of a word line WL based on specification of a row address RAD and erroneous selection of a bit line BL based on specification of a column address CAD are detected. In this ninth embodiment, erroneous selection of a memory cell MC based on address specification that combines a row address RAD and a column address CAD is detected.

[0168] FIG. 20 is a block diagram illustrating an example of the configuration of a storage device according to the ninth embodiment.

[0169] In the figure, this storage device includes a data memory 111" and a determination circuit 113" instead of the data memory 111' and the determination circuit 113' of the seventh embodiment. The rest of the configuration of the storage device of the ninth embodiment is the same as that of the storage device of the seventh embodiment.

[0170] The data memory 111'' includes data cells DC. The data cells DC are provided for each row, the number of which corresponds to the number of columns in the memory cell array 101. The gates of the transistors TR' are connected to different word lines WL for each row. The sources of the transistors TR' are connected to sub-source lines PSL'. The drains of the transistors TR' are connected to or disconnected from sub-bit lines PBL' depending on the value of the parity bit. For example, when the parity bit value is 0, the transistor TR' is connected to the sub-bit line PBL', and when the parity bit value is 1, the transistor TR' can be disconnected from the sub-bit line PBL'. A parity bit can be stored in each data cell DC according to the parity bit set at an address obtained by combining a row address RAD and a column address CAD. The read circuit 112' outputs encoded data COD'' to a decision circuit 113'' based on the parity bit stored in each data cell DC.

[0171] The decision circuit 113" can include a combinational circuit to which the row address RAD, the column address CAD, and the coded data COD" are input. The combinational circuit may be an XOR circuit 125". The XOR circuit 125" performs an XOR operation on the coded data COD" read from the data cell DC based on the selection of the word line WL and the bit line BL, the row address RAD, and the column address CAD, and outputs the operation result DB".

[0172] Here, when data cells DC are provided for each row in a number equal to the number of columns in the memory cell array 101, the decision circuit 113" can detect a one-bit error in the selection of memory cells MC based on the decoded results of the row address RAD and the column address CAD. For example, a parity bit of the coded data COD" can be determined for each data cell DC so that an XOR operation of the coded data COD", the row address RAD, and the column address CAD results in 0, and a value corresponding to the determined parity bit can be stored for each data cell DC. Then, when there is no error in the selection of memory cells MC based on the decoded results of the row address RAD and the column address CAD, the XOR circuit 125" outputs 0 as the operation result DB". On the other hand, when there is a one-bit error in the selection of memory cells MC based on the decoded results of the row address RAD and the column address CAD, the XOR circuit 125" outputs 1 as the operation result DB". Therefore, based on the calculation result DB'' of the XOR circuit 125'', it can be determined whether or not there is an error in the selection of the memory cell MC based on the decoding results of the row address RAD and the column address CAD.

[0173] In this way, in the ninth embodiment described above, erroneous selection of memory cells MC based on address designation combining row addresses RAD and column addresses CAD is detected. This makes it possible to realize fault detection during operation of the address decoder while suppressing an increase in the scale and amount of calculation of the memory device, and to improve reliability while suppressing an increase in the mounting area and power consumption of the memory device.

[0174] 10. Tenth Embodiment In the first embodiment described above, erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check. In this tenth embodiment, a storage device provided with a data memory 111 used to detect erroneous selection of a word line WL based on the specification of a row address RAD is applied to an imaging device.

[0175] FIG. 21 is a block diagram showing an example of the configuration of an imaging apparatus according to the tenth embodiment.

[0176] In the figure, the imaging device includes an optical system 301, a shutter device 302, a solid-state imaging device (image sensor) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. This imaging device is capable of capturing still images and moving images. The imaging device may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0177] The optical system 301 causes light from a subject to be incident on the solid-state imaging device 303, and forms an optical image on the light receiving surface of the solid-state imaging device 303. The optical system 301 may include, for example, a focus lens, a zoom lens, an aperture, etc. The optical system 301 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0178] The shutter device 302 is disposed between the optical system 301 and the solid-state imaging device 303. The shutter device 302 controls the light irradiation period and the light blocking period for the solid-state imaging device 303 under the control of the control circuit 304.

[0179] The solid-state imaging device 303 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 303 may be, for example, a complementary metal oxide semiconductor (CMOS) image sensor or an event-based vision sensor (EVS). The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 303 may be a lateral overflow integration capacitor (LOFIC) CMOS image sensor, or may be a charge domain global shutter type or a voltage domain global shutter type.

[0180] The control circuit 304 outputs drive signals that control the transfer operation of the solid-state imaging device 303 and the shutter operation of the shutter device 302, thereby driving the solid-state imaging device 303 and the shutter device 302. At this time, the control circuit 304 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 303.

[0181] The signal processing circuit 305 performs various signal processing on the signal output from the solid-state imaging device 303. The image (image data) obtained by performing the signal processing by the signal processing circuit 305 is supplied to the monitor 306 and the memory 307. The signal processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The signal processing circuit 305 may include a processor that executes processing based on software.

[0182] The monitor 306 displays captured images and various information that supports the image capturing operation, etc. The monitor 306 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0183] The memory 307 stores images captured by the solid-state imaging device 303, imaging parameters of the solid-state imaging device 303, etc. The memory 307 can also store a program that operates the imaging device based on software. The memory 307 may include a read-only memory (ROM), a random access memory (RAM), and a memory card. The memory 307 may include any of the storage devices described in the first to tenth embodiments.

[0184] In this imaging device, by providing the memory 307 with a storage device according to any one of the first to tenth embodiments described above, it is possible to improve reliability while suppressing increases in the mounting area and power consumption of the memory 307.

[0185] FIG. 22 is a block diagram showing an example of the configuration of a solid-state imaging device according to the tenth embodiment.

[0186] In the figure, the solid-state imaging device 502 includes a pixel array section 511 , a vertical scanning circuit 512 , a column readout circuit 513 , a column signal processing section 514 , a horizontal scanning circuit 515 , and a control circuit 516 .

[0187] The pixel array unit 511 includes a plurality of pixels 520. These pixels 520 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 520 can form a source follower with the column readout circuit 513 when reading out a signal.

[0188] Each pixel 520 is connected to a horizontal drive line 531 for each row and to a vertical signal line 532 for each column. The horizontal drive line 531 drives each pixel 520 for each row when reading out a signal from each pixel 120. Each vertical signal line 532 transmits a potential based on a current that flows when reading out a signal from each pixel 520 to the column signal processing unit 514 for each column.

[0189] The pixels 520 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 520 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0190] The vertical scanning circuit 512 scans the pixels 520 to be read in the column direction. The vertical scanning circuit 512 may be configured using vertical registers. The vertical scanning circuit 512 may also include a decoder that specifies the pixels 520 to be read.

[0191] The column readout circuit 513 can form a source follower between itself and each pixel 520 when reading out a signal from the pixel 520. At this time, the column readout circuit 513 can change the potential of each vertical signal line 532 based on the charge held in each pixel 520.

[0192] The column signal processing unit 514 processes signals transmitted in the column direction from each pixel 520. For example, the column signal processing unit 514 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 520. The column signal processing unit 514 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 520, and output an imaging signal Gout.

[0193] The column signal processing unit 514 includes a column ADC unit 514A. The column ADC unit 514A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 514A can perform AD conversion for each column based on the result of comparing the pixel signal read from each pixel 520 with a reference signal.

[0194] The horizontal scanning circuit 515 scans the pixels 520 to be read in the row direction. The horizontal scanning circuit 515 may be configured using a horizontal register.

[0195] The control circuit 516 controls the vertical scanning circuit 512, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515. For example, the control circuit 516 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 513, and the processing timing of the column signal processing unit 514. In this case, the control circuit 516 can coordinate the vertical scanning circuit 512, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0196] The control circuit 516 may include any one of the storage devices according to the first to tenth embodiments. In this case, the control circuit 516 may control the solid-state imaging device 502 based on data stored in the storage device.

[0197] FIG. 23 is a perspective view showing an example of lamination of a pixel array unit according to the tenth embodiment.

[0198] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0199] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0200] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, an interface 927, a control circuit 928, and a memory device 929 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The memory device 929 may include any of the memory devices according to the first to tenth embodiments described above.

[0201] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0202] In this way, in the tenth embodiment described above, a memory device capable of detecting erroneous selection of word lines or bit lines based on addressing is applied to an imaging device, thereby making it possible to improve the reliability of imaging while suppressing increases in the size and power consumption of the imaging device.

[0203] 11. Eleventh Embodiment In the first embodiment described above, erroneous selection of a word line WL based on the specification of a row address RAD is detected based on a parity check. In this eleventh embodiment, a storage device provided with a data memory 111 used to detect erroneous selection of a word line WL based on the specification of a row address RAD is applied to a distance measuring device.

[0204] FIG. 24 is a block diagram showing an example of the configuration of a distance measuring device according to the eleventh embodiment.

[0205] In the figure, the distance measuring device includes a light source unit 401, an optical system 402, a solid-state imaging device (image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. This distance measuring device emits light from the light source unit 401 to an object and receives incident light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0206] The light source unit 401 emits light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, can be used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0207] The optical system 402 causes light from a subject to be incident on the solid-state imaging device 403, and forms an optical image on the light receiving surface of the solid-state imaging device 403. The optical system 401 may include, for example, a focus lens, a zoom lens, an aperture, etc. The optical system 401 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0208] The solid-state imaging device 403 accumulates signal charges in response to light that is imaged on the light-receiving surface via the optical system 402. A distance signal indicating a distance determined from a light-receiving signal output from the solid-state imaging device 403 is supplied to the signal processing circuit 405. The solid-state imaging device 403 may be, for example, a solid-state imaging element such as an image sensor. In this case, pixels may be arranged in a matrix along the row and column directions on the light-receiving surface of the solid-state imaging device 403. Each pixel outputs, as pixel data, the count result of pulses generated in response to incident photons. In this case, each pixel may include a SPAD (Single Photon Avalanche Diode).

[0209] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the solid-state imaging device 403, etc., and drives the light source unit 401, the solid-state imaging device 403, etc.

[0210] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the solid-state imaging device 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to the monitor 406 and the memory 407.

[0211] The monitor 406 displays the distance image captured by the solid-state imaging device 403 based on the image data supplied from the signal processing circuit 405. As the monitor 406, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel is used.

[0212] The memory 407 stores the image data supplied from the signal processing circuit 405, i.e., the image data of the distance image captured by the solid-state imaging device 403. The memory 407 may include any of the storage devices according to the first to tenth embodiments described above.

[0213] In this distance measuring device, by providing a memory device according to any one of the first to tenth embodiments described above in the memory 407, it is possible to improve reliability while suppressing increases in the mounting area and power consumption of the memory 407.

[0214] In this way, in the eleventh embodiment described above, a memory device capable of detecting erroneous selection of word lines or bit lines based on addressing is applied to a distance measuring device, thereby making it possible to improve the reliability of distance measurement while suppressing increases in the size and power consumption of the distance measuring device.

[0215] 12. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0216] FIG. 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0217] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0218] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0219] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0220] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0221] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0222] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0223] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0224] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0225] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0226] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 25, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0227] FIG. 26 is a diagram showing an example of the installation position of the imaging unit 12031.

[0228] In FIG. 26, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0229] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0230] 26 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0231] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0232] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0233] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0234] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0235] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031 among the above-described configurations. Specifically, for example, the storage devices according to the first to tenth embodiments described above can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to detect a fault during operation of the address decoder while suppressing an increase in the size of the storage device.

[0236] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0237] The present technology can also be configured as follows: (1) A storage device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells, each row containing coded data coded based on a row address, are arranged; word lines connecting the memory cells and the data cells for each row; bit lines connecting the memory cells for each column; a word selection circuit selecting the word line based on the row address; a read circuit reading the coded data stored in the data memory; and an arithmetic unit outputting a result of an operation between the coded data read based on the selection of the word line and the row address. (2) The storage device according to (1), further comprising sub-bit lines connected to the data cells, wherein the read circuit inputs the coded data to the arithmetic unit based on a potential transmitted to the sub-bit line via the data cell. (3) The storage device according to (1) or (2), wherein the data cell comprises a transistor that is open or shorted with respect to the read circuit or a memory element that is conductive or insulated from the read circuit. (4) The storage device according to any one of (1) to (3), wherein the arithmetic unit comprises a combinational circuit to which the row address and the encoded data are input. (5) The storage device according to any one of (1) to (4), wherein the arithmetic unit comprises an exclusive OR circuit to which the row address and the encoded data are input. (6) The storage device according to any one of (1) to (5), wherein the encoded data is a parity bit of a row address assigned to the word line. (7) The storage device according to any one of (1) to (6), wherein the data memories and the readout circuits are provided for a plurality of columns. (8) The storage device according to any one of (1) to (7), wherein the arithmetic unit comprises an ECC (Error Correction Code) circuit. (9) The storage device according to any one of (1) to (8), wherein the memory cells comprise: transistors having gates connected to the word lines; and storage elements connected in series to the transistors.(10) The memory device according to any one of (1) to (9), further comprising a sense amplifier that determines data stored in the memory cell based on the potential of the bit line, wherein the read circuit reads the encoded data from the data memory based on a data read command input to the sense amplifier. (11) The memory device according to (10), wherein the read circuit has the same configuration as the sense amplifier. (12) The memory device according to any one of (1) to (11), wherein the word selection circuit reselects the word line based on a calculation result by the calculation unit. (13) A storage device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells, each column storing coded data coded based on a column address, are arranged; word lines connecting the memory cells to each row; bit lines connecting the memory cells to each column; sub-bit lines connecting the data cells to each column; a column selection circuit selecting the bit lines and the sub-bit lines based on the column address; a read circuit reading the coded data stored in the data memory; and an arithmetic unit outputting a result of an operation between the coded data read based on the selection of the sub-bit lines and the column address. (14) The storage device according to (13), wherein the data cells comprise data lines that set the sub-bit lines to an open or short state. (15) The storage device according to (14), wherein the data memory comprises the same number of data cells for each row of the memory cell array as the number of columns of the memory cell array. (16) The column selection circuit comprises a switch for each column that connects the selected sub-bit line to the read circuit. (17) The memory device according to any one of (14) to (16), wherein the column selection circuit is caused to reselect the bit lines and the sub-bit lines based on the calculation result by the calculation unit.(18) A memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells storing encoded data encoded based on an address are arranged in rows and columns; word lines connecting the memory cells and the data cells in each row; bit lines connecting the memory cells in each column; sub-bit lines connecting the data cells in each column; a word selection circuit that selects the word line based on a specified row address; a column selection circuit that selects the bit line and the sub-bit line based on a specified column address; a read circuit that reads the encoded data stored in the data memory; and an arithmetic unit that outputs a result of an operation between the coded data read based on the selection of the word line and the sub-bit line and the address. (19) The memory device according to (18), in which the arithmetic unit separately outputs a result of an operation based on the row address and a result of an operation based on the column address. (20) The memory device according to (18), in which the arithmetic unit outputs a result of an operation combining the row address and the column address.

[0238] 101 Memory cell array 102 Row selection circuit 103 Column selection circuit 104 Sense amplifier 105 Row address latch circuit 106 Row selection command issuing circuit 107 Column address latch circuit 108 Data output command issuing circuit MC Memory cell BL Bit line WL Word line SL Source line 121, 122 Switch 111 Data memory 112 Read circuit 113 Decision circuit 123 Resistor 124 Buffer 125 XOR circuit DC Data cell PBL Sub-bit line PSL Sub-source line

Claims

1. A memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells are arranged in rows, each row storing coded data coded based on a row address; word lines connecting the memory cells and the data cells in each row; bit lines connecting the memory cells in each column; a word selection circuit that selects the word line based on the row address; a read circuit that reads the coded data stored in the data memory; and an arithmetic unit that outputs the result of an operation between the coded data read based on the selection of the word line and the row address.

2. The memory device according to claim 1, further comprising sub-bit lines connected to the data cells, wherein the read circuit inputs the encoded data to the operation unit based on a potential transmitted to the sub-bit lines via the data cells.

3. The memory device according to claim 1, wherein the data cell comprises a transistor that is set open or shorted with respect to the read circuit, or a memory element that is conductive or insulated with respect to the read circuit.

4. The memory device according to claim 1, wherein said arithmetic unit comprises a combinational circuit to which said row address and said encoded data are input.

5. The memory device according to claim 1, wherein said arithmetic unit comprises an exclusive OR circuit to which said row address and said encoded data are input.

6. The memory device according to claim 1, wherein the encoded data is a parity bit of a row address assigned to the word line.

7. The storage device according to claim 1, wherein the data memories and the readout circuits are provided for a plurality of columns.

8. The storage device according to claim 1, wherein the arithmetic unit includes an ECC (Error Correction Code) circuit.

9. The memory device according to claim 1, wherein the memory cell comprises: a transistor having a gate connected to the word line; and a memory element connected in series to the transistor.

10. The memory device according to claim 1, further comprising a sense amplifier that determines the data stored in the memory cell based on the potential of the bit line, and the read circuit reads the coded data from the data memory based on a data read command input to the sense amplifier.

11. The memory device according to claim 10, wherein the read circuit has the same configuration as the sense amplifier.

12. The memory device according to claim 1, wherein said word selection circuit is caused to reselect said word line based on the result of the operation by said operation unit.

13. A memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells, each column containing coded data coded based on a column address, are arranged; word lines connecting the memory cells row by row; bit lines connecting the memory cells column by column; sub-bit lines connecting the data cells column by column; a column selection circuit that selects the bit lines and sub-bit lines based on the column address; a read circuit that reads out the coded data stored in the data memory; and an arithmetic unit that outputs the result of an operation between the coded data read based on the selection of the sub-bit lines and the column address.

14. The memory device according to claim 13, wherein the data cell includes a data line that sets the sub-bit line to an open or short state.

15. The storage device according to claim 14, wherein said data memory comprises the data cells for each row of said memory cell array, the number of which corresponds to the number of columns of said memory cell array.

16. The memory device according to claim 14, wherein the column selection circuit includes a switch for each of the columns that connects the selected sub-bit line to the read circuit.

17. The memory device according to claim 14, wherein said column selection circuit is caused to reselect said bit lines and said sub-bit lines based on the result of the operation by said operation unit.

18. A memory device comprising: a memory cell array in which memory cells are arranged in a matrix in the row and column directions; a data memory in which data cells in which coded data coded based on an address are stored are arranged in rows and columns; word lines connecting the memory cells and the data cells to each row; bit lines connecting the memory cells to each column; sub-bit lines connecting the data cells to each column; a word selection circuit selecting the word lines based on a specified row address; a column selection circuit selecting the bit lines and the sub-bit lines based on a specified column address; a read circuit reading the coded data stored in the data memory; and an arithmetic unit outputting a result of an operation between the coded data read based on the selection of the word lines and the sub-bit lines and the address.

19. The memory device according to claim 18, wherein the arithmetic unit outputs the result of the arithmetic operation based on the row address and the result of the arithmetic operation based on the column address separately.

20. The storage device according to claim 18, wherein the calculation unit outputs a calculation result obtained by combining the row address and the column address.

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