Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention includes: a first delay circuit which generates a third signal and a fourth signal by delaying, by a first period, a first signal having a low level at a first voltage and a second signal that is an inversion signal of the first signal; a first current supply unit which includes a first current supply terminal in which current supply capacity is switched according to the third signal and a second current supply terminal in which current supply capacity is switched according to the fourth signal; and a first voltage conversion unit which outputs either or both of a first voltage conversion signal and a second voltage conversion signal obtained by level-shifting the low levels of the first signal and the second signal from the first voltage to a third voltage.

Description

Semiconductor Devices

[0001] TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Conventionally, level shifters that output signals with waveforms similar to those of input signals but different voltage values ​​have been used in various applications. An example of an application in which level shifters are used is a switching regulator in which a control circuit operates on a power supply voltage of, for example, 0V-5V, and a high-side pre-driver drive circuit that drives the gate of a high-side switch transistor operates on a power supply voltage of, for example, 15V-20V. Because the control circuit and the high-side pre-driver drive circuit operate on different operating voltages, a level shifter is used to transmit signals between the control circuit and the high-side pre-driver drive circuit. Specifically, a step-up level shifter is used to level-shift the voltage of a control signal to the power supply voltage of the high-side pre-driver drive circuit. Furthermore, a step-down level shifter is used to level-shift the voltage of an output signal from the high-side pre-driver drive circuit to the power supply voltage of the control circuit.

[0003] JP 2024-30334 Public Relations

[0004] [Summary] Consider the case where the high-side switch transistor of a switching regulator is an n-channel MOS transistor. In order to efficiently drive the high-side switch transistor, it is useful to set the low level of the gate voltage of the high-side switch transistor to the voltage of the output terminal of the switching regulator. The high level of the gate voltage is set to the voltage at the output terminal plus 5V, for example, as the voltage at which the high-side switch transistor turns on.

[0005] A level shifter used between the control circuit and the drive circuit of the high-side pre-driver uses the voltage of the output terminal as the low-level power supply voltage, and uses a voltage obtained by adding 5V or the like to the voltage of the output terminal as the high-level power supply voltage. However, the voltage of the output terminal changes when the high-side or low-side switch transistor turns on or when a load current flows. In particular, when the voltage of the output terminal drops, the power supply voltage used by the level shifter drops, slowing down the state transition speed of the level shifter, which causes the output signal of the high-side pre-driver to fail to operate at the appropriate timing.

[0006] In view of the above-mentioned problems discovered by the inventors of the present disclosure, an object of the present disclosure is to provide a semiconductor device including a level shifter that can perform high-speed level shifting even when the power supply voltage used by the level shifter is low.

[0007] A semiconductor device according to one aspect of the present disclosure includes a first delay circuit, a first current supply unit, and a first voltage conversion unit. The first delay circuit generates a third signal and a fourth signal by delaying a first signal, the low level of which is a first voltage, and a second signal, the second signal being an inverted version of the first signal, by a first period. The first current supply unit includes a first current supply terminal whose current supply capacity is switched in response to the third signal and a second current supply terminal whose current supply capacity is switched in response to the fourth signal. The first voltage conversion unit is connected to a second power supply that supplies a second voltage lower than the first voltage, and outputs one or both of a first voltage-converted signal and a second voltage-converted signal obtained by level-shifting the low levels of the first signal and the second signal from the first voltage to the second voltage. The first voltage conversion unit receives current from the first current supply unit and uses it to generate the high levels of the first voltage-converted signal and the second voltage-converted signal.

[0008] A semiconductor device according to another aspect of the present disclosure includes a first delay circuit, a first current supply unit, and a first voltage conversion unit. The first delay circuit generates a third signal and a fourth signal by delaying a first signal, the high level of which is a first voltage, and a second signal, the second signal being an inverted version of the first signal, by a first period. The first current supply unit includes a first current supply terminal whose current supply capacity is switched in response to the third signal and a second current supply terminal whose current supply capacity is switched in response to the fourth signal. The first voltage conversion unit is connected to a second power supply that supplies a second voltage higher than the first voltage, and outputs one or both of a first voltage-converted signal and a second voltage-converted signal obtained by level-shifting the high levels of the first signal and the second signal from the first voltage to the second voltage. The first voltage conversion unit receives current from the first current supply unit and uses it to generate the low levels of the first voltage-converted signal and the second voltage-converted signal.

[0009] FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment. FIG. 2 is a configuration diagram of a high-side pre-driver of the semiconductor device according to the first embodiment. FIG. 3 is a configuration diagram of a step-down level shifter of the semiconductor device according to the first embodiment. FIG. 4 is a configuration diagram of the step-down level shifter of the semiconductor device according to the first embodiment, showing the configurations of the first current supply unit, the first voltage conversion unit, and the second voltage conversion unit of FIG. 3. FIG. 5 is a configuration diagram of a fifth power supply generation circuit of the semiconductor device according to the first embodiment. FIG. 6 is a configuration diagram of a first delay circuit of the semiconductor device according to the first embodiment. FIG. 7 is a configuration diagram of a first individual delay circuit and a second individual delay circuit of the semiconductor device according to the first embodiment. FIG. 8 is an operation waveform diagram of the semiconductor device according to the first embodiment. FIG. 9 is a configuration diagram of a step-up level shifter of the semiconductor device according to the second embodiment. FIG. 10 is a configuration diagram of a step-up level shifter of the semiconductor device according to the second embodiment, showing the configurations of the first current supply unit, the first voltage conversion unit, and the second voltage conversion unit of FIG. 9. FIG. 11 is a configuration diagram of a fifth power supply generation circuit in the semiconductor device according to the second embodiment. Fig. 12 is a configuration diagram of a first delay circuit in a semiconductor device according to a second embodiment. Fig. 13 is a configuration diagram of a first individual delay circuit and a second individual delay circuit in a semiconductor device according to the second embodiment. Fig. 14 is an operation waveform diagram of a semiconductor device according to the second embodiment. Fig. 15 is a configuration diagram of a step-down level shifter in a semiconductor device according to a third embodiment. Fig. 16 is a configuration diagram of a step-up level shifter in a semiconductor device according to a fourth embodiment.

[0010] [Detailed Description] The embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and the description thereof will be omitted. The drawings are schematic.

[0011] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of each component part. Various modifications can be made to these embodiments within the scope of the claims.

[0012] First Embodiment (Configuration of Semiconductor Device) Fig. 1 is a configuration diagram of a semiconductor device 400 according to a first embodiment. The semiconductor device 400 shown in Fig. 1 is a switching regulator.

[0013] The switching regulator 400 includes a high-side switch transistor 401 , a low-side switch transistor 402 , a high-side pre-driver 403 , a low-side pre-driver 404 , a control circuit 405 , and a boost circuit 406 .

[0014] The switching regulator 400 includes an external power supply terminal VPWR, an output terminal VOUT, and an output voltage detection terminal VOSNS. The high-side switch transistor 401 is an n-channel MOS transistor. The high-side switch transistor 401 has a source connected to the output terminal VOUT, a drain connected to the external power supply terminal VPWR, a gate connected to a high-side pre-driver 403, and a high-side drive signal HG input to its gate. The low-side switch transistor 402 is an n-channel MOS transistor. The source is connected to a second power supply GND, a drain connected to the output terminal VOUT, a gate connected to a low-side pre-driver 404, and a low-side drive signal LG input to its gate.

[0015] The high-side pre-driver 403 receives the voltage output to the output terminal VOUT and receives power from the second power supply GND, the third power supply VOUT+5V, and the fourth power supply VCC. The high-side pre-driver 403 outputs a high-side drive signal HG and a high-side feedback signal HGFB in response to a high-side control signal HGCTRL. The second power supply GND and the fourth power supply VCC are constant voltages. The low level of the high-side drive signal HG corresponds to the voltage of the output terminal VOUT, and the high level corresponds to the voltage of the third power supply VOUT+5V. When the high-side drive signal HG is at a low level, the high-side feedback signal HGFB becomes a low level, indicating that the high-side switch transistor 401 is turned off. When the high-side feedback signal HGFB is at a low level, the low-side pre-driver 404 outputs a low-side drive signal LG in response to a low-side control signal LGCTRL.

[0016] The control circuit 405 receives power from the second power supply GND and the fourth power supply VCC. When an enable signal EN is asserted, the control circuit 405 outputs a high-side control signal HGCTRL and a low-side control signal LGCTRL in accordance with the voltage at the output terminal VOUT and the voltage at the output voltage detection terminal VOSNS. The enable signal EN is asserted, for example, when a circuit (not shown) detects that the voltage at the external power supply terminal VPWR has risen to or exceeded a predetermined voltage. Alternatively, the enable signal EN is asserted in accordance with, for example, an operating mode set externally to the switching regulator 400. The control circuit 405 sets the high-side control signal HGCTRL to a high level when the voltage at the output voltage detection terminal VOSNS is lower than the predetermined voltage, and sets the low-side control signal LGCTRL to a high level when the voltage at the output voltage detection terminal VOSNS is higher than the predetermined voltage. When the voltage of the output terminal VOUT reaches a predetermined voltage, the control circuit 405 sets the high-side control signal HGCTRL and the low-side control signal LGCTRL to low level. The low level of the high-side control signal HGCTRL and the low-side control signal LGCTRL is the voltage of the second power supply GND, and the high level is the voltage of the fourth power supply VCC.

[0017] The boost circuit 406 receives the voltage output to the output terminal VOUT and generates a third power supply VOUT+5V. The voltage of the third power supply VOUT+5V is higher than the voltage of the output terminal VOUT by, for example, 5V, and is generated to follow the voltage of the output terminal VOUT. The boost circuit 406 may be, for example, a charge pump boost circuit.

[0018] Generally, an inductor 407 having an inductance L and a capacitor 408 having a capacitance C are used outside the switching regulator 400 to smooth the voltage at the output terminal VOUT. One end of the inductor 407 is connected to the output terminal VOUT, and the other end is connected to an output node VO. One electrode of the capacitor 408 is connected to the output node VO, and the other electrode is connected to the second power supply GND. The voltage at the output terminal VOUT is smoothed by the inductor 407 and the capacitor 408 and transmitted to the output node VO. The output node VO is connected to an output voltage detection terminal VOSNS, and the voltage at the output node VO is input to a control circuit 405 inside the switching regulator 400.

[0019] The switching regulator 400 controls the on / off of the high-side switch transistor 401 and the low-side switch transistor 402 according to the detected voltage of the output terminal VOUT and the detected voltage of the output node VO, thereby maintaining the voltage of the output node VO constant.

[0020] The low level of the high-side control signal HGCTRL output from the control circuit 405 is the voltage of the second power supply GND, and the high level is the voltage of the fourth power supply VCC. On the other hand, the low level of the high-side drive signal HG is the voltage of the output terminal VOUT, and the high level is the voltage of the third power supply VOUT+5V. The high-side pre-driver 403 uses a level shifter that converts a signal whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC into a signal whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT+5V.

[0021] 2 is a configuration diagram of a high-side pre-driver 403 of a semiconductor device according to an embodiment. The high-side pre-driver 403 includes a step-down level shifter 301, a step-up level shifter 302, a drive circuit 303, and inverters 304, 305, 306, and 307. The high-side control signal HGCTRL, whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC, is inverted by an inverter 307 to become a high-side control inversion signal HGCTRLB. The high-side control inversion signal HGCTRLB is converted by a step-up level shifter 302 to a signal whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT+5V, to become a first high-side drive inversion original signal HGPB. The first high-side drive inversion original signal HGPB is inverted by an inverter 306 to become a high-side drive original signal HGP. The high potential side drive original signal HGP drives the drive circuit 303, which then outputs the high potential side drive signal HG.

[0022] The high potential side drive original signal HGP is inverted by an inverter 305 to become a second high potential side drive inverted original signal HGP2B. The second high potential side drive inverted original signal HGP2B is level shifted by a step-down level shifter 301 to become a high potential side feedback inverted signal HGFBB. The second high potential side drive inverted original signal HGP2B is converted from a signal whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT+5V to a signal whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC. The high potential side feedback inverted signal HGFBB is inverted by an inverter 304 to become a high potential side feedback signal HGFB.

[0023] 1 , when the high-side drive signal HG is at a high level, the high-side switch transistor 401 turns on, raising the voltage at the output terminal VOUT to the voltage at the external power supply terminal VPWR. When the high-side feedback signal HGFB is at a high level, the low-side pre-driver 404 sets the low-side drive signal LG to a low level to prevent the high-side switch transistor 401 and the low-side switch transistor 402 from turning on simultaneously. When the high-side feedback signal HGFB is at a low level, the low-side pre-driver 404 generates the low-side drive signal LG in response to the low-side control signal LGCTRL.

[0024] FIG. 3 is a configuration diagram of a step-down level shifter 301 of the semiconductor device according to the first embodiment.

[0025] The step-down level shifter 301 includes a first delay circuit 15a, a first current supply unit 16a, a first voltage conversion unit 17a, a second voltage conversion unit 18a, and inverters 19a and 20a. The step-down level shifter 301 receives a level shifter input signal LSINa whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT+5V. The step-down level shifter 301 outputs a level shifter output signal LSOUTa whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC.

[0026] The level shifter input signal LSINa is inverted by an inverter 19a to become a second signal IN2a. The second signal IN2a is inverted by an inverter 20a to become a first signal INa. The second signal IN2a has polarity that is the inverse of that of the first signal INa. The first signal INa and the second signal IN2a are input to a first delay circuit 15a and a first voltage conversion unit 17a. The first signal INa and the second signal IN2a are delayed by the first delay circuit 15a to generate a third signal INDLYBa and a fourth signal IN2DLYBa. The third signal INDLYBa and the fourth signal IN2DLYBa are input to a first current supply unit 16a.

[0027] The first current supply unit 16a has a first current supply terminal 35a and a second current supply terminal 36a, and supplies current to the first voltage conversion unit 17a via the first current supply terminal 35a and the second current supply terminal 36a. The first current supply unit 16a switches the amount of current supplied to the first voltage conversion unit 17a in response to the third signal INDLYBa and the fourth signal IN2DLYBa. The amount of current supplied to the first voltage conversion unit 17a switches between a relatively large inrush current required to quickly transition the state of the first voltage conversion unit 17a and a relatively small bias current required to maintain the state of the first voltage conversion unit 17a.

[0028] The first voltage conversion unit 17a level-shifts the low levels of the first signal INa and the second signal IN2a from the voltage of the output terminal VOUT to the voltage of the second power supply GND, and outputs a first voltage-converted signal 39a and a second voltage-converted signal 40a. The first voltage conversion unit 17a generates a sixth voltage, which is the high level of the first voltage-converted signal 39a and the second voltage-converted signal 40a, using the current supplied from the first current supply unit 16a via the first current supply terminal 35a and the second current supply terminal 36a.

[0029] The second voltage conversion unit 18a level-shifts the high level of the second voltage conversion signal 40a from the sixth voltage to the voltage of the fourth power supply VCC, and outputs a level shifter output signal LSOUTa whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC.

[0030] 3 operates as follows as a whole. The step-down level shifter 301 of the semiconductor device according to the first embodiment shown in FIG. 3 converts the voltage of a level shifter input signal LSINa, whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT+5V. The step-down level shifter 301 outputs a level shifter output signal LSOUTa, whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC.

[0031] FIG. 4 is a configuration diagram of a step-down level shifter 301 showing the configurations of the first current supply unit 16a, the first voltage conversion unit 17a, and the second voltage conversion unit 18a of FIG.

[0032] 4 includes a first constant current transistor 5a and a second constant current transistor 6a, each having a source connected to the third power supply VOUT+5V and a gate connected to the fifth power supply VGa. The first constant current transistor 5a and the second constant current transistor 6a are p-channel MOS transistors with a first conductivity type channel. In the first embodiment, the first conductivity type is p-type and the second conductivity type is n-type. The drain of the first constant current transistor 5a is connected to a first current supply terminal 35a, and the drain of the second constant current transistor 6a is connected to a second current supply terminal 36a.

[0033] FIG. 5 is a configuration diagram of a fifth power supply generating circuit that generates the fifth power supply VGa in the semiconductor device according to the first embodiment shown in FIG. 4 . The first resistor R1a has one end connected to the output terminal VOUT and the other end connected to the drain of the fifth power supply generating transistor 63a. This resistor R1a determines the amount of constant bias current supplied to the first voltage conversion unit 17a by the first current supply unit 16a shown in FIG. 4 . The amount of bias current is, for example, 2.5 μA. The fifth power supply generating transistor 63a is a transistor having substantially the same or similar size as the first constant current transistor 5a and the second constant current transistor 6a shown in FIG. 4 , and is diode-connected with its drain and gate connected. The fifth power supply generating transistor 63a is a p-channel MOS transistor with a first conductivity type channel. The fifth power supply generating transistor 63a has a source connected to the third power supply VOUT+5V, a drain and a gate connected to the first resistor R1a, and a gate-source voltage that is uniquely determined by passing a constant current determined by the first resistor R1a. The gate voltage of the fifth power supply generating transistor 63a is output as the fifth power supply VGa.

[0034] 4, the first constant current transistor 5a and the second constant current transistor 6a have substantially the same or similar size as the fifth power supply generating transistor 63a, and have their gates connected to the fifth power supply VGa. The first constant current transistor 5a and the second constant current transistor 6a form a current mirror configuration with the fifth power supply generating transistor 63a, and pass a constant current that is the same as or similar to that of the fifth power supply generating transistor 63a to the first current supply terminal 35a and the second current supply terminal 36a.

[0035] The first current supply unit 16a further includes a first switch transistor 7a and a second switch transistor 8a, the sources of which are connected to the third power supply VOUT+5V. The first switch transistor 7a and the second switch transistor 8a are p-channel MOS transistors with a first conductivity type channel. The first switch transistor 7a receives a third signal INDLYBa at its gate and has its drain connected to the first current supply terminal 35a. When the third signal INDLYBa is at a high level, the first switch transistor 7a is turned off. When the third signal INDLYBa is at a low level, the first switch transistor 7a is turned on and passes a current larger than the current of the first constant current transistor 5a to the first current supply terminal 35a. In other words, the current supplied by the first current supply unit 16a via the first current supply terminal 35a becomes relatively small when the third signal INDLYBa is at a high level, and becomes relatively large when the third signal INDLYBa is at a low level.

[0036] The second switch transistor 8a has a gate to which the fourth signal IN2DLYBa is input, and a drain to which the second current supply terminal 36a is connected. When the fourth signal IN2DLYBa is at a high level, the second switch transistor 8a is turned off. When the fourth signal IN2DLYBa is at a low level, the second switch transistor 8a is turned on, causing a current greater than the current of the second constant current transistor 6a to flow to the second current supply terminal 36a. In other words, the current supplied by the first current supply unit 16a via the second current supply terminal 36a is relatively small when the fourth signal IN2DLYBa is at a high level, and is relatively large when the fourth signal IN2DLYBa is at a low level.

[0037] The first voltage conversion unit 17a shown in FIG. 4 includes a first transistor 1a and a second transistor 2a. The first transistor 1a and the second transistor 2a are p-channel MOS transistors with a first conductivity type channel. The first transistor 1a has a source connected to a first current supply terminal 35a and a gate to which a first signal INa is input. The second transistor 2a has a source connected to a second current supply terminal 36a and a gate to which a second signal IN2a is input. When the first signal INa is at a low level, the first transistor 1a is turned on and causes a current to flow from the first current supply terminal 35a. When the second signal IN2a is at a low level, the second transistor 2a is turned on and causes a current to flow from the second current supply terminal 36a.

[0038] The third signal INDLYBa is a signal obtained by delaying and inverting the first signal INa by the first delay circuit 15a. That is, when the first signal INa goes low and the first transistor 1a turns on, the third signal INDLYBa is low, and the first switch transistor 7a turns on. The amount of current supplied to the first voltage conversion unit 17a via the first current supply terminal 35a increases by the amount of on-current of the first switch transistor 7a. By increasing the amount of current supplied to the first voltage conversion unit 17a via the first current supply terminal 35a, the voltage of the first current supply terminal 35a can be maintained so as not to drop below the voltage of the third power supply VOUT+5V used by the level shifter. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17a, the first voltage conversion unit 17a can perform state transitions at high speed.

[0039] After a first period has elapsed since the first signal INa went low and the first transistor 1a was turned on, the third signal INDLYBa went high and the first switch transistor 7a was turned off. The amount of current supplied via the first current supply terminal 35a is reduced to the amount of current of the first constant current transistor 5a. By reducing the amount of current supplied to the first voltage conversion unit 17a, the current consumption of the step-down level shifter 301 can be kept small.

[0040] Similarly, the fourth signal IN2DLYBa is a signal obtained by delaying and inverting the second signal IN2a by the first delay circuit 15a. That is, when the second signal IN2a goes low and the second transistor 2a turns on, the fourth signal IN2DLYBa is low, and the second switch transistor 8a turns on. The amount of current supplied to the first voltage conversion unit 17a via the second current supply terminal 36a increases by the amount of on-current of the second switch transistor 8a. By increasing the amount of current supplied to the first voltage conversion unit 17a via the second current supply terminal 36a, the voltage of the second current supply terminal 36a can be maintained so as not to drop below the voltage of the third power supply VOUT+5V used by the level shifter. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17a, the first voltage conversion unit 17a can perform state transitions at high speed.

[0041] After the second signal IN2a goes low and the second transistor 2a turns on, the fourth signal IN2DLYBa goes high and the second switch transistor 8a turns off after a first period has elapsed. The amount of current supplied via the second current supply terminal 36a is reduced to the amount of current of the second constant current transistor 6a. By reducing the amount of current supplied to the first voltage conversion unit 17a, the current consumption of the step-down level shifter 301 can be kept small.

[0042] The first voltage conversion unit 17a further includes a third transistor 3a and a fourth transistor 4a, each having a source connected to the second power supply GND. The third transistor 3a and the fourth transistor 4a are n-channel MOS transistors with a channel of the second conductivity type. The drain 37a of the third transistor 3a is connected to the drain of the first transistor 1a, and the gate is connected to the drain 38a of the fourth transistor 4a. The drain 38a of the fourth transistor 4a is connected to the drain of the second transistor 2a, and the gate is connected to the drain 37a of the third transistor 3a.

[0043] When the first signal INa is at a low level and the second signal IN2a is at a high level, the first transistor 1a turns on and a large current flows via the first current supply terminal 35a, thereby raising the voltage of the drain 37a of the third transistor 3a. The voltage of the drain 37a of the third transistor 3a is raised, turning on the fourth transistor 4a. Since the second transistor 2a is off, the voltage of the drain 38a of the fourth transistor 4a and the gate of the third transistor 3a is lowered to the voltage of the second power supply GND, turning off the third transistor 3a.

[0044] Conversely, when the first signal INa is at a high level and the second signal IN2a is at a low level, the second transistor 2a turns on and a large current flows via the second current supply terminal 36a, thereby raising the voltage of the drain 38a of the fourth transistor 4a. The raising of the voltage of the drain 38a of the fourth transistor 4a turns on the third transistor 3a. Since the first transistor 1a is off, the voltages of the drain 37a of the third transistor 3a and the gate of the fourth transistor 4a are lowered to the voltage of the second power supply GND, turning off the fourth transistor 4a.

[0045] The first voltage conversion unit 17a further includes a first voltage generation circuit 13a and a second voltage generation circuit 14a. The first voltage generation circuit 13a includes diode-connected transistors 13Aa and 13Ba connected in series, with their gates and drains connected. The diode-connected transistors 13Aa and 13Ba are n-channel MOS transistors with second conductivity types. The drain of the high-side diode-connected transistor 13Aa is connected to the drain 37a of the third transistor 3a, and the source of the low-side diode-connected transistor 13Ba is connected to the second power supply GND. The first voltage generation circuit 13a passes the output current from the first transistor 1a to the second power supply GND, generates a constant voltage based on the thresholds of the diode-connected transistors 13Aa and 13Ba, and transmits it to the drain 37a of the third transistor 3a. A first voltage conversion signal 39a is output from the drain 37a of the third transistor 3a. The high level of the first voltage conversion signal 39a is set to a sixth voltage by the voltage of the first current supply terminal 35a and the output voltage of the first voltage generating circuit 13a.

[0046] Similarly, the second voltage generating circuit 14a has a configuration in which diode-connected transistors 14Aa and 14Ba are connected in series, with their gates and drains connected together. The diode-connected transistors 14Aa and 14Ba are n-channel MOS transistors with second conductivity types. The drain of the high-side diode-connected transistor 14Aa is connected to the drain 38a of the fourth transistor 4a, and the source of the low-side diode-connected transistor 14Ba is connected to the second power supply GND. The second voltage generating circuit 14a passes the output current from the second transistor 2a to the second power supply GND, generates a constant voltage based on the thresholds of the diode-connected transistors 14Aa and 14Ba, and transmits it to the drain 38a of the fourth transistor 4a. A second voltage conversion signal 40a is output from the drain 38a of the fourth transistor 4a. The high level of the second voltage conversion signal 40a is set to a sixth voltage by the voltage of the second current supply terminal 36a and the output voltage of the second voltage generating circuit 14a.

[0047] The first voltage conversion unit 17a sets the low level of the first converted voltage signal 39a and the second converted voltage signal 40a to the voltage of the second power supply GND, and sets the high level to the sixth voltage.

[0048] 4 includes a fifth transistor 9a and a sixth transistor 10a whose sources are connected to the second power supply GND, and a seventh transistor 11a and an eighth transistor 12a whose sources are connected to the fourth power supply VCC. The fifth transistor 9a and the sixth transistor 10a are n-channel MOS transistors with a second conductivity type channel. The seventh transistor 11a and the eighth transistor 12a are MOS transistors with a first conductivity type p-channel channel. The second voltage conversion unit 18a further includes an inverter 21a.

[0049] A first voltage-converted signal 39a is input to the gate of the fifth transistor 9a, and a second voltage-converted signal 40a is input to the gate of the sixth transistor 10a. The gate of the seventh transistor 11a is connected to the drain 42a of the eighth transistor 12a, and the drain 41a of the seventh transistor 11a is connected to the drain of the fifth transistor 9a. The gate of the eighth transistor 12a is connected to the drain 41a of the seventh transistor 11a, and the drain 42a of the eighth transistor 12a is connected to the drain of the sixth transistor 10a. A level shifter inverted output signal LSOUTBa, which is a fourth voltage-converted signal, is output from the drain 42a of the eighth transistor 12a. The level shifter inverted output signal LSOUTBa is inverted by an inverter 21a to become a level shifter output signal LSOUTa, which is a third voltage-converted signal. The level shifter output signal LSOUTa, which is the third voltage conversion signal, may be output from the drain 41a of the seventh transistor 11a.

[0050] When the first voltage conversion signal 39a is at a high level and the second voltage conversion signal 40a is at a low level, the fifth transistor 9a is turned on, the gate of the eighth transistor 12a is pulled down, and the eighth transistor 12a is turned on. Since the sixth transistor 10a is off, the eighth transistor 12a is turned on, and the voltages of the drain 42a of the eighth transistor 12a and the gate of the seventh transistor 11a are pulled up to the voltage of the fourth power supply VCC. The level shifter inverted output signal LSOUTBa is also pulled up to the voltage of the fourth power supply VCC, and the level shifter output signal LSOUTa becomes the voltage of the second power supply GND. The voltage of the gate of the seventh transistor 11a is pulled up to the voltage of the fourth power supply VCC, and the seventh transistor 11a is turned off, and the voltage of the drain 41a of the seventh transistor 11a is pulled down to the voltage of the second power supply GND by the fifth transistor 9a.

[0051] Conversely, when the first voltage conversion signal 39a is low and the second voltage conversion signal 40a is high, the sixth transistor 10a is turned on, the voltage of the gate of the seventh transistor 11a is pulled down, and the seventh transistor 11a is turned on. Since the fifth transistor 9a is off, the seventh transistor 11a is turned on, and the voltage of the drain 41a of the seventh transistor 11a and the gate of the eighth transistor 12a is pulled up to the voltage of the fourth power supply VCC. The gate voltage of the eighth transistor 12a is pulled up to the voltage of the fourth power supply VCC, and the voltage of the drain 42a of the eighth transistor 12a is pulled down to the voltage of the second power supply GND by the sixth transistor 10a. The level shifter inverted output signal LSOUTBa is also pulled down to the voltage of the second power supply GND, and the level shifter output signal LSOUTa becomes the voltage of the fourth power supply VCC.

[0052] 6 is a configuration diagram of a first delay circuit 15a of the semiconductor device according to the first embodiment. The first delay circuit 15a includes a first individual delay circuit 151a and a second individual delay circuit 152a. The first individual delay circuit 151a delays and inverts the first signal INa by a first period to generate a third signal INDLYBa. The second individual delay circuit 152a delays and inverts the second signal IN2a by a first period to generate a fourth signal IN2DLYBa.

[0053] 7 is a configuration diagram of the first individual delay circuit 151a and the second individual delay circuit 152a of the semiconductor device according to the first embodiment. Since the configuration diagrams of the first individual delay circuit 151a and the second individual delay circuit 152a are the same, the first individual delay circuit 151a will be described as a representative.

[0054] The first individual delay circuit 151a includes an inverter 22a, a first delay transistor 51a, a second delay transistor 52a, a third delay transistor 53a, and a fourth delay transistor 54a. The first individual delay circuit 151a further includes a fifth delay transistor 59a, a sixth delay transistor 60a, a seventh delay transistor 61a, and an eighth delay transistor 62a, and a delay adjustment circuit 23a. The first individual delay circuit 151a receives the first signal INa as a delay circuit input signal DLYINa and outputs the third signal INDLYBa as a delay circuit inverted output signal DLYOUTBa.

[0055] The first delay transistor 51a and the second delay transistor 52a have sizes substantially identical to or similar to the first transistor 1a and the second transistor 2a of the first voltage conversion unit 17a shown in FIG. 4 . The first delay transistor 51a and the second delay transistor 52a are p-channel MOS transistors with a first conductivity type channel. The sources of the first delay transistor 51a and the second delay transistor 52a are connected to the third power supply VOUT+5V. The third delay transistor 53a and the fourth delay transistor 54a have sizes substantially identical to or similar to the third transistor 3a and the fourth transistor 4a of the first voltage conversion unit 17a shown in FIG. 4 . The third delay transistor 53a and the fourth delay transistor 54a are n-channel MOS transistors with a second conductivity type channel. The sources of the third delay transistor 53a and the fourth delay transistor 54a are connected to the output terminal VOUT.

[0056] A drain 77a of the third delay transistor 53a is connected to the drain of the first delay transistor 51a and the gate of the fourth delay transistor 54a. A drain 78a of the fourth delay transistor 54a is connected to the drain of the second delay transistor 52a and the gate of the third delay transistor 53a. The connections of the first to fourth delay transistors 51a, 52a, 53a, and 54a are the same as the connections of the first to fourth transistors 1a, 2a, 3a, and 4a of the first voltage conversion unit 17a shown in FIG. 4.

[0057] The fifth delay transistor 59a and the sixth delay transistor 60a have sizes substantially identical to or similar to the fifth transistor 9a and the sixth transistor 10a of the second voltage conversion unit 18a shown in FIG. 4 . The fifth delay transistor 59a and the sixth delay transistor 60a are n-channel MOS transistors with a second conductivity type channel. The fifth delay transistor 59a and the sixth delay transistor 60a have sources connected to the output terminal VOUT. The seventh delay transistor 61a and the eighth delay transistor 62a have sizes substantially identical to or similar to the seventh transistor 11a and the eighth transistor 12a of the second voltage conversion unit 18a shown in FIG. 4 . The seventh delay transistor 61a and the eighth delay transistor 62a are p-channel MOS transistors with a first conductivity type channel. The sources of the seventh delay transistor 61a and the eighth delay transistor 62a are connected to the third power supply VOUT+5V.

[0058] The drain 81a of the seventh delay transistor 61a is connected to the drain of the fifth delay transistor 59a and the gate of the eighth delay transistor 62a. The drain 82a of the eighth delay transistor 62a is connected to the drain of the sixth delay transistor 60a and the gate of the seventh delay transistor 61a. The connection relationship between the fifth to eighth delay transistors 59a, 60a, 61a, and 62a is the same as the connection relationship between the fifth to eighth transistors 9a, 10a, 11a, and 12a of the second voltage conversion unit 18a shown in FIG. 4.

[0059] The drain 77a of the third delay transistor 53a is connected to the gate of the fifth delay transistor 59a, and the drain 78a of the fourth delay transistor 54a is connected to the gate of the sixth delay transistor 60a. Meanwhile, the drain 37a of the third transistor 3a in Figure 4 is connected to the gate of the fifth transistor 9a, and the drain 38a of the fourth transistor 4a is connected to the gate of the sixth transistor 10a. The connection relationship of the third to sixth delay transistors 53a, 54a, 59a, and 60a is the same as the connection relationship of the third to sixth transistors 3a, 4a, 9a, and 10a in Figure 4.

[0060] The first individual delay circuit 151a includes transistors that are substantially the same as or similar in size and connection to the transistors that make up the first voltage conversion unit 17a and the second voltage conversion unit 18a in FIG. 4. The first individual delay circuit 151a can generate a delay time of a first period that includes the time it takes for the first voltage conversion unit 17a and the second voltage conversion unit 18a in FIG. 4 to transition between states in response to an input signal. The delay adjustment circuit 23a adjusts the delay time so that the first individual delay circuit 151a can generate a delay time that includes the time it takes for the first voltage conversion unit 17a and the second voltage conversion unit 18a in FIG. 4 to transition between states, even if there is variation in elements. The first individual delay circuit 151a is composed of transistors and has a smaller area than delay circuits that use resistors or capacitors.

[0061] The step-down level shifter 301 of the semiconductor device according to the first embodiment shown in Figure 4 operates as follows as a whole. The step-down level shifter 301 converts the voltage of a level shifter input signal LSINa, whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the third power supply VOUT + 5V. The step-down level shifter 301 outputs a level shifter output signal LSOUTa, whose low level is the voltage of the second power supply GND and whose high level is the voltage of the fourth power supply VCC. The level shifter input signal LSINa and the level shifter output signal LSOUTa are in phase.

[0062] 8 is an operational waveform diagram of the step-down level shifter 301 of the semiconductor device 400. The horizontal axis of FIG. 8 represents time, and the vertical axis represents voltage. In FIG. 8, the third power supply VOUT+5V is indicated by a thin dashed line, the second current supply terminal 36a is indicated by a thick solid line, the second signal IN2a is indicated by a thin dashed line, and the level shifter inverted output signal LSOUTBa is indicated by a thin solid line. Furthermore, the first voltage-converted signal 39a is indicated by a thin two-dot chain line, the second voltage-converted signal 40a is indicated by a thick dashed line, and the fourth signal IN2DLYBa is indicated by a thick two-dot chain line.

[0063] Since the step-down level shifter 301 is applied to the switching regulator of FIG. 1 , the voltage of the output terminal VOUT and the voltage of the third power supply VOUT+5V change depending on the output to the output terminal VOUT of the switching regulator and the load current. FIG. 8 shows an example in which the voltage of the output terminal VOUT is pulled down by the load current between time t0 and time t1. Following the pull-down of the voltage of the output terminal VOUT, the voltage of the third power supply VOUT+5V also drops. At time t1, the second signal IN2a is at a high level, and the fourth signal IN2DLYBa is at a low level. At time t2, the level shifter input signal LSINa (not shown in FIG. 8) goes high, causing the second signal IN2a to go low, and turning on the second transistor 2a in FIG. 4 . Because the first period has not yet elapsed since the second signal IN2a went low, the fourth signal IN2DLYBa is low, the second switch transistor 8a is turned on, and an inrush current flows to the second current supply terminal 36a. By flowing an inrush current to the second current supply terminal 36a, the voltage of the second current supply terminal 36a can be maintained so as not to drop below the voltage of the third power supply VOUT+5V.

[0064] 4 is turned on, the voltage of the second voltage conversion signal 40a is raised. The high level of the second voltage conversion signal 40a is set to a sixth voltage by the voltage of the second current supply terminal 36a and the output voltage of the second voltage generation circuit 14a.

[0065] 4 is turned on, and the level shifter inverted output signal LSOUTBa is pulled down from the voltage of the fourth power supply VCC to the voltage of the second power supply GND, which is low level. When the level shifter inverted output signal LSOUTBa becomes low level, the level shifter output signal LSOUTa (not shown in FIG. 8) becomes the voltage of the fourth power supply VCC, which is high level.

[0066] 4 is turned on when the voltage of the second voltage conversion signal 40a rises and the voltage of its gate is pulled up, and the voltage of the first voltage conversion signal 39a and the gate of the fourth transistor 4a are pulled down to the voltage of the second power supply GND. The fourth transistor 4a is turned off when the voltage of its gate is pulled down to the voltage of the second power supply GND. When the voltage of the first voltage conversion signal 39a is pulled down to the voltage of the second power supply GND, the state transition of the step-down level shifter 301 is completed.

[0067] After a first period has elapsed since the second signal IN2a went low, at time t3, the fourth signal IN2DLYBa goes high, the second switch transistor 8a in FIG. 4 turns off, and the amount of current supplied via the second current supply terminal 36a decreases. As the amount of current supplied via the second current supply terminal 36a decreases to the bias current, the voltage at the second current supply terminal 36a decreases and becomes constant at a voltage that can be maintained by the bias current. By reducing the amount of current supplied to the first voltage conversion unit 17a after the state transition of the step-down level shifter 301 is completed, the current consumption of the step-down level shifter 301 can be kept small.

[0068] The operation of the high-side pre-driver 403 will be described with reference to the configuration diagram of the high-side pre-driver 403 shown in Figure 2. When the high-side control signal HGCTRL goes low, the high-side drive original signal HGP goes low, and the second high-side drive inverted original signal HGP2B goes high. The level shifter input signal LSINa, which is the input to the step-down level shifter 301 shown in Figure 3, goes high, and the level shifter output signal LSOUTa goes high. The high-side feedback inverted signal HGFBB in Figure 2 goes high, and the high-side feedback signal HGFB goes low.

[0069] 1 shows the configuration of the switching regulator 400. When the high-side feedback signal HGFB goes low, the low-side pre-driver 404 changes from a state in which the low-side drive signal LG is fixed at low to a state in which it can generate the low-side drive signal LG in response to the low-side control signal LGCTRL.

[0070] (Effects of the First Embodiment) According to the first embodiment, when the step-down level shifter 301 transitions its state in response to a change in the input signal, the amount of current supplied to the first voltage conversion unit 17a via the first current supply terminal 35a or the second current supply terminal 36a is relatively increased during a first period following the change in the input signal. By increasing the amount of current supplied to the first voltage conversion unit 17a, the voltage of the first current supply terminal 35a or the second current supply terminal 36a can be kept from dropping below the power supply voltage used by the step-up level shifter 302. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17a, the state transition of the first voltage conversion unit 17a becomes faster. By keeping the voltage of the first current supply terminal 35a or the second current supply terminal 36a from dropping, the step-down level shifter 301 can perform high-speed level shifting even when the power supply voltage used by the step-down level shifter 301 is low.

[0071] The step-down level shifter 301 can reduce the current consumption of the step-down level shifter 301 by relatively reducing the amount of current supplied to the first voltage conversion unit 17a after the first period has elapsed since the change in the input signal.

[0072] The first delay circuit 15a includes transistors that are substantially the same as or similar in size and connection to the transistors that make up the first voltage conversion unit 17a and the second voltage conversion unit 18a. The first delay circuit 15a generates a first period, thereby generating a delay time that includes the time it takes for the first voltage conversion unit 17a and the second voltage conversion unit 18a to transition between states. The first delay circuit 15a is composed of transistors, and therefore can occupy a smaller area than a delay circuit that uses resistors or capacitors.

[0073] Second Embodiment (Configuration of Semiconductor Device) FIG. 9 is a diagram showing the configuration of a boost level shifter 302 of a semiconductor device 400 according to a second embodiment.

[0074] The configuration diagram of the high-side pre-driver to which the boost level shifter 302 of the semiconductor device according to the second embodiment is applied is the same as the configuration diagram of the high-side pre-driver 403 of the semiconductor device 400 according to the first embodiment shown in FIG. 2 . Also, the configuration diagram of the semiconductor device to which the high-side pre-driver 403 of the semiconductor device according to the second embodiment is applied is the same as the configuration diagram of the semiconductor device 400 according to the first embodiment shown in FIG. 1 . However, the correspondence between the names and symbols of the power supplies is changed from the first embodiment as follows. In the first embodiment, the second power supply is GND and the third power supply is VOUT+5V, whereas in the second embodiment, the second power supply is VOUT+5V and the third power supply is GND. Also, in the first embodiment, the fourth power supply is VCC, whereas in the second embodiment, the first power supply is VCC.

[0075] 9 includes a first delay circuit 15b, a first current supply unit 16b, a first voltage conversion unit 17b, a second voltage conversion unit 18b, and inverters 19b and 20b. The step-up level shifter 302 receives a level shifter input signal LSINb whose low level is the voltage of the third power supply GND and whose high level is the voltage of the first power supply VCC. The step-up level shifter 302 outputs a level shifter output signal LSOUTb whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the second power supply VOUT+5V.

[0076] The configuration of the step-up level shifter 302 of the semiconductor device according to the second embodiment corresponds to a configuration in which the conductivity types of the connected power supplies and transistor channels are swapped with respect to the configuration of the step-down level shifter 301 of the semiconductor device according to the first embodiment. Explanations of matters similar to those of the step-down level shifter 301 of the semiconductor device according to the first embodiment will be brief or omitted.

[0077] The level shifter input signal LSINb is inverted by an inverter 19b to become a second signal IN2b. The second signal IN2b is inverted by an inverter 20b to become a first signal INb. The second signal IN2b has polarity that is the inverse of that of the first signal INb. The first signal INb and the second signal IN2b are input to a first delay circuit 15b and a first voltage conversion unit 17b. The first signal INb and the second signal IN2b are delayed by the first delay circuit 15b to generate a third signal INDLYBb and a fourth signal IN2DLYBb. The third signal INDLYBb and the fourth signal IN2DLYBb are input to a first current supply unit 16b.

[0078] The first current supply unit 16b has a first current supply terminal 35b and a second current supply terminal 36b, and supplies current to the first voltage conversion unit 17b via the first current supply terminal 35b and the second current supply terminal 36b. The first current supply unit 16b switches the amount of current supplied to the first voltage conversion unit 17b in response to the third signal INDLYBb and the fourth signal IN2DLYBb.

[0079] The first voltage conversion unit 17b level-shifts the high levels of the first signal INb and the second signal IN2b from the voltage of the first power supply VCC to the voltage of the second power supply VOUT+5V, and outputs a first voltage-converted signal 39b and a second voltage-converted signal 40b. The first voltage conversion unit 17b uses the current supplied from the first current supply unit 16b via the first current supply terminal 35b and the second current supply terminal 36b to generate a sixth voltage which is the low level of the first voltage-converted signal 39b and the second voltage-converted signal 40b.

[0080] The second voltage conversion unit 18b converts the low level of the second voltage conversion signal 40b from the sixth voltage to the voltage of the output terminal VOUT, and outputs a level shifter output signal LSOUTb whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the second power supply VOUT + 5V.

[0081] 9 operates as follows as a whole. The step-up level shifter 302 converts the voltage of a level shifter input signal LSINb, whose low level is the voltage of the third power supply GND and whose high level is the voltage of the first power supply VCC. The step-up level shifter 302 outputs a level shifter output signal LSOUTb, whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the second power supply VOUT+5V.

[0082] FIG. 10 is a configuration diagram of a step-up level shifter 302 showing the configurations of the first current supply unit 16b, the first voltage conversion unit 17b, and the second voltage conversion unit 18b of FIG.

[0083] 10 includes a first constant current transistor 5b and a second constant current transistor 6b, each having a source connected to the third power supply GND and a gate to which the fifth power supply VGb is input. The first constant current transistor 5b and the second constant current transistor 6b are n-channel MOS transistors with a first conductivity type channel. In the second embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

[0084] FIG. 11 is a configuration diagram of a fifth power supply generating circuit that generates the fifth power supply VGb of the semiconductor device according to the second embodiment shown in FIG. 10. The first resistor R1b has one end connected to the first power supply VCC and the other end connected to the drain of the fifth power supply generating transistor 63b. This resistor R1b determines the amount of constant bias current supplied to the first voltage conversion unit 17b by the first current supply unit 16b shown in FIG. 10. The amount of bias current is, for example, 2.5 μA. The fifth power supply generating transistor 63b is a transistor having substantially the same or similar size as the first constant current transistor 5b and the second constant current transistor 6b shown in FIG. 10, and is diode-connected with its drain and gate connected. The fifth power supply generating transistor 63b is an n-channel MOS transistor with a first conductivity type channel. The fifth power supply generating transistor 63b has a source connected to the third power supply GND, a drain and a gate connected to the first resistor R1b, and a gate-source voltage that is uniquely determined by passing a constant current determined by the first resistor R1b. The gate voltage of the fifth power supply generating transistor 63b is output as the fifth power supply VGb.

[0085] 10, the first constant current transistor 5b and the second constant current transistor 6b have substantially the same or similar sizes as the fifth power supply generation transistor 63b, and have gates connected to the fifth power supply VGb. The first constant current transistor 5b and the second constant current transistor 6b form a current mirror configuration with the fifth power supply generation transistor 63b, and pass a constant current that is the same as or similar to that of the fifth power supply generation transistor 63b to the first current supply terminal 35b and the second current supply terminal 36b.

[0086] The first current supply unit 16b further includes a first switch transistor 7b and a second switch transistor 8b, each having a source connected to the third power supply GND. The first switch transistor 7b and the second switch transistor 8b are n-channel MOS transistors with a first conductivity type channel. The first switch transistor 7b receives a third signal INDLYBb at its gate and has a drain connected to the first current supply terminal 35b. The current supplied by the first current supply unit 16b via the first current supply terminal 35b is relatively small when the third signal INDLYBb is at a low level and is relatively large when the third signal INDLYBb is at a high level.

[0087] The second switch transistor 8b has a gate to which the fourth signal IN2DLYBb is input and a drain to which the second current supply terminal 36b is connected. The current supplied from the first current supply unit 16b via the second current supply terminal 36b is relatively small when the fourth signal IN2DLYBb is at a low level, and is relatively large when the fourth signal IN2DLYBb is at a high level.

[0088] 10 includes a first transistor 1b and a second transistor 2b. The first transistor 1a and the second transistor 2b are n-channel MOS transistors with a first conductivity type channel. The first transistor 1b has a source connected to a first current supply terminal 35b, and a first signal INb is input to its gate. The second transistor 2b has a source connected to a second current supply terminal 36b, and a second signal IN2b is input to its gate.

[0089] The third signal INDLYBb is a signal obtained by delaying and inverting the first signal INb by the first delay circuit 15b. When the first signal INb goes high and the first transistor 1b turns on, the first switch transistor 7b turns on, and the amount of current supplied to the first voltage conversion unit 17b via the first current supply terminal 35b increases. By increasing the amount of current supplied to the first voltage conversion unit 17b via the first current supply terminal 35b, the voltage of the first current supply terminal 35b can be kept from rising above the voltage of the second power supply GND used by the level shifter. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17b, the first voltage conversion unit 17b can perform state transitions at high speed.

[0090] After the first signal INb goes high and the first transistor 1b turns on, the first switch transistor 7b turns off after a first period has elapsed, and the amount of current supplied via the first current supply terminal 35b decreases to the amount of current from the first constant current transistor 5b. By reducing the amount of current supplied to the first voltage conversion unit 17b, the current consumption of the step-up level shifter 302 can be kept small.

[0091] Similarly, the fourth signal IN2DLYBb is a signal obtained by delaying and inverting the second signal IN2b by the first delay circuit 15b. When the second signal IN2b goes high and the second transistor 2b turns on, the second switch transistor 8b turns on, and the amount of current supplied to the first voltage conversion unit 17b via the second current supply terminal 36b increases. By increasing the amount of current supplied to the first voltage conversion unit 17b via the second current supply terminal 36b, the voltage of the second current supply terminal 36b can be kept from rising above the voltage of the second power supply GND used by the level shifter. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17b, the first voltage conversion unit 17b can perform state transitions at high speed.

[0092] After the second signal IN2b goes high and the second transistor 2b turns on, the second switch transistor 8b turns off after a first period has elapsed, and the amount of current supplied via the second current supply terminal 36b decreases to the amount of current from the second constant current transistor 6b. By reducing the amount of current supplied to the first voltage conversion unit 17b, the current consumption of the step-up level shifter 302 can be kept small.

[0093] The first voltage conversion unit 17b further includes a third transistor 3b and a fourth transistor 4b, each having a source connected to the second power supply VOUT+5V. The third transistor 3b and the fourth transistor 4b are p-channel MOS transistors with a channel of the second conductivity type. A drain 37b of the third transistor 3b is connected to the drain of the first transistor 1b, and a gate is connected to a drain 38b of the fourth transistor 4b. A drain 38b of the fourth transistor 4b is connected to the drain of the second transistor 2b, and a gate is connected to the drain 37b of the third transistor 3b.

[0094] When the first signal INb is at a high level and the second signal IN2b is at a low level, the first transistor 1b turns on and a relatively large current flows through the first current supply terminal 35b, thereby pulling down the voltage at the drain 37b of the third transistor 3b. As the voltage at the drain 37b of the third transistor 3b is pulled down, the fourth transistor 4b turns on. Since the second transistor 2b is off, the voltage at the drain 38b of the fourth transistor 4b and the gate of the third transistor 3b is pulled up to the voltage of the second power supply VOUT+5V, turning off the third transistor 3b.

[0095] Conversely, when the first signal INb is low and the second signal IN2b is high, the second transistor 2b turns on and a large current flows through the second current supply terminal 36b, thereby pulling down the voltage at the drain 38b of the fourth transistor 4b. Pulling down the voltage at the drain 38b of the fourth transistor 4b turns on the third transistor 3b. Since the first transistor 1b is off, the voltage at the drain 37b of the third transistor 3b and the gate of the fourth transistor 4b is pulled up to the voltage of the second power supply VOUT+5V, turning off the fourth transistor 4b.

[0096] The first voltage conversion unit 17b further includes a first voltage generation circuit 13b and a second voltage generation circuit 14b. The first voltage generation circuit 13b has a configuration in which diode-connected transistors 13Ab and 13Bb are connected in series, with their gates and drains connected. The diode-connected transistors 13Ab and 13Bb are p-channel MOS transistors with second conductivity types. The drain of the low-potential-side diode-connected transistor 13Ab is connected to the drain 37b of the third transistor 3b, and the source of the high-potential-side diode-connected transistor 13Bb is connected to the second power supply VOUT+5V. The first voltage generation circuit 13b passes the output current from the first transistor 1b to the second power supply VOUT+5V, generates a constant voltage based on the thresholds of the diode-connected transistors 13Ab and 13Bb, and transmits it to the drain 37b of the third transistor 3b. A first voltage conversion signal 39b is output from the drain 37b of the third transistor 3b. The low level of the first voltage conversion signal 39b is set to a sixth voltage by the voltage of the first current supply terminal 35b and the output voltage of the first voltage generating circuit 13b.

[0097] Similarly, the second voltage generation circuit 14b has a configuration in which diode-connected transistors 14Ab and 14Bb are connected in series, with their gates and drains connected together. The diode-connected transistors 14Ab and 14Bb are p-channel MOS transistors with second conductivity types. The drain of the low-potential-side diode-connected transistor 14Ab is connected to the drain 38b of the fourth transistor 4b, and the source of the high-potential-side diode-connected transistor 14Bb is connected to the second power supply VOUT+5V. The second voltage generation circuit 14b passes the output current from the second transistor 2b to the second power supply VOUT+5V, generates a constant voltage based on the thresholds of the diode-connected transistors 14Ab and 14Bb, and transmits it to the drain 38b of the fourth transistor 4b. A second voltage conversion signal 40b is output from the drain 38b of the fourth transistor 4b. The low level of the second voltage conversion signal 40b is set to a sixth voltage by the voltage of the second current supply terminal 36b and the output voltage of the second voltage generating circuit 14b.

[0098] The first voltage conversion unit 17b sets the high level of the first voltage conversion signal 39b and the second voltage conversion signal 40b to the voltage of the second power supply VOUT+5V, and sets the low level to the sixth voltage.

[0099] 10 includes a fifth transistor 9b and a sixth transistor 10b whose sources are connected to the second power supply VOUT+5V, and a seventh transistor 11b and an eighth transistor 12b whose sources are connected to the output terminal VOUT. The fifth transistor 9b and the sixth transistor 10b are p-channel MOS transistors whose channels are the second conductivity type. The seventh transistor 11b and the eighth transistor 12b are n-channel MOS transistors whose channels are the first conductivity type. The second voltage conversion unit 18b further includes an inverter 21b.

[0100] A first voltage-converted signal 39b is input to the gate of the fifth transistor 9b, and a second voltage-converted signal 40b is input to the gate of the sixth transistor 10b. The gate of the seventh transistor 11b is connected to the drain 42b of the eighth transistor 12b, and the drain 41b of the seventh transistor 11b is connected to the drain of the fifth transistor 9b. The gate of the eighth transistor 12b is connected to the drain 41b of the seventh transistor 11b, and the drain 42b of the eighth transistor 12b is connected to the drain of the sixth transistor 10b. A level shifter inverted output signal LSOUTBb, which is a fourth voltage-converted signal, is output from the drain 42b of the eighth transistor 12b. The level shifter inverted output signal LSOUTBb is inverted by an inverter 21b to become a level shifter output signal LSOUTb, which is a third voltage-converted signal. The level shifter output signal LSOUTb, which is the third voltage conversion signal, may be output from the drain 41b of the seventh transistor 11b.

[0101] When the first voltage conversion signal 39b is at a low level and the second voltage conversion signal 40b is at a high level, the fifth transistor 9b and the eighth transistor 12b are turned on, and the sixth transistor 10b and the seventh transistor 11b are turned off. The voltage of the drain 42b of the eighth transistor 12b is pulled down to the voltage of the output terminal VOUT. The level shifter inverted output signal LSOUTBb is also pulled down to the voltage of the output terminal VOUT, and the level shifter output signal LSOUTb becomes the voltage of the second power supply VOUT+5V.

[0102] Conversely, when the first voltage conversion signal 39b is at a high level and the second voltage conversion signal 40b is at a low level, the sixth transistor 10b and the seventh transistor 11b are turned on, and the fifth transistor 9b and the eighth transistor 12b are turned off. The voltage of the drain 42b of the eighth transistor 12b is pulled up to the voltage of the second power supply VOUT+5V. The level shifter inverted output signal LSOUTBb is also pulled up to the voltage of the second power supply VOUT+5V, and the level shifter output signal LSOUTb becomes the voltage of the output terminal VOUT.

[0103] 12 is a configuration diagram of a first delay circuit 15b of a semiconductor device according to the second embodiment. The first delay circuit 15b includes a first individual delay circuit 151b and a second individual delay circuit 152b. The first individual delay circuit 151b delays and inverts the first signal INb by a first period to generate a third signal INDLYBb. The second individual delay circuit 152b delays and inverts the second signal IN2b by a first period to generate a fourth signal IN2DLYBb.

[0104] 13 is a configuration diagram of a first individual delay circuit 151b and a second individual delay circuit 152b of a semiconductor device according to the second embodiment. Since the configuration diagrams of the first individual delay circuit 151b and the second individual delay circuit 152b are the same, the first individual delay circuit 151b will be described as a representative.

[0105] The first individual delay circuit 151b includes an inverter 22b, a first delay transistor 51b, a second delay transistor 52b, a third delay transistor 53b, and a fourth delay transistor 54b. The first individual delay circuit 151b further includes a fifth delay transistor 59b, a sixth delay transistor 60b, a seventh delay transistor 61b, an eighth delay transistor 62b, and a delay adjustment circuit 23b. The first individual delay circuit 151b receives the first signal INb as a delay circuit input signal DLYINb and outputs the third signal INDLYBb as a delay circuit inverted output signal DLYOUTBb.

[0106] The first delay transistor 51b and the second delay transistor 52b are substantially the same as or have similar sizes to the first transistor 1b and the second transistor 2b of the first voltage conversion unit 17b shown in FIG. 10 . The first delay transistor 51b and the second delay transistor 52b are n-channel MOS transistors with a first conductivity type channel. The sources of the first delay transistor 51b and the second delay transistor 52b are connected to the third power supply GND. The third delay transistor 53b and the fourth delay transistor 54b are substantially the same as or have similar sizes to the third transistor 3b and the fourth transistor 4b of the first voltage conversion unit 17b shown in FIG. 10 . The third delay transistor 53b and the fourth delay transistor 54b are p-channel MOS transistors with a second conductivity type channel. The sources of the third delay transistor 53b and the fourth delay transistor 54b are connected to the first power supply VCC.

[0107] A drain 77b of the third delay transistor 53b is connected to the drain of the first delay transistor 51b and the gate of the fourth delay transistor 54b. A drain 78b of the fourth delay transistor 54b is connected to the drain of the second delay transistor 52b and the gate of the third delay transistor 53b. The connections of the first to fourth delay transistors 51b, 52b, 53b, and 54b are the same as the connections of the first to fourth transistors 1b, 2b, 3b, and 4b of the first voltage conversion unit 17b shown in FIG.

[0108] The fifth delay transistor 59b and the sixth delay transistor 60b are substantially the same as or have similar sizes to the fifth transistor 9b and the sixth transistor 10b of the second voltage conversion unit 18b shown in FIG. 10 . The fifth delay transistor 59b and the sixth delay transistor 60b are p-channel MOS transistors with a second conductivity type channel. The fifth delay transistor 59b and the sixth delay transistor 60b have sources connected to the first power supply VCC. The seventh delay transistor 61b and the eighth delay transistor 62b are substantially the same as or have similar sizes to the seventh transistor 11b and the eighth transistor 12b of the second voltage conversion unit 18b shown in FIG. 10 . The seventh delay transistor 61b and the eighth delay transistor 62b are n-channel MOS transistors with a first conductivity type channel. The sources of the seventh delay transistor 61b and the eighth delay transistor 62b are connected to the third power supply GND.

[0109] The drain 81b of the seventh delay transistor 61b is connected to the drain of the fifth delay transistor 59b and the gate of the eighth delay transistor 62b. The drain 82b of the eighth delay transistor 62b is connected to the drain of the sixth delay transistor 60b and the gate of the seventh delay transistor 61b. The connection relationship between the fifth to eighth delay transistors 59b, 60b, 61b, and 62b is the same as the connection relationship between the fifth to eighth transistors 9b, 10b, 11b, and 12b of the second voltage conversion unit 18b shown in FIG.

[0110] The drain 77b of the third delay transistor 53b is connected to the gate of the fifth delay transistor 59b, and the drain 78b of the fourth delay transistor 54b is connected to the gate of the sixth delay transistor 60b. Meanwhile, the drain 37b of the third transistor 3b in Figure 10 is connected to the gate of the fifth transistor 9b, and the drain 38b of the fourth transistor 4b is connected to the gate of the sixth transistor 10b. The connections of the third to sixth delay transistors 53b, 54b, 59b, and 60b are the same as the connections of the third to sixth transistors 3b, 4b, 9b, and 10b in Figure 10.

[0111] The first individual delay circuit 151b includes transistors that are substantially the same as or similar in size and connection to the transistors that make up the first voltage conversion unit 17b and the second voltage conversion unit 18b in FIG. 10. The first individual delay circuit 151b can generate a delay time of a first period that includes the time it takes for the first voltage conversion unit 17b and the second voltage conversion unit 18b in FIG. 10 to transition between states in response to an input signal. The delay adjustment circuit 23b adjusts the delay time so that the first individual delay circuit 151b can generate a delay time that includes the time it takes for the first voltage conversion unit 17b and the second voltage conversion unit 18b in FIG. 10 to transition between states, even if there is variation in elements. The first individual delay circuit 151b is composed of transistors and has a smaller area than delay circuits that use resistors or capacitors.

[0112] 10 operates as follows as a whole. The boost level shifter 302 converts the voltage of a level shifter input signal LSINb, whose low level is the voltage of the third power supply GND and whose high level is the voltage of the first power supply VCC. The boost level shifter 302 outputs a level shifter output signal LSOUTb, whose low level is the voltage of the output terminal VOUT and whose high level is the voltage of the second power supply VOUT+5V. The level shifter input signal LSINb and the level shifter output signal LSOUTb are in phase.

[0113] 14 is an operational waveform diagram of the boost level shifter 302. The horizontal axis of FIG. 14 represents time, and the vertical axis represents voltage. In FIG. 14, the second power supply VOUT+5V is indicated by a thin dashed line, the second current supply terminal 36b is indicated by a thick solid line, the second signal IN2b is indicated by a thin dashed line, and the level shifter inverted output signal LSOUTBb is indicated by a thin solid line. Furthermore, the second voltage conversion signal 40b is indicated by a thick dashed line, and the fourth signal IN2DLYBb is indicated by a thick dashed line.

[0114] Since the step-up level shifter 302 is applied to the switching regulator 400 of FIG. 1 , the voltage of the output terminal VOUT and the voltage of the second power supply VOUT+5V change depending on the output to the output terminal VOUT of the switching regulator 400 and the load current. FIG. 14 shows an example in which the voltage of the output terminal VOUT is pulled up by the high-side switch transistor 401 from a low voltage state at time t0. The voltage of the second power supply VOUT+5V is low at time t0, but rises following the voltage of the output terminal VOUT being pulled up. At time t0, the second signal IN2b is at a low level, and the fourth signal IN2DLYBb is at a high level. At time t1, the level shifter input signal LSINb (not shown in FIG. 14) goes low, causing the second signal IN2b to go high, and turning on the second transistor 2b in FIG. 10. Because the first period has not yet elapsed since the second signal IN2b went high, the fourth signal IN2DLYBb is at high level, the second switch transistor 8b is turned on, and an inrush current flows to the second current supply terminal 36b. By flowing an inrush current to the second current supply terminal 36b, the voltage of the second current supply terminal 36b can be maintained so as not to rise above the voltage of the third power supply GND.

[0115] 10 is turned on, the voltage of the second voltage conversion signal 40b is pulled down. The low level of the second voltage conversion signal 40b is set to the sixth voltage by the voltage of the second current supply terminal 36b and the output voltage of the second voltage generation circuit 14b.

[0116] 10 is turned on, and the level shifter inverted output signal LSOUTBb is raised from the voltage of the output terminal VOUT to the high level voltage of the second power supply VOUT+5 V. When the level shifter inverted output signal LSOUTBb becomes high level, the level shifter output signal LSOUTb (not shown in FIG. 14) becomes the low level voltage of the output terminal VOUT.

[0117] The voltage of the second voltage-converted signal 40b decreases, and the voltage of the gate of the third transistor 3b in Fig. 10 is pulled down, turning on the third transistor 3b. When the third transistor 3b is turned on, the voltage of the first voltage-converted signal 39b and the gate voltage of the fourth transistor 4b (not shown in Fig. 14) are pulled up to the voltage of the second power supply VOUT + 5V, turning off the fourth transistor 4b. When the voltage of the first voltage-converted signal 39b is pulled up to the voltage of the second power supply VOUT + 5V, the state transition of the step-up level shifter 302 is completed.

[0118] After a first period has elapsed since the second signal IN2b went high, the fourth signal IN2DLYBb goes low at time t2, the second switch transistor 8b in FIG. 10 turns off, and the amount of current supplied via the second current supply terminal 36b decreases. As the amount of current supplied via the second current supply terminal 36b decreases to the bias current, the voltage of the second current supply terminal 36b increases and becomes constant at a voltage that can be maintained by the bias current. By reducing the amount of current supplied to the first voltage conversion unit 17b after the state transition of the step-up level shifter 302 is complete, the current consumption of the step-up level shifter 302 can be kept low.

[0119] The operation of the high-side pre-driver 403 will be described with reference to the configuration diagram of the high-side pre-driver 403 of the semiconductor device according to the first embodiment shown in FIG. 2. When the high-side control signal HGCTRL goes high, the high-side control inversion signal HGCTRLB goes low. The level shifter input signal LSINb, which is the input to the boost level shifter 302 shown in FIG. 3, goes low, and the level shifter output signal LSOUTb goes low. The first high-side driver inversion original signal HGPB in FIG. 2 goes low. The high-side driver original signal HGP goes high, and the high-side drive signal HG goes high.

[0120] Referring to the configuration diagram of the switching regulator 400, which is a semiconductor device according to the first embodiment, shown in FIG. 1, when the high-side drive signal HG goes high, the voltage at the output terminal VOUT of the switching regulator 400 increases.

[0121] Returning to the explanation of the operational waveform diagram of the step-up level shifter 302 shown in FIG. 14, at time t3, the voltage of the output terminal VOUT rises, and the voltage of the second power supply VOUT+5V also rises.

[0122] (Effects of the Second Embodiment) According to the second embodiment, when the step-up level shifter 302 transitions its state in response to a change in the input signal, the amount of current supplied to the first voltage conversion unit 17b via the first current supply terminal 35b or the second current supply terminal 36b is relatively increased during a first period following the change in the input signal. By increasing the amount of current supplied to the first voltage conversion unit 17b, the voltage of the first current supply terminal 35b or the second current supply terminal 36b can be kept from rising above the power supply voltage used by the step-up level shifter 302. Furthermore, by increasing the amount of current supplied to the first voltage conversion unit 17b, the state transition of the first voltage conversion unit 17b becomes faster. By keeping the voltage of the first current supply terminal 35b or the second current supply terminal 36b from rising, the step-up level shifter 302 can perform high-speed level shifting even when the power supply voltage used by the step-up level shifter 302 is low.

[0123] The boost level shifter 302 can reduce the current consumption of the boost level shifter 302 by relatively reducing the amount of current supplied to the first voltage conversion unit 17b after the first period has elapsed since the change in the input signal.

[0124] The first delay circuit 15b includes transistors that are substantially the same as or similar in size and connection to the transistors that make up the first voltage conversion unit 17b and the second voltage conversion unit 18b. The first delay circuit 15b generates a first period, thereby generating a delay time that includes the time it takes for the first voltage conversion unit 17b and the second voltage conversion unit 18b to transition between states. The first delay circuit 15b is composed of transistors, and therefore can occupy a smaller area than a delay circuit that uses resistors or capacitors.

[0125] Third Embodiment (Configuration of Semiconductor Device) FIG. 15 is a configuration diagram of a step-down level shifter 301 of a semiconductor device according to a third embodiment.

[0126] 15 differs from the first voltage conversion unit 17a of the step-down level shifter 301 of the semiconductor device according to the first embodiment shown in FIG. 4 in that it further includes the following elements: The first voltage conversion unit 17a further includes a first clamp transistor 25a, a second clamp transistor 26a, a third clamp transistor 27a, and a fourth clamp transistor 28a. The first clamp transistor 25a, the second clamp transistor 26a, the third clamp transistor 27a, and the fourth clamp transistor 28a are diode-connected with their drains and gates connected together.

[0127] The first clamp transistor 25a has a source that receives a first signal INa and a drain and gate that are connected to the source of the first transistor 1a. When the first signal INa is at a high level, the first clamp transistor 25a clamps the source voltage of the first transistor 1a so that it does not fall below a voltage obtained by subtracting the threshold value of the first clamp transistor 25a from the voltage of the third power supply VOUT+5V. The second clamp transistor 26a has a source that receives a second signal IN2a and a drain and gate that are connected to the source of the second transistor 2a. When the second signal IN2a is at a high level, the second clamp transistor 26a clamps the source voltage of the second transistor 2a so that it does not fall below a voltage obtained by subtracting the threshold value of the second clamp transistor 26a from the voltage of the third power supply VOUT+5V.

[0128] The third clamp transistor 27a has a source connected to the drain 37a of the third transistor 3a, and a drain and gate connected to the fourth power supply VCC. When the drain 37a of the third transistor 3a is at a high level, the third clamp transistor 27a prevents the voltage of the drain 37a of the third transistor 3a from rising above the voltage obtained by adding the voltage of the fourth power supply VCC to the threshold of the third clamp transistor 27a. The fourth clamp transistor 28a has a source connected to the drain 38a of the fourth transistor 4a, and a drain and gate connected to the fourth power supply VCC. When the drain 38a of the fourth transistor 4a is at a high level, the fourth clamp transistor 28a prevents the voltage of the drain 38a of the fourth transistor 4a from rising above the voltage obtained by adding the voltage of the fourth power supply VCC to the threshold of the fourth clamp transistor 28a.

[0129] (Effects of the Third Embodiment) According to the third embodiment, when the step-down level shifter 301 transitions states in response to a change in the input signal, the source voltages of the first transistor 1 a and the second transistor 2 a are clamped so as not to drop below a predetermined voltage. Also, the drain voltages of the third transistor 3 a and the fourth transistor 4 a are clamped so as not to rise above a predetermined voltage. By maintaining the source voltages of the first and second transistors 1 a and 2 a and the drain voltages of the third and fourth transistors 3 a and 4 a within a predetermined voltage range, it is possible to prevent a forward bias or a voltage exceeding the breakdown voltage from being applied to elements included in the step-down level shifter 301.

[0130] Fourth Embodiment (Configuration of Semiconductor Device) FIG. 16 is a configuration diagram of a boost level shifter 302 of a semiconductor device according to a fourth embodiment.

[0131] 16 differs from the first voltage conversion unit 17b of the boost level shifter 302 of the semiconductor device according to the second embodiment shown in FIG. 10 in that it further includes the following elements: The first voltage conversion unit 17b further includes a first clamp transistor 25b, a second clamp transistor 26b, a third clamp transistor 27b, and a fourth clamp transistor 28b. The first clamp transistor 25b, the second clamp transistor 26b, the third clamp transistor 27b, and the fourth clamp transistor 28b are diode-connected with their drains and gates connected together.

[0132] The first clamp transistor 25b has a source that receives the first signal INb and a drain and gate that are connected to the source of the first transistor 1b. When the first signal INb is at a low level, the first clamp transistor 25b clamps the source voltage of the first transistor 1b so that it does not exceed the voltage obtained by adding the voltage of the third power supply GND to the threshold of the first clamp transistor 25b. The second clamp transistor 26b has a source that receives the second signal IN2b and a drain and gate that are connected to the source of the second transistor 2b. When the second signal IN2b is at a low level, the second clamp transistor 26b clamps the source voltage of the second transistor 2b so that it does not exceed the voltage obtained by adding the voltage of the third power supply GND to the threshold of the second clamp transistor 26b.

[0133] The third clamp transistor 27b has a source connected to the drain 37b of the third transistor 3b, and a drain and gate connected to the output terminal VOUT. The third clamp transistor 27b prevents the voltage at the drain 37b of the third transistor 3b from falling below the voltage at the output terminal VOUT minus the threshold value of the third clamp transistor 27b when the drain 37b of the third transistor 3b is at a low level. The fourth clamp transistor 28b has a source connected to the drain 38b of the fourth transistor 4b, and a drain and gate connected to the output terminal VOUT. The fourth clamp transistor 28b prevents the voltage at the drain 38b of the fourth transistor 4b from falling below the voltage at the output terminal VOUT minus the threshold value of the fourth clamp transistor 28b when the drain 38b of the fourth transistor 4b is at a low level.

[0134] (Effects of the Fourth Embodiment) According to the fourth embodiment, when the step-up level shifter 302 transitions states in response to a change in the input signal, the source voltages of the first transistor 1b and the second transistor 2b are clamped so as not to exceed a predetermined voltage. Also, the drain voltages of the third transistor 3b and the fourth transistor 4b are clamped so as not to fall below a predetermined voltage. By maintaining the source voltages of the first and second transistors 1b and 2b and the drain voltages of the third and fourth transistors 3b and 4b within a predetermined voltage range, it is possible to prevent a forward bias or a voltage exceeding the breakdown voltage from being applied to elements included in the step-up level shifter 302.

[0135] [Other Embodiments] Several embodiments of the present disclosure have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. One or more elements of one embodiment can be combined with one or more elements of another embodiment. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0136] For example, in some embodiments of the present disclosure described above, the first delay circuit delays and inverts the first signal using the first individual delay circuit to generate the third signal, and delays and inverts the second signal using the second individual delay circuit to generate the fourth signal. However, the first delay circuit may also invert the third signal to generate the fourth signal, or invert the fourth signal to generate the third signal.

[0137] For example, in the fifth power supply generating circuit according to some embodiments of the present disclosure described above, the amount of the constant bias current is determined by the first resistor. However, the fifth power supply generating circuit may be supplied with a constant current from a constant current source.

[0138] Furthermore, for example, the boost circuit according to some of the embodiments of the present disclosure may be a charge pump boost circuit or a bootstrap circuit.

[0139] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0140] (Supplementary Note 1) The semiconductor device includes a first delay circuit 15a, a first current supply unit 16a, and a first voltage conversion unit 17a. The first delay circuit 15a delays a first signal INa, whose low level is a first voltage output from an output terminal VOUT, and a second signal IN2a, which is an inverted signal of the first signal INa, by a first period to generate a third signal INDLYBa and a fourth signal IN2DLYBa. The first current supply unit 16a includes a first current supply terminal 35a whose current supply capacity switches in response to the third signal INDLYBa and a second current supply terminal 36a whose current supply capacity switches in response to the fourth signal IN2DLYBa. The first voltage conversion unit 17a is connected to a second power supply GND that supplies a second voltage lower than the first voltage. The first voltage conversion unit 17a outputs either or both of a first voltage-converted signal 39a and a second voltage-converted signal 40a obtained by level-shifting the low levels of the first signal INa and the second signal IN2a from the first voltage to the second voltage. The first voltage conversion unit 17a receives a current from the first current supply unit 16a and uses it to generate the high levels of the first voltage-converted signal 39a and the second voltage-converted signal 40a.

[0141] According to the semiconductor device, high-speed level shifting is possible even when the power supply voltage used by the step-down level shifter 301 is low, and the current consumption of the step-down level shifter 301 can be kept small.

[0142] (Supplementary Note 2) The semiconductor device includes a first delay circuit 15b, a first current supply unit 16b, and a first voltage conversion unit 17b. The first delay circuit 15b delays a first signal INb, whose high level is a first voltage supplied by a first power supply VCC, and a second signal IN2b, which is an inverted signal of the first signal INb, by a first period to generate a third signal INDLYBb and a fourth signal IN2DLYBb. The first current supply unit 16b includes a first current supply terminal 35b whose current supply capacity switches in response to the third signal INDLYBb and a second current supply terminal 36b whose current supply capacity switches in response to the fourth signal IN2DLYBb. The first voltage conversion unit 17b is connected to a second power supply VOUT+5V that supplies a second voltage higher than the first voltage. The first voltage conversion unit 17b outputs either or both of a first voltage-converted signal 39b and a second voltage-converted signal 40b obtained by level-shifting the high levels of the first signal INb and the second signal IN2b from the first voltage to the second voltage. The first voltage conversion unit 17b receives a current from the first current supply unit 16b and uses it to generate the low levels of the first voltage-converted signal 39b and the second voltage-converted signal 40b.

[0143] According to the semiconductor device, high-speed level shifting is possible even when the power supply voltage used by the step-up level shifter 302 is low, and the current consumption of the step-up level shifter 302 can be kept small.

[0144] (Supplementary Note 3) The first voltage conversion unit 17a of the semiconductor device described in Supplementary Note 1 includes a first transistor 1a, a second transistor 2a, a third transistor 3a, and a fourth transistor 4a. The conduction state of the first transistor 1a is controlled by a first signal INa, and in the on state, an output current flows from the first current supply terminal 35a. The conduction state of the second transistor 2a is controlled by a second signal IN2a, and in the on state, an output current flows from the second current supply terminal 36a. The third transistor 3a and the fourth transistor 4a are controlled in accordance with the on / off states of the first transistor 1a and the second transistor 2a. A first voltage conversion signal 39a is output from a second main electrode 37a of the third transistor, and a second voltage conversion signal 40a is output from a second main electrode 38a of the fourth transistor 4a.

[0145] (Supplementary Note 4) The first voltage conversion unit 17b of the semiconductor device described in Supplementary Note 2 includes a first transistor 1b, a second transistor 2b, a third transistor 3b, and a fourth transistor 4b. The conduction state of the first transistor 1b is controlled by a first signal INb, and an output current flows from the first current supply terminal 35b when the first transistor 1b is in the on state. The conduction state of the second transistor 2b is controlled by a second signal IN2b, and an output current flows from the second current supply terminal 36b when the second transistor 2b is in the on state. The third transistor 3b and the fourth transistor 4b are controlled according to the on / off states of the first transistor 1b and the second transistor 2b. A first voltage conversion signal 39b is output from a second main electrode 37b of the third transistor, and a second voltage conversion signal 40b is output from a second main electrode 38b of the fourth transistor 4b.

[0146] (Supplementary Note 5) The first voltage conversion unit 17a of the semiconductor device described in Supplementary Note 3 further includes a first voltage generation circuit 13a and a second voltage generation circuit 14a. The first voltage generation circuit 13a flows the output current from the first transistor 1a to the second power supply GND to generate a constant voltage, which is transmitted to the second main electrode 37a of the third transistor 3a. The second voltage generation circuit 14a flows the output current from the second transistor 2a to the second power supply GND to generate a constant voltage, which is transmitted to the second main electrode 38a of the fourth transistor 4a. The high levels of the first voltage conversion signal 39a and the second voltage conversion signal 40a can be set to a sixth voltage.

[0147] (Supplementary Note 6) The first voltage conversion unit 17b of the semiconductor device described in Supplementary Note 4 further includes a first voltage generation circuit 13b and a second voltage generation circuit 14b. The first voltage generation circuit 13b flows the output current from the first transistor 1b to a second power supply VOUT+5V to generate a constant voltage, which is transmitted to the second main electrode 37b of the third transistor 3b. The second voltage generation circuit 14b flows the output current from the second transistor 2b to a second power supply VOUT+5V to generate a constant voltage, which is transmitted to the second main electrode 38b of the fourth transistor 4b. The low levels of the first voltage conversion signal 39b and the second voltage conversion signal 40b can be set to a sixth voltage.

[0148] (Supplementary Note 7) The first voltage generating circuit 13a of the semiconductor device described in Supplementary Note 5 has one diode-connected transistor or multiple diode-connected transistors 13Aa, 13Ba. The single diode-connected transistor has a second main electrode connected to a control electrode. The multiple diode-connected transistors 13Aa, 13Ba have their second main electrodes connected to their control electrodes and are connected in series. The second voltage generating circuit 14a has one diode-connected transistor or multiple diode-connected transistors 14Aa, 14Ba. The single diode-connected transistor has its second main electrode connected to its control electrode. The multiple diode-connected transistors 14Aa, 14Ba have their second main electrodes connected to their control electrodes and are connected in series.

[0149] A second main electrode of one diode-connected transistor 13Aa in the first voltage generating circuit 13a is connected to a second main electrode 37a of the third transistor 3a. A second main electrode of one diode-connected transistor 14Aa in the second voltage generating circuit 14a is connected to a second main electrode 38a of the fourth transistor 4a. A first main electrode of one diode-connected transistor 13Ba or 14Ba in each of the first and second voltage generating circuits 13a and 14a is connected to the second power supply GND. The first voltage generating circuit 13a can generate a constant voltage and transmit it to the second main electrode 38a of the fourth transistor 4a.

[0150] (Supplementary Note 8) The first voltage generating circuit 13b of the semiconductor device described in Supplementary Note 6 has one diode-connected transistor or multiple diode-connected transistors 13Ab, 13Bb. The single diode-connected transistor has a second main electrode connected to a control electrode. The multiple diode-connected transistors 13Ab, 13Bb have their second main electrodes connected to their control electrodes and are connected in series. The second voltage generating circuit 14b has one diode-connected transistor or multiple diode-connected transistors 14Ab, 14Bb. The single diode-connected transistor has a second main electrode connected to its control electrode. The multiple diode-connected transistors 14Ab, 14Bb have their second main electrodes connected to their control electrodes and are connected in series.

[0151] A second main electrode of one diode-connected transistor 13Ab in the first voltage generation circuit 13b is connected to a second main electrode 37b of the third transistor 3b. A second main electrode of one diode-connected transistor 14Ab in the second voltage generation circuit 14b is connected to a second main electrode 38b of the fourth transistor 4b. A first main electrode of one diode-connected transistor 13Bb or 14Bb in each of the first and second voltage generation circuits 13b and 14b is connected to a second power supply VOUT+5V. The second voltage generation circuit 14b can generate a constant voltage and transmit it to the second main electrode 38b of the fourth transistor 4b.

[0152] (Supplementary Note 9) In the semiconductor device described in any one of Supplementary Notes 3, 5, and 7, the high levels of the first signal INa and the second signal IN2a are a third voltage supplied by a third power supply VOUT+5V, and the first current supply unit 16a is connected to the third power supply VOUT+5V. The current supply capacity of the first current supply terminal 35a is relatively large when the first signal INa transitions to one of the first and third voltages output from the output terminal VOUT, which voltage turns on the first transistor 1a. The current supply capacity of the first current supply terminal 35a becomes relatively small after a first period has elapsed since the first signal INa transitioned to the voltage at which the first transistor 1a turns on. The current supply capacity of the second current supply terminal 36a is relatively large when the second signal IN2a transitions to one of the first and third voltages, which voltage turns on the second transistor 2a. The current supply capability of the second current supply terminal 36a becomes relatively small after the first period has elapsed since the second signal IN2a transitioned to a voltage that turns on the second transistor 2a.

[0153] According to the semiconductor device, high-speed level shifting is possible even when the power supply voltage used by the step-down level shifter 301 is low, and the current consumption of the step-down level shifter 301 can be kept small.

[0154] (Supplementary Note 10) In the semiconductor device described in any one of Supplementary Notes 4, 6, and 8, the low levels of the first signal INb and the second signal IN2b are a third voltage supplied by the third power supply GND, and the first current supply unit 16b is connected to the third power supply GND. The current supply capacity of the first current supply terminal 35b is relatively large when the first signal INb transitions to one of the first voltage and the third voltage supplied by the first power supply VCC, at which the first transistor 1b is turned on. The current supply capacity of the first current supply terminal 35b becomes relatively small after a first period has elapsed since the first signal INb transitioned to the voltage at which the first transistor 1b is turned on. The current supply capacity of the second current supply terminal 36b is relatively large when the second signal IN2b transitions to one of the first voltage and the second voltage, at which the second transistor 2b is turned on. The current supply capability of the second current supply terminal 36b becomes relatively small after the first period has elapsed since the second signal IN2b transitioned to a voltage at which the second transistor 2b turns on.

[0155] According to the semiconductor device, high-speed level shifting is possible even when the power supply voltage used by the step-up level shifter 302 is low, and the current consumption of the step-up level shifter 302 can be kept small.

[0156] (Supplementary Note 11) In the semiconductor device described in Supplementary Note 7, the high levels of the first signal INa and the second signal IN2a are a third voltage supplied by a third power supply VOUT+5V. The first current supply unit 16a includes a first constant current transistor 5a, a second constant current transistor 6a, a first switch transistor 7a, and a second switch transistor 8a. The first constant current transistor 5a has a first main electrode connected to the third power supply VOUT+5V, a second main electrode connected to a first current supply terminal 35a, and a control electrode to which a fifth voltage supplied by a fifth power supply VGa is applied, thereby controlling the amount of current to be constant. The second constant current transistor 6a has a first main electrode connected to the third power supply VOUT+5V, a second main electrode connected to a second current supply terminal 36a, and a control electrode to which a fifth voltage is applied, thereby controlling the amount of current to be constant. The first switch transistor 7a has a first main electrode connected to the third power supply VOUT+5V, a second main electrode connected to the first current supply terminal 35a, and a control electrode to which the third signal INDLYBa is input. The second switch transistor 8a has a first main electrode connected to the third power supply VOUT+5V, a second main electrode connected to the second current supply terminal 36a, and a control electrode to which the fourth signal IN2DLYBa is input.

[0157] (Supplementary Note 12) In the semiconductor device described in Supplementary Note 8, the low levels of the first signal INb and the second signal IN2b are a third voltage supplied by the third power supply GND. The first current supply unit 16b includes a first constant current transistor 5b, a second constant current transistor 6b, a first switch transistor 7b, and a second switch transistor 8b. The first constant current transistor 5b has a first main electrode connected to the third power supply GND, a second main electrode connected to the first current supply terminal 35b, and a control electrode to which a fifth voltage supplied by the fifth power supply VGb is applied, thereby controlling the amount of current to be constant. The second constant current transistor 6b has a first main electrode connected to the third power supply GND, a second main electrode connected to the second current supply terminal 36b, and a control electrode to which a fifth voltage is applied, thereby controlling the amount of current to be constant. The first switch transistor 7b has a first main electrode connected to the third power supply GND, a second main electrode connected to the first current supply terminal 35b, and a control electrode to which the third signal INDLYBb is input. The second switch transistor 8b has a first main electrode connected to the third power supply GND, a second main electrode connected to the second current supply terminal 36b, and a control electrode to which the fourth signal IN2DLYBb is input.

[0158] (Supplementary Note 13) In the semiconductor device described in Supplementary Note 11, a first signal INa, which is a voltage at which the first transistor 1a turns on out of a first voltage output from the output terminal VOUT and a third voltage supplied by a third power supply VOUT+5V, is input to a control electrode of the first transistor 1a. After a first period has elapsed since the input of the first signal INa, a third signal INDLYBa, which is a voltage at which the first switch transistor 7a turns off out of the first voltage and the third voltage, is input to a control electrode of the first switch transistor 7a. A second signal IN2a, which is a voltage at which the second transistor 2a turns on out of the first voltage and the third voltage, is input to a control electrode of the second transistor 2a. After a first period has elapsed since the second signal IN2a was input, a fourth signal IN2DLYBa, which is a voltage between the first voltage and the third voltage that turns off the second switch transistor 8a, is input to the control electrode of the second switch transistor 8a.

[0159] (Supplementary Note 14) In the semiconductor device described in Supplementary Note 12, a first signal INb, which is a voltage at which the first transistor 1b is turned on out of a first voltage supplied by the first power supply VCC and a third voltage supplied by the third power supply GND, is input to a control electrode of the first transistor 1b. After a first period has elapsed since the input of the first signal INb, a third signal INDLYBb, which is a voltage at which the first switch transistor 7b is turned off out of the first voltage and the third voltage, is input to a control electrode of the first switch transistor 7b. A second signal IN2b, which is a voltage at which the second transistor 2b is turned on out of the first voltage and the third voltage, is input to a control electrode of the second transistor 2b. After a first period has elapsed since the input of the second signal IN2b, a fourth signal IN2DLYBb, which is a voltage at which the second switch transistor 8b is turned off out of the first voltage and the third voltage, is input to a control electrode of the second switch transistor 8b.

[0160] (Supplementary Note 15) In the semiconductor device described in Supplementary Note 1, the high levels of the first signal INa and the second signal IN2a are a third voltage supplied by a third power supply VOUT+5V, and the first current supply unit 16a is connected to the third power supply VOUT+5V. The semiconductor device further includes a second voltage conversion unit 18a. The second voltage conversion unit 18a is connected to a fourth power supply VCC. The second voltage conversion unit 18a outputs one or both of a third voltage-converted signal LSOUTa and a fourth voltage-converted signal LSOUTBa obtained by level-shifting the high levels of the first voltage-converted signal 39a and the second voltage-converted signal 40a to a fourth voltage supplied by the fourth power supply VCC.

[0161] (Supplementary Note 16) In the semiconductor device described in Supplementary Note 2, the low levels of the first signal INb and the second signal IN2b are a third voltage supplied by a third power supply GND, and the first current supply unit 16b is connected to the third power supply GND. The semiconductor device further includes a second voltage conversion unit 18b. The second voltage conversion unit 18b is connected to the output terminal VOUT. The second voltage conversion unit 18b outputs one or both of a third voltage-converted signal LSOUTb and a fourth voltage-converted signal LSOUTBb, which are obtained by level-shifting the low levels of the first voltage-converted signal 39b and the second voltage-converted signal 40b to a fourth voltage that is output from the output terminal VOUT.

[0162] (Supplementary Note 17) The semiconductor device according to Supplementary Note 11 or 13 further includes a second voltage conversion unit 18a. The second voltage conversion unit 18a is connected to a fourth power supply VCC that supplies a fourth voltage. The second voltage conversion unit 18a outputs one or both of a third voltage conversion signal LSOUTa and a fourth voltage conversion signal LSOUTBa, which are obtained by level-shifting the high levels of the first voltage conversion signal 39a and the second voltage conversion signal 40a to a fourth voltage. The second voltage conversion unit 18a includes a fifth transistor 9a whose conduction state is controlled by the first voltage conversion signal 39a and a sixth transistor 10a whose conduction state is controlled by the second voltage conversion signal 40a. The second voltage conversion unit 18a further includes a seventh transistor 11a and an eighth transistor 12a that are controlled depending on the conduction states of the fifth transistor 9a and the sixth transistor 10a.

[0163] (Supplementary Note 18) The semiconductor device described in Supplementary Note 12 or 14 further includes a second voltage conversion unit 18b. The second voltage conversion unit 18b is connected to an output terminal VOUT that outputs a fourth voltage. The second voltage conversion unit 18b outputs one or both of a third voltage conversion signal LSOUTb and a fourth voltage conversion signal LSOUTBb, which are obtained by level-shifting the low levels of the first voltage conversion signal 39b and the second voltage conversion signal 40b to a fourth voltage. The second voltage conversion unit 18b includes a fifth transistor 9b whose conduction state is controlled by the first voltage conversion signal 39b and a sixth transistor 10b whose conduction state is controlled by the second voltage conversion signal 40b. The second voltage conversion unit 18b further includes a seventh transistor 11b and an eighth transistor 12b that are controlled depending on the conduction states of the fifth transistor 9b and the sixth transistor 10b.

[0164] (Supplementary Note 19) In the semiconductor device described in Supplementary Note 17, the first period is generated by a first delay circuit 15 a including transistors that are substantially the same as or similar in size to and connected in the same manner as transistors included in the first voltage conversion unit 17 a and the second voltage conversion unit 18 a. The first delay circuit 15 a can generate a delay time that includes the time it takes for the first voltage conversion unit 17 a and the second voltage conversion unit 18 a to transition between states, and can have a smaller area than a delay circuit using a resistor or a capacitor.

[0165] (Supplementary Note 20) In the semiconductor device described in Supplementary Note 18, the first period is generated by a first delay circuit 15b including transistors that are substantially the same as or similar in size to and connected in the same manner as transistors included in the first voltage conversion unit 17b and the second voltage conversion unit 18b. The first delay circuit 15b can generate a delay time that includes the time it takes for the first voltage conversion unit 17b and the second voltage conversion unit 18b to transition between states, and can have a smaller area than a delay circuit that uses a resistor or a capacitor.

[0166] (Supplementary Note 21) The semiconductor device according to any one of Supplementary Notes 9, 11, 13, 15, 17, and 19 includes a high-side switch transistor 401 and a low-side switch transistor 402. The high-side switch transistor 401 and the low-side switch transistor 402 generate a first voltage output from an output terminal VOUT based on a fifth signal HG and a sixth signal LG. The semiconductor device includes a boost circuit 406 that receives the first voltage and generates a third power supply VOUT+5V that supplies a third voltage. The first voltage and the third voltage change according to the fifth signal HG and the sixth signal LG.

[0167] (Supplementary Note 22) The semiconductor device described in any one of Supplementary Notes 16, 18, and 20 includes a high-side switch transistor 401 and a low-side switch transistor 402. The high-side switch transistor 401 and the low-side switch transistor 402 generate a fourth voltage output from an output terminal VOUT based on a fifth signal HG and a sixth signal LG. The semiconductor device includes a boost circuit 406 that receives the fourth voltage and generates a second power supply VOUT+5V that supplies a second voltage. The fourth voltage and the second voltage change according to the fifth signal HG and the sixth signal LG.

[0168] (Supplementary Note 23) In the semiconductor device according to Supplementary Note 11 or 13, the channels of the first transistor 1a, the second transistor 2a, the first constant current transistor 5a, the second constant current transistor 6a, the first switch transistor 7a, and the second switch transistor 8a are of the first conductivity type. In the semiconductor device, the channels of the third transistor 3a, the fourth transistor 4a, and the diode-connected transistors 13Aa, 13Ba, 14Aa, and 14Ba are of the second conductivity type. The polarity of the third signal INDLYBa is opposite in phase to that of the first signal INa, and the polarity of the fourth signal IN2DLYBa is opposite in phase to that of the second signal IN2a.

[0169] (Supplementary Note 24) In the semiconductor device according to Supplementary Note 12 or 14, the channels of the first transistor 1b, the second transistor 2b, the first constant current transistor 5b, the second constant current transistor 6b, the first switch transistor 7b, and the second switch transistor 8b are of the first conductivity type. In the semiconductor device, the channels of the third transistor 3b, the fourth transistor 4b, and the diode-connected transistors 13Ab, 13Bb, 14Ab, and 14Bb are of the second conductivity type. The polarity of the third signal INDLYBb is opposite in phase to that of the first signal INb, and the polarity of the fourth signal IN2DLYBb is opposite in phase to that of the second signal IN2b.

[0170] (Supplementary Note 25) In the semiconductor device according to Supplementary Note 17 or 19, the channels of the first transistor 1a, the second transistor 2a, the first constant current transistor 5a, and the second constant current transistor 6a are of the first conductivity type. The channels of the first switch transistor 7a, the second switch transistor 8a, the seventh transistor 11a, and the eighth transistor 12a are of the first conductivity type. The channels of the third transistor 3a, the fourth transistor 4a, the fifth transistor 9a, the sixth transistor 10a, and the diode-connected transistors 13Aa, 13Ba, 14Aa, and 14Ba are of the second conductivity type. The polarity of the third signal INDLYBa is opposite in phase to that of the first signal INa, and the polarity of the fourth signal IN2DLYBa is opposite in phase to that of the second signal IN2a.

[0171] (Supplementary Note 26) In the semiconductor device according to Supplementary Note 18 or 20, the channels of the first transistor 1b, the second transistor 2b, the first constant current transistor 5b, and the second constant current transistor 6b are of the first conductivity type. The channels of the first switch transistor 7b, the second switch transistor 8b, the seventh transistor 11b, and the eighth transistor 12b are of the first conductivity type. The channels of the third transistor 3b, the fourth transistor 4b, the fifth transistor 9b, the sixth transistor 10b, and the diode-connected transistors 13Ab, 13Bb, 14Ab, and 14Bb are of the second conductivity type. The polarity of the third signal INDLYBb is opposite in phase to that of the first signal INb, and the polarity of the fourth signal IN2DLYBb is opposite in phase to that of the second signal IN2b.

[0172] (Supplementary Note 27) In the semiconductor device according to any one of Supplementary Notes 11, 13, 17, 19, 23, and 25, the current driving capability when the first switch transistor 7a or the second switch transistor 8a is turned on is greater than the current driving capability of the first constant current transistor 5a or the second constant current transistor 6a.

[0173] (Supplementary Note 28) In the semiconductor device according to any one of Supplementary Notes 12, 14, 18, 20, 24, and 26, the current driving capability when the first switch transistor 7b or the second switch transistor 8b is turned on is greater than the current driving capability of the first constant current transistor 5b or the second constant current transistor 6b.

[0174] (Supplementary Note 29) In the semiconductor device according to any one of Supplementary Notes 3, 5, 7, 9, 11, 13, 17, 19, 23, 25, and 27, the first voltage conversion unit 17a further includes first to fourth clamp transistors 25a, 26a, 27a, and 28a. The first and second clamp transistors 25a and 26a prevent the voltages of the sources of the first and second transistors 1a and 2a from falling below a voltage obtained by subtracting the threshold of either of the first and second clamp transistors 25a and 26a from the voltage of the third power supply VOUT+5V. The third and fourth clamp transistors 27a and 28a prevent the voltages of the drains 37a and 38a of the third and fourth transistors 3a and 4a from rising above a voltage obtained by adding the voltage of the fourth power supply VCC to the threshold of either of the third and fourth clamp transistors 27a and 28a. According to the semiconductor device, it is possible to prevent a forward bias or a voltage exceeding the breakdown voltage from being applied to the elements of the step-down level shifter 301 .

[0175] (Supplementary Note 30) In the semiconductor device described in any one of Supplementary Notes 4, 6, 8, 10, 12, 14, 18, 20, 24, 26, and 28, the first voltage conversion unit 17b further includes first to fourth clamp transistors 25b, 26b, 27b, and 28b. The first and second clamp transistors 25b and 26b prevent the voltages of the sources of the first and second transistors 1b and 2b from rising above a voltage obtained by adding the voltage of the third power supply GND to a threshold value of either the first or second clamp transistor 25b or 26b. The third and fourth clamp transistors 27b and 28b prevent the voltages of the drains 37b and 38b of the third and fourth transistors 3b and 4b from falling below a voltage obtained by subtracting the threshold value of either the third or fourth clamp transistor 27b or 28b from the voltage of the output terminal VOUT. According to the semiconductor device, it is possible to prevent a forward bias or a voltage exceeding the breakdown voltage from being applied to the elements of the step-up level shifter 302 .

[0176] Reference Signs List 1a, 1b First transistor 2a, 2b Second transistor 3a, 3b Third transistor 4a, 4b Fourth transistor 5a, 5b First constant current transistor 6a, 6b Second constant current transistor 7a, 7b First switch transistor 8a, 8b Second switch transistor 9a, 9b Fifth transistor 10a, 10b Sixth transistor 11a, 11b Seventh transistor 12a, 12b Eighth transistor 13a, 13b First voltage generating circuit 13Aa, 13Ab, 13Ba, 13Bb Diode-connected transistor 14a, 14b Second voltage generating circuit 14Aa, 13Ab, 14Ba, 14Bb Diode-connected transistor 15a, 15b First delay circuit 16a, 16b First current supply unit 17a, 17b First voltage conversion unit 18a, 18b Second voltage conversion unit 19a, 19b, 20a, 20b, 21a, 21b Inverter 25a, 25b First clamp transistor 26a, 26b Second clamp transistor 27a, 27b Third clamp transistor 28a, 28b Fourth clamp transistor 35a, 35b First current supply terminal 36a, 36b Second current supply terminal 39a, 39b First converted voltage signal 40a, 40b Second converted voltage signal 51a, 51b First delay transistor 52a, 52b Second delay transistor 53a, 53b Third delay transistor 54a, 54b Fourth delay transistor 59a, 59b Fifth delay transistor 60a, 60b Sixth delay transistor 61a, 61b Seventh delay transistor 62a, 62b Eighth delay transistor 63a, 63b Fifth power supply generation transistor 151a, 151b First individual delay circuit 152a, 152b Second individual delay circuit 301 Step-down level shifter 302 Step-up level shifter 303 Driver circuit 304, 305, 306,307 Inverter 400 Semiconductor device 401 High potential side switch transistor 402 Low potential side switch transistor 403 High potential side pre-driver 404 Low potential side pre-driver 405 Control circuit 406 Boost circuit 407 Inductor 408 Capacitor EN Enable signal GND Second power supply or third power supply HG High potential side drive signal HGFB High potential side feedback signal HGFBB High potential side feedback inverted signal HGP High potential side drive original signal HGP2B Second high potential side drive inverted original signal HGPB First high potential side drive inverted original signal IN2a, IN2b Second signal IN2DLYBa, IN2DLYBb Fourth signal INa, INb First signal INDLYBa, INDLYBb Third signal LG Low potential side drive signal LSOUTa, LSOUTb Level shifter output signal which is the third voltage conversion signal LSOUTBa, LSOUTBb Level shifter inverted output signal which is the fourth voltage conversion signal VCC Fourth power supply or first power supply VGa, VGb Fifth power supply VO Output node VOSNS Output voltage detection terminal VOUT Output terminal VOUT+5V Third power supply or second power supply VPWR External power supply terminal,

Claims

1. A semiconductor device comprising: a first delay circuit that generates a third signal and a fourth signal by delaying a first signal, the low level of which is a first voltage, and a second signal, the second signal being an inverted signal of the first signal, by a first period; a first current supply unit including a first current supply terminal whose current supply capacity switches in response to the third signal and a second current supply terminal whose current supply capacity switches in response to the fourth signal; and a first voltage conversion unit that is connected to a second power supply that supplies a second voltage lower than the first voltage, and outputs either or both of a first voltage-converted signal and a second voltage-converted signal obtained by level-shifting the low levels of the first signal and the second signal from the first voltage to the second voltage, and that receives current from the first current supply unit and is used to generate the high levels of the first voltage-converted signal and the second voltage-converted signal.

2. A semiconductor device comprising: a first delay circuit that generates a third signal and a fourth signal by delaying a first signal, the high level of which is a first voltage, and a second signal, the second signal being an inverted version of the first signal, by a first period; a first current supply unit including a first current supply terminal whose current supply capacity switches in response to the third signal and a second current supply terminal whose current supply capacity switches in response to the fourth signal; and a first voltage conversion unit that is connected to a second power supply that supplies a second voltage higher than the first voltage, outputs one or both of a first voltage-converted signal and a second voltage-converted signal obtained by level-shifting the high levels of the first signal and the second signal from the first voltage to the second voltage, and receives current from the first current supply unit and uses it to generate the low levels of the first voltage-converted signal and the second voltage-converted signal.

3. The semiconductor device according to claim 1 or 2, wherein the first voltage conversion unit includes: a first transistor whose conduction state is controlled by the first signal and through which an output current flows from the first current supply terminal when in the on state; a second transistor whose conduction state is controlled by the second signal and through which an output current flows from the second current supply terminal when in the on state; and a third transistor and a fourth transistor controlled in accordance with the on / off states of the first transistor and the second transistor, wherein the first voltage conversion signal is output from a second main electrode of the third transistor, and the second voltage conversion signal is output from a second main electrode of the fourth transistor.

4. The semiconductor device according to claim 3, wherein the first voltage conversion unit further includes: a first voltage generation circuit that generates a constant voltage by passing an output current from the first transistor through the second power supply and transmits the constant voltage to the second main electrode of the third transistor; and a second voltage generation circuit that generates a constant voltage by passing an output current from the second transistor through the second power supply and transmits the constant voltage to the second main electrode of the fourth transistor.

5. The semiconductor device according to claim 4, wherein the first voltage generating circuit and the second voltage generating circuit each have one diode-connected transistor having a second main electrode connected to a control electrode, or a plurality of diode-connected transistors each having a second main electrode connected to a control ...

6. The semiconductor device according to any one of claims 3 to 5, wherein the high level or low level of the first signal and the second signal is a third voltage, the first current supply unit is connected to a third power supply that supplies the third voltage, the current supply capacity of the first current supply terminal is relatively large when the first signal transitions to one of the first voltage and the third voltage at which the first transistor turns on, and becomes relatively small after the first period has elapsed since the first signal transitioned to the voltage at which the first transistor turns on, and the current supply capacity of the second current supply terminal is relatively large when the second signal transitions to one of the first voltage and the third voltage at which the second transistor turns on, and becomes relatively small after the first period has elapsed since the second signal transitioned to the voltage at which the second transistor turns on.

7. The semiconductor device according to claim 5, wherein the high level or low level of the first signal and the second signal is a third voltage, and the first current supply unit includes: a first constant current transistor having a first main electrode connected to a third power supply that supplies the third voltage, a second main electrode connected to the first current supply terminal, and a control electrode to which a fifth voltage is applied to control the amount of current to be constant; a second constant current transistor having a first main electrode connected to the third power supply, a second main electrode connected to the second current supply terminal, and a control electrode to which a fifth voltage is applied to control the amount of current to be constant; a first switch transistor having a first main electrode connected to the third power supply, a second main electrode connected to the first current supply terminal, and a control electrode to which the third signal is input; and a second switch transistor having a first main electrode connected to the third power supply, a second main electrode connected to the second current supply terminal, and a control electrode to which the fourth signal is input.

8. The semiconductor device according to claim 7, wherein the first signal, which is a voltage of the first voltage and the third voltage that turns on the first transistor, is input to the control electrode of the first transistor after the first period has elapsed, and the third signal, which is a voltage of the first voltage and the third voltage that turns off the first switch transistor, is input to the control electrode of the first switch transistor after the first period has elapsed, and the second signal, which is a voltage of the first voltage and the third voltage that turns on the second transistor, is input to the control electrode of the second switch transistor after the first period has elapsed.

9. The semiconductor device according to claim 1, further comprising a second voltage conversion unit connected to a third power supply that supplies the third voltage, the first current supply unit connected to a fourth power supply that supplies a fourth voltage, and outputting either or both of a third voltage conversion signal and a fourth voltage conversion signal obtained by level-shifting the high levels of the first voltage conversion signal and the second voltage conversion signal to the fourth voltage, wherein the high levels of the first signal and the second signal are a third voltage, the first current supply unit connected to a third power supply that supplies the third voltage, and the second current supply unit connected to a fourth power supply that supplies a fourth voltage.

10. The semiconductor device according to claim 2, further comprising: a second voltage conversion unit connected to an output terminal that outputs a fourth voltage, wherein the low levels of the first signal and the second signal are a third voltage; the first current supply unit is connected to a third power supply that supplies the third voltage; and the second voltage conversion unit is connected to a third output terminal that outputs a fourth voltage, and wherein the low levels of the first voltage conversion signal and the second voltage conversion signal are level-shifted to the fourth voltage to output either or both of a third voltage conversion signal and a fourth voltage conversion signal.

11. The semiconductor device according to claim 7 or 8, further comprising a second voltage conversion unit connected to a fourth power supply that supplies a fourth voltage or an output terminal that outputs a fourth voltage, and that outputs either or both of a third voltage conversion signal and a fourth voltage conversion signal obtained by level-shifting the high level or low level of the first voltage conversion signal and the second voltage conversion signal to the fourth voltage, wherein the second voltage conversion unit includes: a fifth transistor whose conduction state is controlled by the first voltage conversion signal; a sixth transistor whose conduction state is controlled by the second voltage conversion signal; and seventh and eighth transistors that are controlled in accordance with the conduction states of the fifth and sixth transistors.

12. The semiconductor device according to claim 11, wherein the first period is generated by the first delay circuit including transistors that are substantially the same as or similar in size to and have the same connection relationship as transistors included in the first voltage conversion section and the second voltage conversion section.

13. A semiconductor device according to any one of claims 6 to 9 and 11 to 12, comprising: a high-side switch transistor and a low-side switch transistor that output the first voltage based on a fifth signal and a sixth signal; and a boost circuit that receives the first voltage and generates the third voltage, wherein the first voltage and the third voltage change according to the fifth signal and the sixth signal.

14. The semiconductor device according to any one of claims 10 to 12, comprising: a high-side switch transistor and a low-side switch transistor that output the fourth voltage based on a fifth signal and a sixth signal; and a boost circuit that receives the fourth voltage and generates the second voltage, wherein the fourth voltage and the second voltage change according to the fifth signal and the sixth signal.

15. The semiconductor device according to claim 7, wherein the channels of the first transistor, the second transistor, the first constant current transistor, the second constant current transistor, the first switch transistor, and the second switch transistor are of a first conductivity type; the channels of the third transistor, the fourth transistor, and the diode-connected transistor are of a second conductivity type; the polarity of the third signal is the opposite phase of the first signal; and the polarity of the fourth signal is the opposite phase of the second signal.

16. The semiconductor device according to claim 11, wherein the channels of the first transistor, the second transistor, the first constant current transistor, the second constant current transistor, the first switch transistor, the second switch transistor, the seventh transistor, and the eighth transistor are of a first conductivity type; the channels of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the diode-connected transistor are of a second conductivity type; the polarity of the third signal is the opposite phase of the first signal; and the polarity of the fourth signal is the opposite phase of the second signal.

17. The semiconductor device according to any one of claims 7, 8, 11, 12, 15, and 16, wherein the current driving capability of the first switch transistor or the second switch transistor when turned on is greater than the current driving capability of the first constant current transistor or the second constant current transistor.

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