Transistor and method for manufacturing the same

Abstract

A transistor that may include a silicon carbide substrate. A silicon carbide drift layer formed on the silicon carbide substrate. The silicon carbide drift layer having a trench. A silicon layer formed within the trench in the silicon carbide drift layer. A well layer formed within the silicon carbide drift layer. A portion of the well layer over a portion of the silicon layer. A source layer formed within a portion of the well layer. An insulating layer formed within the trench over a portion of the silicon layer and surrounded by the well layer. A poly layer formed over the insulating layer within the trench and surrounded by the insulating layer.

Description

TRANSISTOR AND METHOD FOR MANUFACTURING SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to U.S. Non-Pro visional Patent Application No. 18 / 923,450, filed on October 22, 2024, and U.S. Provisional Patent Application No. 63 / 634,260, filed on April 15, 2024, the contents of which are hereby incorporated by reference in their entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to trench power semiconductor devices, and more specifically to a transistor having a hybrid trench that includes silicon carbide and silicon, and a method for manufacturing same.SUMMARY

[0003] According to an aspect of one or more examples, there is provided a transistor that may include a silicon carbide substrate, a silicon carbide drift layer formed on the silicon carbide substrate, the silicon carbide drift layer having a trench, a silicon layer formed within the trench in the silicon carbide drift layer, a well layer formed within the silicon carbide drift layer, a portion of the well layer over a portion of the silicon layer, a source layer formed within a portion of the well layer, an insulating layer formed within the trench over a portion of the silicon layer and surrounded by the well layer, and a poly layer formed over the insulating layer within the trench and surrounded by the insulating layer. The silicon carbide substrate may comprise a first concentration of a first type dopant. The silicon carbide drift layer may comprise a second concentration of the first type dopant, the first concentration may be greater than the second concentration. The well layer may comprise a third concentration of a second type dopant. The insulating layer may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The firsttype dopant may comprise an n-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.

[0004] According to an aspect of one or more examples, there is provided a transistor that may include a silicon carbide substrate, a silicon carbide drift layer formed on the silicon carbide substrate, the silicon carbide drift layer having a protruding portion, a well layer formed within the silicon carbide drift layer, the well layer surrounded by the protruding portion of the silicon carbide drift layer, a source layer formed within a portion of the well layer, a silicon layer formed over a portion of the well layer and formed over the protruding portion of the silicon carbide drift layer, an insulating layer formed over the silicon layer and formed over a portion of the source layer, and a poly layer formed over the insulating layer. The silicon carbide substrate may comprise a first concentration of a first type dopant. The silicon carbide drift layer may comprise a second concentration of the first type dopant, the first concentration may be greater than the second concentration. The well layer may comprise a third concentration of a second type dopant. The insulating layer may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The first type dopant may comprise an n-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.

[0005] According to an aspect of one or more examples, there is provided a method of manufacturing a transistor. The method may include providing a silicon carbide substrate, forming a silicon carbide drift layer on the silicon carbide substrate, forming a trench into the silicon carbide drift layer, forming a silicon layer within the trench of the silicon carbide drift layer, implanting a well layer into the silicon carbide drift layer, a portion of the well layer over a portion of the siliconlayer, forming a source layer within a portion of the well layer, forming an insulating layer within the trench over a portion of the silicon layer and surrounded by the well layer, and forming a poly layer over the insulating layer within the trench over a portion of the silicon layer and surrounded by the insulating layer. The silicon carbide substrate may comprise a first concentration of a first type dopant. The silicon carbide drift layer may comprise a second concentration of the first type dopant, the first concentration may be greater than the second concentration. The well layer may comprise a third concentration of a second type dopant. The insulating layer may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The first type dopant may comprise an n-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.

[0006] According to an aspect of one or more examples, there is provided a method of manufacturing a transistor. The method may include providing a silicon carbide substrate, forming a silicon carbide drift layer on the silicon carbide substrate, bonding a silicon layer to the silicon carbide drift layer, forming a trench into the silicon layer, implanting a well layer into the silicon layer, forming a source layer within a portion of the well layer, forming an insulating layer within the trench over a portion of the silicon layer and surrounded by the well layer, and forming a poly layer over the insulating layer within the trench over a portion of the silicon layer and surrounded by the insulating layer. The silicon carbide substrate may comprise a first concentration of a first type dopant. The silicon carbide drift layer may comprise a second concentration of the first type dopant, the first concentration may be greater than the second concentration. The well layer may comprise a third concentration of a second type dopant. The insulating layer may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The first type dopant may comprise ann-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 A shows a transistor according to one or more examples.

[0008] FIG. IB shows a transistor according to one or more examples.

[0009] FIGS. 2A through 2G show a method of manufacturing a transistor according to one or more examples.

[0010] FIGS. 3A through 3G show a method of manufacturing a transistor according to one or more examples.DETAILED DESCRIPTION OF VARIOUS EXAMPLES

[0011] Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be embodied in various forms without being limited to the examples set forth herein.

[0012] Silicon carbide (SiC) is often used as a substrate to create many semiconductor devices, and may result in reduced switching losses, higher power density, improved heat dissipation, and increased bandwidth as compared with other materials. For example SiC is often used in metal-oxide-semiconductor field-effect transistors (MOSFETs), including trench MOSFETs. However, electron mobility in SiC is relatively low and results in a higher resistance than may be suitable for certain applications. Therefore, there is a need for a transistor that that may improve carrier mobility and reduce resistance.

[0013] FIG. 1A shows a transistor 10 according to one or more examples. The example transistor 10 shown in FIG. 1A may include a silicon carbide substrate 20. The silicon carbidesubstrate 20 may comprise a first concentration of a first type dopant. The example transistor 10 shown in FIG. 1A may include a silicon carbide drift layer 40 formed a first side of the silicon carbide substrate 20. The silicon carbide drift layer 40 may comprise a second concentration of the first type dopant. The first concentration of first type dopant in the silicon carbide substrate 20 may be greater than the second concentration of first type dopant in the silicon carbide drift layer 40. In the example transistor 10 shown in FIG. 1A, a drain contact 30 may be formed on a second side of the substrate 20. The drain contact 30 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. 1A, a silicon layer 100 may be formed within a trench 45 in the silicon carbide drift layer 40. In the example transistor 10 shown in FIG. 1A, a well layer 70 may be implanted within the silicon carbide drift layer 40. A portion of the well layer 70 may be over a portion of the silicon layer 100. The well layer 70 may comprise a third concentration of a second type dopant. The example transistor 10 shown in FIG. 1A may also include a source layer 110 formed within a portion of the well layer 70. The source layer 110 may comprise a fourth concentration of the first type dopant. The example transistor 10 shown in FIG. 1 A may include a body layer 120 formed within a portion of the well layer 70. The example transistor 10 shown in FIG. 1A may include a source contact 115 operatively connected to the source layer 110 and the body layer 120. The source contact 115 may be made from a metal, polysilicon, or other suitable material. The example transistor 10 shown in FIG. 1A may also include an insulating layer 130 formed over a portion of the silicon layer 100 and surrounded by the well layer 70 and the source layer 110. The insulating layer 130 may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The example transistor 10 shown in FIG. 1A may also include a poly layer 140 formed over the insulating layer 130. The poly layer 140 may comprise a metal and / or polysilicon. In FIG. 1A, the example transistor 10 may include a gateelectrode 145 connected to the poly layer 140. The gate electrode 145 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. 1A, the trench 45 created in the silicon carbide drift layer 40 creates a channel by which charge carriers flow from the gate terminal 145 to the drain terminal 30. The use of silicon for the silicon layer 100 and silicon carbide for the drift layer 40 creates a hybrid channel. Silicon has a greater electron mobility than silicon carbide, which may result in the hybrid channel being able to accommodate higher current, and having a lower resistance than a channel having only silicon carbide.

[0014] In the example transistor 10 of FIG. 1A, the first type dopant may be an n-type dopant with the second type dopant being a p-type dopant. Alternatively, the first type dopant may be a p-type dopant with the second type dopant being an n-type dopant.

[0015] FIG. IB shows a transistor 10 according to one or more examples. The example transistor 10 shown in FIG. IB may include a silicon carbide substrate 20. The silicon carbide substrate 20 may comprise a first concentration of a first type dopant. The example transistor 10 shown in FIG. IB may include a silicon carbide drift layer 40 formed a first side of the silicon carbide substrate 20. The silicon carbide drift layer 40 may have a protruding portion 50. The silicon carbide drift layer 40 may comprise a second concentration of the first type dopant. The first concentration of first type dopant in the silicon carbide substrate 20 may be greater than the second concentration of first type dopant in the silicon carbide drift layer 40. In the example transistor 10 shown in FIG. IB, a drain contact 30 may be formed on a second side of the substrate 20. The drain contact 30 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. IB, a well layer 70 may be formed within the silicon carbide drift layer 40. The well layer 70 may be surrounded by the protruding portion 50 of the silicon carbide drift layer 40. The well layer 70 may comprise a third concentration of a second typedopant. The example transistor 10 shown in FIG. IB may also include a source layer 110 formed within a portion of the well layer 70. The source layer 110 may comprise a fourth concentration of the first type dopant. The example transistor 10 shown in FIG. IB may include a body layer 120 formed within a portion of the well layer 70. The example transistor 10 shown in FIG. IB may include a source contact 115 operatively connected to the source layer 110 and the body layer 120. The source contact 115 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. IB, a silicon layer 100 may be formed over a portion of the well layer 70 and may be formed over the protruding portion 50 of the silicon carbide drift layer 40. The example transistor 10 shown in FIG. IB may include an insulating layer 130 that may be formed over the silicon layer 100 and may be formed over a portion of the source layer 110. The insulating layer 130 may comprise polysilicon, oxide or a mixture of polysilicon and oxide. The example transistor 10 shown in FIG. IB may also include a poly layer 140 that may be formed over the insulating layer 130. The poly layer 140 may comprise a metal and / or polysilicon. In FIG. IB, the example transistor 10 may include a gate electrode 145 connected to the poly layer 140. The gate electrode 145 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. IB, the protruding portion 50 of the silicon carbide drift layer 40 creates a channel by which charge carriers flow from the gate terminal 145 to the drain terminal 30. The use of silicon for the silicon layer 100 and silicon carbide for the drift layer 40 creates a hybrid channel. Silicon has a greater electron mobility than silicon carbide, which may result in the hybrid channel being able to accommodate higher current, and having a lower resistance than a channel having only silicon carbide.

[0016] In the example transistor 10 of FIG. IB, the first type dopant may be an n-type dopant with the second type dopant being a p-type dopant. Alternatively, the first type dopant may be a p-type dopant with the second type dopant being an n-type dopant.

[0017] FIGS. 2A-2G show a method of manufacturing a transistor 10 according to one or more examples. Although the example method shown in FIGS. 2A-2G include steps shown in a particular order, the steps may be performed in a different order, and may include additional steps that are not explicitly shown. In addition, each step presented herein may have multi-steps necessary to carry out the stated step that are not explicitly shown or stated herein.

[0018] FIG. 2A is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2A, the example method may include providing a silicon carbide substrate 20 that may have a first concentration of a first type dopant. In FIG. 2A, the example method may include forming a silicon carbide drift layer 40 on a first side of the silicon carbide substrate 20. The silicon carbide drift layer 40 may have a second concentration of the first type dopant. The first concentration of first type dopant in the silicon carbide substrate 20 may be greater than the second concentration of first type dopant in the silicon carbide drift layer 40.

[0019] FIG. 2B is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2B, the example method may include forming a trench 45 into the silicon carbide drift layer 40.

[0020] FIG. 2C is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2C, the example method may include forming a silicon layer 100 within the trench 45 of the silicon carbide drift layer 40. The silicon layer 100 may be grown or deposited.

[0021] FIG. 2D is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2D, the example method may include implanting a well layer 70 into the silicon carbide drift layer 40. A portion of the well layer 70 may be over a portion of the silicon layer 100. The well layer 70 may comprise a third concentration of a second type dopant. In FIG. 2D, the example method may include implanting a body layer 120 that may be formed within a portion of the well layer 70. In FIG. 2D, the example method may include forming an insulating layer 130 within the trench 45 over a portion of the silicon layer 100 and surrounded by the well layer 70. The insulating layer 130 may comprise polysilicon, oxide or a mixture of polysilicon and oxide.

[0022] FIG. 2E is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2E, the example method may include forming a source layer 110 within a portion of the well layer 70. The source layer 110 may comprise a fourth concentration of the first type dopant.

[0023] FIG. 2F is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2F, the example method may include forming a poly layer 140 over the insulating layer 130 within the trench 45 over a portion of the silicon layer 100 and surrounded by the insulating layer 130. The poly layer 140 may comprise a metal and / or polysilicon. The poly layer 140 may be deposited or epitaxially grown in the trench 45 over the insulating layer 130. The insulating layer 130 and the poly layer 140 may extend to a top surface of the trench 45 that is coplanar with a top surface of the source layer 110.

[0024] FIG. 2G is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2G, the example method may include forming a drain contact 30 on a second side of the substrate 20. The drain contact 30 may be madefrom a metal, polysilicon, or other suitable material. In FIG. 2G, the example method may include forming a source contact 115 operatively connected to the source layer 110 and the body layer 120. The source contact 115 may be made from a metal, polysilicon, or other suitable material. In FIG. 2G, the example method may include forming a gate electrode 145 operatively connected to the poly layer 140. The gate electrode 145 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. 2G, the trench 45 created in the silicon carbide drift layer 40 creates a channel by which charge carriers flow from the gate terminal 145 to the drain terminal 30. The use of silicon for the silicon layer 100 and silicon carbide for the drift layer 40 creates a hybrid channel. Silicon has a greater electron mobility than silicon carbide, which may result in the hybrid channel being able to accommodate higher current, and having a lower resistance than a channel having only silicon carbide.

[0025] In the example transistor 10 of FIGS. 2A-2G, the first type dopant may be an n- type dopant with the second type dopant being a p-type dopant. Alternatively, the first type dopant may be a p-type dopant with the second type dopant being an n-type dopant.

[0026] FIGS. 3A-3G show a method of manufacturing a transistor 10 according to one or more examples. Although the example method shown in FIGS. 3A-3G include steps shown in a particular order, the steps may be performed in a different order, and may include additional steps that are not explicitly shown. In addition, each step presented herein may have multi-steps necessary to carry out the stated step that are not explicitly shown or stated herein.

[0027] FIG. 3A is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3A, the example method may include providing a silicon carbide substrate 20 that may have a first concentration of a first type dopant. In FIG. 3A, the example method may includeforming a silicon carbide drift layer 40 on a first side of the silicon carbide substrate 20. The silicon carbide drift layer 40 may have a second concentration of the first type dopant. The first concentration of first type dopant in the silicon carbide substrate 20 may be greater than the second concentration of first type dopant in the silicon carbide drift layer 40.

[0028] FIG. 3B is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3B, the example method may include bonding a silicon layer 100 to the silicon carbide drift layer 40.

[0029] FIG. 3C is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3C, the example method may include forming a trench 45 into the silicon layer 100.

[0030] FIG. 3D is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3D, the example method may include implanting a well layer 70 into the silicon layer 100. The well layer 70 may comprise a third concentration of a second type dopant. In FIG. 3D, the example method may include implanting a body layer 120 that may be formed within a portion of the well layer 70. In FIG. 3D, the example method may include forming an insulating layer 130 within the trench 45 over a portion of the silicon layer 100 and surrounded by the well layer 70. The insulating layer 130 may comprise polysilicon, oxide or a mixture of polysilicon and oxide.

[0031] FIG. 3E is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3E, the example method mayinclude forming a source layer 110 within a portion of the well layer 70. The source layer 110 may comprise a fourth concentration of the first type dopant.

[0032] FIG. 3F is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3F, the example method may include forming a poly layer 140 over the insulating layer 130 within the trench 45 over a portion of the silicon layer 100 and surrounded by the insulating layer 130. The poly layer 140 may comprise a metal and / or polysilicon. The poly layer 140 may be deposited or epitaxially grown in the trench 45 over the insulating layer 130. The insulating layer 130 and the poly layer 140 may extend to a top surface of the trench 45 that is coplanar with a top surface of the source layer 110.

[0033] FIG. 3G is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 3G, the example method may include forming a drain contact 30 on a second side of the substrate 20. The drain contact 30 may be made from a metal, polysilicon, or other suitable material. In FIG. 3G, the example method may include forming a source contact 115 operatively connected to the source layer 110 and the body layer 120. The source contact 115 may be made from a metal, polysilicon, or other suitable material. In FIG. 3G, the example method may include forming a gate electrode 145 operatively connected to the poly layer 140. The gate electrode 145 may be made from a metal, polysilicon, or other suitable material. In the example transistor 10 shown in FIG. 3G, the trench 45 created in the silicon layer 100 creates a channel by which charge carriers flow from the gate terminal 145 through the silicon carbide drift layer 40 to the drain terminal 30. The use of silicon for the silicon layer 100 and silicon carbide for the drift layer 40 creates a hybrid channel. Silicon has agreater electron mobility than silicon carbide, which may result in the hybrid channel being able to accommodate higher current, and having a lower resistance than a channel having only silicon carbide.

[0034] In the example transistor 10 of FIGS. 3A-3G, the first type dopant may be an n- type dopant with the second type dopant being a p-type dopant. Alternatively, the first type dopant may be a p-type dopant with the second type dopant being an n-type dopant.

[0035] Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and sub combination of these examples. Accordingly, all examples may be combined in any way and / or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0036] It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.

Claims

What is claimed is:

1. A transistor comprising: a silicon carbide substrate; a silicon carbide drift layer formed on the silicon carbide substrate, the silicon carbide drift layer having a trench; a silicon layer formed within the trench in the silicon carbide drift layer; a well layer formed within the silicon carbide drift layer, a portion of the well layer over a portion of the silicon layer; a source layer formed within a portion of the well layer; an insulating layer formed within the trench over a portion of the silicon layer and surrounded by the well layer; and a poly layer formed over the insulating layer within the trench and surrounded by the insulating layer.

2. The transistor of claim 1, wherein the silicon carbide substrate comprises a first concentration of a first type dopant and the silicon carbide drift layer comprises a second concentration of the first type dopant, the first concentration is greater than the second concentration.

3. The transistor of claim 2, wherein the well layer comprises a third concentration of a second type dopant.

4. The transistor of claim 3, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

5. The transistor of claim 3, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.

6. A transistor comprising: a silicon carbide substrate; a silicon carbide drift layer formed on the silicon carbide substrate, the silicon carbide drift layer having a protruding portion; a well layer formed within the silicon carbide drift layer, the well layer surrounded by the protruding portion of the silicon carbide drift layer; a source layer formed within a portion of the well layer; a silicon layer formed over a portion of the well layer and formed over the protruding portion of the silicon carbide drift layer; an insulating layer formed over the silicon layer and formed over a portion of the source layer; and a poly layer formed over the insulating layer.

7. The transistor of claim 6, wherein the silicon carbide substrate comprises a first concentration of a first type dopant and the silicon carbide drift layer comprises a second concentration of the first type dopant, the first concentration is greater than the second concentration.

8. The transistor of claim 7, wherein the well layer comprises a third concentration of a second type dopant.

9. The transistor of claim 8, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

10. The transistor of claim 8, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.

11. A method of manufacturing a transistor, the method comprising: providing a silicon carbide substrate; forming a silicon carbide drift layer on the silicon carbide substrate; forming a trench into the silicon carbide drift layer; forming a silicon layer within the trench of the silicon carbide drift layer; implanting a well layer into the silicon carbide drift layer, a portion of the well layer over a portion of the silicon layer; forming a source layer within a portion of the well layer; forming an insulating layer within the trench over a portion of the silicon layer and surrounded by the well layer; and forming a poly layer over the insulating layer within the trench over a portion of the silicon layer and surrounded by the insulating layer.

12. The method of claim 11, wherein the silicon carbide substrate comprises a first concentration of a first type dopant and the silicon carbide drift layer comprises a second concentration of the first type dopant, the first concentration is greater than the second concentration.

13. The method of claim 12, wherein the well layer comprises a third concentration of a second type dopant.

14. The method of claim 13, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

15. The method of claim 13, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.

16. A method of manufacturing a transistor, the method comprising: providing a silicon carbide substrate; forming a silicon carbide drift layer on the silicon carbide substrate; bonding a silicon layer to the silicon carbide drift layer; forming a trench into the silicon layer; implanting a well layer into the silicon layer; forming a source layer within a portion of the well layer; forming an insulating layer within the trench over a portion of the silicon layer and surrounded by the well layer; and forming a poly layer over the insulating layer within the trench over a portion of the silicon layer and surrounded by the insulating layer.

17. The method of claim 16, wherein the silicon carbide substrate comprises a first concentration of a first type dopant and the silicon carbide drift layer comprises a second concentration of the first type dopant, the first concentration is greater than the second concentration.

18. The method of claim 17, wherein the well layer comprises a third concentration of a second type dopant.

19. The method of claim 18, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

20. The method of claim 18, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.

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