Supporting multiple power amplifier circuits of different power classes INA power management circuit

Abstract

Supporting multiple power amplifier circuits of different power classes in a power management circuit is disclosed. The power management circuit includes multiple power amplifier circuits and a power management integrated circuit (PMIC). Herein, the power amplifier circuits can belong to different power classes (e.g., power classes 2 and 3) and the PMIC can generate different modulated voltages to drive the power amplifier circuits to different maximum power levels (e.g., 26 dBm and 23 dBm). In embodiments disclosed herein, the PMIC is configured to flexibly distribute the modulated voltages based on respective output power levels of the power amplifier circuits. As such, the power management circuit can be provided in a wireless device to enable multiple simultaneous transmissions based on power amplifier circuits of different power classes.

Description

SUPPORTING MULTIPLE POWER AMPLIFIER CIRCUITS OF DIFFERENT POWER CLASSES INA POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 635,845, filed on April 18, 2024, and U.S. provisional patent application serial number 63 / 673,816, filed on July 22, 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management circuit that can support multiple power amplifier circuits of different power classes in a wireless device.Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] A state-of-the-art mobile communication device must be able to communicate a radio frequency (RF) signal(s) in a variety of wireless communication systems, such as long-term evolution (LTE) and new radio (NR), based on a variety of transmit / receive configurations, such as uplink / downlink multiple-input, multiple-output (UL / DL-MIMO), enhanced dual-connectivity (EN- DC), and diversity receive (DRX). As an example, many multi-transmission proposals have been made for third-generation partnership project (3GPP) release 18 to support concurrent UL-MIMO and EN-DC transmissions on multiple RF bands. In this regard, a wireless communication device is required toconcurrently transmit at least three RF signals (2xMIMO + 1 xEN-DC). In this regard, the mobile communication device must employ a power management circuit that can simultaneously support multiple power amplifiers to enable multiple concurrent transmissions.

[0005] Embodiments of the disclosure relate to supporting multiple power amplifier circuits of different power classes in a power management circuit. The power management circuit includes multiple power amplifier circuits and a power management integrated circuit (PMIC). Herein, the power amplifier circuits can belong to different power classes (e.g., power classes 2 and 3) and the PMIC can generate different modulated voltages to drive the power amplifier circuits to different maximum power levels (e.g., 26 dBm and 23 dBm). In embodiments disclosed herein, the PMIC is configured to flexibly distribute the modulated voltages based on respective output power levels of the power amplifier circuits. As such, the power management circuit can be provided in a wireless device to enable multiple simultaneous transmissions based on power amplifier circuits of different power classes.

[0006] In one aspect, a power management circuit is provided. The power management circuit includes multiple power amplifier circuits. Each of the multiple power amplifier circuits is configured to amplify a signal based on a respective one or more multiple modulated voltages. The power management circuit also includes a PMIC. The PMIC includes a first voltage modulation circuit. The first voltage modulation circuit is configured to generate a first one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal up to a first maximum power level. The PMIC also includes a second voltage modulation circuit. The second voltage modulation circuit is configured to generate a second one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level. The PMIC also includes a control circuit. The controlcircuit is configured to determine that a first one of the multiple power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the multiple power amplifier circuits is configured to amplify the signal to be below the second maximum power level. The control circuit is also configured to cause the first one of the multiple modulated voltages to be provided to the first one of the multiple power amplifier circuits. The control circuit is also configured to cause the second one of the multiple modulated voltages to be provided to the second one of the multiple power amplifier circuits.

[0007] In another aspect, a wireless device is provided. The wireless device includes a power management circuit. The power management circuit includes multiple power amplifier circuits. Each of the multiple power amplifier circuits is configured to amplify a signal based on a respective one or more multiple modulated voltages. The power management circuit also includes a PMIC. The PMIC includes a first voltage modulation circuit. The first voltage modulation circuit is configured to generate a first one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal up to a first maximum power level. The PMIC also includes a second voltage modulation circuit. The second voltage modulation circuit is configured to generate a second one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level. The PMIC also includes a control circuit. The control circuit is configured to determine that a first one of the multiple power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the multiple power amplifier circuits is configured to amplify the signal to be below the second maximum power level. The control circuit is also configured to cause the first one of the multiple modulated voltages to be provided to the first one of the multiple power amplifier circuits. The control circuit is also configured to cause the second one of the multiple modulated voltages to be provided to the second one of the multiple power amplifier circuits.

[0008] In another aspect, a method for supporting multiple power amplifier circuits in a power management circuit is provided. The method includes configuring multiple power amplifier circuits to each amplify a signal based on a respective one or more of multiple modulated voltages. The method also includes generating a first one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal up to a first maximum power level. The method also includes generating a second one of the multiple modulated voltages that can drive any one of the multiple power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level. The method also includes determining that a first one of the multiple power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the multiple power amplifier circuits is configured to amplify the signal to be below the second maximum power level. The method also includes causing the first one of the multiple modulated voltages to be provided to the first one of the multiple power amplifier circuits. The method also includes causing the second one of the multiple modulated voltages to be provided to the second one of the multiple power amplifier circuits.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1 is a schematic diagram of an exemplary power management circuit wherein a power management integrated circuit (PMIC) is configured according to an embodiment of the present disclosure to support multiple power amplifier circuits of different power classes;

[0012] Figure 2 is a schematic diagram of an exemplary voltage modulation circuit in the PMIC of Figure 1 ;

[0013] Figure 3 is a schematic diagram of an exemplary dual-output voltage conversion circuit in the PMIC of Figure 1 ;

[0014] Figures 4A-40 are schematic diagrams illustrating various operating scenarios of the power management circuit of Figure 1 ;

[0015] Figure 5 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 1 can be provided; and

[0016] Figure 6 is a flowchart of an exemplary process for supporting the power amplifier circuits in the power management circuit of Figure 1 .Detailed Description

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being"directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaningthat is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Embodiments of the disclosure relate to supporting multiple power amplifier circuits of different power classes in a power management circuit. The power management circuit includes multiple power amplifier circuits and a power management integrated circuit (PMIC). Herein, the power amplifier circuits can belong to different power classes (e.g., power classes 2 and 3) and the PMIC can generate different modulated voltages to drive the power amplifier circuits to different maximum power levels (e.g., 26 dBm and 23 dBm). In embodiments disclosed herein, the PMIC is configured to flexibly distribute the modulated voltages based on respective output power levels of the power amplifier circuits. As such, the power management circuit can be provided in a wireless device to enable multiple simultaneous transmissions based on power amplifier circuits of different power classes.

[0024] Figure 1 is a schematic diagram of an exemplary power management circuit 10 wherein a PMIC 12 is configured according to an embodiment of the present disclosure to support a first power amplifier circuit 14A and a second power amplifier circuit 14B. In a non-limiting example, the first power amplifier circuit 14A is a power class 2 power amplifier with a first output power POUTI up to a first maximum power level PMAXI of 26 dBm (Poun < PMAXI), whereas the second power amplifier circuit 14B is a class 3 power amplifier with a second output power POUT2 up to a second maximum power level PMAX2 of 23 dBm (POUT2 < PMAX2). In other words, the second maximum power level PMAX2 is one-half of the first maximum power level PMAXI (PMAX2 =1 / 2PMAXI ). In an embodiment, the first power amplifier circuit 14A and the second power amplifier circuit 14B can be configured to amplify a signal 16 for concurrent transmission via such schemes as uplink multiple-input multiple-output (UL-MIMO).

[0025] Understandably, the power management circuit 10 is not limited to support only power classes 2 and 3 power amplifiers. As an example, the power management circuit 10 may further include a third power amplifier circuit 14C thatcan amplify another signal 18 to an even higher output power level POUTS that can be higher than the first maximum power level PMAXI (POUTS > PMAXI) for transmission in, for example, a satellite channel. It should be appreciated that the power management circuit 10 may be further configured to include power amplifier circuits of additional power classes.

[0026] The PMIC 12 includes a first voltage modulation circuit 20 and a second voltage modulation circuit 22. Herein, the first voltage modulation circuit 20 is configured to generate a first modulated voltage Vcci that can drive any of the first power amplifier circuit 14A and the second power amplifier circuit 14B above the second maximum power level PMAXS and up to the first maximum power level PMAXI (> PMAXS but < PMAXI). In contrast, the second voltage modulation circuit 22 is configured to generate a second modulated voltage Vcc2 that can drive any of the first power amplifier circuit 14A and the second power amplifier circuit 14B up to the second maximum power level PMAX2 (< PMAX2). In this regard, the first voltage modulation circuit 20 and the second voltage modulation circuit 22 are configured to have different capabilities in terms of driving the maximum power levels. Nevertheless, the first voltage modulation circuit 20 and the second voltage modulation circuit 22 can be configured in accordance with an identical architecture.

[0027] In this regard, Figure 2 is a schematic diagram of an exemplary voltage modulation circuit 24, which can function as any of the first voltage modulation circuit 20 and the second voltage modulation circuit 22 in the PMIC 12 in Figure 1 . Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0028] The voltage modulation circuit 24 can include a voltage amplifier 26 and an offset capacitor COFF. When the voltage modulation circuit 24 functions as the first voltage modulation circuit 20, the voltage amplifier 26 is configured to generate an initial voltage VAMP based on a supply voltage VSUP and a first modulated target voltage VTGTI . The offset capacitor COFF is configured to raise the initial voltage VAMP by an offset voltage VOFF to thereby generate the first modulated voltage Vcci (Vcci = VAMP + VOFF).

[0029] When the voltage modulation circuit 24 functions as the second voltage modulation circuit 22, the voltage amplifier 26 is configured to generate the initial voltage VAMP based on the supply voltage VSUP and a second modulated target voltage VTGT2. The offset capacitor COFF is configured to raise the initial voltage VA P by the offset voltage VOFF to thereby generate the second modulated voltage Vcc2 (Vcc2 = VAMP + VOFF).

[0030] In one embodiment, the voltage modulation circuit 24 is configured to generate the first modulated voltage Vcci and / or the second modulated voltage Vcc2 as an envelope tracking (ET) voltage. In this regard, the voltage amplifier 26 may be configured to source and / or sink an alternating current IAC to help modulate the offset voltage VOFF. In another embodiment, the voltage modulation circuit 24 is configured to generate the first modulated voltage Vcci and / or the second modulated voltage Vcc2 as an average power tracking (APT) voltage. As such, it is not necessary for the voltage amplifier 26 to source and / or sink the alternating current IAC. Instead, the offset voltage VOFF can be adjusted by a first low-frequency current IDCI when the voltage modulation circuit 24 functions as the first voltage modulation circuit 20 or a second low-frequency current IDC2 when the voltage modulation circuit 24 functions as the second voltage modulation circuit 22.

[0031] With reference back to Figure 1 , the PMIC 12 is configured to also include a dual-output voltage conversion circuit 28 that provides the first low- frequency current IDCI and the second low-frequency current IDC2 to the first voltage modulation circuit 20 and the second voltage modulation circuit 22, respectively. Specifically, the dual-output voltage conversion circuit 28 includes a main multi-level charge pump (MCP) 30 and a lightweight MCP 32. The main MCP 30 and the lightweight MCP 32 are configured to simultaneously generate a first low-frequency voltage VDCI and a second low-frequency voltage VDC2, respectively. In a non-limiting example, each of the first low-frequency voltage VDCI and the second low-frequency voltage VDC2 can be a direct-current (DC) voltage.

[0032] In an embodiment, the main MCP 30 is a buck-boost DC-DC voltage conversion circuit that can toggle between a buck mode and a boost mode in accordance with a first duty cycle 34 to generate the first low-frequency voltage VDCI as a function (e.g., a multiple) of a battery voltage VBAT. The lightweight MCP 32, on the other hand, can be a buck-only DC-DC voltage conversion circuit that receives a transfer voltage VTX, which is higher than the battery voltage VBAT, from the main MCP 30. Accordingly, the lightweight MCP 32 can operate based on a second duty cycle 36 to generate the second low-frequency voltage VDC2 as a function (e.g., a fraction) of the transfer voltage VTX. In a non-limiting example, the first duty cycle 34 and the second duty cycle 36 can both be pulse-width modulation (PWM) signals. By operating based on the transfer voltage VTX that is higher than the battery voltage VBAT, it is possible to eliminate some components (e.g., capacitors) required for boosting the battery voltage VBAT in the lightweight MCP 32. As a result, it is possible to reduce the footprint of the lightweight MCP 32 and the dual-output voltage conversion circuit 28 as a whole.

[0033] In an embodiment, the main MCP 30 is configured to provide the transfer voltage VTX that equals 2XVBAT (VTX = 2XVBAT) to the lightweight MCP 32. The lightweight MCP 32 can be configured to toggle between a one-times multiple of the transfer voltage VTX (1 XVTX = 2XVBAT) , a one-half-times multiple of the transfer voltage VTX (0.5XVTX = 1 XVBAT), and a zero-times multiple of the transfer voltage VTX (O XVTX = O XVBAT) in accordance with the second duty cycle 36 to thereby generate the second low-frequency voltage VDC2.

[0034] Figure 3 is a schematic diagram providing an exemplary illustration of the dual-output voltage conversion circuit 28 in the PMIC 12 of Figure 1 .Common elements between Figures 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0035] In an embodiment, the main MCP 30 includes a first buck-boost voltage converter 38 and a second buck-boost voltage converter 40 that are coupled in parallel to each other. Herein, the first buck-boost voltage converter 38 and the second buck-boost voltage converter 40 are configured to alternately provide the transfer voltage VTX to the lightweight MCP 32. As described below,by configuring the first buck-boost voltage converter 38 and the second buckboost voltage converter 40 to alternately provide the transfer voltage VTX to the lightweight MCP 32, it is possible to ensure that the lightweight MCP 32 can consistently receive the transfer voltage TX that equals two times the battery voltage VBAT (VTX = 2XVBAT).

[0036] The main MCP 30 may be configured to include a first common switch SW_A and a second common switch SW_B. The first buck-boost voltage converter 38 includes a respective first switch SW1_1 coupled between the battery voltage VBAT and a respective first middle node NIA, a respective second switch SW1_2 coupled to the respective first middle node NIA, a respective third switch SW1_3 coupled between the battery voltage VBAT and a respective second middle node NIB, a respective fourth switch SW1_4 coupled to the respective second middle node NIB, and a respective fly capacitor Ci coupled between the respective first middle node NIA and the respective second middle node NI B.

[0037] The second buck-boost voltage converter 40 includes a respective first switch SW2_1 coupled between the battery voltage VBAT and a respective first middle node N2A, a respective second switch SW2_2 coupled to the respective first middle node N2A, a respective third switch SW2_3 coupled between the battery voltage VBAT and a respective second middle node N2B, a respective fourth switch SW2_4 coupled to the respective second middle node N2B, and a respective fly capacitor C2 coupled between the respective first middle node N2A and the respective second middle node N2B.

[0038] According to an embodiment of the present disclosure, the respective first middle node NIA in the first buck-boost voltage converter 38 and the respective first middle node N2A in the second buck-boost voltage converter 40 are each coupled to the lightweight MCP 32. Accordingly, the first buck-boost voltage converter 38 and the second buck-boost voltage converter 40 are configured to alternately provide the transfer voltage VTX to the lightweight MCP 32 by alternately coupling the respective first middle node NIA and the respective first middle node N2A to the lightweight MCP 32.

[0039] In a non-limiting example, the main MCP 30 can output 1 XVBAT by closing the first common switch SW_A and output OXVBAT by closing the second common switch SW_B. To output 2XVBAT, the main MCP 30 must first charge the first fly capacitor Ci and / or the second fly capacitor C2 to the battery voltage VBAT.

[0040] In an example, to configure the first buck-boost voltage converter 38 to output 2XVBAT, the respective first switch SW1_1 and the respective fourth switch SW1_4 are first closed, while the respective second switch SW1_2 and the respective third switch SW1_3 are opened, to thereby charge the first fly capacitor Ci to the battery voltage VBAT at the respective first middle node NIA. Subsequently, the respective second switch SW1_2 and the respective third switch SW1_3 are closed, while the respective first switch SW1_1 and the respective fourth switch SW1_4 are opened. As a result, the voltage at the respective first middle node NIA will be equal to 2XVBAT. Accordingly, the first buck-boost voltage converter 38 can output 2XVBAT and provide the transfer voltage VTX that is substantially equal to 2XVBAT to the lightweight MCP 32 via the respective first middle node NIA. Herein, the transfer voltage VTX is said to be substantially equal to (a.k.a. approximately equal to) 2XVBAT when a difference between the transfer voltage VTX is equal to plus-minus 1 % of 2XVBAT (VTX » 2XVBAT ± 1 %).

[0041] In another example, to configure the second buck-boost voltage converter 40 to output 2XVBAT, the respective first switch SW2_1 and the respective fourth switch SW2_4 are first closed, while the respective second switch SW2_2 and the respective third switch SW2_3 are opened, to thereby charge the second fly capacitor C2 to the battery voltage VBAT at the respective first middle node N2A. Subsequently, the respective second switch SW2_2 and the respective third switch SW2_3 are closed, while the respective first switch SW2_1 and the respective fourth switch SW2_4 are opened. As a result, the voltage at the respective first middle node N2A will be equal to 2XVBAT. Accordingly, the second buck-boost voltage converter 40 can output 2XVBAT andprovide the transfer voltage VTX that is substantially equal to 2XVBAT to the lightweight MOP 32 via the respective first middle node N2A.

[0042] In an embodiment, to ensure that the lightweight MCP 32 can consistently receive the transfer voltage TX that is substantially equal to 2XVBAT, the main MCP 30 can be configured to alternately charge the first fly capacitor Ci in the first buck-boost voltage converter 38 and the second fly capacitor C2 in the second buck-boost voltage converter 40. Specifically, the respective second switch SW1_2 and the respective third switch SW1_3 in the first buck-boost voltage converter 38 may be closed to provide the transfer voltage VTX that is substantially equal to 2XVBAT to the lightweight MCP 32 via the respective first middle node NIA. In the meantime, the respective first switch SW2_1 and the respective fourth switch SW2_4 in the second buck-boost voltage converter 40 are closed to charge the respective second fly capacitor C2 to the battery voltage VBAT. When the respective second fly capacitor C2 is charged up to the battery voltage VBAT, the respective second switch SW2_2 and the respective third switch SW2_3 in the second buck-boost voltage converter 40 may be closed to provide the transfer voltage VTX that is substantially equal to 2XVBAT to the lightweight MCP 32 via the respective first middle node N2A. In the meantime, the respective first switch SW1_1 and the respective fourth switch SW1_4 in the first buck-boost voltage converter 38 are closed to charge the respective first fly capacitor Ci to the battery voltage VBAT.

[0043] The lightweight MCP 32 includes a third common switch SW_C. The lightweight MCP 32 also includes a first switch SW3_1 , a second switch SW3_2, and a third switch SW3_3. Specifically, the first switch SW3_1 is coupled between the respective first middle node NIA in the first buck-boost voltage converter 38 and a common node 44, the second switch SW3_2 is coupled between the respective first middle node N2A in the second buck-boost voltage converter 40 and the common node 44, and the third switch SW3_3 is coupled to the common node 44. For an in-depth discussion of various configurations and operations of the dual-output voltage conversion circuit 28, please refer to U.S.Patent Application Number 19 / 038,799, entitled “DUAL OUTPUT VOLTAGE CONVERSION CIRCUIT IN A POWER MANAGEMENT CIRCUIT.”

[0044] With reference back to Figure 1 , the PMIC 12 also includes a first power inductor LPI and a second power inductor LP2. The first power inductor LPI is coupled to the main MCP 30 and configured to generate the first low-frequency current IDCI based on the first low-frequency voltage VDCI . The second power inductor LP2 is coupled to the lightweight MCP 32 and configured to generate the second low-frequency current IDC2 based on the second low-frequency voltage VDC2.

[0045] The PMIC 12 also includes a switching circuit 46. The switching circuit 46 is coupled to the first voltage modulation circuit 20, the first power inductor LPI , the second voltage modulation circuit 22, and the second power inductor L 2. In a non-limiting example, the switching circuit 46 includes multiple switches S1-1 ,51-2, S1-3, S2-1, S2-2, S2-3 that are coupled as illustrated. The PMIC 12 further includes a control circuit 48. As described in the exemplary operating scenarios in Figures 4A-4C, the control circuit 48 can control the switches S1-1 , S1-2, S1-3,52-1, S2-2, S2-3 in the switching circuit 46 to flexibly provide the first modulated voltage Vcm and / or the second modulated voltage Vcc2 to any of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and / or the third power amplifier circuit 14C.

[0046] Figures 4A-4C are schematic diagrams illustrating various operating scenarios of the power management circuit 10 of Figure 1 . Common elements between Figures 1 and 4A-4C are shown therein with common element numbers and will not be re-described herein.

[0047] Figure 4A illustrates a scenario where the first power amplifier circuit 14A is configured to amplify the signal 16 to the first output power POUTI that is above the second maximum power level PMAX2 (PMAXI > POUTI > PMAX2), whereas the second power amplifier circuit 14B is configured to concurrently amplify the signal 16 to the second output power POUT2 that is below the second maximum power level PMAX2 (POUT2 < PMAX2). In this regard, the control circuit 48 can close the switches S1-1 and S2-1 to thereby provide the first modulated voltage Vcci andthe second modulated voltage Vcc2 to the first power amplifier circuit 14A and the second power amplifier circuit 14B, respectively.

[0048] Figure 4B illustrates a scenario where the first power amplifier circuit 14A is configured to amplify the signal 16 to the first output power POUTI that is equal to the second maximum power level PMAX2 (POUTI = PMAX2), and the second power amplifier circuit 14B is also configured to concurrently amplify the signal 16 to the second output power POUT2 that is equal to the second maximum power level PMAX2 (POUT2 = PMAX2). In this regard, the control circuit 48 can close the switches S1-1 and S2-1 to thereby provide the first modulated voltage Vcm and the second modulated voltage Vcc2 to the first power amplifier circuit 14A and the second power amplifier circuit 14B, respectively.

[0049] Figure 4C illustrates a scenario where the third power amplifier circuit 14C is configured to amplify the signal 18 to the third output power POUTS that is above the first maximum power level PMAXI (POUTS > PMAXI ). In this regard, the control circuit 48 can close the switches S1-3 and S23 to thereby provide both the first modulated voltage Vcm and the second modulated voltage Vcc2 to the third power amplifier circuit 14C. In the meantime, the first power amplifier circuit 14A and the second power amplifier circuit 14B may be deactivated.

[0050] The power management circuit 10 of Figure 1 can be provided in a communication device (e.g., a wireless device) to support the embodiments described above. In this regard, Figure 5 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 10 of Figure 1 can be provided.

[0051] Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, base stations (e.g., eNB, gNB, etc.), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antennaswitching circuitry 1 10, multiple antennas 11 , and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 1 10 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0052] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0053] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0054] In an exemplary embodiment, the power management circuit 10 may be provided between the transmit circuitry 106 and the antenna switching circuitry 1 10. In another exemplary embodiment, the communication device 100 can also include more than one of the power management circuits 10.

[0055] In an embodiment, the power management circuit 10 can be configured to support multiple power amplifier circuits of different power classes in accordance with a process. In this regard, Figure 6 is a flowchart of an exemplary process 200 whereby the power management circuit 10 of Figure 1 can be configured to support the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C.

[0056] Herein, the process 200 includes configuring the power amplifier circuits 14A, 14B, 14C to each amplify the signal 16 or 18 based on a respective one or more of the first modulated voltage Vcm and the second modulated voltage Vcc2 (step 202). The process 200 also includes generating a first one of the first modulated voltage Vcci and the second modulated voltage Vcc2 that can drive any one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C to amplify the signal 16 or 18 up to the first maximum power level PMAXI (step 204). The process 200 also includes generating a second one of the first modulated voltage Vcci and the second modulated voltage cc2 that can drive any one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C to amplify the signal 16 or 18 to the second maximum power level PMAX2 lower than the first maximum power level PMAXI (step 206). The process 200 also includes determining that a first one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C is configured to amplify the signal 16 or 18 to be above the second maximum power level PMAX2, and a second one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C is configured to amplify the signal 16 or 18 to be below the second maximum power level PMAX2 (step 208). The process 200 also includes causing the first one of the first modulated voltage Vcci and the second modulatedvoltage Vcc2 to be provided to the first one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C (step 210). The process 200 also includes causing the second one of the first modulated voltage Vcci and the second modulated voltage Vcc2 to be provided to the second one of the first power amplifier circuit 14A, the second power amplifier circuit 14B, and the third power amplifier circuit 14C (step 212).

[0057] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A power management circuit comprising: a plurality of power amplifier circuits each configured to amplify a signal based on a respective one or more of a plurality of modulated voltages; and a power management integrated circuit (PMIC) comprising: a first voltage modulation circuit configured to generate a first one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal up to a first maximum power level; a second voltage modulation circuit configured to generate a second one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level; and a control circuit configured to: determine that a first one of the plurality of power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the plurality of power amplifier circuits is configured to amplify the signal to be below the second maximum power level; cause the first one of the plurality of modulated voltages to be provided to the first one of the plurality of power amplifier circuits; and cause the second one of the plurality of modulated voltages to be provided to the second one of the plurality of power amplifier circuits.

2. The power management circuit of claim 1 , wherein the control circuit is further configured to: determine that each of the plurality of power amplifier circuits is configured to amplify the signal to the second maximum power level; cause the first one of the plurality of modulated voltages to be provided to any one of the plurality of power amplifier circuits; and cause the second one of the plurality of modulated voltages to be provided to any other one of the plurality of power amplifier circuits.

3. The power management circuit of claim 1 , wherein the control circuit is further configured to: determine that a third one of the plurality of power amplifier circuits is configured to amplify the signal above the first maximum power level; and cause the plurality of modulated voltages to be provided to the third one of the plurality of power amplifier circuits.

4. The power management circuit of claim 1 , wherein the PMIC further comprises a switching circuit whereby the control circuit can cause any of the plurality of modulated voltages to be provided to any of the plurality of power amplifier circuits.

5. The power management circuit of claim 1 , wherein the first voltage modulation circuit and the second voltage modulation circuit each comprise: a voltage amplifier configured to generate an initial voltage based on a modulated target voltage; and an offset capacitor configured to raise the initial voltage by an offset voltage to thereby generate a respective one of the plurality of modulated voltages.

6. The power management circuit of claim 1 , wherein the PMIC further comprises a dual-output voltage conversion circuit, the dual-output voltage conversion circuit comprising: a main multi-level charge pump (MCP) configured to generate a first low- frequency voltage as a function of a battery voltage based on a first duty cycle; and a lightweight MCP configured to: receive a transfer voltage higher than the battery voltage from the main MCP; and generate a second low-frequency voltage as a function of the transfer voltage based on a second duty cycle.

7. The power management circuit of claim 6, wherein the transfer voltage is equal to two times the battery voltage.

8. The power management circuit of claim 6, wherein the main MCP comprises a first buck-boost voltage converter and a second buck-boost voltage converter coupled in parallel and configured to alternately provide the transfer voltage to the lightweight MCP via a respective first middle node.

9. A wireless device comprising a power management circuit, the power management circuit comprising: a plurality of power amplifier circuits each configured to amplify a signal based on a respective one or more of a plurality of modulated voltages; and a power management integrated circuit (PMIC) comprising: a first voltage modulation circuit configured to generate a first one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal up to a first maximum power level;a second voltage modulation circuit configured to generate a second one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level; and a control circuit configured to: determine that a first one of the plurality of power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the plurality of power amplifier circuits is configured to amplify the signal to be below the second maximum power level; cause the first one of the plurality of modulated voltages to be provided to the first one of the plurality of power amplifier circuits; and cause the second one of the plurality of modulated voltages to be provided to the second one of the plurality of power amplifier circuits.

10. The wireless device of claim 9, wherein the control circuit is further configured to: determine that each of the plurality of power amplifier circuits is configured to amplify the signal to the second maximum power level; cause the first one of the plurality of modulated voltages to be provided to any one of the plurality of power amplifier circuits; and cause the second one of the plurality of modulated voltages to be provided to any other one of the plurality of power amplifier circuits.1 1 . The wireless device of claim 9, wherein the control circuit is further configured to:determine that a third one of the plurality of power amplifier circuits is configured to amplify the signal above the first maximum power level; and cause the plurality of modulated voltages to be provided to the third one of the plurality of power amplifier circuits.

12. The wireless device of claim 9, wherein the PMIC further comprises a switching circuit whereby the control circuit can cause any of the plurality of modulated voltages to be provided to any of the plurality of power amplifier circuits.

13. The wireless device of claim 9, wherein the first voltage modulation circuit and the second voltage modulation circuit each comprise: a voltage amplifier configured to generate an initial voltage based on a modulated target voltage; and an offset capacitor configured to raise the initial voltage by an offset voltage to thereby generate a respective one of the plurality of modulated voltages.

14. The wireless device of claim 9, wherein the PMIC further comprises a dual-output voltage conversion circuit, the dual-output voltage conversion circuit comprising: a main multi-level charge pump (MCP) configured to generate a first low- frequency voltage as a function of a battery voltage based on a first duty cycle; and a lightweight MCP configured to: receive a transfer voltage higher than the battery voltage from the main MCP; and generate a second low-frequency voltage as a function of the transfer voltage based on a second duty cycle.

15. The wireless device of claim 14, wherein the transfer voltage is equal to two times the battery voltage.

16. The wireless device of claim 14, wherein the main MCP comprises a first buck-boost voltage converter and a second buck-boost voltage converter coupled in parallel and configured to alternately provide the transfer voltage to the lightweight MCP via a respective first middle node.

17. A method for supporting multiple power amplifier circuits in a power management circuit comprising: configuring a plurality of power amplifier circuits to each amplify a signal based on a respective one or more of a plurality of modulated voltages; generating a first one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal up to a first maximum power level; generating a second one of the plurality of modulated voltages that can drive any one of the plurality of power amplifier circuits to amplify the signal to a second maximum power level lower than the first maximum power level; determining that a first one of the plurality of power amplifier circuits is configured to amplify the signal to be above the second maximum power level and a second one of the plurality of power amplifier circuits is configured to amplify the signal to be below the second maximum power level; causing the first one of the plurality of modulated voltages to be provided to the first one of the plurality of power amplifier circuits; and causing the second one of the plurality of modulated voltages to be provided to the second one of the plurality of power amplifier circuits.

18. The method of claim 17, further comprising: determining that each of the plurality of power amplifier circuits is configured to amplify the signal to the second maximum power level; causing the first one of the plurality of modulated voltages to be provided to any one of the plurality of power amplifier circuits; and causing the second one of the plurality of modulated voltages to be provided to any other one of the plurality of power amplifier circuits.

19. The method of claim 17, further comprising: determining that a third one of the plurality of power amplifier circuits is configured to amplify the signal above the first maximum power level; and causing the plurality of modulated voltages to be provided to the third one of the plurality of power amplifier circuits.

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