Timing analysis method and apparatus, and device and medium

Abstract

Disclosed are a timing analysis method and apparatus, and a device and a medium. The method comprises: for each timing path to be analyzed among a plurality of timing paths to be analyzed, acquiring a clock time delay and a data time delay which correspond to the timing path to be analyzed; acquiring a reference clock time delay and a reference data time delay; and on the basis of the reference clock time delay and the reference data time delay, determining a timing analysis result corresponding to each timing path to be analyzed among the plurality of timing paths to be analyzed, wherein the timing analysis result corresponding to the timing path to be analyzed comprises a clock skew and a data skew which correspond to the timing path to be analyzed.

Description

Time series analysis methods, apparatus, equipment and media Technical Field

[0001] This application belongs to the field of circuit design technology, and in particular relates to a timing analysis method, apparatus, device and medium. Background Technology

[0002] Timing delay affects circuit performance and stability, making integrated circuit (IC) delay analysis crucial. With the development of ICs, large-scale (LSI) and very large-scale (VLSI) circuits have emerged, leading to a geometric increase in transistor density within ICs. Currently, delay analysis of ICs typically uses the `set_data_check` method in static timing analysis to check the delay of sequential circuits. However, this method is not only very slow but also provides unintuitive results, especially for VLSI circuits, where it is particularly inefficient. Therefore, related technologies for IC timing analysis are generally inefficient. Technical solutions

[0003] This application provides an implementation scheme that differs from related technologies, in order to solve the technical problem of low efficiency in timing analysis of integrated circuits in related technologies.

[0004] Firstly, this application provides a time series analysis method, including:

[0005] For each of the multiple timing paths to be analyzed, obtain the clock delay and data delay corresponding to the timing path to be analyzed;

[0006] Obtain the reference clock delay and reference data delay;

[0007] Based on the reference clock delay and the reference data delay, the timing analysis results corresponding to each of the multiple timing paths to be analyzed are determined, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

[0008] Secondly, this application provides a timing analysis apparatus, comprising:

[0009] The acquisition unit is used to acquire the clock delay and data delay corresponding to each of the multiple timing paths to be analyzed.

[0010] The acquisition unit is also used to acquire the reference clock delay and the reference data delay;

[0011] The determining unit is used to determine the timing analysis results corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

[0012] Thirdly, this application provides an electronic device, comprising:

[0013] Processor; and

[0014] Memory for storing the executable instructions of the processor;

[0015] The processor is configured to execute the first aspect, or any method in any possible implementation of the first aspect, by executing the executable instructions.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the first aspect, or any method in any possible implementation of the first aspect.

[0017] This application provides a method for obtaining clock and data delays for each of multiple timing paths to be analyzed; obtaining reference clock and data delays; and determining timing analysis results for each of the multiple timing paths to be analyzed based on the reference clock and data delays. The timing analysis results for each timing path to be analyzed include a scheme for determining clock and data offsets. By obtaining the clock and data delays for each of the multiple timing paths to be analyzed, and further obtaining reference clock and data delays, and determining the timing analysis results for each of the multiple timing paths to be analyzed based on the reference clock and data delays, the scheme provided in this application significantly improves processing speed compared to the traditional method of using `set_data_check` in STA for timing path analysis, thereby achieving the technical effect of improving the efficiency of timing path analysis for integrated circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0019] Figure 1 is a flowchart illustrating a timing analysis method provided in an embodiment of this application;

[0020] Figure 2 is a schematic diagram of the structure of a timing analysis device provided in an embodiment of this application;

[0021] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The embodiments of this application are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0023] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the solution can be implemented in a different order than that illustrated or described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] First, some terms used in the embodiments of this application will be explained below to facilitate understanding by those skilled in the art.

[0025] Timing analysis: Timing analysis is a crucial step in the sequential circuit design process. It typically includes clock skew analysis and data skew analysis of timing paths based on specific timing requirements or constraints. Through timing analysis, it is possible to identify timing violation paths in integrated circuits that pose a risk of timing violations, and then repair these risky timing paths.

[0026] STA: Static Timing Analysis, or STA for short, uses an exhaustive analysis method to extract all timing paths in the entire circuit, calculates the propagation delay of signals on these paths, checks whether the setup and hold times of signals meet timing requirements, and identifies and reports errors that violate timing constraints by analyzing the maximum and minimum path delays.

[0027] Clock skew refers to the difference in time it takes for a clock signal to arrive at different clock nodes in a digital circuit. For most digital integrated circuit systems, such as computer systems, various signals are synchronized according to the clock frequency of the system time pulse signal, so that these signals operate in the same rhythm. Ideally, the input signal switches and remains stable at its correct logic level before the effective level or signal edge of the next clock cycle arrives, thus ensuring that the behavior of the entire circuit system conforms to the preset parameters.

[0028] Data skew: The difference in propagation delay between individual bits of parallel data.

[0029] With the development of integrated circuits, large-scale circuits and very large-scale circuits have emerged. Correspondingly, the transistor density in integrated circuits has also increased exponentially. In ST, using the traditional set_data_check to check data offsets is not only very slow but also unintuitive, especially when using set_data_check for timing analysis on very large data buses.

[0030] To address the aforementioned technical problems, this application provides a timing analysis method, apparatus, device, and medium to solve the technical problem of low efficiency in timing analysis of integrated circuits in related technologies.

[0031] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0032] Figure 1 is a flowchart illustrating a timing analysis method provided in an exemplary embodiment of this application. The method can be applied to computing devices and includes at least the following steps S11-S13:

[0033] S11. For each of the multiple timing paths to be analyzed, obtain the clock delay and data delay corresponding to the timing path to be analyzed;

[0034] In some embodiments, when obtaining multiple timing paths to be analyzed, the get_timing_path command can be used to obtain the multiple timing paths to be analyzed corresponding to multiple data ports in the circuit to be analyzed.

[0035] Specifically, by opening the design file of the circuit to be analyzed in an EDA tool, and using the `get_timing_path` command in conjunction with the `-from`, `-to`, and `-through` commands, multiple timing paths can be obtained from the design file corresponding to each data port or bit to be analyzed. Here, `-from` specifies the source port corresponding to the data port or bit to be analyzed, `-to` specifies the target port, and `-through` specifies the intermediate node. For each data port or bit to be analyzed, a corresponding timing path can be obtained, including the specified source port, intermediate node, and target port. The data port or bit to be analyzed can be either the source port or the target port.

[0036] Alternatively, you can specify only the source and destination ports for the data port or bits to be analyzed, without specifying intermediate nodes.

[0037] In other embodiments, multiple timing paths to be analyzed are pre-stored in a database, and multiple timing paths to be analyzed can be obtained from the database.

[0038] In some embodiments, obtaining the clock delay of the clock path corresponding to the timing path to be analyzed and the data delay of the data path includes:

[0039] Use the get_attribute command to obtain the clock delay of the clock path and the data delay of the data path corresponding to the timing path to be analyzed.

[0040] Specifically, get_attribute and get_timing_path are both commands provided in STA.

[0041] S12, Obtain the reference clock delay and reference data delay;

[0042] In some embodiments, the reference clock delay and reference data delay can be set by relevant personnel according to the actual design requirements of the circuit to be analyzed, so as to better realize the timing analysis of multiple timing paths to be analyzed.

[0043] In some other embodiments, in S12, obtaining the reference clock delay and the reference data delay includes:

[0044] One timing path to be analyzed is selected from the multiple timing paths to be analyzed as the reference timing path, and the clock delay and data delay corresponding to the reference timing path are respectively used as the reference clock delay and reference data delay.

[0045] In some embodiments, determining a timing path to be analyzed from the plurality of timing paths to be analyzed specifically includes: randomly selecting a timing path to be analyzed from the plurality of timing paths to be analyzed as a reference timing path.

[0046] In other embodiments, determining a timing path to be analyzed from the plurality of timing paths to be analyzed specifically includes: relevant personnel selecting a timing path to be analyzed from the plurality of timing paths to be analyzed as a reference timing path based on the actual design requirements of the circuit to be analyzed.

[0047] S13. Based on the reference clock delay and the reference data delay, determine the timing analysis results corresponding to each of the multiple timing paths to be analyzed, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

[0048] In some embodiments, S13, determining the timing analysis result corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay includes:

[0049] For each of the multiple timing paths to be analyzed, the clock delay corresponding to the timing path to be analyzed is subtracted from the reference clock delay to obtain the clock offset corresponding to the timing path to be analyzed, and the data delay corresponding to the timing path to be analyzed is subtracted from the reference data delay to obtain the data offset corresponding to the timing path to be analyzed.

[0050] In some embodiments, the clock delay and data delay corresponding to multiple timing paths to be analyzed can be recorded separately. Then, for each timing path to be analyzed, a polling comparison is performed based on the clock delay and data delay of each timing path to be analyzed. The calculation of subtracting the reference clock delay from the clock delay of the timing path to be analyzed and the calculation of subtracting the reference data delay from the data delay of the timing path to be analyzed are performed one by one to obtain the clock offset and data offset of each timing path to be analyzed.

[0051] In some embodiments, both clock offset and data offset are positive numbers.

[0052] Accordingly, when determining the timing analysis results for each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay, for each of the multiple timing paths to be analyzed, if the result obtained by subtracting the reference clock delay from the clock delay corresponding to the timing path to be analyzed is negative, then the absolute value of the result is taken as the clock offset corresponding to the timing path to be analyzed; if the result obtained by subtracting the reference data delay from the data delay corresponding to the timing path to be analyzed is negative, then the absolute value of the result is taken as the data offset corresponding to the timing path to be analyzed.

[0053] In some embodiments, after obtaining the timing analysis results corresponding to each of the multiple timing paths to be analyzed, the data such as the name of the data port or bit to be analyzed, clock delay, data delay, clock offset, and data offset corresponding to each of the multiple timing paths to be analyzed can be stored.

[0054] In some embodiments, the method further comprises:

[0055] For each of the multiple timing paths to be analyzed, it is determined whether the total offset corresponding to each timing path to be analyzed is greater than a preset threshold. Each timing path to be analyzed corresponds to a preset threshold, and the total offset is equal to the sum of the absolute values ​​of the clock offset and the absolute values ​​of the data offset corresponding to each timing path to be analyzed.

[0056] If so, determine that the timing path to be analyzed has a timing violation risk, and add the timing analysis results corresponding to the timing path to be analyzed to the target set.

[0057] In some embodiments, each timing path to be analyzed corresponds to a preset threshold, which represents the maximum value of the sum of the clock offset and data offset corresponding to the timing path to be analyzed. Specifically, the preset threshold is set according to the design specifications of the circuit to be analyzed. The preset threshold may be different for different timing paths to be analyzed. For timing paths with high latency requirements, the corresponding preset threshold is relatively small, and for timing paths with low latency requirements, the corresponding preset threshold is relatively large. This application does not limit the specific value of the preset threshold corresponding to the timing path to be analyzed.

[0058] In some embodiments, each time series path to be analyzed in the target set is sorted according to the total offset value in the time series analysis results corresponding to the time series path to be analyzed. For multiple time series paths to be analyzed with equal total offset values, they are sorted according to the values ​​of multiple preset thresholds corresponding to the multiple time series paths to be analyzed.

[0059] For example, each time series path to be analyzed in the target set is sorted from largest to smallest according to the total offset value in the time series analysis results corresponding to the time series path to be analyzed. For multiple time series paths to be analyzed with equal total offset values, they are sorted from largest to smallest according to multiple preset thresholds corresponding to the multiple time series paths to be analyzed.

[0060] In some embodiments, for each timing path to be analyzed, the data delay and clock delay corresponding to the timing path to be analyzed can also be added to the target set along with the timing analysis results.

[0061] Since all timing paths in the target set are timing paths with timing violation risks, based on the target set, for all timing paths to be analyzed, the timing paths with timing violation risks and their corresponding timing analysis results can be quickly obtained. For example, it can quickly determine which timing path has the largest total offset, i.e., which timing path has the greatest timing violation risk, and its clock offset and data offset, etc. By reviewing the target set obtained according to the scheme provided in this application, relevant personnel can quickly and efficiently identify timing paths with abnormal timing analysis results, and further determine the abnormal data ports or bits that violate circuit design requirements. It can also efficiently determine whether the abnormality is caused by clock offset or data offset, facilitating timing convergence of the circuit under analysis.

[0062] This application uses the `get_timing_path` command in the STA (Station Analysis Tool) to obtain the timing paths corresponding to each data port in the circuit under analysis. It then uses the `get_attribute` command to obtain the clock and data delays corresponding to each timing path. The names of the data ports under analysis, along with their clock and data delays, are recorded. After obtaining the clock and data delays of the timing paths corresponding to each data port, the clock and data delays are compared with reference clock and reference data delays to calculate the clock offset, data offset, and total offset (the sum of the absolute values ​​of the clock and data offsets) for each timing path under analysis. This determines whether the data port or bit corresponding to each timing path is positively or negatively biased, and the data is arranged in order of magnitude of the offset. This allows for efficient identification of which data ports or bits to be analyzed have significant transmission delays, which data ports or bits to be analyzed have abnormal transmission delays (i.e., violate design requirements), and whether the abnormality is caused by the clock path or the data path corresponding to the timing path to be analyzed for the data port or bit. It also determines whether the clock delay of the clock path or the data delay of the data path has a greater impact.

[0063] This application provides a method for obtaining clock and data delays for each of multiple timing paths to be analyzed; obtaining reference clock and data delays; and determining timing analysis results for each of the multiple timing paths to be analyzed based on the reference clock and data delays. The timing analysis results for each timing path to be analyzed include a scheme for determining clock and data offsets. By obtaining the clock and data delays for each of the multiple timing paths to be analyzed, and further obtaining reference clock and data delays, and determining the timing analysis results for each timing path to be analyzed based on the reference clock and data delays, the scheme provided in this application significantly improves processing speed compared to the traditional method of using `set_data_check` in STA for timing path analysis, thereby achieving the technical effect of improving the efficiency of delay analysis for timing paths of integrated circuits.

[0064] Figure 2 is a schematic diagram of the structure of a timing analysis device provided in an exemplary embodiment of this application;

[0065] The device includes:

[0066] The acquisition unit 21 is used to acquire the clock delay and data delay corresponding to each of the multiple timing paths to be analyzed.

[0067] The acquisition unit 21 is also used to acquire the reference clock delay and the reference data delay;

[0068] The determining unit 22 is used to determine the timing analysis results corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

[0069] In some embodiments, when the device is used to acquire the reference clock delay and the reference data delay, it is specifically used for:

[0070] One timing path to be analyzed is selected from the multiple timing paths to be analyzed as the reference timing path, and the clock delay and data delay corresponding to the reference timing path are respectively used as the reference clock delay and reference data delay.

[0071] In some embodiments, when the apparatus determines the timing analysis result corresponding to each of the plurality of timing paths to be analyzed based on the reference clock delay and the reference data delay, it is specifically used for:

[0072] For each of the multiple timing paths to be analyzed, the clock delay corresponding to the timing path to be analyzed is subtracted from the reference clock delay to obtain the clock offset corresponding to the timing path to be analyzed, and the data delay corresponding to the timing path to be analyzed is subtracted from the reference data delay to obtain the data offset corresponding to the timing path to be analyzed.

[0073] In some embodiments, the device is further configured to:

[0074] For each of the multiple timing paths to be analyzed, it is determined whether the total offset corresponding to each timing path to be analyzed is greater than a preset threshold. Each timing path to be analyzed corresponds to a preset threshold, and the total offset is equal to the sum of the absolute values ​​of the clock offset and the absolute values ​​of the data offset corresponding to each timing path to be analyzed.

[0075] If so, determine that the timing path to be analyzed has a timing violation risk, and add the timing analysis results corresponding to the timing path to be analyzed to the target set.

[0076] In some embodiments, each time series path to be analyzed in the target set is sorted according to the total offset value in the time series analysis results corresponding to the time series path to be analyzed. For multiple time series paths to be analyzed with equal total offset values, they are sorted according to the values ​​of multiple preset thresholds corresponding to the multiple time series paths to be analyzed.

[0077] It should be understood that the device embodiments and method embodiments can correspond to each other, and similar descriptions can be referred to the method embodiments. To avoid repetition, further details are omitted here. Specifically, the device can execute the above method embodiments, and the foregoing and other operations and / or functions of each module in the device correspond to the respective processes in the methods of the above method embodiments. For the sake of brevity, these details are omitted here.

[0078] The apparatus of this application embodiment has been described above from the perspective of functional modules in conjunction with the accompanying drawings. It should be understood that this functional module can be implemented in hardware, in software instructions, or in a combination of hardware and software modules. Specifically, the steps of the method embodiments in this application can be completed by integrated logic circuits in the processor's hardware and / or by software instructions. The steps of the method disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. Optionally, the software module can be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps in the above method embodiments.

[0079] Figure 3 is a schematic block diagram of an electronic device provided in an embodiment of this application. The electronic device may include:

[0080] The system includes a memory 301 and a processor 302. The memory 301 stores computer programs and transfers the program code to the processor 302. In other words, the processor 302 can retrieve and run the computer programs from the memory 301 to implement the methods described in the embodiments of this application.

[0081] For example, the processor 302 can be used to execute the above-described method embodiments according to instructions in the computer program.

[0082] In some embodiments of this application, the processor 302 may include, but is not limited to:

[0083] General-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0084] In some embodiments of this application, the memory 301 includes, but is not limited to:

[0085] Volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0086] In some embodiments of this application, the computer program may be divided into one or more modules, which are stored in the memory 301 and executed by the processor 302 to perform the method provided in this application. The one or more modules may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0087] As shown in Figure 3, the electronic device may further include:

[0088] Transceiver 303, which can be connected to processor 302 or memory 301.

[0089] The processor 302 can control the transceiver 303 to communicate with other devices; specifically, it can send information or data to other devices or receive information or data sent by other devices. The transceiver 303 may include a transmitter and a receiver. The transceiver 303 may further include antennas, and the number of antennas may be one or more.

[0090] It should be understood that the various components in the electronic device are connected through a bus system, which includes a data bus, a power bus, a control bus, and a status signal bus.

[0091] This application also provides a computer storage medium storing a computer program thereon, which, when executed by a computer, enables the computer to perform the methods of the above-described method embodiments. Alternatively, embodiments of this application also provide a computer program product containing instructions that, when executed by a computer, cause the computer to perform the methods of the above-described method embodiments.

[0092] When implemented using software, it can be implemented entirely or partially as a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0093] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0095] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. For example, the functional modules in the various embodiments of this application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0096] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time series analysis method, comprising: For each of the multiple timing paths to be analyzed, obtain the clock delay and data delay corresponding to the timing path to be analyzed; Obtain the reference clock delay and reference data delay; Based on the reference clock delay and the reference data delay, the timing analysis results corresponding to each of the multiple timing paths to be analyzed are determined, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

2. The method according to claim 1, wherein, Obtain the reference clock delay and reference data delay, including: One timing path to be analyzed is selected from the multiple timing paths to be analyzed as the reference timing path, and the clock delay and data delay corresponding to the reference timing path are respectively used as the reference clock delay and reference data delay.

3. The method according to claim 1, wherein, The step of determining the timing analysis results corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay includes: For each of the multiple timing paths to be analyzed, the clock delay corresponding to the timing path to be analyzed is subtracted from the reference clock delay to obtain the clock offset corresponding to the timing path to be analyzed, and the data delay corresponding to the timing path to be analyzed is subtracted from the reference data delay to obtain the data offset corresponding to the timing path to be analyzed.

4. The method according to claim 3, wherein, The method further includes: For each of the multiple timing paths to be analyzed, it is determined whether the total offset corresponding to each timing path to be analyzed is greater than a preset threshold. Each timing path to be analyzed corresponds to a preset threshold, and the total offset is equal to the sum of the absolute values ​​of the clock offset and the absolute values ​​of the data offset corresponding to each timing path to be analyzed. If so, determine that the timing path to be analyzed has a timing violation risk, and then... The time series analysis results corresponding to the sequence path are added to the target set.

5. The method according to claim 4, wherein, The time series paths to be analyzed in the target set are sorted according to the total offset value in the time series analysis results corresponding to the time series paths to be analyzed. For multiple time series paths to be analyzed with equal total offset values, they are sorted according to the values ​​of multiple preset thresholds corresponding to the multiple time series paths to be analyzed.

6. A timing analysis apparatus, comprising: The acquisition unit is used to acquire the clock delay and data delay corresponding to each of the multiple timing paths to be analyzed. The acquisition unit is also used to acquire the reference clock delay and the reference data delay; The determining unit is used to determine the timing analysis results corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay, wherein the timing analysis results corresponding to the timing paths to be analyzed include the clock offset and data offset corresponding to the timing paths to be analyzed.

7. The apparatus according to claim 6, wherein, When the device is used to acquire the reference clock delay and the reference data delay, it is specifically used for: One timing path to be analyzed is selected from the multiple timing paths to be analyzed as the reference timing path, and the clock delay and data delay corresponding to the reference timing path are respectively used as the reference clock delay and reference data delay.

8. The apparatus according to claim 6, wherein, When the device is used to determine the timing analysis result corresponding to each of the multiple timing paths to be analyzed based on the reference clock delay and the reference data delay, it is specifically used for: For each of the multiple timing paths to be analyzed, the clock delay corresponding to the timing path to be analyzed is subtracted from the reference clock delay to obtain the clock offset corresponding to the timing path to be analyzed, and the data delay corresponding to the timing path to be analyzed is subtracted from the reference data delay to obtain the data offset corresponding to the timing path to be analyzed.

9. An electronic device, comprising: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1-5 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method of any one of claims 1-5.

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