Data processing method and related device

Abstract

Embodiments of the present application provide a data processing method. The method comprises: acquiring an image which comprises a first node and a second node, wherein the first node and the second node are different pixel points or image blocks on the image; processing the image by means of a graph neural network to obtain a processing result, wherein the processing result comprises a first fusion result and a second fusion result, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image, the degree of impact of the first node on the accuracy of an image processing task is greater than the degree of impact of the second node on the accuracy of the image processing task, and M is greater than N; and executing the image processing task on the basis of the processing result. The present application can reduce the computing power overhead of graph neural networks.

Description

A data processing method and related apparatus

[0001] This application claims priority to Chinese Patent Application No. 202410494329.1, filed with the State Intellectual Property Office of China on April 23, 2024, entitled “A Data Processing Method and Related Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of artificial intelligence (AI) technology, and in particular to a data processing method and related apparatus. Background Technology

[0003] Super-resolution (SR) aims to construct a high-resolution image from a low-resolution image. SR work typically applies knowledge from deep neural networks learned from high-resolution training images to reconstruct missing details in low-resolution inputs.

[0004] When performing image processing tasks (e.g., SR tasks) using graph neural networks, graph construction is required. During the graph construction process, different nodes in the image can be connected and fused. In existing technologies, the same operational paradigm is performed on each node, which means that different nodes are considered to have the same importance. For example, when constructing the graph, the number of nodes fused on each node is the same, which leads to a large overall computational cost for the graph neural network. Summary of the Invention

[0005] In a first aspect, this application provides a data processing method, the method comprising: acquiring an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image; processing the image through a graph neural network to obtain a processing result; the processing result including a first fusion result and a second fusion result, the first fusion result being obtained by aggregating the information of the first node and the information of M nodes on the image, the second fusion result being obtained by aggregating the information of the second node and the information of N nodes on the image, wherein the influence of the first node on the accuracy of the image processing task is greater than the influence of the second node on the accuracy of the image processing task, and M is greater than N; and executing the image processing task according to the processing result.

[0006] In existing technologies, the same computational paradigm is applied to each node, assuming that different nodes are of equal importance. In this case, the number of nodes fused is the same for different nodes (or the number of fusions is unrelated to the importance of the nodes). However, for image processing tasks, the importance of different nodes in an image (i.e., their impact on the performance or accuracy of the image processing task) may differ. For example, in this embodiment, the image includes a first node and a second node. The number of fusions used when fusing node information for the first node is M, and the number of fusions used when fusing node information for the second node is N. The first node is more important to the image processing task than the second node; therefore, M is set to be greater than N. In this case, for less important nodes, setting the number of fusions lower (compared to more important nodes) will not significantly affect the processing result of the image processing task, while also reducing the computational overhead of the graph neural network.

[0007] In one possible implementation, the image processing task is super-resolution, image denoising, image segmentation, or image recognition.

[0008] In one possible implementation, the first node is a node in the high-frequency region of the image relative to the second node.

[0009] For example, super-resolution tasks are characterized by "imbalanced restoration." In the process of super-resolution of low-resolution images, the vast majority of the low-resolution portion of the image does not require extensive modification; only a small number of high-frequency details require significant reconstruction by the neural network. Therefore, for nodes in low-frequency regions, it is not necessary to fuse many nodes to ensure good super-resolution results. Existing super-resolution techniques fail to fully utilize the "imbalanced restoration" characteristic of super-resolution. This application designs a graph with varying node degrees (in this embodiment, node degree can also be referred to as the number of fused nodes), enabling the graph neural network used for super-resolution tasks to focus more on the high-frequency reconstruction portions of the image.

[0010] In one possible implementation, the graph neural network includes multiple blocks, the first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image through a target block among the multiple blocks, and the second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image through the target block.

[0011] In one possible implementation, the total aggregate value and the total influence of nodes on the image on the accuracy of the image processing task can also be obtained, where the total aggregate value is related to the current computing power. The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence. The value of N is determined based on the total aggregate value and the relationship between the influence of the second node on the accuracy of the image processing task and the total influence. In other words, when determining the number of nodes to be fused, a total number is determined based on the current computing power requirements. Then, given this total number, the number of nodes to be fused is allocated based on this total number, thereby allowing the computational overhead of the graph neural network to adapt to the computing power requirements.

[0012] In one possible implementation, the graph neural network includes a first block and a second block; the step of processing the image through the graph neural network to obtain a processing result includes: performing a first aggregation on nodes in the image through the first block; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from nodes included in a continuous image region; and performing aggregation on nodes in the image through the second block; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions in the multiple regions.

[0013] Existing graph neural network image processing algorithms cannot be directly applied to low-level vision domains: previous graph algorithms often used small image patches as graph nodes; however, low-level vision has high requirements for pixel reconstruction, and the aggregation of patch nodes can affect image quality. Therefore, individual pixels can be used as graph nodes to ensure the image quality of super-resolution reconstruction. The problem with using individual pixels as graph nodes is that, since the image resolution to be processed in low-level vision is relatively large, directly using pixels as graph nodes during graph construction results in an excessively large search space for similar nodes, leading to excessive computational overhead. Therefore, this application proposes a sampling method that can significantly reduce the search space for similar nodes, thereby controlling the computational overhead of graph construction. Specifically, for each node, nodes can be sampled from local and global pixels within a smaller sampling space, thereby significantly reducing the computational overhead of graph construction.

[0014] Secondly, this application provides a data processing apparatus, the apparatus comprising:

[0015] The acquisition module is used to acquire an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image;

[0016] A processing module is used to process the image using a graph neural network to obtain a processing result. The processing result includes a first fusion result and a second fusion result. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image. The first node has a greater impact on the accuracy of the image processing task than the second node, and M is greater than N. The image processing task is executed according to the processing result.

[0017] In one possible implementation, the image processing task is super-resolution, image denoising, image segmentation, or image recognition.

[0018] In one possible implementation, the first node is a node in the high-frequency region of the image relative to the second node.

[0019] In one possible implementation, the graph neural network includes multiple blocks, the first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image through a target block among the multiple blocks, and the second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image through the target block.

[0020] In one possible implementation, the processing module is further configured to:

[0021] Obtain the total aggregate value and the total impact of the nodes on the image on the accuracy of the image processing task. The total aggregate value is related to the current computing power.

[0022] The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence.

[0023] The value of N is determined based on the total aggregate value and the relationship between the degree of influence of the second node on the accuracy of the image processing task and the total degree of influence.

[0024] In one possible implementation, the graph neural network includes a first block and a second block;

[0025] The processing module is specifically used for:

[0026] The first block is used to perform a first aggregation on the nodes in the image; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from the nodes included in a continuous image region.

[0027] The second block aggregates nodes in the image; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions in the multiple regions.

[0028] Thirdly, this application provides a chip including at least one processing unit and an interface circuit. The interface circuit is used to provide program instructions or data to the at least one processing unit. The at least one processing unit is used to execute the program instructions to implement the method described in any one of the first aspects. The at least one processing unit includes a first hardware unit and a second hardware unit. The first hardware unit is used to calculate the prefix sum in the channel dimension, and the second hardware unit is used to calculate the prefix sum in the spatial dimension.

[0029] Fourthly, embodiments of this application provide a data processing apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect and any of the optional methods thereon.

[0030] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0031] Sixthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the first aspect and any of its optional methods described above.

[0032] Seventhly, this application provides a chip system including a processor for supporting a data processing device in implementing the functions involved in the foregoing aspects, such as transmitting or processing data involved in the foregoing methods; or, information. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for execution or training devices. The chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0033] To more clearly illustrate the technical methods of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below.

[0034] Figure 1 is a schematic diagram of an application architecture provided in an embodiment of this application;

[0035] Figures 2 to 7 are schematic diagrams of an application architecture provided in an embodiment of this application;

[0036] Figure 8 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0037] Figure 9 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0038] Figure 10 is a schematic diagram of a search space according to an embodiment of this application;

[0039] Figure 11 is a schematic diagram of an embodiment of this application;

[0040] Figure 12 is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0041] Figure 13 is a schematic diagram of a device provided in an embodiment of this application;

[0042] Figure 14 is a schematic diagram of a device provided in an embodiment of this application;

[0043] Figure 15 is a schematic diagram of a chip provided in an embodiment of this application. Detailed Implementation

[0044] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0045] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0046] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0047] First, the overall workflow of an artificial intelligence system is described, as shown in Figure 1. Figure 1 is a structural diagram of the main framework of artificial intelligence. The framework is then elaborated on from two dimensions: the "Intelligent Information Chain" (horizontal axis) and the "IT Value Chain" (vertical axis). The "Intelligent Information Chain" reflects a series of processes from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. In this process, data undergoes a condensation process of "data—information—knowledge—wisdom." The "IT Value Chain" reflects the value that artificial intelligence brings to the information technology industry, from the underlying infrastructure of human intelligence and information (provided and processed by technology) to the industrial ecosystem of the system.

[0048] (1) Infrastructure

[0049] Infrastructure provides computing power to support artificial intelligence systems, enabling communication with the external world and providing support through a basic platform. This communication occurs through sensors; computing power is provided by intelligent chips (hardware acceleration chips such as CPUs, NPUs, GPUs, ASICs, and FPGAs); and the basic platform includes distributed computing frameworks and related platform guarantees and support, which may include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to acquire data, and this data is provided to intelligent chips in the distributed computing system provided by the basic platform for computation.

[0050] (2) Data

[0051] The data at the next layer of infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data from traditional devices, including business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0052] (3) Data processing

[0053] Data processing typically includes methods such as data training, machine learning, deep learning, search, reasoning, and decision-making.

[0054] Among them, machine learning and deep learning can perform intelligent information modeling, extraction, preprocessing, and training on data, including symbolization and formalization.

[0055] Reasoning refers to the process in which, in a computer or intelligent system, the machine thinks and solves problems by simulating human intelligent reasoning, based on reasoning control strategies and using formalized information. Typical functions include search and matching.

[0056] Decision-making refers to the process of making decisions based on intelligent information after reasoning, and it typically provides functions such as classification, sorting, and prediction.

[0057] (4) General ability

[0058] After the data processing mentioned above, the results of the data processing can be used to form some general capabilities, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0059] (5) Smart Products and Industry Applications

[0060] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields. They are the encapsulation of overall artificial intelligence solutions, productizing intelligent information decision-making and realizing practical applications. Their application areas mainly include: intelligent terminals, intelligent transportation, intelligent healthcare, autonomous driving, smart cities, etc.

[0061] This application can be applied, but is not limited to, to the field of natural language processing in the field of artificial intelligence. Specifically, it can be applied to neural network search and neural network inference in the field of natural language processing. The following will introduce several application scenarios that have been implemented in products.

[0062] To better understand the solutions of the embodiments of this application, the possible application scenarios of the embodiments of this application will be briefly introduced below with reference to Figures 2 to 5.

[0063] I. Image Processing Applications

[0064] The product form of this application embodiment can be an image processing application. Image processing applications can run on terminal devices or cloud-based servers.

[0065] In one possible implementation, referring to Figure 2, an image processing application can perform image processing tasks and obtain processing results.

[0066] Image processing tasks can include image enhancement, image recognition, image segmentation, and generative tasks.

[0067] In one possible implementation, a user can open an image processing application installed on a terminal device and input an image. The image processing application can process the image using a model trained by the method provided in the embodiments of this application, or by the method provided in the embodiments of this application, and present the processing result to the user (the presentation method may include, but is not limited to, displaying, playing, saving, uploading to the cloud, etc.).

[0068] In one possible implementation, a user can open an image processing application installed on a terminal device and input an image. The image processing application can then send the image to a cloud-based server. The cloud-based server processes the image using a model trained by the method provided in this application embodiment and sends the processing result back to the terminal device. The terminal device can then present the processing result to the user (the presentation method may include, but is not limited to, displaying, playing, saving, or uploading to the cloud).

[0069] The image processing application in this application will be described below, focusing on its functional architecture and the product architecture that implements its functions.

[0070] Referring to Figure 2, which is a schematic diagram of the functional architecture of the image processing application in an embodiment of this application:

[0071] In one possible implementation, as shown in FIG2, an image processing application 102 may receive input parameters 101 (e.g., including an image) and produce a processing result 103. The image processing application 102 may execute on at least one computer system (for example) and includes computer code that, when executed by one or more computers, causes the computers to execute a model trained using the methods provided in the embodiments of this application.

[0072] Referring to Figure 3, which is a schematic diagram of the entity architecture of the image processing application running in an embodiment of this application:

[0073] Referring to Figure 3, which illustrates a system architecture, the system may include a terminal 100 and a server 200. The server 200 may include one or more servers (Figure 3 uses one server as an example), and the server 200 can provide image processing functions for one or more terminals.

[0074] The terminal 100 may have an image processing application installed or a webpage related to image processing functions open. The application and webpage can provide an interface. The terminal 100 can receive relevant parameters input by the user on the image processing function interface and send the parameters to the server 200. The server 200 can obtain the processing result based on the received parameters and return the processing result to the terminal 100.

[0075] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters on its own, without the need for the server to cooperate. This application embodiment is not limited to this.

[0076] The product form of terminal 100 in Figure 3 is described below;

[0077] The terminal 100 in this application embodiment can be a mobile phone, tablet computer, wearable device, vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc., and this application embodiment does not impose any restrictions on it.

[0078] Figure 4 shows a schematic diagram of an optional hardware structure for terminal 100.

[0079] Referring to Figure 4, terminal 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, and a power supply 190. Those skilled in the art will understand that Figure 4 is merely an example of a terminal or multi-functional device and does not constitute a limitation on the terminal or multi-functional device; it may include more or fewer components than illustrated, or combine certain components, or use different components.

[0080] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 may include a touchscreen 131 (optional) and / or other input devices 132. The touchscreen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using fingers, knuckles, styluses, or any suitable object on or near the touchscreen), and drive the corresponding connection devices according to a pre-set program. The touchscreen can detect the user's touch actions, convert the touch actions into touch signals and send them to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal includes at least touch point coordinate information. The touchscreen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, various types of touchscreens, such as resistive, capacitive, infrared, and surface acoustic wave, can be used to implement the touchscreen. Besides the touchscreen 131, the input unit 130 may also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons, power buttons, etc.), trackball, mouse, joystick, etc.

[0081] Other input devices 132 can receive input images.

[0082] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In this embodiment, the display unit 140 can be used to display the interface and processing results of an image processing application.

[0083] The memory 120 can be used to store instructions and data. The memory 120 may primarily include an instruction storage area and a data storage area. The data storage area can store various types of data, such as multimedia files and text. The instruction storage area can store software units such as operating systems, applications, and instructions required for at least one function, or subsets or extended sets thereof. It may also include non-volatile random access memory. It provides the processor 170 with hardware, software, and data resources for managing the computing device, supporting control software and applications. It is also used for storing multimedia files, as well as storing running programs and applications.

[0084] The processor 170 is the control center of the terminal 100. It connects various parts of the terminal 100 via various interfaces and lines. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions and processes data of the terminal 100, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory can be implemented on a single chip; in some embodiments, they can also be implemented separately on independent chips. The processor 170 can also be used to generate corresponding operation control signals, send them to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that the various functional modules therein perform corresponding functions, thereby controlling the corresponding components to act according to the instructions.

[0085] The memory 120 can be used to store software code related to the data processing method, and the processor 170 can execute the steps of the chip's data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve the corresponding functions.

[0086] The radio frequency unit 110 (optional) can be used for receiving and transmitting signals during information transmission or calls. For example, it can receive downlink information from the base station and process it for the processor 170; additionally, it can transmit uplink data to the base station. Typically, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the radio frequency unit 110 can also communicate wirelessly with network devices and other devices. This wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0087] In this embodiment of the application, the radio frequency unit 110 can send an image to the server 200 and receive the processing result sent by the server 200.

[0088] It should be understood that the radio frequency unit 110 is optional and can be replaced with other communication interfaces, such as a network port.

[0089] The terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0090] Terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect terminal 100 to other devices for communication or to connect a charger to charge terminal 100.

[0091] Although not shown, terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, and sensors with various functions, which will not be described in detail here. Some or all of the methods described below can be applied to terminal 100 as shown in Figure 4.

[0092] The product form of server 200 in Figure 4 is described below;

[0093] Figure 5 provides a schematic diagram of the structure of a server 200. As shown in Figure 5, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate with each other via the bus 201.

[0094] Bus 201 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, only one thick line is used in Figure 5, but this does not indicate that there is only one bus or one type of bus.

[0095] The processor 202 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0096] Memory 204 may include volatile memory, such as random access memory (RAM). Memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0097] The memory 204 can be used to store software code related to the data processing method, and the processor 202 can execute the steps of the chip's data processing method, and can also schedule other units to achieve corresponding functions.

[0098] It should be understood that the aforementioned terminal 100 and server 200 can be centralized or distributed devices. The processors (e.g., processor 170 and processor 202) in the aforementioned terminal 100 and server 200 can be hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0099] It should be understood that the steps related to the model inference process in the embodiments of this application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and the server is not limited to the processor-memory architecture described above. The system architecture provided in the embodiments of this application will be described in detail below with reference to Figure 6.

[0100] Figure 6 is a schematic diagram of the system architecture provided in an embodiment of this application. As shown in Figure 6, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0101] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0102] The execution device 510 can be a terminal device or a server that runs the aforementioned image processing applications.

[0103] The data acquisition device 560 is used to collect training samples. Training samples can be images, etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0104] The training device 520 can maintain training samples in the database 530 to obtain the target model / rule 501 from the neural network to be trained (e.g., the graph neural network in the embodiments of this application).

[0105] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0106] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0107] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in Figure 6. The execution device 510 can be a terminal, such as a mobile terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0108] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0109] In Figure 6, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. Users can input data (such as images in the embodiments of this application) into the I / O interface 512 through the client device 540.

[0110] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0111] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0112] Finally, the I / O interface 512 provides the processing result to the client device 540, thereby providing it to the user.

[0113] In the scenario shown in Figure 6, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various forms such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0114] It is worth noting that Figure 6 is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc. shown in the figure do not constitute any limitation. For example, in Figure 6, the data storage system 550 is an external memory relative to the execution device 510. In other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the aforementioned execution device 510 can be deployed in the client device 540.

[0115] The following section describes the more detailed architecture of the execution entity of the data processing method in the embodiments of this application.

[0116] The system architecture provided in this application embodiment will be described in detail below with reference to Figure 6. Figure 6 is a schematic diagram of the system architecture provided in this application embodiment. As shown in Figure 6, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0117] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0118] The data acquisition device 560 is used to collect training samples. Training samples can be images, text data, audio data, etc. In this embodiment, the training samples are the data used to train multiple candidate neural networks. After collecting the training samples, the data acquisition device 560 stores them in the database 530.

[0119] It should be understood that a search space can also be maintained in database 530.

[0120] The training device 520 can construct multiple candidate neural networks based on the search space maintained in the database 530, and train the multiple candidate neural networks based on training samples to search for the target model / rule 501. In this embodiment, the target model / rule 501 can be the target neural network.

[0121] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0122] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in Figure 6. The execution device 510 can be a terminal, such as a mobile terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server or cloud, etc.

[0123] Specifically, the training device 520 can transmit the target neural network to the execution device 510.

[0124] In Figure 6, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. Users can input data (e.g., data to be processed in the embodiments of this application) into the I / O interface 512 through the client device 540.

[0125] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0126] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0127] Finally, the I / O interface 512 presents the processing results (such as the data processing results in this embodiment) to the client device 540, thereby providing them to the user.

[0128] From the inference side of the model:

[0129] In this embodiment, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the data processing method in this embodiment.

[0130] In this embodiment of the application, the computing module 511 of the execution device 510 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0131] Specifically, the computing module 511 of the execution device 510 can be a hardware system with the function of executing instructions. The data processing method provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the data processing method provided in this application embodiment.

[0132] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps of the data processing method provided in the embodiments of this application can also be implemented by the hardware system without the function of executing instructions in the computing module 511 of the execution device 510, which is not limited here.

[0133] From the training side of the model:

[0134] In this embodiment, the training device 520 can obtain the code stored in the memory (not shown in Figure 6, which can be integrated into the training device 520 or deployed separately from the training device 520) to implement the neural network search method in this embodiment.

[0135] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0136] Specifically, the training device 520 can be a hardware system with instruction execution capabilities. The data processing method provided in this application embodiment can be software code stored in a memory. The training device 520 can retrieve the software code from the memory and execute the retrieved software code to implement the neural network search method provided in this application embodiment.

[0137] It should be understood that the training device 520 can be a combination of a hardware system without instruction execution function and a hardware system with instruction execution function. Some steps of the neural network search method provided in this application embodiment can also be implemented by the hardware system in the training device 520 without instruction execution function, which is not limited here.

[0138] II. Image processing functions provided by the server (like cloud services):

[0139] In one possible implementation, the server can provide image processing services to the client side through an application programming interface (API).

[0140] In this process, the terminal device can send relevant parameters (such as image data) to the server through the API provided by the cloud. The server can obtain the processing results based on the received parameters and return the processing results to the terminal.

[0141] The description of the terminal and server can be found in the above embodiments, and will not be repeated here.

[0142] Figure 7 illustrates the process of using a cloud service with image processing capabilities provided by a cloud platform.

[0143] 1. Activate and purchase image processing services.

[0144] 2. Users can download the software development kit (SDK) corresponding to the image processing service. Cloud platforms usually provide multiple development versions of the SDK for users to choose from according to their development environment needs, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0145] 3. After downloading the corresponding version of the SDK to their local machine according to their needs, users can import the SDK project into their local development environment, configure and debug it in the local development environment, and develop other functions in the local development environment to form an application that integrates image processing capabilities.

[0146] 4. When an image processing application is used, it can trigger an API call for the image processing function when image processing is required. When the application triggers the image processing function, it sends an API request to the running instance of the image processing function service in the cloud environment. The API request carries the image, and the running instance in the cloud environment processes the image to obtain the processing result.

[0147] 5. The cloud environment returns the processing result to the application, thus completing one image processing function call.

[0148] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0149] (1) Neural Network

[0150] A neural network can be composed of neural units, which can be operational units that take xs and an intercept of 1 as inputs, and whose output can be:

[0151] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0152] (2) Loss Function

[0153] In training a deep neural network, to ensure the output closely approximates the desired predicted value, we compare the network's prediction with the target value. Based on the difference, we update the weight vector of each layer (usually pre-configuring parameters before the initial update). For example, if the prediction is too high, the weight vector is adjusted to predict a lower value. This adjustment continues until the deep neural network predicts the target value or a value very close to it. Therefore, we need to predefine "how to compare the difference between the predicted and target values," which is the loss function or objective function. These are important equations used to measure the difference between the predicted and target values. Taking the loss function as an example, a higher output value (loss) indicates a greater difference, and training the deep neural network becomes a process of minimizing this loss.

[0154] (3) Backpropagation algorithm

[0155] Convolutional neural networks can employ backpropagation (BP) to correct the parameters in the initial super-resolution model during training, thereby reducing the reconstruction error loss. Specifically, forward propagation of the input signal to the output generates an error loss; this error loss information is then propagated back to update the parameters in the initial super-resolution model, leading to convergence of the error loss. The backpropagation algorithm is an error-loss-driven backpropagation process aimed at obtaining the optimal parameters of the super-resolution model, such as the weight matrix.

[0156] (4) Deep Neural Networks

[0157] Deep Neural Networks (DNNs), also known as multilayer neural networks, can be understood as neural networks with many hidden layers, though there's no specific metric for "many." DNNs can be categorized into three layers based on their position: input layers, hidden layers, and output layers. Generally, the first layer is the input layer, the last layer is the output layer, and the layers in between are hidden layers. All layers are fully connected, meaning that any neuron in the i-th layer is connected to any neuron in the (i+1)-th layer. Although DNNs appear complex, the operation of each layer is actually quite simple, resembling a linear relationship as follows: in, It is the input vector. It is the output vector. α is the offset vector, W is the weight matrix (also called coefficients), and α() is the activation function. Each layer is simply an adjustment of the input vector. The output vector is obtained through such a simple operation. Because DNNs have many layers, the coefficients W and the offset vector... The number of these parameters is therefore quite large. The definitions of these parameters in a DNN are as follows: Taking the coefficient W as an example: Assuming a three-layer DNN, the linear coefficient from the 4th neuron in the second layer to the 2nd neuron in the third layer is defined as... The superscript 3 represents the layer number where coefficient W resides, while the subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary, the coefficients from the k-th neuron in layer L-1 to the j-th neuron in layer L are defined as follows: It's important to note that the input layer does not have a W parameter. In deep neural networks, more hidden layers allow the network to better represent complex real-world situations. Theoretically, the more parameters a model has, the higher its complexity and "capacity," meaning it can perform more complex learning tasks. Training a deep neural network is essentially the process of learning the weight matrix, with the ultimate goal of obtaining the weight matrix of all layers in the trained deep neural network (a weight matrix formed by the vectors W from many layers).

[0158] Super-resolution (SR) aims to construct a high-resolution image from a low-resolution image. SR work typically applies knowledge from deep neural networks learned from high-resolution training images to reconstruct missing details in low-resolution inputs.

[0159] When performing image processing tasks (e.g., SR tasks) using graph neural networks, graph construction is required. During the graph construction process, different nodes in the image can be connected and fused. In existing technologies, the same operational paradigm is performed on each node, which means that different nodes are considered to have the same importance. For example, when constructing the graph, the number of nodes fused on each node is the same, which leads to a large overall computational cost for the graph neural network.

[0160] To address the aforementioned problems, this application provides a data processing method. Referring to Figure 8, which is a schematic illustration of an embodiment of the data processing method provided by this application, the data processing method provided by this application may include:

[0161] 901. Acquire an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image;

[0162] The image can be an image that requires image processing.

[0163] The image may include multiple nodes, which may correspond to pixels or be an image patch (e.g., a 2*2 pixel patch) composed of multiple pixels. This application embodiment is not limited to these.

[0164] 902. The image is processed using a graph neural network to obtain a processing result; the processing result includes a first fusion result and a second fusion result, wherein the first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image, and the second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image, wherein the influence of the first node on the accuracy of the image processing task is greater than the influence of the second node on the accuracy of the image processing task, and M is greater than N.

[0165] Graph neural networks can extract features from images to obtain feature representations for each node. Specifically, a graph neural network can include multiple blocks, each corresponding to a stage. For example, referring to Figure 11, the MGB module (or GAL module) in Figure 11 can be a block. Each block can obtain information (e.g., feature representations) for each node, and then connect and fuse the nodes. For example, for a node, information from a certain number of other nodes in the image that are highly similar to that node can be fused into that node to update the information of that node, thereby completing the information interaction between nodes.

[0166] For example, in one possible implementation, the graph neural network includes multiple blocks. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes in the image through a target block among the multiple blocks. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes in the image through the target block. That is, the number of aggregations used by the same block of the graph neural network is different when aggregating nodes for different nodes.

[0167] In existing technologies, the same operational paradigm is applied to each node, which means that different nodes are considered to have the same level of importance. In this case, the number of nodes to be merged is the same for different nodes (or the number of nodes to be merged is unrelated to the importance of the nodes).

[0168] For example, for convolution, the same convolutional kernel scans all pixels in the feature map; for attention mechanisms, each pixel needs to aggregate information from a fixed number of pixels within a fixed-size neighborhood; for graph neural networks, any pixel needs to aggregate its K nearest neighbor nodes. Previous super-resolution schemes were too rigid and did not fully utilize the "imbalance recovery" characteristic of super-resolution.

[0169] However, for image processing tasks, the importance of different nodes in an image (i.e., their impact on the execution effect or accuracy of the image processing task) may differ. For example, in this embodiment, the image includes a first node and a second node. The number of nodes fused when fusing node information for the first node is M, and the number of nodes fused when fusing node information for the second node is N. The first node is more important to the image processing task than the second node; therefore, M is set to be greater than N. In this case, for less important nodes, setting the number of nodes fused to a lower value (compared to more important nodes) will not significantly affect the processing result of the image processing task, while also reducing the computational overhead of the graph neural network.

[0170] For example, super-resolution tasks are characterized by "imbalanced restoration." In the process of super-resolution of low-resolution images, the vast majority of the low-resolution portion of the image does not require extensive modification; only a small number of high-frequency details require significant reconstruction by the neural network. Therefore, for nodes in low-frequency regions, it is not necessary to fuse many nodes to ensure good super-resolution results. Existing super-resolution techniques fail to fully utilize the "imbalanced restoration" characteristic of super-resolution. This application designs a graph with varying node degrees (in this embodiment, node degree can also be referred to as the number of fused nodes), enabling the graph neural network used for super-resolution tasks to focus more on the high-frequency reconstruction portions of the image.

[0171] The following section provides a detailed illustration of the graph construction in this embodiment. In this embodiment, each pixel on the feature map can be used as a node in the constructed graph. Assume the feature map has a dimension of R. H*W*C If the dimension is , then there are a total of H*W nodes; each node is an R C Features. It should be noted that this embodiment is also effective when using image patches (e.g., 2x2 pixel patches) as nodes.

[0172] In one possible implementation, taking image processing as a super-resolution task as an example, it is necessary to accurately determine which locations in the image belong to high-frequency regions and which belong to low-frequency regions. For example, referring to Figure 9, the difference between the effect of downsampling and upsampling the feature map and the original feature map can be used as an indicator to determine high- and low-frequency regions.

[0173] In addition, the standard deviation of a feature can also be used as a criterion for judging the importance of a node, but this application does not limit this.

[0174] It should be understood that traditional edge detection operators can also be used to process feature maps, such as Sobel, Laplacian, Canny, and Prewitt methods.

[0175] In one possible implementation, the total aggregate value and the total influence of nodes on the image on the accuracy of the image processing task can also be obtained, where the total aggregate value is related to the current computing power. The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence. The value of N is determined based on the total aggregate value and the relationship between the influence of the second node on the accuracy of the image processing task and the total influence. In other words, when determining the number of nodes to be fused, a total number is determined based on the current computing power requirements. Then, given this total number, the number of nodes to be fused is allocated based on this total number, thereby allowing the computational overhead of the graph neural network to adapt to the computing power requirements.

[0176] For example, based on the current computing power, the sum of the degrees (i.e., the number of fusions) of all nodes in the graph (the budget, i.e., the total aggregation value) can be set to Deg. The degree of each node v can be obtained as follows: deg(v) = D F (v)Deg / ∑D F ;

[0177] Where Df(v) represents the degree of influence of a node, Deg represents the total aggregate value, the sum of DF represents the total degree of influence, and deg(v) represents the degree of a node.

[0178] It should be noted that the allocation of node degrees may not necessarily follow the above formula. For example, the importance index can be normalized using softmax before the node degree is allocated.

[0179] In one possible implementation, the graph neural network includes a first block and a second block; the first block can be used to perform a first aggregation on nodes in the image; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from nodes included in a continuous image region; the second block can be used to aggregate nodes in the image; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions.

[0180] Existing graph neural network image processing algorithms cannot be directly applied to low-level vision domains: previous graph algorithms often used small image patches as graph nodes; however, low-level vision has high requirements for pixel reconstruction, and the aggregation of patch nodes can affect image quality. Therefore, individual pixels can be used as graph nodes to ensure the image quality of super-resolution reconstruction. The problem with using individual pixels as graph nodes is that, since the image resolution to be processed in low-level vision is relatively large, directly using pixels as graph nodes during graph construction results in an excessively large search space for similar nodes, leading to excessive computational overhead. Therefore, this application proposes a sampling method that can significantly reduce the search space for similar nodes, thereby controlling the computational overhead of graph construction. Specifically, for each node, nodes can be sampled from local and global pixels within a smaller sampling space, thereby significantly reducing the computational overhead of graph construction.

[0181] For each node, it is necessary to find and connect nodes similar to that node in the image to complete the graph construction. However, since super-resolution tasks often need to process images with high resolution, using pixels as graph nodes often leads to an excessive number of graph nodes, resulting in an excessively large space for searching for similar nodes and consuming a lot of computing power. To solve this problem, this embodiment of the application performs global and local sampling on all nodes for each node, allowing each node to search for similar nodes in a smaller sampling space (rather than the global one). Then, in the sampling space, based on the node degree Deg(v) set in the previous step, the most similar Deg(v) nodes are selected and connected to the current node v.

[0182] For example, local sampling can be to sample all nodes around the current node (for example, see the middle diagram of Figure 10).

[0183] For example, global sampling can be performed every N pixels across the entire image (see the right side of Figure 10 for example).

[0184] When performing node aggregation, each node can be weighted and aggregated according to the constructed graph. Let v be the current node; u be the critical node of v; f k (u,v) is a learnable neural network that measures the similarity between nodes u and v. Given the characteristics of node u in the Kth layer of the IPG network, node aggregation can be represented as:

[0185] Referring to Figure 11, which shows a structural diagram of the model using the underlying visual network SwinIR as an example.

[0186] 903. Based on the processing result, execute the image processing task.

[0187] Referring to Table 1, which illustrates an experimental result based on an embodiment of this application.

[0188] Table 1

[0189] Referring to FIG12, FIG12 is a schematic diagram of an embodiment of a data processing apparatus provided in this application. As shown in FIG12, the data processing apparatus 1200 provided in this application embodiment may include:

[0190] The acquisition module 1201 is used to acquire an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image;

[0191] The description of the acquisition module 1201 can be found in the description of step 901 in the above embodiments, and will not be repeated here.

[0192] The processing module 1202 is used to process the image using a graph neural network to obtain a processing result. The processing result includes a first fusion result and a second fusion result. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image. The first node has a greater impact on the accuracy of the image processing task than the second node, and M is greater than N. The image processing task is executed according to the processing result.

[0193] The description of the processing module 1202 can be found in the description of steps 902 and 903 in the above embodiments, and will not be repeated here.

[0194] In one possible implementation, the image processing task is super-resolution, image denoising, image segmentation, or image recognition.

[0195] In one possible implementation, the first node is a node in the high-frequency region of the image relative to the second node.

[0196] In one possible implementation, the graph neural network includes multiple blocks, the first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image through a target block among the multiple blocks, and the second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image through the target block.

[0197] In one possible implementation, the processing module 1202 is further configured to:

[0198] Obtain the total aggregate value and the total impact of the nodes on the image on the accuracy of the image processing task. The total aggregate value is related to the current computing power.

[0199] The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence.

[0200] The value of N is determined based on the total aggregate value and the relationship between the degree of influence of the second node on the accuracy of the image processing task and the total degree of influence.

[0201] In one possible implementation, the graph neural network includes a first block and a second block;

[0202] The processing module 1202 is specifically used for:

[0203] The first block is used to perform a first aggregation on the nodes in the image; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from the nodes included in a continuous image region.

[0204] The second block aggregates nodes in the image; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions in the multiple regions.

[0205] The following describes an execution device provided in an embodiment of this application. Please refer to Figure 13, which is a schematic diagram of the structure of an execution device provided in an embodiment of this application. The execution device 1300 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop, a smart wearable device, a monitoring data processing device, or a server, etc., and is not limited here. Specifically, the execution device 1300 includes: a receiver 1301, a transmitter 1302, a processor 1303, and a memory 1304 (the number of processors 1303 in the execution device 1300 can be one or more; Figure 13 shows one processor as an example). The processor 1303 may include an application processor 13031 and a communication processor 13032. In some embodiments of this application, the receiver 1301, transmitter 1302, processor 1303, and memory 1304 can be connected via a bus or other means.

[0206] Memory 1304 may include read-only memory and random access memory, and provides instructions and data to processor 1303. A portion of memory 1304 may also include non-volatile random access memory (NVRAM). Memory 1304 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0207] Processor 1303 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0208] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1303. The processor 1303 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuits in the hardware of the processor 1303 or by instructions in software form. The processor 1303 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1303 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1304. Processor 1303 reads the information in memory 1304 and, in conjunction with its hardware, completes the steps of the above method.

[0209] Receiver 1301 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1302 can be used to output digital or character information; transmitter 1302 can also be used to send instructions to the disk group to modify the data in the disk group.

[0210] In one embodiment of this application, the processor 1303 is used to execute the data processing method executed by the execution device in the above embodiment.

[0211] This application embodiment also provides a training device. Please refer to Figure 14, which is a structural schematic diagram of the training device provided in this application embodiment. The training device 1400 may deploy the device described in the embodiment corresponding to Figure 12. Specifically, the training device 1400 is implemented by one or more servers. The training device 1400 may vary considerably due to different configurations or performance. It may include one or more central processing units (CPUs) 1414 (e.g., one or more processors) and memory 1432, and one or more storage media 1430 (e.g., one or more mass storage devices) for storing application programs 1442 or data 1444. The memory 1432 and storage media 1430 may be temporary or persistent storage. The program stored in the storage media 1430 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the training device. Furthermore, the CPU 1414 may be configured to communicate with the storage media 1430 and execute the series of instruction operations in the storage media 1430 on the training device 1400.

[0212] The training device 1400 may also include one or more power supplies 1426, one or more wired or wireless network interfaces 1450, one or more input / output interfaces 1458; or, one or more operating systems 1441, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0213] In this embodiment, the central processing unit 1414 is used to execute the method in the embodiment corresponding to FIG8.

[0214] This application also provides a computer program product that, when run on a computer, causes the computer to perform steps as performed by the aforementioned data processing device, or causes the computer to perform steps as performed by the aforementioned data processing device.

[0215] This application also provides a computer-readable storage medium storing a program for performing signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned data processing apparatus, or causes the computer to perform steps as performed by the aforementioned data processing apparatus.

[0216] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the data processing method described in the above embodiments, or to cause the chip within the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0217] Specifically, please refer to Figure 15, which is a schematic diagram of a chip structure provided in an embodiment of this application. This chip can be represented as a neural network processor (NPU) 1500. The NPU 1500 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1503, which is controlled by the controller 1504 to extract matrix data from the memory and perform multiplication operations.

[0218] In some implementations, the arithmetic circuit 1503 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1503 is a two-dimensional pulsating array. The arithmetic circuit 1503 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1503 is a general-purpose matrix processor.

[0219] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1502 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1501 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1508.

[0220] Unified memory 1506 is used to store input and output data. Weight data is directly transferred to weight memory 1502 via Direct Memory Access Controller (DMAC) 1505. Input data is also transferred to unified memory 1506 via DMAC.

[0221] BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1509.

[0222] The Bus Interface Unit (BIU) 1510 is used by the instruction fetch memory 1509 to fetch instructions from external memory, and also by the memory access controller 1505 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0223] The DMAC is mainly used to move input data from external memory DDR to unified memory 1506, or to weight data to weight memory 1502, or to input data to input memory 1501.

[0224] The vector computation unit 1507 includes multiple arithmetic processing units that further process the output of the computation circuit as needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes.

[0225] In some implementations, the vector computation unit 1507 can store the processed output vector in the unified memory 1506. For example, the vector computation unit 1507 can apply a linear function, or a nonlinear function, to the output of the computation circuit 1503, such as linear interpolation of feature planes extracted by a convolutional layer, or, for example, a vector of accumulated values, to generate activation values. In some implementations, the vector computation unit 1507 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as activation input to the computation circuit 1503, for example, for use in subsequent layers of the neural network.

[0226] The instruction fetch buffer 1509 connected to the controller 1504 is used to store the instructions used by the controller 1504;

[0227] Unified memory 1506, input memory 1501, weighted memory 1502, and instruction fetch memory 1509 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0228] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0229] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0230] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0231] In the above embodiments, the implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0232] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A data processing method, characterized in that, The method includes: Acquire an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image; The image is processed using a graph neural network to obtain a processing result. The processing result includes a first fusion result and a second fusion result. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image. The first node has a greater impact on the accuracy of the image processing task than the second node, and M is greater than N. Based on the processing result, the image processing task is executed.

2. The method according to claim 1, characterized in that, The image processing task is super-resolution, image denoising, image segmentation, or image recognition.

3. The method according to claim 1 or 2, characterized in that, The first node is a node in the high-frequency region of the image relative to the second node.

4. The method according to any one of claims 1 to 3, characterized in that, The graph neural network includes multiple blocks. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image through the target block among the multiple blocks. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image through the target block.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Obtain the total aggregate value and the total impact of the nodes on the image on the accuracy of the image processing task. The total aggregate value is related to the current computing power. The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence. The value of N is determined based on the total aggregate value and the relationship between the degree of influence of the second node on the accuracy of the image processing task and the total degree of influence.

6. The method according to any one of claims 1 to 5, characterized in that, The graph neural network includes a first block and a second block; The process of processing the image using a graph neural network to obtain the processing result includes: The first block is used to perform a first aggregation on the nodes in the image; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from the nodes included in a continuous image region. The second block aggregates nodes in the image; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions in the multiple regions.

7. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire an image, the image including a first node and a second node, the first node and the second node being different pixels or image blocks on the image; A processing module is used to process the image using a graph neural network to obtain a processing result. The processing result includes a first fusion result and a second fusion result. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image. The first node has a greater impact on the accuracy of the image processing task than the second node, and M is greater than N. The image processing task is executed according to the processing result.

8. The apparatus according to claim 7, characterized in that, The image processing task is super-resolution, image denoising, image segmentation, or image recognition.

9. The apparatus according to claim 7 or 8, characterized in that, The first node is a node in the high-frequency region of the image relative to the second node.

10. The apparatus according to any one of claims 7 to 9, characterized in that, The graph neural network includes multiple blocks. The first fusion result is obtained by aggregating the information of the first node and the information of M nodes on the image through the target block among the multiple blocks. The second fusion result is obtained by aggregating the information of the second node and the information of N nodes on the image through the target block.

11. The apparatus according to any one of claims 7 to 10, characterized in that, The processing module is further configured to: Obtain the total aggregate value and the total impact of the nodes on the image on the accuracy of the image processing task. The total aggregate value is related to the current computing power. The value of M is determined based on the total aggregate value and the relationship between the influence of the first node on the accuracy of the image processing task and the total influence. The value of N is determined based on the total aggregate value and the relationship between the degree of influence of the second node on the accuracy of the image processing task and the total degree of influence.

12. The apparatus according to any one of claims 7 to 11, characterized in that, The graph neural network includes a first block and a second block; The processing module is specifically used for: The first block is used to perform a first aggregation on the nodes in the image; wherein, when performing the first aggregation, the aggregation object of the nodes is selected from the nodes included in a continuous image region. The second block aggregates nodes in the image; wherein, when performing the second aggregation, the aggregation object of the nodes is selected from nodes in multiple regions of the image, and there are intervals between adjacent regions in the multiple regions.

13. A computing device, characterized in that, The device includes at least one processor and at least one memory, wherein the at least one memory stores computer-readable instructions; the at least one processor executes the computer-readable instructions to cause the computing device to perform the method as described in any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, Includes computer-readable instructions; the computer-readable instructions are used to implement the method according to any one of claims 1 to 6.

15. A computer program product, characterized in that, Includes computer-readable instructions; the computer-readable instructions are used to implement the method according to any one of claims 1 to 6.

16. A chip, characterized in that, It includes at least one processing unit and an interface circuit, the interface circuit being used to provide program instructions or data to the at least one processing unit, the at least one processing unit being used to execute the program instructions to implement the method of any one of claims 1 to 6.

Images