Data processing method and related device

Abstract

Embodiments of the present application provide a data processing method. The method comprises: acquiring an image which comprises a first node and a second node, wherein the first node and the second node are different pixel points or image blocks on the image; processing the image by means of a graph neural network to obtain a processing result, wherein the processing result comprises a first fusion result and a second fusion result, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image, the degree of impact of the first node on the accuracy of an image processing task is greater than the degree of impact of the second node on the accuracy of the image processing task, and M is greater than N; and executing the image processing task on the basis of the processing result. The present application can reduce the computing power overhead of graph neural networks.

Description

A data processing method and related apparatus

[0001] The present application claims priority from the Chinese patent application No. 202410494329.1 filed on April 23, 2024, and entitled "A data processing method and related apparatus", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of artificial intelligence (AI), and in particular, to a data processing method and related apparatus. BACKGROUND

[0003] The purpose of super-resolution (SR) is to construct a high-resolution image from a low-resolution image. SR work usually applies deep neural network knowledge learned from high-resolution training images to construct missing details in low-resolution inputs.

[0004] When performing an image processing task (for example, an SR task) by a graph neural network, graph construction needs to be performed. In the graph construction process, different nodes in the image can be connected and fused. In the prior art, the same operation paradigm is performed on each node, that is, the importance of different nodes is considered to be the same. For example, the number of nodes fused on each node is the same when constructing the graph, which results in a large overall computing power consumption of the graph neural network. SUMMARY

[0005] In a first aspect, the present application provides a data processing method, the method comprising: obtaining an image, the image comprising a first node and a second node, the first node and the second node being different pixel points or image blocks on the image; processing the image by a graph neural network to obtain a processing result; the processing result comprising a first fusion result and a second fusion result, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image, wherein the influence degree of the first node on the accuracy of the image processing task is greater than the influence degree of the second node on the accuracy of the image processing task, and the M is greater than the N; and performing the image processing task according to the processing result.

[0006] In the prior art, the same operation paradigm is performed on each node, that is, the importance of different nodes is considered to be the same, in which case the number of nodes for fusion is the same for different nodes (or the number of fusions is independent of the importance of the nodes). However, for image processing tasks, the importance of different nodes on the image (that is, the degree of influence on the execution effect or execution accuracy of the image processing task) can be different. For example, in an embodiment of the present application, the image includes a first node and a second node, the number of fusions used for performing fusion of node information of the first node is M, and the number of fusions used for performing fusion of node information of the second node is N. The importance of the first node to the image processing task is greater than that of the second node, and therefore M is set to be greater than N. In this case, for nodes that are not very important, the number of fusions is set to be lower (compared to nodes with higher importance), which will not greatly affect the processing result of the image processing task, and at the same time can reduce the computational power consumption of the graph neural network.

[0007] In a possible implementation, the image processing task is super resolution, image denoising, image segmentation, or image recognition.

[0008] In a possible implementation, the first node is a node in a high-frequency region of the image relative to the second node.

[0009] For example, the super resolution task has the feature of "restoring imbalance". In the process of performing super resolution on a low-resolution image, the low-resolution part, which accounts for a large part of the image, does not need to be changed a lot; only a small amount of high-frequency detail part needs to be reconstructed by the neural network. Therefore, for nodes in the low-frequency region, a large number of nodes do not need to be fused, and a good super resolution effect can be ensured. The existing super resolution technical solution fails to fully utilize the feature of "restoring imbalance" in super resolution. The present application designs a graph with varying node degrees (in an embodiment of the present application, the node degrees can also be referred to as the number of fusions), so that the graph neural network used for performing the super resolution task can pay more attention to the part of the image that needs high-frequency reconstruction.

[0010] In a possible implementation, the graph neural network includes a plurality of blocks, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image through a target block in the plurality of blocks, and the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image through the target block.

[0011] In a possible implementation, a total aggregation value related to the current computing power and a total influence degree of the nodes on the image on the accuracy of the image processing task can also be acquired, the value of M is determined according to the total aggregation value and a relationship between the influence degree of the first node on the accuracy of the image processing task and the total influence degree, and the value of N is determined according to the total aggregation value and a relationship between the influence degree of the second node on the accuracy of the image processing task and the total influence degree. That is, in the determination of the fusion quantity of the nodes, a total number is determined based on the current power requirement, and then the fusion quantity of each node is allocated based on the total number in the case of meeting the total number determination, so that the computing overhead of the graph neural network can be adapted to the power requirement.

[0012] In a possible implementation, the graph neural network includes a first block and a second block, and processing the image by using the graph neural network to obtain a processing result includes: performing first aggregation on the nodes in the image by using the first block, wherein the aggregation object of the nodes in the first aggregation is selected from the nodes included in one continuous image region; and performing aggregation on the nodes in the image by using the second block, wherein the aggregation object of the nodes in the second aggregation is selected from the nodes in a plurality of regions of the image, and there is a gap between adjacent regions in the plurality of regions.

[0013] The existing graph neural network image processing algorithm cannot be directly applied to the bottom vision field: previous graph algorithms often take small image patches as nodes of the graph; and the bottom vision has a higher requirement for the reconstruction of pixels, and the aggregation of patch nodes will affect the image quality. Therefore, a single pixel can be taken as a node of the graph to ensure the image quality of super-resolution reconstruction. The problem brought by taking a single pixel as a node of the graph is that, in the field of bottom vision, the resolution of the image to be processed is large, and if the pixels are directly taken as nodes of the graph in the process of constructing the graph, the search space of similar nodes is too large, which will cause a large power consumption. Therefore, an embodiment of the present application designs a sampling method, which can significantly reduce the search space of similar nodes to control the power consumption of graph construction. Specifically, for each node, the nodes can be collected in the local pixels and the global pixels and in a smaller sampling space, so as to significantly reduce the power consumption of graph construction.

[0014] In a second aspect, the present application provides a data processing apparatus, the apparatus comprising:

[0015] An acquisition module is configured to acquire an image, the image comprising a first node and a second node, the first node and the second node being different pixel points or image blocks on the image;

[0016] A processing module is configured to process the image by using a graph neural network to obtain a processing result, the processing result comprising a first fusion result and a second fusion result, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image, wherein the first node has a greater influence on the accuracy of an image processing task than the second node, and M is greater than N; and the image processing task is performed according to the processing result.

[0017] In a possible implementation, the image processing task is super-resolution, image denoising, image segmentation, or image recognition.

[0018] In a possible implementation, the first node is a node in a high-frequency region of the image relative to the second node.

[0019] In a possible implementation, the graph neural network comprises a plurality of blocks, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image by using a target block in the plurality of blocks, and the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image by using the target block.

[0020] In a possible implementation, the processing module is further configured to:

[0021] acquire a total aggregation value and a total influence degree of nodes on the image on the accuracy of the image processing task, the total aggregation value being related to a current computing power;

[0022] determine a value of M according to the total aggregation value and a relationship between the influence degree of the first node on the accuracy of the image processing task and the total influence degree;

[0023] determine a value of N according to the total aggregation value and a relationship between the influence degree of the second node on the accuracy of the image processing task and the total influence degree.

[0024] In a possible implementation, the graph neural network comprises a first block and a second block;

[0025] The processing module is specifically configured to:

[0026] performing the first aggregation, the aggregation object of a node is selected from nodes included in one continuous image region where the node is located;

[0027] performing the second aggregation, the aggregation object of a node is selected from nodes in a plurality of regions of the image, and there is a gap between adjacent regions in the plurality of regions.

[0028] In a third aspect, a chip is provided, which includes at least one processing unit and an interface circuit, the interface circuit is configured to provide program instructions or data for the at least one processing unit, the at least one processing unit is configured to execute the program instructions to implement the method in any one of the first aspect, the at least one processing unit includes a first hardware unit and a second hardware unit, the first hardware unit is configured to calculate a prefix sum in a channel dimension, and the second hardware unit is configured to calculate a prefix sum in a spatial dimension.

[0029] In a fourth aspect, an embodiment of the present application provides a data processing apparatus, which can include a memory, a processor and a bus system, wherein the memory is configured to store a program, and the processor is configured to execute the program in the memory to perform the method in the first aspect and any optional method thereof.

[0030] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, when the computer program is executed on a computer, the computer is caused to perform the method in the first aspect and any optional method thereof.

[0031] In a sixth aspect, an embodiment of the present application provides a computer program, when the computer program is executed on a computer, the computer is caused to perform the method in the first aspect and any optional method thereof.

[0032] In a seventh aspect, a chip system is provided, which includes a processor configured to support a data processing apparatus to implement the functions involved in the above aspects, for example, to send or process the data involved in the above method; or, information. In a possible design, the chip system further includes a memory, the memory is configured to save necessary program instructions and data for the execution device or the training device. The chip system can be composed of a chip, or can include a chip and other discrete devices. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical method of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows.

[0034] FIG. 1 is a schematic diagram of an application architecture according to an embodiment of the present application;

[0035] FIG. 2 to FIG. 7 are schematic diagrams of an application architecture according to an embodiment of the present application;

[0036] FIG. 8 is a schematic diagram of a data processing method according to an embodiment of the present application;

[0037] FIG. 9 is a schematic diagram of a data processing method according to an embodiment of the present application;

[0038] FIG. 10 is a search space according to an embodiment of the present application;

[0039] FIG. 11 is a model according to an embodiment of the present application;

[0040] FIG. 12 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;

[0041] FIG. 13 is a schematic diagram of an apparatus according to an embodiment of the present application;

[0042] FIG. 14 is a schematic diagram of an apparatus according to an embodiment of the present application;

[0043] FIG. 15 is a schematic diagram of a chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present application will be described below in conjunction with the accompanying drawings. The terms used in the embodiments section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0045] The embodiments of the present application will be described below in conjunction with the accompanying drawings. The terms used in the embodiments section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0046] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged, and this is only a distinguishing way used in the description of the embodiments of the present application to describe the objects with the same attributes. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not necessarily limit to those units, but can include other units not clearly listed or inherent to these processes, methods, products or devices.

[0047] First, the overall workflow of the artificial intelligence system is described, please refer to Figure 1, which shows a structural diagram of an artificial intelligence subject framework, and the following describes the above artificial intelligence subject framework from two dimensions of "intelligent information chain" (horizontal axis) and "IT value chain" (vertical axis). Among them, "intelligent information chain" reflects a series of processes from data acquisition to processing. For example, it can be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, intelligent execution and output. In this process, data undergoes a condensation process of "data-information-knowledge-wisdom". "IT value chain" reflects the value brought by artificial intelligence to the information technology industry from the underlying infrastructure of human intelligence, information (provision and processing technology implementation) to the industrial ecological process of the system.

[0048] (1) Infrastructure

[0049] The infrastructure provides computing power support for the artificial intelligence system, realizes communication with the outside world, and realizes support through the underlying platform. Communication with the outside world through sensors; computing power is provided by intelligent chips (CPU, NPU, GPU, ASIC, FPGA, etc. Hardware acceleration chips); the underlying platform includes distributed computing framework and network related platform guarantee and support, which can include cloud storage and computing, interconnection network, etc. For example, sensors and external communication obtain data, which are provided to intelligent chips in the distributed computing system provided by the underlying platform for calculation.

[0050] (2) Data

[0051] The data on the upper layer of the infrastructure is used to represent the data source in the field of artificial intelligence. Data involves graphics, images, speech, text, and also involves Internet of Things data of traditional devices, including business data of existing systems and sensing data such as force, displacement, liquid level, temperature, humidity, etc.

[0052] (3) Data processing

[0053] Data processing usually includes data training, machine learning, deep learning, search, reasoning, decision-making, etc.

[0054] Among them, machine learning and deep learning can symbolize and formalize intelligent information modeling, extraction, preprocessing, training, etc.

[0055] Reasoning refers to the process of simulating human intelligent reasoning methods in computers or intelligent systems, using formalized information to perform machine thinking and solve problems according to reasoning control strategies, and the typical function is search and matching.

[0056] Decision-making refers to the process of decision-making after intelligent information reasoning, which usually provides functions such as classification, sorting, prediction, etc.

[0057] (4) General capabilities

[0058] After the data is processed by the above-mentioned data processing, some general capabilities can be formed based on the results of the data processing, which can be algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0059] (5) Intelligent products and industry applications

[0060] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields, which are the packaging of overall solutions of artificial intelligence, and realize the application of intelligent information decision products. The application fields mainly include intelligent terminals, intelligent transportation, intelligent medical treatment, automatic driving, smart city, etc.

[0061] The present application can be but not limited to applied in the field of natural language processing in the field of artificial intelligence, and can be specifically applied in neural network search in the field of natural language processing and neural network inference in the field of natural language processing. The following will introduce multiple application scenarios landing in products.

[0062] In order to better understand the scheme of the embodiments of the present application, the possible application scenarios of the embodiments of the present application will be briefly introduced in combination with FIGS. 2 to 5.

[0063] I. Image processing application program

[0064] The product form of the embodiments of the present application can be an image processing application program. The image processing application program can run on a terminal device or a server on the cloud side.

[0065] In one possible implementation, referring to FIG. 2, the image processing application program can implement an image processing task to obtain a processing result.

[0066] The image processing task can be image enhancement, image recognition, image segmentation, generation task, etc.

[0067] In one possible implementation, a user can open an image processing application program installed on a terminal device and input an image. The image processing application program can process the image by using the model trained by the method provided in the embodiments of the present application or by using the method provided in the embodiments of the present application, and present the processing result to the user (the presentation mode can be but is not limited to display, play, save, upload to the cloud side, etc.).

[0068] In a possible implementation, a user can open an image processing application installed on a terminal device, and input an image. The image processing application can send the image to a server at a cloud side. The server at the cloud side processes the image by using a model trained by the method provided in the embodiments of the present application, and returns the processing result to the terminal device. The terminal device can present the processing result to the user (the presentation manner can be, but is not limited to, display, play, save, upload to the cloud side, etc.).

[0069] Next, the image processing application in the embodiments of the present application is introduced from the functional architecture and the product architecture implementing the function respectively.

[0070] Referring to FIG. 2, FIG. 2 is a functional architecture diagram of the image processing application in the embodiments of the present application:

[0071] In a possible implementation, as shown in FIG. 2, the image processing application 102 can receive an input parameter 101 (for example, containing an image) and generate a processing result 103. The image processing application 102 can be executed on, for example, at least one computer system, and includes computer code that, when executed by one or more computers, causes the computers to perform a model trained by the method provided in the embodiments of the present application.

[0072] Referring to FIG. 3, FIG. 3 is a schematic diagram of an entity architecture for running the image processing application in the embodiments of the present application:

[0073] Referring to FIG. 3, FIG. 3 shows a schematic diagram of a system architecture. The system can include a terminal 100 and a server 200. The server 200 can include one or more servers (one server is shown in FIG. 3 as an example), and the server 200 can provide an image processing function for one or more terminals.

[0074] The terminal 100 can install an image processing application or open a webpage related to the image processing function. The application and the webpage can provide an interface. The terminal 100 can receive parameters input by a user on the image processing function interface, and send the parameters to the server 200. The server 200 can obtain a processing result based on the received parameters, and return the processing result to the terminal 100.

[0075] It should be understood that, in some optional implementations, the terminal 100 can also complete the action of obtaining a processing result based on received parameters by itself without the cooperation of the server. The embodiments of the present application are not limited in this regard.

[0076] Next, the product form of the terminal 100 in FIG. 3 is described.

[0077] The terminal 100 in the embodiments of the present application can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), and the like, and the embodiments of the present application do not make any limitation in this regard.

[0078] FIG. 4 shows a schematic diagram of an optional hardware structure of the terminal 100.

[0079] Referring to FIG. 4, the terminal 100 can include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190, and the like. Those skilled in the art can understand that FIG. 4 is merely an example of the terminal or the multi-functional device, and does not constitute a limitation on the terminal or the multi-functional device, which can include more or fewer components than those shown, or combine some components, or different components.

[0080] The input unit 130 can be used to receive inputted digital or character information, and to generate key signal input related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 can include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can collect touch operations of a user thereon or adjacent thereto (such as operations of the user using a finger, a joint, a stylus, or any suitable object on or adjacent to the touch screen), and drive corresponding connected devices according to a pre-set program. The touch screen can detect touch actions of the user on the touch screen, convert the touch actions into touch signals and send the touch signals to the processor 170, and can receive commands from the processor 170 and execute the commands; the touch signals at least include touch point coordinate information. The touch screen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, the touch screen can be implemented in multiple types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch screen 131, the input unit 130 can also include other input devices. Specifically, the other input devices 132 can include one or more of, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, and the like), a trackball, a mouse, a joystick, and the like.

[0081] The other input devices 132 can receive an inputted image.

[0082] The display unit 140 can be used to display information input by a user or information provided to the user, various menus of the terminal 100, an interactive interface, file display, and / or playing of any kind of multimedia file. In embodiments of the present application, the display unit 140 can be used to display an interface of an image processing application, a processing result, and the like.

[0083] The memory 120 can be used to store instructions and data. The memory 120 can mainly include a storage instruction area and a storage data area. The storage data area can store various data, such as multimedia files, texts, and the like. The storage instruction area can store software units required by the operating system, applications, at least one function, and the like, or a subset, an extended set thereof. It can also include a non-volatile random access memory. It provides the processor 170 with software and applications that include managing hardware, software, and data resources in a computing processing device, supporting control software, and the like. It is also used for storage of multimedia files, and storage of running programs and applications.

[0084] The processor 170 is the control center of the terminal 100. It connects each part of the terminal 100 through various interfaces and lines, executes various functions of the terminal 100 and processes data by running or executing instructions stored in the memory 120 and calling data stored in the memory 120, thereby performing overall control of the terminal device. Optionally, the processor 170 can include one or more processing units. Preferably, the processor 170 can integrate an application processor and a modem processor. The application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 170. In some embodiments, the processor, the memory, and the like can be implemented on a single chip, and in some embodiments, they can also be implemented on separate chips respectively. The processor 170 can also be used to generate corresponding operation control signals to send to corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that each functional module therein performs corresponding functions, thereby controlling the corresponding components to act according to the requirements of the instructions.

[0085] The memory 120 can be used to store software codes related to the data processing method, and the processor 170 can execute the steps of the data processing method of the chip, or can schedule other units (such as the above-mentioned input unit 130 and display unit 140) to realize corresponding functions.

[0086] The RF unit 110 (optional) can be used to receive and send signals in the process of information or communication, for example, after receiving the downlink information of the base station, the processor 170 processes it; in addition, the uplink data is sent to the base station. Generally, the RF circuit includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. In addition, the RF unit 110 can also communicate with network devices and other devices through wireless communication. The wireless communication can use any communication standard or protocol, including but not limited to global system for mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), long term evolution (LTE), email, short messaging service (SMS), etc.

[0087] In the embodiments of the present application, the RF unit 110 can send images to the server 200 and receive the processing results sent by the server 200.

[0088] It should be understood that the RF unit 110 is optional, which can be replaced by other communication interfaces, for example, it can be a network interface.

[0089] The terminal 100 also includes a power supply 190 (such as a battery) for supplying power to each component. Preferably, the power supply can be logically connected to the processor 170 through a power management system, so as to realize the functions of managing charging, discharging, and power consumption management through the power management system.

[0090] The terminal 100 also includes an external interface 180, which can be a standard Micro USB interface, or a multi-pin connector, and can be used to connect the terminal 100 and other devices for communication, or can be used to connect a charger to charge the terminal 100.

[0091] Although not shown, the terminal 100 can also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, different function sensors, etc., which will not be described here. Some or all of the methods described below can be applied in the terminal 100 as shown in FIG. 4.

[0092] Next, the product form of the server 200 in FIG. 4 is described;

[0093] FIG. 5 provides a structural schematic diagram of a server 200. As shown in FIG. 5, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate through the bus 201.

[0094] The bus 201 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is shown in FIG. 5, but it does not mean that there is only one bus or only one type of bus.

[0095] The processor 202 can be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), etc.

[0096] The memory 204 can include a volatile memory, such as a random access memory (RAM). The memory 204 can also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard drive drive (HDD), or a solid state drive (SSD).

[0097] The memory 204 can be used to store software codes related to the data processing method, and the processor 202 can execute the steps of the chip data processing method or schedule other units to realize the corresponding functions.

[0098] It should be understood that the terminal 100 and the server 200 described above can be centralized or distributed devices, and the processors (for example, the processor 170 and the processor 202) in the terminal 100 and the server 200 can be hardware circuits (for example, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor, a microcontroller, or the like) or a combination of the hardware circuits. For example, the processor can be a hardware system with an instruction execution function, such as a CPU, a DSP, or the like, or a hardware system without an instruction execution function, such as an ASIC, an FPGA, or the like, or a combination of the hardware system without an instruction execution function and the hardware system with an instruction execution function.

[0099] It should be understood that the steps related to the model inference process in the embodiments of the present application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and the server is not limited to the architecture of the processor combined with the memory described above. The system architecture provided by the embodiments of the present application will be described in detail below with reference to FIG. 6.

[0100] FIG. 6 is a schematic diagram of a system architecture provided by an embodiment of the present application. As shown in FIG. 6, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data collection system 560.

[0101] The execution device 510 includes a computing module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The target model / rule 501 can be included in the computing module 511, and the preprocessing module 513 and the preprocessing module 514 are optional.

[0102] The execution device 510 can be a terminal device or a server running an image processing application, for example.

[0103] The data collection device 560 is configured to collect training samples. The training samples can be images, for example. After collecting the training samples, the data collection device 560 stores the training samples in the database 530.

[0104] The training device 520 can obtain the target model / rule 501 by training a neural network (for example, a graph neural network in the embodiments of the present application) based on the training samples maintained in the database 530.

[0105] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0106] It should be noted that in actual application, the training samples maintained in the database 530 can not all come from the collection of the data collection device 560, but can also be received from other devices. In addition, it should be noted that the training device 520 can not completely train the target model / rule 501 based on the training samples maintained in the database 530, but can also obtain training samples from the cloud or other places for model training, and the above description should not be regarded as a limitation of the embodiments of the present application.

[0107] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in FIG. 6, which can be a terminal such as a mobile phone terminal, a tablet computer, a notebook computer, an augmented reality (AR) / virtual reality (VR) device, a vehicle-mounted terminal, etc., and can also be a server, etc.

[0108] Specifically, the training device 520 can deliver the trained model to the execution device 510.

[0109] In FIG. 6, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices, and a user can input data (such as images in the embodiments of the present application) to the I / O interface 512 through a client device 540.

[0110] The pre-processing module 513 and the pre-processing module 514 are used for pre-processing the input data received by the I / O interface 512. It should be understood that there can be no pre-processing module 513 and pre-processing module 514 or only one pre-processing module. When there is no pre-processing module 513 and pre-processing module 514, the input data can be directly processed by the calculation module 511.

[0111] During the pre-processing of the input data by the execution device 510 or the calculation of the calculation module 511 of the execution device 510, the execution device 510 can call the data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained by the corresponding processing in the data storage system 550.

[0112] Finally, the I / O interface 512 provides the processing result to the client device 540, thereby providing the user.

[0113] In the case shown in FIG. 6, the user can manually give input data, which can be operated through the interface provided by the I / O interface 512. In another case, the client device 540 can automatically send input data to the I / O interface 512, and if the user's authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permission in the client device 540. The user can view the results output by the execution device 510 in the client device 540, and the specific presentation form can be a specific way such as display, sound, action, etc. The client device 540 can also act as a data acquisition end, and acquire the input data input to the I / O interface 512 and the output results output by the I / O interface 512 as new sample data and store them into the database 530. Of course, the acquisition can also be performed without the client device 540, and the I / O interface 512 can directly store the input data input to the I / O interface 512 and the output results output by the I / O interface 512 as new sample data into the database 530.

[0114] It is worth noting that FIG. 6 is only a schematic diagram of a system architecture provided by the embodiment of the present application, and the positional relationship between the devices, components, modules and the like shown in the figure does not constitute any limitation. For example, in FIG. 6, the data storage system 550 is an external memory relative to the execution device 510, and in other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the above execution device 510 can be deployed in the client device 540.

[0115] Next, a more detailed architecture of the execution subject of the data processing method is introduced.

[0116] Next, the system architecture provided by the embodiment of the present application is described in detail in combination with FIG. 6. FIG. 6 is a schematic diagram of the system architecture provided by the embodiment of the present application. As shown in FIG. 6, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550 and a data acquisition system 560.

[0117] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513 and a preprocessing module 514. The target model / rule 501 can be included in the calculation module 511, and the preprocessing module 513 and the preprocessing module 514 are optional.

[0118] The data acquisition device 560 is used to acquire training samples. The training samples can be images, text data, audio data, etc., and in the embodiment of the present application, the training samples are data used for training a plurality of candidate neural networks. After the training samples are acquired, the data acquisition device 560 stores these training samples into the database 530.

[0119] It should be understood that the search space can also be maintained in the database 530.

[0120] The training device 520 can construct multiple candidate neural networks based on the search space maintained in the database 530, and train the multiple candidate neural networks based on the training samples to search for the target model / rule 501. In the embodiments of the present application, the target model / rule 501 can be a target neural network.

[0121] It should be noted that in actual application, the training samples maintained in the database 530 can not all come from the collection of the data collection device 560, but can also be received from other devices. In addition, it should be noted that the training device 520 can not completely train the target model / rule 501 based on the training samples maintained in the database 530, but can also obtain training samples from the cloud or other places for model training, and the above description should not be regarded as a limitation of the embodiments of the present application.

[0122] The target model / rule 501 trained by the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in FIG. 6. The execution device 510 can be a terminal such as a mobile phone terminal, a tablet computer, a notebook computer, an augmented reality (AR) / virtual reality (VR) device, a vehicle-mounted terminal, etc., and can also be a server or a cloud, etc.

[0123] Specifically, the training device 520 can deliver the target neural network to the execution device 510.

[0124] In FIG. 6, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. The user can input data (for example, the data to be processed in the embodiments of the present application) to the I / O interface 512 through the client device 540.

[0125] The preprocessing modules 513 and 514 are used for preprocessing the input data received by the I / O interface 512. It should be understood that there can be no preprocessing modules 513 and 514 or only one preprocessing module. When there is no preprocessing module 513 and 514, the input data can be directly processed by the calculation module 511.

[0126] In the process of pre-processing the input data by the execution device 510, or in the process of performing calculation by the calculation module 511 of the execution device 510, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, and can also store data, instructions, etc. obtained by corresponding processing in the data storage system 550.

[0127] Finally, the I / O interface 512 presents the processing result (for example, the data processing result in the embodiment of the present application) to the client device 540, thereby providing the user.

[0128] From the inference side of the model:

[0129] In the embodiment of the present application, the calculation module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the data processing method in the embodiment of the present application.

[0130] In the embodiment of the present application, the calculation module 511 of the execution device 510 can include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 can be a hardware system with an execution instruction function, such as a CPU, a DSP, etc., or a hardware system without an execution instruction function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an execution instruction function and the hardware system with an execution instruction function.

[0131] Specifically, the calculation module 511 of the execution device 510 can be a hardware system with an execution instruction function, and the data processing method provided in the embodiment of the present application can be software code stored in a memory. The calculation module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the data processing method provided in the embodiment of the present application.

[0132] It should be understood that the calculation module 511 of the execution device 510 can be a combination of a hardware system without an execution instruction function and a hardware system with an execution instruction function, and part of the steps of the data processing method provided in the embodiment of the present application can also be implemented by the hardware system without an execution instruction function in the calculation module 511 of the execution device 510, which is not limited here.

[0133] From the training side of the model:

[0134] In this embodiment, the training device 520 can obtain the code stored in the memory (not shown in Figure 6, which can be integrated into the training device 520 or deployed separately from the training device 520) to implement the neural network search method in this embodiment.

[0135] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0136] Specifically, the training device 520 can be a hardware system with instruction execution capabilities. The data processing method provided in this application embodiment can be software code stored in a memory. The training device 520 can retrieve the software code from the memory and execute the retrieved software code to implement the neural network search method provided in this application embodiment.

[0137] It should be understood that the training device 520 can be a combination of a hardware system without instruction execution function and a hardware system with instruction execution function. Some steps of the neural network search method provided in this application embodiment can also be implemented by the hardware system in the training device 520 without instruction execution function, which is not limited here.

[0138] II. Image processing functions provided by the server (like cloud services):

[0139] In one possible implementation, the server can provide image processing services to the client side through an application programming interface (API).

[0140] In this process, the terminal device can send relevant parameters (such as image data) to the server through the API provided by the cloud. The server can obtain the processing results based on the received parameters and return the processing results to the terminal.

[0141] The description of the terminal and the server can refer to the description of the above embodiments, which will not be repeated here.

[0142] As shown in FIG. 7, a flow of using a cloud service of an image processing function provided by a cloud platform is shown.

[0143] 1. Open and purchase the image processing service.

[0144] 2. The user can download a software development kit (SDK) corresponding to the image processing service. The cloud platform usually provides multiple development versions of the SDK for the user to select according to the needs of the development environment, such as a JAVA version of the SDK, a python version of the SDK, a PHP version of the SDK, an Android version of the SDK, and the like.

[0145] 3. The user downloads the SDK of the corresponding version to the local according to the needs, imports the SDK project to the local development environment, configures and debugs in the local development environment, and can also develop other functions in the local development environment, so as to form an application that integrates the image processing function.

[0146] 4. During the use of the image processing function application, when the image processing function is needed, the API call of the image processing function can be triggered. When the application triggers the image processing function, an API request is initiated to the running instance of the image processing function service in the cloud environment, wherein the image is carried in the API request. The running instance in the cloud environment processes the image to obtain the processing result.

[0147] 5. The cloud environment returns the processing result to the application, thereby completing one image processing function call.

[0148] Since the embodiments of the present application involve the application of a large number of neural networks, in order to facilitate understanding, the related terms and concepts related to neural networks involved in the embodiments of the present application will be introduced first.

[0149] (1) Neural network

[0150] The neural network can be composed of neural units, and the neural unit can be an operation unit with xs and intercept 1 as inputs. The output of the operation unit can be:

[0151] Wherein, s = 1, 2, … n, n is a natural number greater than 1, Ws is the weight of xs, b is the bias of the neural unit. f is the activation function of the neural unit, which is used to introduce non-linear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of the activation function can be used as the input of the next layer of convolutional layer, and the activation function can be a sigmoid function. The neural network is a network formed by connecting a plurality of the above single neural units, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, and the local receptive field can be a region composed of a plurality of neural units.

[0152] (2) Loss function

[0153] In the process of training the deep neural network, because it is desired that the output of the deep neural network is as close as possible to the value that is really wanted to be predicted, the weight vector of each layer of the neural network can be updated according to the difference between the predicted value of the current network and the target value that is really wanted to be predicted. (Of course, before the first update, there is usually an initialization process, that is, the parameters of each layer in the deep neural network are pre-configured.) For example, if the predicted value of the network is too high, the weight vector is adjusted to make it predict lower, and the adjustment is continuously made until the deep neural network can predict the target value that is really wanted to be predicted or a value very close to it. Therefore, it is necessary to define in advance “how to compare the difference between the predicted value and the target value”, which is the loss function or the objective function, which is an important equation for measuring the difference between the predicted value and the target value. Among them, taking the loss function as an example, the higher the output value (loss) of the loss function, the greater the difference, and then the training of the deep neural network becomes a process of trying to minimize the loss.

[0154] (3) Back propagation algorithm

[0155] The convolutional neural network can use the back propagation (BP) algorithm to correct the size of the parameters in the initial super-resolution model in the training process, so that the reconstruction error loss of the super-resolution model becomes smaller and smaller. Specifically, the forward propagation of the input signal until the output will produce an error loss, and the error loss information is propagated backward to update the parameters in the initial super-resolution model, so as to make the error loss converge. The back propagation algorithm is a back propagation movement dominated by error loss, aiming to obtain the optimal parameters of the super-resolution model, such as the weight matrix.

[0156] (4) Deep neural network

[0157] Deep Neural Network (DNN), also known as multi-layer neural network, can be understood as a neural network with many hidden layers, where "many" is not a specific measure. From the position of different layers, the neural network inside the DNN can be divided into three categories: input layer, hidden layer, and output layer. Generally, the first layer is the input layer, and the last layer is the output layer, and the number of layers in between is the hidden layer. The layers are fully connected, that is, any neuron in the i-th layer is connected to any neuron in the i+1-th layer. Although DNN looks very complex, in terms of the work of each layer, it is actually not complex, which can be simply expressed as the following linear relationship expression: where, is the input vector, is the output vector, is the offset vector, W is the weight matrix (also called coefficient), and a() is the activation function. Each layer only performs the following simple operation on the input vector to obtain the output vector Since the DNN has many layers, the number of coefficients W and offset vectors is also large. These parameters in the DNN are defined as follows: taking the coefficient W as an example: assuming in a three-layer DNN, the linear coefficient from the fourth neuron of the second layer to the second neuron of the third layer is defined as The superscript 3 represents the layer number of the coefficient W, and the subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary: the coefficient from the k-th neuron of the L-1-th layer to the j-th neuron of the L-th layer is defined as It should be noted that the input layer has no W parameter. In a deep neural network, more hidden layers allow the network to better describe complex situations in the real world. In theory, the more parameters a model has, the higher its complexity, and the greater its "capacity", which means it can complete more complex learning tasks. Training a deep neural network is a process of learning the weight matrix, and the ultimate goal is to obtain the weight matrix of all layers of the trained deep neural network (the weight matrix formed by many layers of vectors W).

[0158] The purpose of super-resolution (SR) is to construct a high-resolution image from a low-resolution image. SR work usually applies deep neural network knowledge learned from high-resolution training images to construct missing details in low-resolution inputs.

[0159] In the image processing task (for example, the SR task) by the graph neural network, graphing needs to be performed, in the graphing process, different nodes in the image can be connected and fused, in the prior art, the same operation paradigm is performed on each node, that is, the importance of different nodes is considered to be the same, for example, the number of fused nodes on each node is the same in graphing, which causes the overall computing power consumption of the graph neural network to be large.

[0160] To solve the above problems, an embodiment of the present application provides a data processing method. Referring to FIG. 8, FIG. 8 is an embodiment of a data processing method provided by an embodiment of the present application. As shown in FIG. 8, the data processing method provided by the embodiment of the present application can include:

[0161] 901, acquiring an image, the image including a first node and a second node, the first node and the second node being different pixel points or image blocks on the image;

[0162] Wherein, the image can be an image that needs to be processed.

[0163] Wherein, the image can include a plurality of nodes, and the nodes herein can correspond to pixel points or image blocks (patches) composed of a plurality of pixel points, such as 2*2 pixel patches, and the embodiment of the present application is not limited thereto.

[0164] 902, processing the image by a graph neural network to obtain a processing result; the processing result including a first fusion result and a second fusion result, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image, and the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image, wherein the first node has a greater influence on the accuracy of the image processing task than the second node, and M is greater than N.

[0165] Wherein, the graph neural network can perform feature extraction on the image to obtain feature representation of each node. Specifically, the graph neural network can include a plurality of blocks, and each block corresponds to a stage. For example, referring to FIG. 11, the MGB module (or GAL module) in FIG. 11 can be a block, and each block can obtain information (for example, feature representation) of each node, and then connect and fuse the nodes. For example, for a node, information of a certain number of other nodes in the image that have a large similarity with the node can be fused into the node to update the information of the node, thereby completing the information interaction between the nodes.

[0166] For example, in a possible implementation, the graph neural network comprises a plurality of blocks, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image through a target block in the plurality of blocks, and the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image through the target block. That is, the same block of the graph neural network uses different aggregation quantities when performing node aggregation for different nodes.

[0167] In the prior art, the same operation paradigm is performed on each node, that is, the importance of different nodes is considered to be the same, in which case the number of nodes for fusion is the same for different nodes (or the fusion quantity is independent of the importance of the node).

[0168] For example, for convolution, the same convolution kernel scans all pixels of the feature map; for attention mechanism, each pixel needs to aggregate information from a fixed number of pixels in a fixed size neighborhood; for graph neural network, any pixel needs to aggregate K neighboring nodes around it. The previous super-resolution scheme is too rigid and does not fully utilize the feature of super-resolution "restoring imbalance".

[0169] However, for image processing tasks, the importance of different nodes on the image (that is, the degree of influence on the execution effect or execution precision of the image processing task) can be different. For example, in the embodiments of the present application, the image comprises a first node and a second node, the fusion quantity used for fusion of node information of the first node is M, the fusion quantity used for fusion of node information of the second node is N, the importance of the first node for the image processing task is greater than that of the second node, and therefore M is set to be greater than N. In this case, for nodes that are not very important, the fusion quantity is set to be lower (compared to nodes with higher importance), which will not greatly affect the processing result of the image processing task, and at the same time can reduce the computational power consumption of the graph neural network.

[0170] For example, the super-resolution task has the feature of "restoring imbalance". In the process of super-resolution of a low-resolution image, the low-resolution part which accounts for a large part of the image does not need to be changed a lot; only a small amount of high-frequency detail part needs to be reconstructed by the neural network. Therefore, for nodes in the low-frequency region, a large number of nodes do not need to be fused, and a good super-resolution effect can be ensured. The existing super-resolution technical solution fails to fully utilize the feature of "restoring imbalance" in super-resolution. The present application designs a graph with varying node degrees (in the embodiments of the present application, the node degree can also be referred to as the fusion quantity), so that the graph neural network used for the super-resolution task can pay more attention to the part of the image that needs high-frequency reconstruction.

[0171] Next, the construction of the graph in the embodiment of the application is specifically introduced. In the embodiment, each pixel on the feature map can be taken as a node of the constructed graph. Assuming that the dimension of the feature map is R H*W*C , there are a total of H*W nodes; each node is an R C -dimensional feature. It should be noted that the embodiment is also applicable to the case where an image patch (for example, a patch composed of 2*2 pixels) is used as a node.

[0172] [Corrected according to Rule 26 on 04.11.2025] In a possible implementation, taking the super-resolution task as an example of an image processing task, it is necessary to accurately determine which positions in the image belong to a high-frequency region and which positions belong to a low-frequency region. Referring to FIG. 9, for example, the difference between the effect of down-sampling and then up-sampling of the feature map and the original feature map can be used as an index for determining the high-frequency and low-frequency regions:

[0173] In addition, the standard deviation of the feature can also be used as a standard for judging the importance of the node, and the embodiment of the application does not limit this.

[0174] It should be understood that a traditional edge detection operator or the like can also be used to process the feature map, such as the Sobel, Laplacian, Canny, Prewitt, and the like.

[0175] In a possible implementation, the total aggregation value and the total influence degree of the nodes on the image on the accuracy of the image processing task can also be obtained, the total aggregation value being related to the current computing power; the value of M is determined according to the relationship between the total aggregation value and the influence degree of the first node on the accuracy of the image processing task and the total influence degree; the value of N is determined according to the relationship between the total aggregation value and the influence degree of the second node on the accuracy of the image processing task and the total influence degree. That is, when determining the fusion quantity of the nodes, a total number is determined based on the current power requirement, and then the fusion quantity of each node is allocated based on the total number under the condition that the total number is determined, so that the computing overhead of the graph neural network can be adapted to the power requirement.

[0176] For example, based on the current computing power, the sum (budget, that is, the total aggregation value) of the degrees (that is, the fusion quantity) of each node of the graph can be set as Deg, and the degree Deg(v) of each node v can be obtained as follows: deg(v) = D F (v) Deg / ∑D F ;

[0177] Wherein, Df(v) is the influence degree of the node, Deg is the total aggregation value, the accumulation of DF represents the total influence degree, and deg(v) is the degree of the node.

[0178] It should be noted that the allocation of node degrees is not necessarily allocated according to the above formula, for example, the importance index can be normalized by softmax before the node degree is allocated.

[0179] In a possible implementation, the graph neural network includes a first block and a second block; the first aggregation of the nodes in the image can be performed through the first block; wherein the aggregation object of the node when performing the first aggregation is selected from the nodes included in one continuous image region; the aggregation of the nodes in the image is performed through the second block; wherein the aggregation object of the node when performing the second aggregation is selected from the nodes in the multiple regions of the image, and there is a gap between adjacent regions in the multiple regions.

[0180] The existing graph neural network image processing algorithm cannot be directly applied to the bottom vision field: previous graph algorithms often take small image patches as nodes of the graph; and the bottom vision has a higher requirement for the reconstruction of pixels, and the aggregation of patch nodes will affect the image quality. Therefore, a single pixel can be taken as a node of the graph to ensure the image quality of super-resolution reconstruction. The problem brought by taking a single pixel as a node of the graph is that, in the field of bottom vision, the image resolution to be processed is large, and if the pixels are directly taken as nodes of the graph in the process of constructing the graph, the search space of similar nodes is too large, which will cause a large algorithmic cost. Therefore, an embodiment of the present application designs a sampling method, which can significantly reduce the search space of similar nodes, so as to control the algorithmic cost of graph construction. Specifically, for each node, the nodes can be collected in the local pixels and the global pixels and in a smaller sampling space, so as to significantly reduce the algorithmic cost of graph construction.

[0181] For each node, it is necessary to find and connect similar nodes in the image to complete the construction of the graph. However, since the super-resolution task often needs to process images with large resolution, when the pixels are taken as the nodes of the graph, it often leads to too many graph nodes and too large search space of similar nodes, consuming a large amount of algorithmic cost. To solve this problem, for each node, the embodiment of the present application performs global and local sampling on all nodes, so that each node searches for similar nodes in a smaller sampling space (rather than globally). Then in the sampling space, according to the node degree Deg(v) set in the previous step, the Deg(v) most similar nodes are selected and connected with the current node v.

[0182] For example, local sampling can be to sample all nodes around the current node (for example, refer to the middle diagram of FIG. 10).

[0183] For example, global sampling can be to sample every N pixels in the full image range (for example, refer to the right diagram of FIG. 10).

[0184] When performing node aggregation, each node can be aggregated with the nodes connected thereto according to the constructed graph. Let v be the current node; u be the critical node of v; f k (u, v) is a learnable neural network for measuring the similarity between nodes u and v; is the feature of the u node of the Kth layer of the IPG network, and the node aggregation can be represented as:

[0185] Referring to FIG. 11, FIG. 11 shows a structure of a model taking the bottom visual network SwinIR as an example.

[0186] 903. According to the processing result, the image processing task is performed.

[0187] Referring to Table 1, Table 1 shows an experimental result based on an embodiment of the present application.

[0188] [Corrected according to Rule 26 04.11.2025] Table 1

[0189] Referring to FIG. 12, FIG. 12 shows an embodiment of a data processing apparatus provided by the present application. As shown in FIG. 12, the data processing apparatus 1200 provided by the present application can include:

[0190] The acquisition module 1201 is configured to acquire an image, the image including a first node and a second node, the first node and the second node being different pixel points or image blocks on the image.

[0191] The description of the acquisition module 1201 can refer to the description of step 901 in the above embodiments, which will not be repeated here.

[0192] The processing module 1202 is configured to perform processing on the image by using a graph neural network to obtain a processing result, wherein the processing result includes a first fusion result and a second fusion result, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image, and the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image, wherein the first node has a greater influence on the accuracy of the image processing task than the second node, and M is greater than N; and the image processing task is performed according to the processing result.

[0193] The description of the processing module 1202 can refer to the description of steps 902 and 903 in the above embodiments, and will not be repeated here.

[0194] In a possible implementation, the image processing task is super-resolution, image denoising, image segmentation, or image recognition.

[0195] In a possible implementation, the first node is a node in a high-frequency region of the image relative to the second node.

[0196] In a possible implementation, the graph neural network includes a plurality of blocks, the first fusion result is obtained by aggregating information of the first node and information of M nodes on the image by using a target block in the plurality of blocks, and the second fusion result is obtained by aggregating information of the second node and information of N nodes on the image by using the target block.

[0197] In a possible implementation, the processing module 1202 is further configured to:

[0198] obtain a total aggregation value and a total influence degree of nodes on the image on the accuracy of the image processing task, wherein the total aggregation value is related to the current computing power;

[0199] determine the value of M according to the total aggregation value and a relationship between the influence degree of the first node on the accuracy of the image processing task and the total influence degree;

[0200] determine the value of N according to the total aggregation value and a relationship between the influence degree of the second node on the accuracy of the image processing task and the total influence degree.

[0201] In a possible implementation, the graph neural network includes a first block and a second block.

[0202] The processing module 1202 is specifically configured to:

[0203] The first block is used to perform the first aggregation of the nodes in the image, wherein the aggregation object of the nodes in the first aggregation is selected from the nodes included in one continuous image region.

[0204] The second block is used to perform the aggregation of the nodes in the image, wherein the aggregation object of the nodes in the second aggregation is selected from the nodes in the plurality of regions of the image, and there is a gap between adjacent regions in the plurality of regions.

[0205] Next, an execution device provided by an embodiment of the present application is introduced. Referring to FIG. 13, FIG. 13 is a structural schematic diagram of an execution device provided by an embodiment of the present application. The execution device 1300 can be specifically a virtual reality (VR) device, a mobile phone, a tablet computer, a notebook computer, a smart wearable device, a monitoring data processing device, a server, or the like, which is not limited here. Specifically, the execution device 1300 includes a receiver 1301, a transmitter 1302, a processor 1303, and a memory 1304 (wherein the number of the processor 1303 in the execution device 1300 can be one or more, and one processor is taken as an example in FIG. 13). The processor 1303 can include an application processor 13031 and a communication processor 13032. In some embodiments of the present application, the receiver 1301, the transmitter 1302, the processor 1303, and the memory 1304 can be connected through a bus or other means.

[0206] The memory 1304 can include a read-only memory and a random access memory, and provide the processor 1303 with instructions and data. A part of the memory 1304 can also include a non-volatile random access memory (NVRAM). The memory 1304 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or expanded sets thereof, wherein the operation instructions can include various operation instructions for implementing various operations.

[0207] The processor 1303 controls the operation of the execution device. In specific applications, various components of the execution device are coupled together through a bus system, which can include a data bus, a power supply bus, a control bus, and a state signal bus, etc. However, for the sake of clarity, all kinds of buses are referred to as a bus system in the figure.

[0208] The method disclosed in the embodiments of the present application can be applied to the processor 1303 or implemented by the processor 1303. The processor 1303 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 1303 or by instructions in the form of software. The processor 1303 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor 1303 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the storage 1304, and the processor 1303 reads the information in the storage 1304 and combines the hardware to complete the steps of the above method.

[0209] The receiver 1301 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the execution device. The transmitter 1302 can be used to output digital or character information; the transmitter 1302 can also be used to send instructions to the disk set to modify the data in the disk set.

[0210] In the embodiments of the present application, in one case, the processor 1303 is used to execute the data processing method executed by the execution device in the above embodiments.

[0211] The embodiment of the present application further provides a training device. Please refer to FIG. 14, which is a structural schematic diagram of the training device according to the embodiment of the present application. The training device 1400 can be deployed with the device described in the embodiment corresponding to FIG. 12. Specifically, the training device 1400 is implemented by one or more servers. The training device 1400 can be quite different due to different configurations or performances, and can include one or more central processing units (CPUs) 1414 (for example, one or more processors) and a memory 1432, one or more storage media 1430 (for example, one or more mass storage devices) for storing application programs 1442 or data 1444. The memory 1432 and the storage media 1430 can be temporary storage or persistent storage. The programs stored in the storage media 1430 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the training device. Furthermore, the central processing unit 1414 can be configured to communicate with the storage media 1430 and execute the series of instruction operations in the storage media 1430 on the training device 1400.

[0212] The training device 1400 can further include one or more power supplies 1426, one or more wired or wireless network interfaces 1450, one or more input and output interfaces 1458, or one or more operating systems 1441, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

[0213] In the embodiment of the present application, the central processing unit 1414 is configured to execute the method in the embodiment corresponding to FIG. 8.

[0214] The embodiment of the present application further provides a computer program product, which, when running on a computer, causes the computer to perform the steps performed by the data processing device described above, or causes the computer to perform the steps performed by the data processing device described above.

[0215] The embodiment of the present application further provides a computer readable storage medium, which stores a program for signal processing, and when running on a computer, causes the computer to perform the steps performed by the data processing device described above, or causes the computer to perform the steps performed by the data processing device described above.

[0216] The execution device, the training device or the terminal device provided in the embodiments of the present application can specifically be a chip, which comprises a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin or a circuit, etc. The processing unit can execute computer execution instructions stored in a storage unit, so that the chip in the execution device executes the data processing method described in the above embodiments, or so that the chip in the training device executes the data processing method described in the above embodiments. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0217] Specifically, refer to FIG. 15, which is a structural schematic diagram of a chip provided in the embodiments of the present application. The chip can be a neural network processor NPU 1500, which is mounted on a host CPU (Host CPU) as a coprocessor and is assigned tasks by the Host CPU. The core part of the NPU is an operation circuit 1503, which extracts matrix data in a memory and performs multiplication operation under the control of a controller 1504.

[0218] In some implementations, the operation circuit 1503 internally comprises a plurality of processing units (PEs). In some implementations, the operation circuit 1503 is a two-dimensional systolic array. The operation circuit 1503 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 1503 is a general-purpose matrix processor.

[0219] For example, it is assumed that there are an input matrix A, a weight matrix B and an output matrix C. The operation circuit takes corresponding data of the matrix B from the weight memory 1502 and caches it on each PE in the operation circuit. The operation circuit takes the matrix A data from the input memory 1501 and performs matrix operation with the matrix B, and the partial result or final result of the obtained matrix is saved in an accumulator 1508.

[0220] The unified memory 1506 is used to store input data and output data. The weight data is transferred to the weight memory 1502 through a direct memory access controller (DMAC) 1505. The input data is also transferred to the unified memory 1506 through the DMAC.

[0221] BIU is Bus Interface Unit, i.e., the bus interface unit 1510, which is used for the interaction between the AXI bus and the DMAC and the instruction fetch buffer (IFB) 1509.

[0222] The bus interface unit 1510 (Bus Interface Unit, referred to as BIU) is used for the instruction fetch buffer 1509 to obtain instructions from the external memory, and is also used for the storage unit access controller 1505 to obtain the original data of the input matrix A or the weight matrix B from the external memory.

[0223] The DMAC is mainly used to carry the input data in the external memory DDR to the unified memory 1506, or carry the weight data to the weight memory 1502, or carry the input data to the input memory 1501.

[0224] The vector calculation unit 1507 includes a plurality of operation processing units, which further process the output of the operation circuit as needed, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolution / full connection layer network calculation in neural network, such as batch normalization, pixel-level summation, upsampling of feature plane, etc.

[0225] In some implementations, the vector calculation unit 1507 can store the processed output vector to the unified memory 1506. For example, the vector calculation unit 1507 can apply a linear function; or, a nonlinear function to the output of the operation circuit 1503, such as linear interpolation on the feature plane extracted by the convolution layer, and for example, a vector of accumulated values to generate an activation value. In some implementations, the vector calculation unit 1507 generates normalized values, pixel-level summation values, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 1503, for example, for use in subsequent layers in the neural network.

[0226] The controller 1504 is connected to the instruction fetch buffer 1509, which is used to store instructions used by the controller 1504;

[0227] The unified memory 1506, the input memory 1501, the weight memory 1502, and the instruction fetch buffer 1509 are all on-chip memories. The external memory is private to the NPU hardware architecture.

[0228] The processor mentioned in any of the above can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling execution of the above programs.

[0229] It should be noted that the above-described apparatus embodiments are merely illustrative, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. In addition, the connection relationship between the modules in the apparatus embodiments provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0230] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware, and of course it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including a plurality of instructions for making a computer device (which can be a personal computer, training device, or network device, etc.) execute the methods described in various embodiments of the present application.

[0231] In the above embodiments, all or part can be realized by software, hardware, firmware or any combination thereof. When realized by software, it can be realized in the form of a computer program product in whole or in part.

[0232] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as a training device, a data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A data processing method, characterized by, The method comprises: obtaining an image, the image comprising a first node and a second node, the first node and the second node being different pixel points or image blocks on the image; processing the image by a graph neural network to obtain a processing result, the processing result comprising a first fusion result and a second fusion result, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image, wherein the first node has a greater influence on the accuracy of an image processing task than the second node, and M is greater than N; performing the image processing task according to the processing result.

2. The method of claim 1, wherein, The image processing task is super-resolution, image denoising, image segmentation, or image recognition.

3. The method according to claim 1 or 2, characterized in that, The first node is a node in a high-frequency region of the image relative to the second node.

4. The method according to any one of claims 1 to 3, characterized in that, The graph neural network comprises a plurality of blocks, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image by a target block in the plurality of blocks, and the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image by the target block.

5. The method according to any one of claims 1 to 4, characterized in that, The method further comprises: obtaining a total aggregation value and a total influence of nodes on the image on the accuracy of the image processing task, the total aggregation value being related to a current computing power; determining the value of M according to the total aggregation value and a relationship between the influence of the first node on the accuracy of the image processing task and the total influence; determining the value of N according to the total aggregation value and a relationship between the influence of the second node on the accuracy of the image processing task and the total influence.

6. The method according to any one of claims 1 to 5, characterized in that, The graph neural network comprises a first block and a second block. The processing of the image by the graph neural network to obtain a processing result comprises: performing first aggregation on nodes in the image by the first block, wherein the aggregation objects of the nodes during the first aggregation are selected from nodes included in a continuous image region; performing aggregation on nodes in the image by the second block, wherein the aggregation objects of the nodes during the second aggregation are selected from nodes in a plurality of regions of the image, and there is a gap between adjacent regions in the plurality of regions.

7. A data processing apparatus, characterized by The apparatus comprises: an obtaining module configured to obtain an image, the image comprising a first node and a second node, the first node and the second node being different pixel points or image blocks on the image; The processing module is configured to process the image by using a graph neural network to obtain a processing result, the processing result including a first fusion result and a second fusion result, the first fusion result being obtained by aggregating information of the first node and information of M nodes on the image, the second fusion result being obtained by aggregating information of the second node and information of N nodes on the image, the first node having a greater influence on the accuracy of the image processing task than the second node, and the M being greater than the N; and the image processing task being performed according to the processing result.

8. The apparatus of claim 7, wherein, The image processing task is super-resolution, image denoising, image segmentation, or image recognition.

9. The apparatus of claim 7 or 8, wherein, The first node is a node in a high-frequency region of the image relative to the second node.

10. The apparatus of any one of claims 7 to 9, wherein, The graph neural network includes a plurality of blocks, the first fusion result being obtained by aggregating, by a target block of the plurality of blocks, the information of the first node and the information of the M nodes on the image, and the second fusion result being obtained by aggregating, by the target block, the information of the second node and the information of the N nodes on the image.

11. The apparatus of any one of claims 7 to 10, wherein, The processing module is further configured to: obtain a total aggregation value and a total influence of nodes on the image on the accuracy of the image processing task, the total aggregation value being related to a current computing power; determine the value of the M according to the total aggregation value and a relationship between the influence of the first node on the accuracy of the image processing task and the total influence; determine the value of the N according to the total aggregation value and a relationship between the influence of the second node on the accuracy of the image processing task and the total influence.

12. The apparatus of any one of claims 7 to 11, wherein, The graph neural network includes a first block and a second block. The processing module is specifically configured to: perform first aggregation on the nodes in the image by using the first block, the aggregation objects of the nodes being selected from nodes included in one continuous image region during the first aggregation; perform aggregation on the nodes in the image by using the second block, the aggregation objects of the nodes being selected from nodes in a plurality of regions of the image, and there being a gap between adjacent regions of the plurality of regions.

13. A computing device, comprising: The computing device includes at least one processor and at least one memory having computer-readable instructions stored therein, and the at least one processor executes the computer-readable instructions to cause the computing device to perform the method of any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, The computer-readable instructions are configured to implement the method of any one of claims 1 to 6.

15. A computer program product, characterised in that, The computer-readable instructions are configured to implement the method of any one of claims 1 to 6.

16. A chip, characterized by comprising at least one processing unit and an interface circuit for providing program instructions or data to the at least one processing unit, the at least one processing unit being configured to execute the program instructions to implement the method of any one of claims 1 to 6.

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