Shift register, light-emission driving circuit, and display apparatus

Abstract

A shift register, a light-emission control circuit, and a display apparatus. The shift register comprises: an input sub-circuit (1), which is configured to control, in response to a clock signal (CK), the potential of a first node (N1) by using an input signal (EMM(i-1)); a first control sub-circuit (2), which is configured to control, in response to the input signal (EMM(i-1)), the potential of a second node (N2) by using a first power signal (VGL1), or control, in response to a control signal (QB), the potential of the second node (N2) by using the clock signal (CK); a second control sub-circuit (3), which is configured to control, in response to the potential of the second node (N2), the potential of the third node (N3) by using the clock signal (CK), or control, in response to the potential of the first node (N1), the potential of the third node (N3) by using the first power signal (VGL1); and an output sub-circuit (4), which is configured to output a second power signal (VGH 1) via a signal output end (OUT) in response to the potential of the first node (N1), or output the first power signal (VGL1) via the signal output end (OUT) in response to the potential of the third node (N3).

Description

Shift register, light-emitting driving circuit and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a light-emitting driving circuit, and a display device. Background Technology

[0002] The display of an Organic Light-Emitting Diode (OLED) display panel requires a scan drive sub-circuit to provide scan drive signals. This scan drive sub-circuit mainly consists of two parts: a display panel scan drive (Gate D-IC On Array, GOA) sub-circuit and a display panel emission drive (Emission D-IC On Array, EOA) sub-circuit. The EOA sub-circuit outputs the emission control signal EM.

[0003] In display products, screen display latency is a key performance parameter. The higher the screen display latency, the more noticeable the ghosting phenomenon caused by the latency. To achieve lower screen display latency and solve the ghosting problem caused by response time, black insertion compensation can be performed on the internal pixel sub-circuit. For example, the light emission control signal EM can be adjusted to a multi-pulse signal (i.e., a black insertion signal) to perform low grayscale dimming.

[0004] However, the inventors found that the existing EOA sub-circuit is relatively complex, and its practicality and stability are poor. Summary of the Invention

[0005] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a shift register, a light-emitting driving circuit, and a display device.

[0006] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a shift register, including an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit;

[0007] The input sub-circuit is configured to control the potential of the first node in response to a clock signal using an input signal;

[0008] The first control sub-circuit is configured to control the potential of the second node using a first power supply signal in response to the input signal; or, in response to a control signal, control the potential of the second node using the clock signal.

[0009] The second control sub-circuit is configured to control the potential of the third node using the clock signal in response to the potential of the second node; or, to control the potential of the third node using the first power supply signal in response to the potential of the first node.

[0010] The output sub-circuit is configured to output a second power signal through the signal output terminal in response to the potential of the first node, or to output a first power signal through the signal output terminal in response to the potential of the third node.

[0011] In some embodiments, the second control sub-circuit includes a fourth transistor and an eighth transistor;

[0012] The first electrode of the fourth transistor is electrically connected to the clock signal line that transmits the clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node.

[0013] The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line that transmits the first power signal, and the control electrode is electrically connected to the first node.

[0014] In some embodiments, the first control sub-circuit includes a sixth transistor and a seventh transistor;

[0015] The first electrode of the sixth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal.

[0016] The first electrode of the seventh transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal.

[0017] In some embodiments, the input sub-circuit includes a first transistor; the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, and a fifth transistor;

[0018] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the clock signal line that transmits the clock signal.

[0019] The first electrode of the third transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the control electrode is electrically connected to the first node.

[0020] The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

[0021] The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor.

[0022] The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor.

[0023] In some embodiments, the shift register further includes a pull-up sub-circuit;

[0024] The pull-up sub-circuit is configured to isolate the first node and the input sub-circuit electrically connected to the first node;

[0025] The pull-up sub-circuit is electrically connected to the fourth node and the first node, the input sub-circuit is electrically connected to the fourth node, and the second control sub-circuit is electrically connected to the fourth node and the third node.

[0026] In some embodiments, the input sub-circuit includes a first transistor; the pull-up sub-circuit includes a second transistor; the first control sub-circuit includes a sixth transistor and a seventh transistor; the second control sub-circuit includes a fourth transistor and an eighth transistor; and the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, and a fifth transistor.

[0027] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the clock signal line that transmits the clock signal.

[0028] The first electrode of the second transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the second power signal line that transmits the second power signal.

[0029] The first electrode of the sixth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal.

[0030] The first electrode of the seventh transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal.

[0031] The first electrode of the fourth transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node;

[0032] The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line, and the control electrode is electrically connected to the fourth node.

[0033] The first electrode of the third transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the second power signal line, and the control electrode is electrically connected to the first node.

[0034] The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

[0035] The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor.

[0036] The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor.

[0037] In some embodiments, the first control sub-circuit includes a sixth transistor, a seventh transistor, a ninth transistor, and a tenth transistor;

[0038] The first electrode of the sixth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the signal input terminal.

[0039] The first electrode of the ninth transistor is electrically connected to the fifth node, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal.

[0040] The first electrode of the tenth transistor is electrically connected to the fifth node, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the control electrode is electrically connected to the second node.

[0041] The first electrode of the seventh transistor is electrically connected to the clock signal line that transmits the clock signal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal.

[0042] In some embodiments, the input sub-circuit includes a first transistor, a thirteenth transistor, and a fourteenth transistor; the first transistor has its first electrode electrically connected to a seventh node, its second electrode electrically connected to the first node, and its control electrode electrically connected to the clock signal line; the thirteenth transistor has its first electrode electrically connected to the signal input terminal, its second electrode electrically connected to the seventh node, and its control electrode electrically connected to the clock signal line; the fourteenth transistor has its first electrode electrically connected to the seventh node, its second electrode electrically connected to the second power supply signal line, and its control electrode electrically connected to the first node.

[0043] In some embodiments, the second control sub-circuit includes a fourth transistor, an eighth transistor, a fifteenth transistor, and a sixteenth transistor; the first electrode of the fourth transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; the first electrode of the eighth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first power signal line, and the control electrode is electrically connected to the first node; the first electrode of the fifteenth transistor is electrically connected to the third node, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first node; the first electrode of the sixteenth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the third node.

[0044] In some embodiments, the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, a fifth transistor, a seventeenth transistor, and an eighteenth transistor;

[0045] The first electrode of the third transistor is electrically connected to the next stage signal input terminal, the second electrode is electrically connected to the second power supply signal line, and the control electrode is electrically connected to the first node; the next stage signal input terminal is the signal input terminal of the next stage shift register cascaded with the shift register;

[0046] The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the next stage signal input terminal, and the control electrode is electrically connected to the third node.

[0047] The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor.

[0048] The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor;

[0049] The first electrode of the seventeenth transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the third power signal line, and the control electrode is electrically connected to the first node.

[0050] The first electrode of the eighteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

[0051] In some embodiments, the absolute value of the voltage of the third power signal transmitted by the third power signal line is less than the absolute value of the voltage of the second power signal transmitted by the second power signal line.

[0052] The absolute value of the voltage of the fourth power signal transmitted by the fourth power signal line is greater than the absolute value of the voltage of the first power signal transmitted by the first power signal line.

[0053] In some embodiments, the input signal and the control signal have the same timing but opposite potentials.

[0054] In some embodiments, at the same time, the potentials of the first node and the second node are opposite.

[0055] Secondly, embodiments of this disclosure also provide a light-emitting driving circuit, including N cascaded shift registers as described in any one of the first aspects;

[0056] Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0057] In some embodiments, the control signal line of the shift register of the (i+1)th stage is electrically connected to the third node of the shift register of the i-th stage.

[0058] In some embodiments, the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, a fifth transistor, a seventeenth transistor, and an eighteenth transistor;

[0059] The first terminal of the third transistor of the i-th stage shift register is electrically connected to the signal input terminal of the (i+1)-th stage shift register, the second terminal is electrically connected to the second power supply signal line, and the control terminal is electrically connected to the first node;

[0060] The first electrode of the fifth transistor in the i-th stage shift register is electrically connected to the first power supply signal line, the second electrode is electrically connected to the signal input terminal of the (i+1)-th stage shift register, and the control electrode is electrically connected to the third node.

[0061] The first plate of the first capacitor of the i-th stage shift register is electrically connected to the first node, and the second plate is electrically connected to the first terminal of the third transistor.

[0062] The first plate of the second capacitor in the i-th stage shift register is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor;

[0063] The first electrode of the seventeenth transistor in the i-th stage shift register is electrically connected to the signal output terminal, the second electrode is electrically connected to the third power supply signal line, and the control electrode is electrically connected to the first node.

[0064] The first electrode of the eighteenth transistor in the i-th stage shift register is electrically connected to the fourth power supply signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

[0065] Thirdly, embodiments of this disclosure also provide a display device, which includes a light-emitting driving circuit as described in any one of the second aspects. Attached Figure Description

[0066] Figure 1a is a schematic diagram of an existing pixel driving circuit;

[0067] Figure 1b is the timing control diagram of the circuit shown in Figure 1a;

[0068] Figure 2 is a schematic diagram of an exemplary pixel driving circuit used in an embodiment of this disclosure;

[0069] Figure 3 is the timing control diagram of the circuit shown in Figure 2;

[0070] Figure 4 is a schematic diagram of a shift register provided in an embodiment of this disclosure;

[0071] Figure 5 is a circuit diagram of a shift register under the first example provided in the embodiments of this disclosure;

[0072] Figure 6 is a circuit diagram of a shift register under the second example provided in the embodiments of this disclosure;

[0073] Figure 7 is a circuit diagram of a shift register under the third example provided in the embodiments of this disclosure;

[0074] Figure 8 is a circuit diagram of a shift register under the fourth example provided in the embodiments of this disclosure;

[0075] Figure 9 is a circuit diagram of a shift register under the fifth example provided in the embodiments of this disclosure;

[0076] Figure 10 is a circuit diagram of a shift register under the sixth example provided in the embodiments of this disclosure;

[0077] Figure 11 is a circuit diagram of a shift register under the seventh example provided in the embodiments of this disclosure;

[0078] Figure 12 is a circuit diagram of a shift register under the eighth example provided in the embodiments of this disclosure;

[0079] Figure 13 is a circuit diagram of a shift register under the ninth example provided in the embodiments of this disclosure;

[0080] Figure 14 is a timing diagram of an exemplary shift register provided in an embodiment of this disclosure;

[0081] Figure 15 is a schematic diagram of a light-emitting driving circuit provided in an embodiment of this disclosure;

[0082] Figure 16 is a schematic diagram of another light-emitting driving circuit provided in an embodiment of this disclosure. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0084] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0085] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0086] In related technologies, as shown in Figure 1a, a 3T1C (i.e., 3 transistors and 1 capacitor) pixel driving circuit is used to drive the OLED light-emitting device to emit light. As shown in Figure 1b, the main stages are the data writing stage and the emission stage. In the data writing stage: G1 and G2 simultaneously provide high-level signals, and T1 and T2 are simultaneously turned on to write DATA data. In the emission stage: G1 and G2 simultaneously provide low-level signals, and T1 and T2 are simultaneously turned off. At this time, node G bootstraps, and the OLED light-emitting device begins to emit light until the next data writing stage. To perform black insertion compensation in the above pixel driving circuit, an external, expensive source driver chip with compensation functionality is required, and the compensation algorithm is also relatively complex.

[0087] This disclosure provides an internal compensation circuit, as shown in Figure 2. A 5T1C (i.e., 5 transistors and 1 capacitor) pixel driving circuit is used to drive the OLED light-emitting device to emit light. During this process, a multi-pulse EM signal is provided for low grayscale dimming. The control timing is shown in Figure 3, mainly divided into a reset phase, an initial compensation phase, a data write phase, a charging phase, a black insertion compensation phase, and a next charging phase. Specifically, in the reset phase: G3 provides a high-level signal, T5 turns on, and node G is reset; subsequently, G2 provides a high-level signal, T2 turns on, and node S is reset. In the compensation phase: G3 provides a low-level signal, T5 turns off, and T2 remains on. At this time, because the driving voltage Vgs of T3 is greater than the threshold voltage Vth, node S begins charging until Vgs = Vth, and T3 turns off. In the data write phase: G1 provides a high-level signal, T1 turns on, the data signal (DATA) is written to node G, and T3 turns on. Charging phase (emission): G1 provides a low-level signal, T1 is off, EM provides a high-level signal, T4 is on, and the OLED starts emitting light. Black insertion phase (insertion black): EM provides a low-level signal, T4 is off, the OLED stops emitting light and is cut off, until EM provides a high-level signal to emit light again. Here, the signal provided by EM is a multi-pulse signal, also known as the black insertion signal (EM signal), used for low grayscale dimming. The circuit used to provide the EM signal is the EOA sub-circuit, i.e., the light-emitting drive circuit. However, the inventors found that the EOA sub-circuit in the prior art is relatively complex, and its practicality and stability are poor.

[0088] Therefore, this disclosure provides a shift register with simple circuitry, high practicality, and good stability. The specific functional structure of the shift register provided in this disclosure will be described in detail below.

[0089] Figure 4 is a schematic diagram of a shift register provided in an embodiment of this disclosure. As shown in Figure 4, the shift register includes an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3, and an output sub-circuit 4.

[0090] Input sub-circuit 1 is electrically connected to the signal input terminal Input, the clock signal line, and the first node N1; input sub-circuit 1 can receive the input signal EM from the signal input terminal Input. <i-1>And receive the clock signal CK transmitted from the clock signal line. Input sub-circuit 1 is configured to respond to the clock signal CK by utilizing the input signal EM. <i-1>Control the potential of the first node N1.

[0091] The first control sub-circuit 2 is electrically connected to the signal input terminal Input, the first power signal line, and the second node N2. The first control sub-circuit 2 can receive the input signal EM from the signal input terminal Input. <i-1>The first control sub-circuit 2 also receives a first power signal VGL1 transmitted from the first power signal line. Additionally, the first control sub-circuit 2 is electrically connected to a control signal line and a clock signal line. The first control sub-circuit 2 can also receive a control signal QB transmitted from the control signal line and a clock signal CK transmitted from the clock signal line. In one case, the first control sub-circuit 2 is configured to respond to an input signal EM. <i-1>The potential of the second node N2 is controlled by the first power supply signal VGL1. Alternatively, in another case, the first control sub-circuit 2 is configured to control the potential of the second node N2 by using the clock signal CK in response to the control signal QB.

[0092] For example, the input signal EM <i-1>The timing is the same as that of the control signal QB, but the potential is opposite, so that the first control sub-circuit 2 controls the potential of the second node N2 in different ways.

[0093] It should be noted that timing in a circuit refers to the sequential switching of signals between high and low potentials. Same timing means that the potential transition times of the compared signals are consistent, but it does not mean that their potentials are the same at the same time point. In this embodiment of the disclosure, the input signal EM... <i-1>The timing is the same as that of the control signal QB, but the potential is opposite, and the absolute value of the potential can be the same.

[0094] For example, the control signal line can be a signal line derived from an independent control signal source, or it can be a signal line electrically connected to the previous cascaded shift register. For instance, the control signal line could be the third node N3 electrically connected to the previous cascaded shift register. <i-1>The signal line.

[0095] The second control sub-circuit 3 is electrically connected to the first node N1, the first power signal line, and the third node N3. The second control sub-circuit 3 can receive the potential from the first node N1 and the first power signal VGL1 transmitted from the first power signal line. Additionally, the second control sub-circuit 3 is also electrically connected to the second node N2 and the clock signal line. The second control sub-circuit 3 can receive the potential from the second node N2 and the clock signal CK transmitted from the clock signal line. In one case, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the clock signal CK in response to the potential of the second node N2. Alternatively, in another case, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first power signal VGL1 in response to the potential of the first node N1.

[0096] For example, the signals of the first node N1 and the second node N2 have the same timing but opposite potentials, thereby enabling the second control sub-circuit 3 to control the potential of the third node N3 in different ways.

[0097] Output sub-circuit 4 is electrically connected to the first node N1 and the second power signal line. Output sub-circuit 4 can receive the voltage from the first node N1 and the second power signal VGH1 transmitted from the second power signal line. Additionally, output sub-circuit 4 is also electrically connected to the third node N3 and the first power signal line. Output sub-circuit 4 can receive the voltage from the third node N3 and the first power signal VGL1 transmitted from the first power signal line. In one configuration, output sub-circuit 4 is configured to output the second power signal VGH1 through the signal output terminal Out in response to the voltage of the first node N1. Alternatively, in another configuration, output sub-circuit 4 is configured to output the first power signal VGL1 through the signal output terminal Out in response to the voltage of the third node N3.

[0098] For example, the signals of the first node N1 and the third node N3 have the same timing but opposite potentials, thereby enabling the output sub-circuit 4 to output different power signals.

[0099] This disclosed embodiment only uses the input signal EM <i-1>With just one clock signal line and one first power supply signal line, the output of either the first power supply signal VGL1 or the second power supply signal VGH1 can be controlled, thereby achieving light emission control. This shift register has a simple circuit structure and is therefore highly practical.

[0100] The shift register described above can adopt a 7T2C (i.e., 7 transistors and 2 capacitors) circuit structure; or, the shift register can adopt an 8T2C (i.e., 8 transistors and 2 capacitors) circuit structure; or, the shift register can adopt a 9T2C (i.e., 9 transistors and 2 capacitors) circuit structure; or, the shift register can adopt an 11T2C (i.e., 11 transistors and 2 capacitors) circuit structure; or, the shift register can adopt a 13T2C (i.e., 13 transistors and 2 capacitors) circuit structure.

[0101] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0102] It should be noted that thin-film transistors (TFTs) can be either N-type or P-type. An N-type TFT refers to a TFT with N-type ion doping in the active layer, while a P-type TFT refers to a TFT with P-type ion doping in the active layer. The operating voltage level for an N-type TFT is high, while the operating voltage level for a P-type TFT is low.

[0103] It should be noted that, in the embodiments of this disclosure, the internal circuit structure of the shift register may be any other number of transistors (with the number of capacitors remaining unchanged) in addition to the 7T2C, 8T2C, 9T2C, 11T2C and 13T2C listed above. This disclosure does not limit this.

[0104] The shift registers with circuit structures of 7T2C, 8T2C, 9T2C, 10T2C, 11T2C, 12T2C, and 13T2C are described in detail below using different embodiments. For ease of understanding, this disclosure uses an N-type thin-film transistor as an example in the following embodiments, but this disclosure is not limited to N-type thin-film transistors.

[0105] In some embodiments, FIG5 is a circuit diagram of a shift register under a first example provided in the present disclosure. As shown in FIG5, the input sub-circuit 1 includes a first transistor T1; the first control sub-circuit 2 includes a sixth transistor T6 and a seventh transistor T7; the second control sub-circuit 3 includes a fourth transistor T4 and an eighth transistor T8; and the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, and a fifth transistor T5.

[0106] For input sub-circuit 1: the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the clock signal line that transmits the clock signal CK. Specifically, the clock signal CK can control the on / off state of the first transistor T1. When the first transistor T1 responds to the clock signal CK and conducts, it can transmit the input signal EM. <i-1>Transmitted to the first node N1.

[0107] For the first control sub-circuit 2: the first electrode of the sixth transistor T6 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input; the first electrode of the seventh transistor T7 is electrically connected to the clock signal line, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line transmitting the control signal QB. Specifically, the input signal EM <i-1>The switching on and off of the sixth transistor T6 can be controlled, and the sixth transistor T6 responds to the input signal EM. <i-1>When the transistor is turned on, the first power supply signal VGL1 can be transmitted to the second node N2. Alternatively, the control signal QB can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the control signal QB and turns on, the clock signal CK can be transmitted to the second node N2.

[0108] For the second control sub-circuit 3: the first electrode of the fourth transistor T4 is electrically connected to the clock signal line, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2; the first electrode of the eighth transistor T8 is electrically connected to the third node N3, the second electrode is electrically connected to the first power signal line, and the control electrode is electrically connected to the first node N1. Specifically, the potential of the second node N2 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the potential of the second node N2 and conducts, the clock signal CK can be transmitted to the third node N3. Alternatively, the potential of the first node N1 can control the on / off state of the eighth transistor T8. When the eighth transistor T8 responds to the potential of the first node N1 and conducts, the first power signal VGL1 can be transmitted to the third node N3.

[0109] For output sub-circuit 4: the first electrode of the third transistor T3 is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the second power signal line transmitting the second power signal VGH1, and the control electrode is electrically connected to the first node N1; the first electrode of the fifth transistor T5 is electrically connected to the first power signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3; the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate is electrically connected to the first electrode of the fifth transistor T5. Specifically, the potential of the first node N1 can control the on / off state of the third transistor T3. When the third transistor T3 responds to the potential of the first node N1 and conducts, the second power signal VGH1 can be output through the signal output terminal Out; or, the potential of the third node N3 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the potential of the third node N3 and conducts, the first power signal VGL1 can be output through the signal output terminal Out.

[0110] Here, the first capacitor C1 is mainly used to bootstrap the potential of the first node N1 to a higher potential, thereby ensuring that the third transistor T3 remains on and thus stabilizing the output of the second power supply signal VGH1. The second capacitor C2 is mainly used to stabilize the potential of the third node N3 for a certain period of time when the fourth transistor T4 is turned off, thereby ensuring that the fifth transistor T5 remains on and thus stabilizing the output of the first power supply signal VGL1.

[0111] This disclosure utilizes a clock signal CK to control the conduction of the first transistor T1, and transmits an input signal EM. <i-1>The third transistor T3 is controlled to conduct, thereby outputting the second power supply signal VGH1; alternatively, the seventh transistor T7 is controlled to conduct using the control signal QB, and the fourth transistor T4 is controlled to conduct using the transmitted clock signal CK. The fifth transistor T5 is then controlled to conduct using the clock signal CK again, thereby outputting the first power supply signal VGL1. This process involves fewer signal lines and a simpler circuit structure. Furthermore, compared to existing technologies that require multiple capacitors (≥3), this embodiment only uses two capacitors, resulting in a simpler circuit structure.

[0112] In some embodiments, FIG6 is a circuit diagram of a shift register under a second example provided in the present disclosure, which differs from the circuit structure shown in FIG5 in that a pull-up circuit 5 is added.

[0113] As shown in Figure 6, the shift register also includes a pull-up sub-circuit 5; the pull-up sub-circuit 5 is configured to isolate the first node N1 and the input sub-circuit 1 electrically connected to the first node N1 to improve the stable output of the second power supply signal VGH1. The pull-up sub-circuit 5 is electrically connected to the fourth node and the first node N1, the input sub-circuit 1 is electrically connected to the fourth node, and the second control sub-circuit 3 is electrically connected to the fourth node and the third node N3.

[0114] Specifically, as shown in Figure 6, the input sub-circuit 1 is configured to respond to the clock signal CK by utilizing the input signal EM. <i-1>The potential of the fourth node is controlled; the second control sub-circuit 3 is configured to control the potential of the third node N3 using the clock signal CK in response to the potential of the second node N2; or, in response to the potential of the fourth node, to control the potential of the third node N3 using the first power supply signal VGL1; the pull-up sub-circuit 5 is configured to control the potential of the first node N1 using the potential of the fourth node in response to the second power supply signal VGH1.

[0115] In some embodiments, as shown in FIG6, the input sub-circuit 1 includes a first transistor T1; the pull-up sub-circuit 5 includes a second transistor T2; the first control sub-circuit 2 includes a sixth transistor T6 and a seventh transistor T7; the second control sub-circuit 3 includes a fourth transistor T4 and an eighth transistor T8; and the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, and a fifth transistor T5.

[0116] For input sub-circuit 1: the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the clock signal line transmitting the clock signal CK. Specifically, the clock signal CK can control the on / off state of the first transistor T1. When the first transistor T1 responds to the clock signal CK and conducts, it can transmit the input signal EM. <i-1>Transmitted to the fourth node.

[0117] For pull-up circuit 5: the first electrode of the second transistor T2 is electrically connected to the fourth node, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second power signal line that transmits the second power signal VGH1. Specifically, the second power signal VGH1 controls the on / off state of the second transistor T2. When the second transistor T2 responds to the second power signal VGH1 and is turned on, it can transmit the signal from the fourth node to the first node N1.

[0118] For the first control sub-circuit 2: the first electrode of the sixth transistor T6 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input; the first electrode of the seventh transistor T7 is electrically connected to the clock signal line, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line transmitting the control signal QB. Specifically, the input signal EM <i-1>The switching on and off of the sixth transistor T6 can be controlled, and the sixth transistor T6 responds to the input signal EM. <i-1>When the transistor is turned on, the first power supply signal VGL1 can be transmitted to the second node N2. Alternatively, the control signal QB can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the control signal QB and turns on, the clock signal CK can be transmitted to the second node N2.

[0119] For the second control sub-circuit 3: the first electrode of the fourth transistor T4 is electrically connected to the clock signal line, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2; the first electrode of the eighth transistor T8 is electrically connected to the third node N3, the second electrode is electrically connected to the first power supply signal line, and the control electrode is electrically connected to the fourth node. Specifically, the potential of the second node N2 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the potential of the second node N2 and conducts, it can transmit the clock signal CK to the third node N3. Alternatively, the potential of the fourth node can control the on / off state of the eighth transistor T8. When the eighth transistor T8 responds to the potential of the fourth node and conducts, it can transmit the first power supply signal VGL1 to the third node N3.

[0120] For output sub-circuit 4: the first electrode of the third transistor T3 is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the second power supply signal line, and the control electrode is electrically connected to the first node N1; the first electrode of the fifth transistor T5 is electrically connected to the first power supply signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3; the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate is electrically connected to the first electrode of the fifth transistor T5. Specifically, the potential of the first node N1 can control the on / off state of the third transistor T3. When the third transistor T3 responds to the potential of the first node N1 and conducts, the second power supply signal VGH1 can be output through the signal output terminal Out; or, the potential of the third node N3 can control the on / off state of the fifth transistor T5. When the fifth transistor T5 responds to the potential of the third node N3 and conducts, the first power supply signal VGL1 can be output through the signal output terminal Out.

[0121] Compared to the circuit structure shown in Figure 5, this embodiment adds a pull-up sub-circuit 5 (i.e., the second transistor T2). By setting the second transistor T2 to isolate the input sub-circuit 1 and the output sub-circuit 4, the input signal EM... <i-1>When a high potential is written, the potential of the first node N1 can be bootstrapped to a higher potential through the second transistor T2. Since the second transistor T2 is turned off when the first node N1 is at a high potential, it can keep the first node N1 at a high potential, thereby ensuring that the third transistor T3 is turned on and the second power supply signal VGH1 is output stably.

[0122] In some embodiments, FIG7 is a circuit diagram of a shift register under a third example provided in the present disclosure, the difference from the circuit structure shown in FIG5 is that a leakage protection structure (e.g., the ninth transistor T9 and the tenth transistor T10 described below) is added.

[0123] As shown in Figure 7, the first control sub-circuit 2 includes a sixth transistor T6, a seventh transistor T7, a ninth transistor T9, and a tenth transistor T10. The first electrode of the sixth transistor T6 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the signal input terminal Input. The first electrode of the ninth transistor T9 is electrically connected to the fifth node, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input. The first electrode of the tenth transistor T10 is electrically connected to the fifth node, the second electrode is electrically connected to the second power signal line transmitting the second power signal VGH1, and the control electrode is electrically connected to the second node N2. The first electrode of the seventh transistor T7 is electrically connected to the clock signal line transmitting the clock signal CK, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line transmitting the control signal QB.

[0124] Specifically, the input signal EM <i-1>It can simultaneously control the on / off state of the sixth transistor T6 and the ninth transistor T9, with the sixth transistor T6 responding to the input signal EM. <i-1>When the transistor is turned on, the first power signal VGL1 can be transmitted to the fifth node. Simultaneously, the ninth transistor T9 responds to the input signal EM. <i-1>When the transistor is turned on, the signal from the fifth node can be transmitted to the second node N2. Additionally, the potential of the second node N2 can control the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the potential of the second node N2 and is turned on, the second power supply signal VGH1 can be written to the fifth node.

[0125] It should be noted that, taking an N-type thin-film transistor as an example, if the threshold voltage of the sixth transistor T6 is negative, the voltage of the high-potential second node N2 will be reverse-propagated, causing the sixth transistor T6 to leak. After leakage, the potential of the second node N2 no longer remains high, causing the fourth transistor T4 to be cut off, and consequently preventing the fifth transistor T5 from turning on. This embodiment, by setting an anti-leakage structure, that is, adding a ninth transistor T9 and a tenth transistor T10 to the sixth transistor T6, when the potential of the second node N2 is high, the tenth transistor T10 turns on, and the second power signal VGH1 is written to the fifth node, making the potential of the fifth node high. At this time, both the first and second terminals of the ninth transistor T9 are high. Regardless of whether the threshold voltages of the sixth transistor T6 and the ninth transistor T9 are negative, the potential of the second node N2 always remains high, thereby suppressing reverse leakage and ensuring the stable conduction of the fourth transistor T4 and the fifth transistor T5.

[0126] In some embodiments, the first control sub-circuit 2 includes a sixth transistor T6, a seventh transistor T7, an eleventh transistor T11, and a twelfth transistor T12; the first electrode of the sixth transistor T6 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input; the first electrode of the seventh transistor T7 is electrically connected to the clock signal line transmitting the clock signal CK, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the control signal line transmitting the control signal QB; the first electrode of the eleventh transistor T11 is electrically connected to the sixth node, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line; the first electrode of the twelfth transistor T12 is electrically connected to the sixth node, the second electrode is electrically connected to the second power signal line transmitting the second power signal VGH1, and the control electrode is electrically connected to the second node N2.

[0127] Specifically, the control signal QB can simultaneously control the on / off state of the seventh transistor T7 and the eleventh transistor T11. When the seventh transistor T7 responds to the control signal QB and is turned on, the clock signal CK can be transmitted to the sixth node. Simultaneously, when the eleventh transistor T11 responds to the control signal QB and is turned on, the signal from the sixth node can be transmitted to the second node N2. Furthermore, the potential of the second node N2 can control the on / off state of the twelfth transistor T12. When the twelfth transistor T12 responds to the potential of the second node N2 and is turned on, the second power supply signal VGH1 can be written to the sixth node.

[0128] The principle of leakage protection in this embodiment is the same as that in Figure 7 above, and the repeated parts will not be described again. In this embodiment, by setting up a leakage protection structure, that is, by adding an eleventh transistor T11 and a twelfth transistor T12 on the basis of the seventh transistor T7, the stable conduction of the fourth transistor T4 and the fifth transistor T5 is ensured.

[0129] In some embodiments, FIG8 is a circuit diagram of a shift register under the fourth example provided in the present disclosure. The difference between FIG8 and the circuit structure shown in FIG5 is that a leakage protection structure is added (e.g., the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 described below). The difference between FIG8 and the circuit structure shown in FIG7 is that the eleventh transistor T11 and the twelfth transistor T12 are added.

[0130] As shown in Figure 8, the first control sub-circuit 2 includes a sixth transistor T6, a seventh transistor T7, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The first electrode of the sixth transistor T6 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the signal input terminal Input. The first electrode of the ninth transistor T9 is electrically connected to the fifth node, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input. The first electrode of the tenth transistor T10 is electrically connected to the fifth node, the second electrode... The first electrode of the seventh transistor T7 is electrically connected to the second power signal line transmitting the second power signal VGH1, and the control electrode is electrically connected to the second node N2; the first electrode of the seventh transistor T7 is electrically connected to the clock signal line transmitting the clock signal CK, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the control signal line transmitting the control signal QB; the first electrode of the eleventh transistor T11 is electrically connected to the sixth node, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line; the first electrode of the twelfth transistor T12 is electrically connected to the sixth node, the second electrode is electrically connected to the second power signal line transmitting the second power signal VGH1, and the control electrode is electrically connected to the second node N2.

[0131] Specifically, the input signal EM <i-1>It can simultaneously control the on / off state of the sixth transistor T6 and the ninth transistor T9, with the sixth transistor T6 responding to the input signal EM. <i-1>When the transistor is turned on, the first power signal VGL1 can be transmitted to the fifth node. Simultaneously, the ninth transistor T9 responds to the input signal EM. <i-1>When the transistor is turned on, the signal from the fifth node can be transmitted to the second node N2. Additionally, the potential of the second node N2 can control the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the potential of the second node N2 and turns on, the second power supply signal VGH1 can be written to the fifth node. The control signal QB can simultaneously control the on / off state of the seventh transistor T7 and the eleventh transistor T11. When the seventh transistor T7 responds to the control signal QB and turns on, the clock signal CK can be transmitted to the sixth node. Simultaneously, when the eleventh transistor T11 responds to the control signal QB and turns on, the signal from the sixth node can be transmitted to the second node N2. Furthermore, the potential of the second node N2 can control the on / off state of the twelfth transistor T12. When the twelfth transistor T12 responds to the potential of the second node N2 and turns on, the second power supply signal VGH1 can be written to the sixth node.

[0132] The principle of leakage protection in this embodiment is the same as that in Figure 7 above, and the repeated parts will not be described again. This embodiment ensures the stable conduction of the fourth transistor T4 and the fifth transistor T5 by setting up a leakage protection structure, that is, by adding the ninth transistor T9 and the tenth transistor T10 to the sixth transistor T6, and by adding the eleventh transistor T11 and the twelfth transistor T12 to the seventh transistor T7.

[0133] In some embodiments, FIG9 is a circuit diagram of a shift register under the fifth example provided in the present disclosure. The difference from the circuit structure shown in FIG5 is that a leakage protection structure is added (e.g., the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 described below).

[0134] As shown in Figure 9, the input sub-circuit 1 includes a first transistor T1, a thirteenth transistor T13, and a fourteenth transistor T14; the first electrode of the first transistor T1 is electrically connected to the seventh node, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the clock signal line; the first electrode of the thirteenth transistor T13 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the seventh node, and the control electrode is electrically connected to the clock signal line; the first electrode of the fourteenth transistor T14 is electrically connected to the seventh node, the second electrode is electrically connected to the second power supply signal line, and the control electrode is electrically connected to the first node N1.

[0135] Specifically, the clock signal CK can simultaneously control the on / off state of the first transistor T1 and the thirteenth transistor T13. When the thirteenth transistor T13 responds to the clock signal CK and turns on, it can transmit the input signal EM. <i-1>The signal is transmitted to the seventh node. Simultaneously, when the first transistor T1 responds to the clock signal CK and turns on, the signal from the seventh node can be transmitted to the first node N1. Furthermore, the potential of the first node N1 can control the on / off state of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the potential of the first node N1 and turns on, the second power supply signal VGH1 can be transmitted to the seventh node.

[0136] For example, when the shift register also includes a pull-up circuit 5, as shown in Figure 6, when the first transistor T1 responds to the clock signal CK and turns on, the signal from the seventh node can be transmitted to the fourth node. The potential of the fourth node can control the on / off state of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the potential of the fourth node and turns on, the second power supply signal VGH1 can be transmitted to the seventh node.

[0137] It should be noted that, taking an N-type thin-film transistor as an example, if the threshold voltage of the first transistor T1 is negative, the voltage of the high-potential first node N1 will be reversed, causing leakage in the first transistor T1; if the input signal EM is at this time... <i-1>When the potential of the first node N1 is low, the potential of the first node N1 after leakage will no longer remain high, causing the third transistor T3 to be cut off, thus preventing the output of the second power signal VGH1. This embodiment addresses this by setting an anti-leakage structure, that is, adding a thirteenth transistor T13 and a fourteenth transistor T14 to the first transistor T1. When the potential of the first node N1 is high, the fourteenth transistor T14 turns on, and the second power signal VGH1 is written to the seventh node, making the potential of the seventh node high. At this time, both the first and second terminals of the first transistor T1 are at high potentials. Regardless of whether the threshold voltages of the first transistor T1 and the thirteenth transistor T13 are negative, the potential of the first node N1 always remains high, thereby suppressing reverse leakage and ensuring the stable conduction of the third transistor T3.

[0138] Optionally, as shown in Figure 9, the second control sub-circuit 3 includes a fourth transistor T4, an eighth transistor T8, a fifteenth transistor T15, and a sixteenth transistor T16; the first electrode of the fourth transistor T4 is electrically connected to the clock signal line, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2; the first electrode of the eighth transistor T8 is electrically connected to the eighth node, the second electrode is electrically connected to the first power supply signal line, and the control electrode is electrically connected to the first node N1; the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first node N1; the first electrode of the sixteenth transistor T16 is electrically connected to the first power supply signal line, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the third node N3.

[0139] Specifically, the first node N1 can simultaneously control the on / off state of the eighth transistor T8 and the fifteenth transistor T15. When the eighth transistor T8 responds to the signal from the first node N1 and is turned on, the first power supply signal VGL1 can be transmitted to the eighth node. Simultaneously, when the fifteenth transistor T15 responds to the signal from the first node N1 and is turned on, the signal from the eighth node can be transmitted to the third node N3. Furthermore, the potential of the third node N3 can control the on / off state of the sixteenth transistor T16. When the sixteenth transistor T16 responds to the signal from the third node N3 and is turned on, the second power supply signal VGH1 can be transmitted to the eighth node.

[0140] For example, when the shift register also includes a pull-up circuit 5, as shown in Figure 6, the potential of the fourth node can simultaneously control the on / off state of the eighth transistor T8 and the fifteenth transistor T15. When the eighth transistor T8 responds to the signal from the fourth node and is turned on, the first power supply signal VGL1 can be transmitted to the eighth node. At the same time, when the fifteenth transistor T15 responds to the signal from the fourth node and is turned on, the signal from the eighth node can be transmitted to the third node N3.

[0141] It should be noted that, taking an N-type thin-film transistor as an example, if the threshold voltage of the fifteenth transistor T15 is negative, the voltage of the high-potential third node N3 will be reverse-propagated, causing leakage in the fifteenth transistor T15. Due to the influence of the first power supply signal VGL1, the potential of the third node N3 after leakage will no longer remain high, causing the fifth transistor T5 to be cut off, thus preventing the first power supply signal VGL1 from being output. This embodiment sets up an anti-leakage structure, that is, adding the fifteenth transistor T15 and the sixteenth transistor T16 on the basis of the eighth transistor T8. When the potential of the third node N3 is high, the sixteenth transistor T16 is turned on, and the second power supply signal VGH1 is written to the eighth node, making the potential of the eighth node high. At this time, the first and second terminals of the fifteenth transistor T15 are both high. Regardless of whether the threshold voltages of the fifteenth transistor T15 and the eighth transistor T8 are negative, the potential of the third node N3 always remains high, thereby suppressing reverse leakage and ensuring the stable conduction of the fifth transistor T5.

[0142] In some embodiments, FIG10 is a circuit diagram of a shift register under the sixth example provided in the present disclosure. The difference between FIG10 and the circuit structure shown in FIG6 is that a voltage regulation unit is added, namely the seventeenth transistor T17 and the eighteenth transistor T18.

[0143] As shown in Figure 10, the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, a fifth transistor T5, a seventeenth transistor T17, and an eighteenth transistor T18. The first electrode of the third transistor T3 is electrically connected to the next-stage signal input terminal Input, the second electrode is electrically connected to the second power supply signal line, and the control electrode is electrically connected to the first node N1. The next-stage signal input terminal Input is the signal input terminal Input of the next-stage shift register cascaded with the shift register. The first electrode of the fifth transistor T5 is electrically connected to the first power supply signal line, and the second electrode is electrically connected to the next-stage signal input terminal Input. The first electrode of the first capacitor C1 is connected to the third node N3; the first plate of the first capacitor C1 is connected to the first node N1, and the second plate is connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 is connected to the third node N3, and the second plate is connected to the first electrode of the fifth transistor T5; the first electrode of the seventeenth transistor T17 is connected to the signal output terminal Out, the second electrode is connected to the third power supply signal line, and the control electrode is connected to the first node N1; the first electrode of the eighteenth transistor T18 is connected to the fourth power supply signal line, the second electrode is connected to the signal output terminal Out, and the control electrode is connected to the third node N3.

[0144] Specifically, as shown in Figure 10, the potential of the first node N1 can simultaneously control the on / off state of the third transistor T3 and the seventeenth transistor T17. The potential of the third node N3 can simultaneously control the on / off state of the fifth transistor T5 and the eighteenth transistor T18. The first capacitor C1 can bootstrap the potential of the first node N1 to a higher potential, thereby ensuring the stable conduction of the third transistor T3 and the seventeenth transistor T17, and thus stabilizing the output of the third power supply signal VGH2. The second capacitor C2 can stabilize the potential of the third node N3 for a certain period of time when the fourth transistor T4 is turned off, thereby ensuring the continuous conduction of the fifth transistor T5 and the eighteenth transistor T18, and thus stabilizing the output of the fourth power supply signal VGL2.

[0145] Figure 11 is a circuit diagram of the shift register under the seventh example provided in the embodiments of this disclosure. As shown in Figure 11, the difference between the circuit structure shown in Figure 10 and the circuit structure shown in Figure 11 is that a leakage protection structure is added, namely the ninth transistor T9 and the tenth transistor T10. For the specific leakage protection principle, please refer to the description of the above embodiments. Repeated parts will not be repeated.

[0146] This disclosure uses an N-type thin-film transistor as an example. For instance, the potential of the first power supply signal VGL1 is lower than the potential of the second power supply signal VGH1, and their potentials are opposite. That is, the first power supply signal VGL1 is a low-level signal (less than 0), and the second power supply signal VGH1 is a high-level signal (greater than 0). For instance, the potential of the fourth power supply signal VGL2 is lower than the potential of the third power supply signal VGH2, and their potentials are opposite. That is, the fourth power supply signal VGL2 is a low-level signal, and the third power supply signal VGH2 is a high-level signal.

[0147] As shown in Figures 5-11, this disclosure uses an N-type thin-film transistor as an example. The absolute value of the voltage of the third power signal VGH2 transmitted through the third power signal line is less than the absolute value of the voltage of the second power signal VGH1 transmitted through the second power signal line. For example, the voltage of the third power signal VGH2 transmitted through the third power signal line is less than the voltage of the second power signal VGH1 transmitted through the second power signal line. That is, both the second power signal VGH1 and the third power signal VGH2 are high-level signals (greater than 0), and the voltage of the third power signal VGH2 is lower than the voltage of the second power signal VGH1. This disclosure sets the voltage of the third power signal VGH2 to be less than the voltage of the first power signal VGL1. For the third transistor T3 and the seventeenth transistor T17, which are simultaneously controlled by the potential of the first node N1, the seventeenth transistor T17 is turned on more completely than the third transistor T3, thereby ensuring the complete output of the third power signal VGH2.

[0148] As shown in Figures 5 to 11, this disclosure uses an N-type thin-film transistor as an example. The absolute value of the voltage of the fourth power signal VGL2 transmitted through the fourth power signal line is greater than the absolute value of the voltage of the first power signal VGL1 transmitted through the first power signal line. For example, the voltage of the fourth power signal VGL2 transmitted through the fourth power signal line is greater than the voltage of the first power signal VGL1 transmitted through the first power signal line. That is, both the first power signal VGL1 and the fourth power signal VGL2 are low-level signals (less than 0), and the voltage of the fourth power signal VGL2 is higher than the voltage of the first power signal VGL1. This disclosure sets the voltage of the fourth power signal VGL2 to be greater than the voltage of the first power signal VGL1. For the fifth transistor T5 and the eighteenth transistor T18, which are simultaneously controlled by the potential of the third node N3, the eighteenth transistor T18 is turned on more completely than the fifth transistor T5, thereby ensuring the complete output of the fourth power signal VGL2.

[0149] Of course, for the case where the transistor is a P-type thin-film transistor, the circuit structure of the shift register remains unchanged (as shown in Figures 5 to 11). The only difference is that the circuit structure electrically connected to the first power signal line is replaced by one electrically connected to the second power signal line, and vice versa. Figure 12 is a circuit diagram of the shift register in the eighth example provided by this disclosure. The difference from the structure shown in Figure 5 is that a P-type transistor is used.

[0150] As shown in Figure 12, the input sub-circuit 1 includes a first transistor T1; the first control sub-circuit 2 includes a sixth transistor T6 and a seventh transistor T7; the second control sub-circuit 3 includes a fourth transistor T4 and an eighth transistor T8; and the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, and a fifth transistor T5. Specifically, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the clock signal line transmitting the clock signal CK; the first electrode of the sixth transistor T6 is electrically connected to the second power signal line transmitting the second power signal VGH1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the signal input terminal Input; the first electrode of the seventh transistor T7 is electrically connected to the clock signal line, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the control signal line transmitting the control signal QB; the first electrode of the fourth transistor T4 is electrically connected to the clock signal line, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2; the eighth transistor T8… The first electrode of the first transistor T3 is electrically connected to the third node N3, the second electrode is electrically connected to the second power signal line, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the first power signal line transmitting the first power signal VGL1, and the control electrode is electrically connected to the first node N1; the first electrode of the fifth transistor T5 is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3; the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate is electrically connected to the first electrode of the fifth transistor T5.

[0151] Optionally, Figure 13 is a circuit diagram of the shift register under the ninth example provided in the embodiments of this disclosure. Compared with the structure shown in Figure 10, the circuit structure of the shift register remains unchanged (as shown in Figures 5 to 11). The difference is that the transistor is a P-type transistor. At this time, the circuit structure electrically connected to the third power supply signal line is replaced by the circuit structure electrically connected to the fourth power supply signal line. Similarly, the circuit structure electrically connected to the fourth power supply signal line is replaced by the circuit structure electrically connected to the third power supply signal line.

[0152] As shown in Figure 13, the input sub-circuit 1 includes a first transistor T1; the first control sub-circuit 2 includes a sixth transistor T6 and a seventh transistor T7; the second control sub-circuit 3 includes a fourth transistor T4 and an eighth transistor T8; and the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, a fifth transistor T5, a seventeenth transistor T17, and an eighteenth transistor T18. Specifically, the first transistor T1 has its first electrode electrically connected to the signal input terminal Input, its second electrode electrically connected to the first node N1, and its control electrode electrically connected to the clock signal line transmitting the clock signal CK; the sixth transistor T6 has its first electrode electrically connected to the second power signal line transmitting the second power signal VGH1, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to the signal input terminal Input; the seventh transistor T7 has its first electrode electrically connected to the clock signal line, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to the control signal line transmitting the control signal QB; the fourth transistor T4 has its first electrode electrically connected to the clock signal line, its second electrode electrically connected to the third node N3, and its control electrode electrically connected to the second node N2; the eighth transistor T8 has its first electrode electrically connected to the third node N3, its second electrode electrically connected to the second power signal line, and its control electrode electrically connected to the first node N1; the third transistor T3 has its first electrode electrically connected to... The first electrode of transistor T5 is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the first power signal line transmitting the first power signal VGL1, and the control electrode is electrically connected to the first node N1; the first electrode of the fifth transistor T5 is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3; the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate is electrically connected to the first electrode of the fifth transistor T5; the first electrode of the seventeenth transistor T17 is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the fourth power signal line, and the control electrode is electrically connected to the first node N1; the first electrode of the eighteenth transistor T18 is electrically connected to the third power signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3.

[0153] This concludes the complete description of the circuit structure of the shift register in this disclosure.

[0154] The working principle of the shift register provided in the embodiments of this disclosure will be described in further detail below.

[0155] Figure 14 is a timing diagram of an exemplary shift register provided in an embodiment of this disclosure. As shown in Figure 14, taking the circuit structure in Figure 5 as an example, its working stages specifically include a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4, wherein:

[0156] Phase 1 t1: Input signal EM <i-1>When the clock signal CK is high and the control signal QB is low, the first transistor T1 is turned on, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. At this time, the second node N2 writes the first power supply signal VGL1, which is a low-level signal, and the fourth transistor T4 is turned off; at this time, the first node N1 writes the input signal EM. <i-1>That is, a high-level signal, the third transistor T3 and the eighth transistor T8 are turned on; then, the third node N3 writes the first power signal VGL1, which is a low-level signal, and the fifth transistor T5 is turned off. The third transistor T3 is turned on, and the second power signal VGH1 is output through the signal output terminal Out.

[0157] Second stage t2: Input signal EM <i-1>When the clock signal CK is low and the control signal QB is low, the first transistor T1 is off, the sixth transistor T6 is on, and the seventh transistor T7 is off. At this time, the second node N2 writes the first power supply signal VGL1, which is a low-level signal, and the fourth transistor T4 is off. The first node N1 maintains the potential from the previous stage, i.e., the high potential corresponding to the high-level signal, and the third transistor T3 and the eighth transistor T8 are on. Then, the third node N3 writes the first power supply signal VGL1, which is a low-level signal, and the fifth transistor T5 is off. The third transistor T3 is on, and the second power supply signal VGH1 is output through the signal output terminal Out.

[0158] Phase 3 t3: Input signal EM <i-1>When the clock signal CK is low and the control signal QB is high, the first transistor T1 is off, the sixth transistor T6 is off, and the seventh transistor T7 is on. At this time, the clock signal CK (low level) is written to the second node N2, and the fourth transistor T4 is off. The first node N1 maintains the potential from the previous stage (the high potential corresponding to the high level signal), and the third transistor T3 and the eighth transistor T8 are on. Then, the first power supply signal VGL1 (low level) is written to the third node N3, and the fifth transistor T5 is off. The third transistor T3 is on, and the second power supply signal VGH1 is output through the signal output terminal Out.

[0159] It should be noted that the duration of the third stage t3 is the same as the duration of two second stages t2.

[0160] Fourth stage t4: Input signal EM <i-1>When the clock signal CK is high and the control signal QB is high, the first transistor T1 is turned on, the sixth transistor T6 is turned off, and the seventh transistor T7 is turned on. At this time, the first node N1 writes the input signal EM. <i-1>When the signal is low, the third transistor T3 and the eighth transistor T8 are turned off. When the clock signal CK is written to the second node N2, which is a high-level signal, the fourth transistor T4 is turned on. When the clock signal CK is written to the third node N3, which is a high-level signal, the fifth transistor T5 is turned on. The first power supply signal VGL1 is output through the signal output terminal Out.

[0161] The above working stages cycle continuously, with the signal output terminal Out outputting a multi-pulse signal for low grayscale dimming; at the same time, it controls the operation of the next-stage shift register.

[0162] For timing control of other circuit structures (Figures 6 to 11), the timing control of the circuit in Figure 5 in Figure 14 can be used in the same way. Repeated parts will not be described again.

[0163] In addition, this disclosure also provides a light-emitting driving circuit, specifically including N cascaded shift registers as described in any of the above embodiments. Figure 15 is a schematic diagram of a light-emitting driving circuit provided by this disclosure. As shown in Figure 15, except for the first-stage shift register, the signal input terminal Input of the (i+1)th-stage shift register is electrically connected to the signal output terminal Out of the i-th-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0164] For a detailed explanation of the specific structure of a shift register, please refer to the detailed description of shift registers mentioned above. Repeated parts will not be repeated here.

[0165] The light-emitting driving circuit provided in this embodiment only uses the input signal EM <i-1>With just one clock signal line and one first power signal line, the output of either the first power signal VGL1 or the second power signal VGH1 can be controlled, thereby achieving light emission control. This light-emitting driver circuit has a simple circuit structure and is therefore highly practical.

[0166] In some embodiments, as shown in FIG15, the control signal line of the (i+1)th stage shift register is electrically connected to the third node N3 of the i-th stage shift register. In this embodiment, the signal of the third node N3 of the i-th stage shift register is used as the control signal QB of the (i+1)th stage shift register. For each stage of the shift register, there is no need to add extra signal control terminals, simplifying the circuit structure and improving practicality.

[0167] In some embodiments, FIG16 is a schematic diagram of another light-emitting driving circuit provided in an embodiment of the present disclosure. As shown in FIG16, the output sub-circuit 4 includes a third transistor T3, a first capacitor C1, a second capacitor C2, a fifth transistor T5, a seventeenth transistor T17, and an eighteenth transistor T18; the first terminal of the third transistor T3 of the i-th stage shift register is electrically connected to the signal input terminal Input of the (i+1)-th stage shift register, the second terminal is electrically connected to the second power supply signal line, and the control terminal is electrically connected to the first node N1; the first terminal of the fifth transistor T5 of the i-th stage shift register is electrically connected to the first power supply signal line, and the second terminal is electrically connected to the signal input terminal Input of the (i+1)-th stage shift register. The control electrode is electrically connected to the third node N3; the first plate of the first capacitor C1 of the i-th stage shift register is electrically connected to the first node N1, and the second plate is electrically connected to the first electrode of the third transistor T3; the first plate of the second capacitor C2 of the i-th stage shift register is electrically connected to the third node N3, and the second plate is electrically connected to the first electrode of the fifth transistor T5; the first electrode of the seventeenth transistor T17 of the i-th stage shift register is electrically connected to the signal output terminal Out, the second electrode is electrically connected to the third power supply signal line, and the control electrode is electrically connected to the first node N1; the first electrode of the eighteenth transistor T18 of the i-th stage shift register is electrically connected to the fourth power supply signal line, the second electrode is electrically connected to the signal output terminal Out, and the control electrode is electrically connected to the third node N3.

[0168] In this embodiment, the i-th stage shift register uses the seventeenth transistor T17 and the eighteenth transistor T18 to control the output signal of the control signal output terminal Out (i.e., the light emission control signal EM of the OLED). The third transistor T3 and the fifth transistor T5 are used to control the input signal EM of the (i+1)-th stage shift register. <i-1>Compared to other methods that use the third transistor T3 and the fifth transistor T5 to control the output of the light emission control signal EM and the input of the i+1th stage shift register, this embodiment simultaneously improves the stability of the output of the light emission control signal EM and the input stability of the i+1th stage shift register.

[0169] In addition, embodiments of this disclosure also provide a display device, which includes the light-emitting driving circuit of any of the above embodiments. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0170] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, comprising an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; The input sub-circuit is configured to control the potential of the first node in response to a clock signal using an input signal; The first control sub-circuit is configured to control the potential of the second node using a first power supply signal in response to the input signal; Alternatively, in response to a control signal, the potential of the second node can be controlled using the clock signal; The second control sub-circuit is configured to control the potential of the third node in response to the potential of the second node using the clock signal; Alternatively, in response to the potential of the first node, the potential of the third node can be controlled using the first power signal; The output sub-circuit is configured to output a second power signal through the signal output terminal in response to the potential of the first node, or to output a first power signal through the signal output terminal in response to the potential of the third node.

2. The shift register according to claim 1, wherein, The second control sub-circuit includes a fourth transistor and an eighth transistor; The first electrode of the fourth transistor is electrically connected to the clock signal line that transmits the clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line that transmits the first power signal, and the control electrode is electrically connected to the first node.

3. The shift register according to claim 2, wherein, The first control sub-circuit includes a sixth transistor and a seventh transistor; The first electrode of the sixth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal. The first electrode of the seventh transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal.

4. The shift register according to claim 3, wherein, The input sub-circuit includes a first transistor; the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, and a fifth transistor. The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the clock signal line that transmits the clock signal. The first electrode of the third transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the control electrode is electrically connected to the first node. The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor. The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor.

5. The shift register according to claim 1, wherein, The shift register also includes a pull-up sub-circuit; The pull-up sub-circuit is configured to isolate the first node and the input sub-circuit electrically connected to the first node; The pull-up sub-circuit is electrically connected to the fourth node and the first node, the input sub-circuit is electrically connected to the fourth node, and the second control sub-circuit is electrically connected to the fourth node and the third node.

6. The shift register according to claim 5, wherein, The input sub-circuit includes a first transistor; the pull-up sub-circuit includes a second transistor; the first control sub-circuit includes a sixth transistor and a seventh transistor; the second control sub-circuit includes a fourth transistor and an eighth transistor; the output sub-circuit includes a third transistor, a first capacitor, a second capacitor, and a fifth transistor. The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the clock signal line that transmits the clock signal. The first electrode of the second transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the second power signal line that transmits the second power signal. The first electrode of the sixth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal. The first electrode of the seventh transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal. The first electrode of the fourth transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line, and the control electrode is electrically connected to the fourth node. The first electrode of the third transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the second power signal line, and the control electrode is electrically connected to the first node. The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor. The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor.

7. The shift register according to claim 2 or 6, wherein, The first control sub-circuit includes a sixth transistor, a seventh transistor, a ninth transistor, and a tenth transistor; The first electrode of the sixth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the signal input terminal. The first electrode of the ninth transistor is electrically connected to the fifth node, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the signal input terminal. The first electrode of the tenth transistor is electrically connected to the fifth node, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the control electrode is electrically connected to the second node. The first electrode of the seventh transistor is electrically connected to the clock signal line that transmits the clock signal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the control signal line that transmits the control signal.

8. The shift register according to claim 7, wherein, The input sub-circuit includes a first transistor, a thirteenth transistor, and a fourteenth transistor; the first transistor's first electrode is electrically connected to the seventh node, its second electrode is electrically connected to the first node, and its control electrode is electrically connected to the clock signal line; the thirteenth transistor's first electrode is electrically connected to the signal input terminal, its second electrode is electrically connected to the seventh node, and its control electrode is electrically connected to the clock signal line; the fourteenth transistor's first electrode is electrically connected to the seventh node, its second electrode is electrically connected to the second power supply signal line, and its control electrode is electrically connected to the first node.

9. The shift register according to claim 7, wherein, The second control sub-circuit includes a fourth transistor, an eighth transistor, a fifteenth transistor, and a sixteenth transistor; the first electrode of the fourth transistor is electrically connected to the clock signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; the first electrode of the eighth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first power signal line, and the control electrode is electrically connected to the first node; the first electrode of the fifteenth transistor is electrically connected to the third node, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first node. The first electrode of the sixteenth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the third node.

10. The shift register according to claim 1 or 5, wherein, The output sub-circuit includes a third transistor, a first capacitor, a second capacitor, a fifth transistor, a seventeenth transistor, and an eighteenth transistor; The first electrode of the third transistor is electrically connected to the next stage signal input terminal, the second electrode is electrically connected to the second power supply signal line, and the control electrode is electrically connected to the first node; the next stage signal input terminal is the signal input terminal of the next stage shift register cascaded with the shift register; The first electrode of the fifth transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the next stage signal input terminal, and the control electrode is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first electrode of the third transistor. The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor; The first electrode of the seventeenth transistor is electrically connected to the signal output terminal, the second electrode is electrically connected to the third power signal line, and the control electrode is electrically connected to the first node. The first electrode of the eighteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

11. The shift register according to claim 10, wherein, The absolute value of the voltage of the third power signal transmitted by the third power signal line is less than the absolute value of the voltage of the second power signal transmitted by the second power signal line. The absolute value of the voltage of the fourth power signal transmitted by the fourth power signal line is greater than the absolute value of the voltage of the first power signal transmitted by the first power signal line.

12. The shift register according to claim 1, wherein, The input signal and the control signal have the same timing but opposite potentials.

13. The shift register according to claim 1, wherein, At the same time, the potentials of the first node and the second node are opposite.

14. A light-emitting driving circuit comprising N cascaded shift registers as described in any one of claims 1 to 13; Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

15. The light-emitting driving circuit according to claim 14, wherein, The control signal line of the shift register of the (i+1)th stage is electrically connected to the third node of the shift register of the i-th stage.

16. The light-emitting driving circuit according to claim 14, wherein, The output sub-circuit includes a third transistor, a first capacitor, a second capacitor, a fifth transistor, a seventeenth transistor, and an eighteenth transistor; The first terminal of the third transistor of the i-th stage shift register is electrically connected to the signal input terminal of the (i+1)-th stage shift register, the second terminal is electrically connected to the second power supply signal line, and the control terminal is electrically connected to the first node; The first electrode of the fifth transistor in the i-th stage shift register is electrically connected to the first power supply signal line, the second electrode is electrically connected to the signal input terminal of the (i+1)-th stage shift register, and the control electrode is electrically connected to the third node. The first plate of the first capacitor of the i-th stage shift register is electrically connected to the first node, and the second plate is electrically connected to the first terminal of the third transistor. The first plate of the second capacitor in the i-th stage shift register is electrically connected to the third node, and the second plate is electrically connected to the first terminal of the fifth transistor; The first electrode of the seventeenth transistor in the i-th stage shift register is electrically connected to the signal output terminal, the second electrode is electrically connected to the third power supply signal line, and the control electrode is electrically connected to the first node. The first electrode of the eighteenth transistor in the i-th stage shift register is electrically connected to the fourth power supply signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node.

17. A display device comprising a light-emitting driving circuit as described in any one of claims 14 to 16.

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