Preparation method for semiconductor device, and semiconductor device

Abstract

Provided in the present disclosure are a preparation method for a semiconductor device, and a semiconductor device. The preparation method comprises: performing oxidization and deposition on a first surface of a first substrate to obtain a composite dielectric layer; performing metal thin film deposition on the composite dielectric layer to obtain a first metal layer; etching the first metal layer on a first top surface and the first metal layer on a second top surface, and exposing the composite dielectric layer, so as to obtain a first sidewall metal layer; performing metal thin film deposition on the first sidewall metal layer, the composite dielectric layer on the first top surface and the composite dielectric layer on the second top surface, so as to obtain a second metal layer; performing metal thin film deposition on the second metal layer to obtain a third metal layer; performing photolithography and etching on the third metal layer and the second metal layer to obtain a gate electrode; and performing doping on the first top surface adjacent to a second side surface of the gate electrode and the second top surface adjacent to a third side surface of the gate electrode, so as to respectively obtain a first source / drain region and a second source / drain region.

Description

Semiconductor device fabrication methods and semiconductor devices Technical Field

[0001] This disclosure relates to the field of semiconductors, and more specifically to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] In the design and manufacturing of integrated circuits, efforts are generally focused on reducing the channel length of transistors to improve device performance. Meanwhile, to achieve higher integration density and smaller chip area, related technologies are based on traditional planar transistors, closely arranging NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor).

[0003] In realizing the present invention, the inventors discovered at least the following problems in the related technology: the small spacing between NMOS and PMOS in planar transistors easily leads to leakage current, resulting in an increase in leakage current. To reduce leakage current, the spacing between NMOS and PMOS cannot meet the requirements for circuit miniaturization and integration. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a method for fabricating a semiconductor device and a semiconductor device.

[0005] According to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising: oxidizing and depositing a composite dielectric layer on a first surface of a first substrate. The first substrate includes a well region. The first surface includes a first top surface, a second top surface, and a first side surface. The first top surface is the upper surface of the non-well region on the first substrate, and the second top surface is the upper surface of the well region, the second top surface being lower than the first top surface. The first side surface is the junction of the first top surface and the second top surface. A metal thin film is deposited on the composite dielectric layer to obtain a first metal layer. The first metal layer located on the first top surface and the first metal layer located on the second top surface are etched to expose the composite dielectric layer, obtaining a first sidewall metal layer. A metal thin film is deposited on the first sidewall metal layer, the composite dielectric layer located on the first top surface, and the composite dielectric layer located on the second top surface to obtain a second metal layer. A metal thin film is deposited on the second metal layer to obtain a third metal layer. The third metal layer and the second metal layer are made of different materials. The third metal layer and the second metal layer are photolithographically etched to obtain a gate. The gate is the unetched third metal layer. Doping is performed on a first top surface adjacent to the second side surface of the gate and a second top surface adjacent to the third side surface of the gate to obtain a first source / drain region and a second source / drain region, respectively. The second side surface is opposite to the third side surface. The first source / drain region is the source / drain region of a vertical gate transistor, and the second source / drain region is the source / drain region of a planar transistor. The vertical gate transistor and the planar transistor share the gate.

[0006] According to embodiments of this disclosure, the vertical gate transistor is an N-type transistor, and the planar transistor is a P-type transistor. Alternatively, the vertical gate transistor is a P-type transistor, and the planar transistor is an N-type transistor.

[0007] According to embodiments of this disclosure, when the vertical gate transistor is an N-type transistor and the planar transistor is a P-type transistor, the first metal layer includes N-type transistor work function metal, the second metal layer includes P-type transistor work function metal, and the third metal layer includes gate electrode fill metal. When the vertical gate transistor is a P-type transistor and the planar transistor is an N-type transistor, the first metal layer includes P-type transistor work function metal, the second metal layer includes N-type transistor work function metal, and the third metal layer includes gate electrode fill metal.

[0008] According to embodiments of this disclosure, the material of the work function metal of the N-tube includes titanium nitride. The material of the work function metal of the P-tube includes titanium aluminum.

[0009] According to embodiments of this disclosure, the above-mentioned metal thin film deposition includes metal deposition, physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0010] According to embodiments of this disclosure, the doping of the first top surface adjacent to the two sides of the gate and the second top surface adjacent to the third side of the gate to obtain the first source / drain region and the second source / drain region respectively includes: depositing a dielectric thin film on the gate and the second side to obtain a second sidewall dielectric layer; depositing a dielectric thin film on the third side of the gate to obtain a third sidewall dielectric layer; performing a deposition process on the second sidewall dielectric layer of the gate, the first top surface adjacent to the second sidewall dielectric layer, the third sidewall dielectric layer, and the second top surface adjacent to the third sidewall dielectric layer to obtain a mask; etching a first region of the mask to obtain a first opening, and performing a first impurity doping on the first opening to obtain the first source / drain region. The first region is located on the first top surface. Etching a second region of the mask to obtain a second opening, and performing a second impurity doping on the second opening to obtain the second source / drain region. The second region is located on the second top surface, and the second opening is located above the well region.

[0011] According to embodiments of this disclosure, the first impurity doping includes N-type impurity doping, and the second impurity doping includes P-type impurity doping. Alternatively, the first impurity doping includes P-type impurity doping, and the second impurity doping includes N-type impurity doping.

[0012] According to embodiments of this disclosure, the method for fabricating a semiconductor device further includes: performing impurity doping on a designated region of a second substrate to obtain the aforementioned well region; performing photolithography on the well region to expose the well region and obtain the aforementioned first top surface, the aforementioned second top surface, and the aforementioned first side surface; and insulating the aforementioned first top surface, the aforementioned second top surface, and the aforementioned first side surface to obtain the aforementioned first substrate.

[0013] According to embodiments of this disclosure, the second substrate is a semiconductor-insulator-semiconductor structure.

[0014] A second aspect of this disclosure provides a semiconductor device comprising: a first substrate; a vertical-gate transistor located on the first substrate, the vertical-gate transistor including a gate and a first source-drain region; and a planar transistor located on the first substrate, the planar transistor including a gate and a second source-drain region. The vertical-gate transistor and the planar transistor share the gate, and the first source-drain region and the second source-drain region are respectively located on opposite sides of the gate.

[0015] According to embodiments of this disclosure, a shared gate for both the vertical gate transistor and the planar transistor is obtained by photolithographic etching of the third metal layer and the second metal layer. That is, the gate of the vertical gate transistor and the gate of the planar transistor are the same gate and controlled by the same voltage source, so that the vertical gate transistor and the planar transistor are controlled by the same gate, reducing the spacing between the two transistors and meeting the requirements of circuit miniaturization and integration. Attached Figure Description

[0016] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 schematically illustrates a process flow diagram for obtaining a first substrate according to an embodiment of the present disclosure;

[0018] Figure 2 schematically illustrates a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0019] Figure 3 schematically illustrates a fabrication process diagram of a gate according to an embodiment of the present disclosure;

[0020] Figure 4 schematically illustrates the processing flow diagram of the first source / drain region and the second source / drain region according to an embodiment of the present disclosure;

[0021] Figure 5 schematically illustrates a side view of a semiconductor device according to an embodiment of the present disclosure; and

[0022] Figure 6 schematically illustrates a top view of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] With the advent of the big data era, the demand for high-performance integrated circuits in the semiconductor field continues to rise. An integrated circuit is a complex circuit system formed by integrating a large number of semiconductor devices (such as transistors) onto a small semiconductor material chip.

[0027] In the design and manufacturing of integrated circuits, efforts are generally focused on reducing the channel length of transistors to improve device performance. Simultaneously, to achieve higher integration density and smaller chip area, the pitch between transistors is also continuously decreasing.

[0028] To achieve higher integration and smaller chip area, the relevant technology is based on traditional planar transistors, which tightly arrange NMOS and PMOS transistors.

[0029] In realizing the present invention, the inventors discovered at least the following problems in the related technology: the small spacing between NMOS and PMOS in planar transistors easily leads to leakage current, resulting in an increase in leakage current. To reduce leakage current, the spacing between NMOS and PMOS cannot meet the requirements for circuit miniaturization and integration.

[0030] In view of this, embodiments of the present disclosure provide a method for fabricating a semiconductor device to reduce the spacing between two transistors, thereby meeting the requirements for miniaturization and integration of circuits.

[0031] Figure 1 schematically illustrates a process flow diagram for obtaining a first substrate according to an embodiment of the present disclosure.

[0032] As shown in Figure 1(A), impurity doping is performed on a designated region of the second substrate 102 to obtain a well region 103.

[0033] As shown in Figure 1(B), the well region 103 is photolithographically etched to expose the well region 103 and obtain the first top surface D1, the second top surface D2 and the first side surface C1.

[0034] As shown in (C) of Figure 1, the first top surface D1, the second top surface D2 and the first side surface C1 are insulated to obtain the first substrate 101.

[0035] According to embodiments of this disclosure, the second substrate is a semiconductor-insulator-semiconductor structure.

[0036] According to embodiments of this disclosure, the second substrate may include a substrate layer, an intermediate layer, and a top layer. The substrate layer may be a semiconductor material, such as silicon or germanium. The intermediate layer may be an insulating material, such as silicon oxide. The top layer may be a semiconductor material, such as silicon.

[0037] According to embodiments of this disclosure, the second substrate may be an SOI (Silicon On Insulator) wafer. An SOI wafer includes a silicon substrate layer for providing support, an insulating silicon dioxide intermediate layer, also known as a BOX layer (Buried Oxide), and a top silicon layer.

[0038] According to embodiments of this disclosure, the intermediate layer of the second substrate is an insulator. This provides electrical isolation between the vertical gate transistor and the planar transistor, as well as between the two transistors and the substrate layer, reducing leakage current generation.

[0039] According to embodiments of this disclosure, the substrate and top layer can be P-type semiconductors. The dominant charge carriers in a P-type semiconductor are holes, while the dominant charge carriers in an N-type semiconductor are electrons. By forming N-wells in designated regions on a P-type substrate, N-type semiconductor characteristics can be provided in those designated regions to construct CMOS (Complementary Metal-Oxide-Semiconductor) circuits.

[0040] According to embodiments of this disclosure, N-type impurities, such as nitrogen, phosphorus, or arsenic, can be implanted into a designated region using an ion implantation process. These N-type impurity atoms replace some silicon atoms in the silicon lattice, causing the designated region to exhibit the characteristics of an N-type semiconductor, i.e., the primary charge carrier is electrons. The designated region after implantation of N-type impurities is called an N-well.

[0041] According to embodiments of this disclosure, photolithography is performed on a portion of the top layer and a portion of the intermediate layer located above the N-well to expose the well region and obtain a first top surface, a second top surface, and a first side surface. Photolithography is a technique that uses a photosensitive material, such as photoresist, and a mask to transfer circuit patterns onto the surface of a silicon wafer. Through the photolithography process, the positions and shapes of the first top surface, the second top surface, and the first side surface can be precisely defined.

[0042] According to embodiments of this disclosure, a first substrate can be obtained by insulating and isolating the exposed first top surface, second top surface, and first side surface using an insulating material, such as silicon dioxide or silicon nitride. The insulating and isolating process can be STI (Shallow Trench Isolation), LOCOS (Local Oxidation of Silicon), or MESA (Mesa Isolation). The first substrate is a structure with insulating properties, on which transistors, interconnects, and other circuit elements can be built, providing a foundation for subsequent semiconductor device fabrication and circuit construction.

[0043] Figure 2 schematically illustrates a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0044] As shown in Figure 2, the preparation method 200 includes operations S210 to S270.

[0045] In operation S210, the first surface of the first substrate is oxidized and deposited to obtain a composite dielectric layer. Here, "composite" means that other dielectric materials with high dielectric constants, such as hafnium dioxide, titanium oxide, aluminum oxide, and hafnium zirconium oxide, are deposited on silicon dioxide. The material of the composite dielectric layer can be at least one of silicon dioxide, hafnium oxide, titanium oxide, and aluminum oxide. The first substrate includes a well region. The first surface includes a first top surface, a second top surface, and a first side surface. The first top surface is the upper surface of the non-well region on the first substrate, and the second top surface is the upper surface of the well region, lower than the first top surface. The first side surface is the junction of the first top surface and the second top surface.

[0046] In operation S220, a metal thin film is deposited on the composite dielectric layer to obtain the first metal layer.

[0047] In operation S230, the first metal layer located on the first top surface and the first metal layer located on the second top surface are etched to expose the composite dielectric layer, thereby obtaining the first sidewall metal layer.

[0048] In operation S240, a metal thin film is deposited on the first sidewall metal layer, the composite dielectric layer on the first top surface, and the composite dielectric layer on the second top surface to obtain a second metal layer.

[0049] In operation S250, a metal thin film is deposited on the second metal layer to obtain a third metal layer. The materials of the third metal layer and the second metal layer are different.

[0050] In operation S260, photolithographic etching is performed on the third metal layer and the second metal layer to obtain the gate. The gate is the unetched third metal layer.

[0051] In operation S270, doping is performed on the first top surface adjacent to the second side of the gate and the second top surface adjacent to the third side of the gate to obtain the first source / drain region and the second source / drain region, respectively. The second side is opposite to the third side. The first source / drain region is the source / drain region of the vertical-gate transistor, and the second source / drain region is the source / drain region of the planar transistor. The vertical-gate transistor and the planar transistor share a gate.

[0052] According to embodiments of this disclosure, a first substrate can be obtained by forming a well region on a silicon wafer.

[0053] According to an embodiment of the present disclosure, a layer of silicon oxide is grown on a first surface of a first substrate, and a dielectric material is deposited on the silicon oxide to obtain a composite dielectric layer.

[0054] According to embodiments of this disclosure, a first metal layer can provide a conductive path for the transistor, laying the foundation for subsequent circuit connections. A first sidewall metal layer is obtained by etching the first metal layer, and this first sidewall metal layer can be used to define the size and shape of the transistor. A second metal layer can be used to implement interconnections with the first sidewall metal layer.

[0055] According to embodiments of this disclosure, photolithographic etching is performed on the third metal layer and the second metal layer to retain specific regions of the third metal layer and the second metal layer, thereby obtaining a gate. The gate is the unetched third metal layer. The retained specific regions of the second metal layer can be used to connect the gate.

[0056] According to embodiments of this disclosure, a shared gate for both the vertical gate transistor and the planar transistor is obtained by photolithographic etching of the third metal layer and the second metal layer. That is, the gate of the vertical gate transistor and the gate of the planar transistor are the same gate and controlled by the same voltage source, so that the vertical gate transistor and the planar transistor are controlled by the same gate, reducing the spacing between the two transistors and meeting the requirements of circuit miniaturization and integration.

[0057] According to embodiments of this disclosure, the vertical-gate transistor is an N-type transistor, and the planar transistor is a P-type transistor. Alternatively, the vertical-gate transistor is a P-type transistor, and the planar transistor is an N-type transistor.

[0058] According to embodiments of this disclosure, the vertical gate transistor can be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The planar transistor can be a P-type MOSFET.

[0059] According to embodiments of this disclosure, a vertical gate transistor can use an N-type semiconductor as the channel, and when a forward bias is applied thereto, a conductive electron channel can be formed between the source and drain. A planar transistor can use a P-type semiconductor as the channel, and when a negative bias is applied thereto, a conductive hole channel can be formed between the source and drain.

[0060] According to embodiments of this disclosure, the vertical gate transistor can also be a P-type transistor, and the planar transistor can be an N-type transistor.

[0061] According to embodiments of this disclosure, the vertical gate transistor can be a P-type MOSFET, and the planar transistor can be an N-type MOSFET.

[0062] According to embodiments of this disclosure, a vertical-gate transistor can use a P-type semiconductor as the channel, and a conductive hole channel can be formed between the source and drain when a negative bias is applied thereon. A planar transistor can use an N-type semiconductor as the channel, and a conductive electron channel can be formed between the source and drain when a positive bias is applied thereon. According to embodiments of this disclosure, based on the vertical-gate transistor being an N-type transistor and the planar transistor being a P-type transistor, and using N-type and P-type semiconductor materials respectively in their channels, CMOS (Complementary Metal-Oxide-Semiconductor) can be constructed. CMOS can also be constructed based on the vertical-gate transistor being a P-type transistor and the planar transistor being an N-type transistor, and using P-type and N-type semiconductor materials respectively in their channels.

[0063] The method for fabricating a semiconductor device according to an embodiment of this disclosure will be described in detail below with reference to Figures 3 and 4.

[0064] Figure 3 schematically illustrates a fabrication process diagram of a gate according to an embodiment of the present disclosure.

[0065] According to embodiments of this disclosure, the first substrate can be cleaned by chemical cleaning and ultrapure water rinsing to remove organic and inorganic contaminants from the surface of the first substrate.

[0066] According to embodiments of this disclosure, metal thin film deposition includes metal deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (Atomic Layer Deposition).

[0067] As shown in Figure 3(A), the first surface of the first substrate 101 is oxidized. The oxidation process can form a layer of silicon dioxide, i.e., a gate oxide layer, on the first surface of the first substrate 101.

[0068] According to embodiments of this disclosure, a high dielectric material, such as HfO2, with a relative dielectric constant of 22-100 can be deposited on the gate oxide layer by PVD, CVD, ALD or other deposition techniques to obtain an HfO2 layer.

[0069] As shown in Figure 3(B), a metal thin film is deposited on the composite dielectric layer 104 to obtain the first metal layer 105.

[0070] As shown in Figure 3(C), the first metal layer 105 located on the first top surface and the first metal layer 105 located on the second top surface are etched to expose the composite dielectric layer, resulting in the first sidewall metal layer 106. The material of the first sidewall metal layer can be titanium nitride and silicon oxide.

[0071] According to embodiments of this disclosure, the first metal layer 105 can be patterned first. A photoresist layer is coated onto the first metal layer 105 using a photolithography process, and then a mask and ultraviolet light source are used to irradiate the area to transfer the pattern from the mask to the photoresist. The unirradiated portions of the photoresist, i.e., those covered by the mask, remain unchanged, while the irradiated portions, i.e., the exposed portions, become soluble. The photoresist in the exposed areas can be removed by a development process. The first metal layer 105 in the exposed areas is removed using wet etching or dry etching techniques, exposing the composite dielectric layer 104 to form the desired sidewall structure, resulting in the first sidewall metal layer 106.

[0072] As shown in Figure 3(D), a metal thin film is deposited on the first sidewall metal layer 106, the composite dielectric layer 104 on the first top surface, and the composite dielectric layer 104 on the second top surface to obtain the second metal layer 107.

[0073] As shown in Figure 3(E), a metal thin film is deposited on the second metal layer 107 to obtain the third metal layer 108.

[0074] As shown in Figure 3(F), photolithography is performed on the third metal layer 108 and the second metal layer 107 to obtain the gate 109 and the unetched second metal layer 107 located above the well region, exposing the first top surface of the first substrate and the second top surface not covered by the gate. The gate 109 is the unetched third metal layer.

[0075] According to an embodiment of the present disclosure, (G) in FIG3 is a side view of the first substrate 101 and the gate 109.

[0076] According to embodiments of this disclosure, when the vertical gate transistor is an N-type transistor and the planar transistor is a P-type transistor, the first metal layer 104 includes N-type transistor work function metal, the second metal layer 107 includes P-type transistor work function metal, and the third metal layer 108 includes gate electrode fill metal. When the vertical gate transistor is a P-type transistor and the planar transistor is an N-type transistor, the first metal layer 104 includes P-type transistor work function metal, the second metal layer 107 includes N-type transistor work function metal, and the third metal layer 108 includes gate electrode fill metal.

[0077] According to embodiments of this disclosure, the first metal layer 105 can serve as the work function layer of an N-type transistor, i.e., the work function layer of a vertical gate transistor, to control the channel for electron flow. The second metal layer 107 can serve as the work function layer of a P-type transistor, i.e., the work function layer of a planar transistor, to control the channel for hole flow.

[0078] According to embodiments of this disclosure, the third metal layer 108 can be used to form a gate shared by both vertical gate transistors and planar transistors. The third metal layer 108 has high conductivity and good process compatibility. The gate electrode filler metal can include metal materials such as aluminum, copper, or tungsten (W), which can provide high conductivity and maintain stability during complex patterning processes.

[0079] According to embodiments of this disclosure, vertical gate transistors and planar transistors use different work function metals, which can optimize the injection efficiency of electrons and holes and improve the operating performance of semiconductor devices.

[0080] According to embodiments of this disclosure, the work function metal of an N-type transistor is made of titanium nitride. The work function metal of a P-type transistor is made of titanium aluminum.

[0081] According to embodiments of this disclosure, the material of the work function metal of an N-transistor may further include titanium, aluminum, or titanium silicon. The material of the work function metal of a P-transistor may further include aluminum, cobalt, or nickel.

[0082] Figure 4 schematically illustrates the processing flow diagram of the first source / drain region and the second source / drain region according to an embodiment of the present disclosure.

[0083] As shown in Figure 4(A), a dielectric thin film is deposited on the second side of the gate 109 to obtain a second sidewall dielectric layer 110. A dielectric thin film is then deposited on the third side of the gate 109 to obtain a third sidewall dielectric layer 111. The materials of the second sidewall dielectric layer 110 and the third sidewall dielectric layer 111 can be silicon nitride and silicon oxide.

[0084] As shown in Figure 4(B), a mask 112 is obtained by deposition on the gate 109, the second sidewall dielectric layer 110, the first top surface D1 adjacent to the second sidewall dielectric layer 110, the third sidewall dielectric layer 111 adjacent to the second sidewall dielectric layer 110, and the second top surface D2 adjacent to the third sidewall dielectric layer.

[0085] According to embodiments of this disclosure, the material of mask 112 can be SiN (Silicon Nitride). SiN is characterized by high hardness, high mechanical strength, and excellent chemical stability. During photolithography, photoresist is typically patterned, and the SiN layer can act as a hard mask to protect non-source / drain regions from being implanted.

[0086] As shown in Figure 4(C), the first region of mask 112 is etched to obtain a first opening, and the first opening is doped with a first impurity to obtain a first source / drain region 113. The first region is located on the first top surface. The second region of mask 112 is etched to obtain a second opening, and the second opening is doped with a second impurity to obtain a second source / drain region 114. The second region is located on the second top surface, and the second opening is located above the well region. The first source / drain region 113 is the source / drain region of a vertical gate transistor, and the second source / drain region 114 is the source / drain region of a planar transistor. The vertical gate transistor and the planar transistor share a gate 109.

[0087] According to embodiments of this disclosure, the first impurity doping includes N-type impurity doping. The second impurity doping includes P-type impurity doping. Alternatively, the first impurity doping includes P-type impurity doping, and the second impurity doping includes N-type impurity doping.

[0088] According to embodiments of this disclosure, the first opening can be doped with N-type impurities to obtain the source / drain region of a vertical gate transistor. The second opening can be doped with P-type impurities to obtain the source / drain region of a planar transistor. Alternatively, the first opening can be doped with P-type impurities to obtain the source / drain region of a vertical gate transistor. The second opening can be doped with N-type impurities to obtain the source / drain region of a planar transistor.

[0089] According to embodiments of this disclosure, the N-type ion can be, for example, phosphorus, arsenic, or antimony. The P-type ion can be, for example, boron or germanium.

[0090] According to embodiments of this disclosure, after obtaining the gate, the first source / drain region, and the second source / drain region, the mask can be removed to obtain a semiconductor device.

[0091] Figure 5 schematically illustrates a side view of a semiconductor device according to an embodiment of the present disclosure.

[0092] Figure 6 schematically illustrates a top view of a semiconductor device according to an embodiment of the present disclosure.

[0093] As shown in Figures 5 and 6, the semiconductor device includes a first substrate 101, a vertical-gate transistor 115, and a planar transistor 116. The vertical-gate transistor 115 is located on the first substrate 101 and includes a gate 109 and a first source / drain region 113. The planar transistor 116 is located on the first substrate 101 and includes a gate 109 and a second source / drain region 114. The vertical-gate transistor 115 and the planar transistor 116 share the gate 109, and the first source / drain region 113 and the second source / drain region 114 are located on opposite sides of the gate 109.

[0094] According to embodiments of this disclosure, the first substrate 101 can be a semiconductor-insulator-semiconductor structure. The semiconductor material can be silicon, and the insulator material can be silicon oxide.

[0095] According to embodiments of this disclosure, the vertical gate transistor and the planar transistor share a common gate, that is, the gate of the vertical gate transistor and the gate of the planar transistor are the same gate and controlled by the same voltage source, so that the vertical gate transistor and the planar transistor are controlled by the same gate, reducing the spacing between the two transistors and meeting the requirements of circuit miniaturization and integration.

[0096] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0097] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor device, comprising: A composite dielectric layer is obtained by oxidizing and depositing on the first surface of a first substrate; wherein the first substrate includes a well region; the first surface includes a first top surface, a second top surface, and a first side surface; the first top surface is the upper surface of the non-well region on the first substrate, the second top surface is the upper surface of the well region, and the second top surface is lower than the first top surface; the first side surface is the connection between the first top surface and the second top surface; A first metal layer is obtained by depositing a metal thin film on the composite dielectric layer. The first metal layer located on the first top surface and the first metal layer located on the second top surface are etched to expose the composite dielectric layer, thereby obtaining the first sidewall metal layer. A second metal layer is obtained by depositing a metal thin film on the first sidewall metal layer, the composite dielectric layer located on the first top surface, and the composite dielectric layer located on the second top surface. A metal thin film is deposited on the second metal layer to obtain a third metal layer; wherein the third metal layer and the second metal layer are made of different materials. Photolithographic etching is performed on the third metal layer and the second metal layer to obtain a gate; wherein the gate is the unetched third metal layer; and Doping is performed on the first top surface adjacent to the second side surface of the gate and the second top surface adjacent to the third side surface of the gate to obtain a first source / drain region and a second source / drain region, respectively; wherein the second side surface is the opposite side of the third side surface; the first source / drain region is the source / drain region of a vertical gate transistor and the second source / drain region is the source / drain region of a planar transistor; the vertical gate transistor and the planar transistor share the gate.

2. The preparation method according to claim 1, wherein, The vertical gate transistor is an N-type transistor, and the planar transistor is a P-type transistor; or, the vertical gate transistor is a P-type transistor, and the planar transistor is an N-type transistor.

3. The preparation method according to claim 2, wherein, When the vertical gate transistor is an N-type transistor and the planar transistor is a P-type transistor, the first metal layer includes N-type transistor work function metal; the second metal layer includes P-type transistor work function metal; and the third metal layer includes gate electrode fill metal. When the vertical gate transistor is a P-type transistor and the planar transistor is an N-type transistor, the first metal layer includes a P-type transistor work function metal; the second metal layer includes an N-type transistor work function metal; and the third metal layer includes a gate electrode fill metal.

4. The preparation method according to claim 3, wherein, The material of the N-tube work function metal includes titanium nitride; the material of the P-tube work function metal includes titanium aluminum.

5. The preparation method according to claim 1, wherein, The metal thin film deposition includes metal deposition, physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

6. The preparation method according to claim 1, wherein, The step of doping the first top surface adjacent to the second side surface of the gate and the second top surface adjacent to the third side surface of the gate to obtain the first source / drain region and the second source / drain region, respectively, includes: A dielectric thin film is deposited on the second side of the gate to obtain a second sidewall dielectric layer; A dielectric thin film is deposited on the third side of the gate to obtain a third sidewall dielectric layer; A mask is obtained by deposition on the gate, the second sidewall dielectric layer, the first top surface adjacent to the second sidewall dielectric layer, the third sidewall dielectric layer, and the second top surface adjacent to the third sidewall dielectric layer. The first region of the mask is etched to obtain a first opening, and the first opening is doped with a first impurity to obtain the first source / drain region; wherein the first region is located on the first top surface; and The second region of the mask is etched to obtain a second opening, and the second opening is doped with a second impurity to obtain a second source / drain region; wherein the second region is located on the second top surface, and the second opening is located above the well region.

7. The preparation method according to claim 6, wherein, The first impurity doping includes N-type impurity doping, and the second impurity doping includes P-type impurity doping; or, the first impurity doping includes P-type impurity doping, and the second impurity doping includes N-type impurity doping.

8. The preparation method according to claim 1, further comprising: Impurity doping is performed on a designated region of the second substrate to obtain the well region; The well region is photolithographically etched to expose the well region and obtain the first top surface, the second top surface, and the first side surface; as well as The first top surface, the second top surface, and the first side surface are insulated to obtain the first substrate.

9. The preparation method according to claim 8, wherein, The second substrate is a semiconductor-insulator-semiconductor structure.

10. A semiconductor device, comprising: First base; A vertical gate transistor, the vertical gate transistor being located on the first substrate, the vertical gate transistor including a gate and a first source / drain region; as well as A planar transistor, the planar transistor being located on the first substrate, the planar transistor including a gate and a second source / drain region; The vertical gate transistor and the planar transistor share the gate, and the first source / drain region and the second source / drain region are located on both sides of the gate.

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