Array substrate, display panel, and display apparatus

Abstract

An array substrate (10), a display panel (100), and a display apparatus (1000). The array substrate (10) comprises a display area (AA) and a fan-out area (BB) located on one side of the display area (AA). The array substrate (10) comprises a base (1), a plurality of data lines (2) and a plurality of fan-out lines (3) arranged on the base (1), and an electrostatic protection structure (4) and a grounding structure (5) arranged in the fan-out area (BB). The plurality of fan-out lines (3) are located in the fan-out area (BB), and each fan-out line (3) is connected to at least one data line (2); and the electrostatic protection structure (4) is located on the side of the plurality of fan-out lines (3) that is away from the base (1), and the electrostatic protection structure (4) is electrically connected to the grounding structure (5). Each fan-out line (3) comprises a target trace segment (31), a plurality of target trace segments (31) of the plurality of fan-out lines (3) are arranged at intervals in a first direction (X), and the first direction (X) is parallel to a boundary line (J1) of the fan-out area (BB) and the display area (AA); and in a direction of thickness of the base (1), the electrostatic protection structure (4) covers the plurality of target trace segments (31) of the plurality of fan-out lines (3).

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent applications filed on September 30, 2024, application number 202411389255.1 and April 25, 2024, application number 202410511619.2, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] Liquid crystal displays (LCDs) are characterized by their small size, low power consumption, thinness, and lack of radiation, and have been widely used in the display field. With the development of display technology, their display quality has also been continuously improved along with advancements in manufacturing processes. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate includes a display area and a fan-out area located on one side of the display area. The array substrate includes a substrate, a plurality of data lines and a plurality of fan-out lines disposed on the substrate, and an electrostatic discharge (ESD) protection structure and a grounding structure disposed in the fan-out area. The plurality of fan-out lines are located in the fan-out area, and each fan-out line is connected to at least one of the data lines. The ESD protection structure is located on the side of the plurality of fan-out lines away from the substrate, and the ESD protection structure is electrically connected to the grounding structure. Each fan-out line includes a target trace segment, and the plurality of target trace segments of the plurality of fan-out lines are arranged at intervals along a first direction, which is parallel to the boundary line between the fan-out area and the display area. In the thickness direction of the substrate, the ESD protection structure covers the plurality of target trace segments of the plurality of fan-out lines.

[0005] In some embodiments, the grounding structure includes a first grounding electrode disposed on at least one side of the plurality of fan-out lines on opposite sides in the first direction; the electrostatic discharge protection structure includes a connected connecting line and at least one shielding portion, the connecting line extending along the first direction and connected to the first grounding electrode; in the thickness direction of the substrate, each of the shielding portions covers at least one target trace segment of at least one fan-out line.

[0006] In some embodiments, the electrostatic protection structure includes a plurality of shielding portions arranged along the first direction, and each shielding portion corresponding to cover a target routing segment of one fan-out line; the connecting line is located on one side of the plurality of shielding portions in a second direction, the second direction being perpendicular to the first direction.

[0007] In some embodiments, the shielding portion includes a first sub-portion and a second sub-portion connected to each other, wherein the width of the first sub-portion is greater than the width of the second sub-portion; the width of the first sub-portion or the second sub-portion is the dimension of the first sub-portion or the second sub-portion in the width direction of the shielding portion.

[0008] In some embodiments, the shielding portion includes two second sub-portions, with the first sub-portion connected between the two second sub-portions.

[0009] In some embodiments, the two second sub-parts have different dimensions in the length direction.

[0010] In some embodiments, the midpoint of the first sub-part in the length direction of the shielding part coincides with the midpoint of the shielding part in the length direction.

[0011] In some embodiments, the fan-out line includes a first sub-fan-out line and a second sub-fan-out line connected together. The first sub-fan-out line is closer to the display area than the second sub-fan-out line. The second sub-fan-out line extends along the second direction, and the extension direction of the first sub-fan-out line intersects the extension direction of the second sub-fan-out line. The distances from the intersection point of the first sub-fan-out line and the second sub-fan-out line of at least two fan-out lines to the connecting line are not equal. The connecting line is located on the side of the plurality of shielding portions closer to the display area. The distance between the first sub-part of the shielding portion and the connecting line is positively correlated with the distance from the intersection point of the first sub-fan-out line and the second sub-fan-out line of the fan-out line corresponding to the shielding portion to the connecting line.

[0012] In some embodiments, the difference between the width of the first sub-part and the width of the second sub-part ranges from 3 μm to 6 μm.

[0013] In some embodiments, the width of the connecting line is equal to the width of the shield.

[0014] In some embodiments, the electrostatic protection structure includes a plurality of shielding portions arranged along the first direction, and each shielding portion corresponding to cover a target routing segment of one fan-out line; the connecting line intersects with the plurality of shielding portions, and the two ends of each shielding portion are respectively located on both sides of the connecting line in a second direction, the second direction being perpendicular to the first direction.

[0015] In some embodiments, the shielding portion includes a first portion and a second portion located on both sides of the connecting line in the second direction, the first portion and the second portion having equal lengths; the length of the first portion or the second portion is the dimension of the first portion or the second portion in the length direction of the shielding portion.

[0016] In some embodiments, the width of the connecting line is greater than the width of the shielding portion.

[0017] In some embodiments, the width of the shielding portion is greater than or equal to the width of the target routing segment of the fan-out line.

[0018] In some embodiments, the electrostatic protection structure includes a shielding portion extending along the first direction and covering at least two target trace segments of at least two fan-out lines; the connecting line is located on one side of the shielding portion in a second direction, which is perpendicular to the first direction.

[0019] In some embodiments, the size of the shielding portion in the second direction is greater than or equal to 400 μm, and the second direction is perpendicular to the first direction.

[0020] In some embodiments, the array substrate further includes a gate conductive layer, a source / drain conductive layer, and a transparent conductive layer sequentially stacked along a direction away from the substrate; wherein, the first ground electrode is located on the gate conductive layer, and the electrostatic protection structure is located on the source / drain conductive layer and / or the transparent conductive layer.

[0021] In some embodiments, the array substrate further includes a gate dielectric layer located between the gate conductive layer and the source / drain conductive layer, and a passivation layer located between the source / drain conductive layer and the transparent conductive layer; the transparent conductive layer includes a first transition electrode disposed on at least one side of the plurality of fan-out lines on opposite sides in the first direction; the electrostatic discharge (ESD) protection structure is located on the source / drain conductive layer; the first transition electrode is connected to the first ground electrode through a first via penetrating the gate dielectric layer and the passivation layer, and the first transition electrode is connected to the connection line of the ESD protection structure through a second via penetrating the passivation layer.

[0022] In some embodiments, the multiple fan-out lines are divided into multiple fan-out line groups, and each fan-out line group includes at least one fan-out line; the electrostatic protection structure further includes a shielded connection portion disposed between two adjacent fan-out line groups, and the shielded connection portion is connected to the connection line.

[0023] In some embodiments, the shielding connection portion is located in the source-drain conductive layer, and the shielding connection portion is provided with a plurality of perforated holes penetrating the shielding connection portion.

[0024] In some embodiments, the plurality of perforations also penetrate the gate dielectric layer and the passivation layer.

[0025] In some embodiments, the dimension of the shielding connection portion in the second direction is greater than the length of the shielding portion, and the second direction is perpendicular to the first direction.

[0026] In some embodiments, the array substrate further includes a plurality of bonding pin groups, each bonding pin group including at least one bonding pin, each bonding pin being connected to a fan-out line; the grounding structure includes a second grounding electrode disposed on at least one side of the bonding pin group in the first direction, the second grounding electrode being connected to the shielding connection portion.

[0027] In some embodiments, two second ground electrodes are provided between two adjacent bonding pin groups, one of which is located near one of the bonding pin groups and the other is located near the other bonding pin group; the shielding connection is connected to the two second ground electrodes at both ends in the first direction.

[0028] In some embodiments, the bonding pin group includes a ground pin; the second ground electrode is located on the side of the ground pin away from the substrate, and the second ground electrode and the ground pin overlap in the thickness direction of the substrate; the second ground electrode is connected to the ground pin.

[0029] In some embodiments, the ground pin is located in the gate conductive layer, and the second ground electrode is located in the source-drain conductive layer; the transparent conductive layer includes a second transition electrode disposed on the side of the second ground electrode away from the substrate; the second transition electrode is connected to the second ground electrode and the ground pin through a third via penetrating the passivation layer, the second ground electrode and the gate dielectric layer.

[0030] On the other hand, a display panel is provided, including an array substrate as described in any of the embodiments above and a counter substrate disposed opposite to the array substrate; wherein, the counter substrate includes a first boundary, the first boundary is located in the region where multiple target trace segments of multiple fan-out lines of the array substrate are located, and the first boundary intersects with the multiple target trace segments.

[0031] In some embodiments, the first boundary of the opposing substrate passes through the midpoint of the plurality of target trace segments in the length direction.

[0032] In another aspect, a display device is provided, comprising: a display panel as described in any of the embodiments of the other aspect above, and a driving circuit board connected to the display panel. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0034] Figure 1 is a plan view of a display device provided according to some embodiments of the present disclosure;

[0035] Figure 2 is another structural diagram of a display device provided according to some embodiments of the present disclosure;

[0036] Figure 3 is another cross-sectional structural diagram of a display device provided according to some embodiments of the present disclosure;

[0037] Figure 4 is a cross-sectional structural diagram of a display device provided in some embodiments of the related art;

[0038] Figure 5A is a planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0039] Figure 5B is a partially enlarged structural view of the array substrate in Figure 5A provided according to some embodiments of the present disclosure;

[0040] Figure 5C is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0041] Figure 5D is a partially enlarged structural view of the array substrate in Figure 5C provided according to some embodiments of the present disclosure;

[0042] Figure 6A is a planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0043] Figure 6B is a partially enlarged structural view of the array substrate in Figure 6A provided according to some embodiments of the present disclosure;

[0044] Figure 6C is a cross-sectional view of the array substrate in Figure 6B provided according to some embodiments of the present disclosure, obtained by taking a section along the section line CC';

[0045] Figure 6D is a cross-sectional view of the array substrate in Figure 6B provided according to some embodiments of the present disclosure, obtained by taking a section along the section line DD'.

[0046] Figure 6E is a cross-sectional view of the array substrate in Figure 5D according to some embodiments of the present disclosure, obtained by taking a section along the section line EE';

[0047] Figure 7A is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0048] Figure 7B is a partially enlarged structural view of the array substrate in Figure 7A provided according to some embodiments of the present disclosure;

[0049] Figure 8 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0050] Figure 9A is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0051] Figure 9B is a partially enlarged structural view of the array substrate in Figure 9A provided according to some embodiments of the present disclosure;

[0052] Figure 10 is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0053] Figure 11A is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0054] Figure 11B is a cross-sectional view of the array substrate in Figure 11A according to some embodiments of the present disclosure, obtained by taking a section along the section line FF'.

[0055] Figure 11C is a cross-sectional view of the array substrate in Figure 11A according to some embodiments of the present disclosure, obtained by taking a section along the section line GG';

[0056] Figure 12 is another planar structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0057] Figure 13 is a structural diagram of a display device provided according to some embodiments of the present disclosure. Detailed Implementation

[0058] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0059] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0060] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0061] "At least one of A, B and C" has the same meaning as "at least one of B or C", and includes the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0062] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0063] As used herein, depending on the context, the term "if" may optionally be interpreted as meaning "when," "at," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrases "if it is determined..." or "if [the stated condition or event] is optionally interpreted as meaning "in response to determination..." or "in response to detection of [the stated condition or event]."

[0064] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0065] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0067] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0068] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0069] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0070] For ease of description below, an XYZ coordinate system is established. The third direction Z is perpendicular to the substrate, i.e., the thickness direction in this application. The XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0071] It should be noted that, for example, 51 / 5 in the accompanying drawings of this disclosure indicates that component 51 belongs to component 5, and 1051 (105) indicates that component 1051 is disposed within the film layer 105. Other similar reference numerals appearing in the drawings also follow the above description.

[0072] As shown in Figure 1, some embodiments of this disclosure provide a display device 1000.

[0073] Exemplarily, the aforementioned display device 1000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, television (TV) products, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 illustrates the display device 1000 as an example of a TV product.

[0074] For example, the display device 1000 may be a thin film transistor liquid crystal display (TFT-LCD) device.

[0075] In some embodiments, referring to Figures 1 and 2, the display device 1000 includes a display panel 100 and a driving circuit board 200. The driving circuit board 200 is electrically connected to the display panel 100.

[0076] For example, the driving circuit board 200 within the display device 1000 may be a printed circuit board.

[0077] For example, the display device 1000 also includes a plurality of chip-on-film (COF) films 300 connected to the driving circuit board 200, and the driving circuit board 200 can be electrically connected to the display panel 100 through the chip-on-film (COF) films 300.

[0078] For example, the display device 1000 also includes a driver chip 400, which is configured to drive the display panel 100 to display images. The driver chip 400 can be packaged by means of a chip-on-glass film 300, chip-on-glass (COG), chip-on-pi (COP), etc., and bonded to the display panel 100.

[0079] For example, the driver chip 400 within the display device 1000 can be packaged using a chip-on-film (COF) film. When the driver chip 400 within the display device 1000 is packaged using a COF film, the display device 1000 includes a COF film assembly, which may include a flexible printed circuit (FPC) and a driver chip bonded to the FPC. Exemplarily, the end of the flexible printed circuit connected to the COF film has gold fingers (not shown), and the gold fingers and the COF film 300 are connected via an anisotropic conductive film (ACF). The ACF film includes an adhesive layer and a plurality of metal balls (e.g., gold balls) distributed within the adhesive layer.

[0080] In some embodiments, the display device 1000 may further include optical elements (not shown).

[0081] For example, the optical element may include a camera, enabling the display device 1000 to perform various functions such as taking pictures, recording videos, or facial recognition.

[0082] Optical components may also include sensors. For example, optical components may include an under-display fingerprint sensor, enabling the display device 1000 to perform functions such as fingerprint recognition. As another example, optical components may include an infrared sensor.

[0083] The display panel 100 described above will be described in detail below.

[0084] In some embodiments, as shown in FIG1, FIG1 is a plan view of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0085] It should be noted that the above-mentioned "rectangular structure" refers to the fact that the shape of the boundary of the display panel 100 is generally rectangular. For example, as shown in Figure 1, the long side and the short side of the rectangle are right angles at each intersection (i.e., at the corner), so that the shape of the boundary of the display panel 100 in the plan view is a right-angled rectangle.

[0086] In other embodiments, the display panel 100 may also be a circular structure or other shapes with corners.

[0087] The following uses a rectangular structure for the display panel 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 100 can also be any other shape.

[0088] In some embodiments, please continue to refer to FIG1, the display panel 100 includes a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0089] For example, the peripheral area AN of the display panel 100 may be located on one side of the display area AA of the display panel 100.

[0090] Alternatively, the peripheral area AN of the display panel 100 may be located on opposite sides of the display area AA of the display panel 100.

[0091] Alternatively, please continue to refer to Figure 1, the peripheral area AN of the display panel 100 can surround the display area AA of the display panel 100.

[0092] It should be noted that the specific arrangement of the peripheral area AN of the display panel 100 is related to the specific design of the display panel 100 and can be designed according to actual needs. The following uses the example of the peripheral area AN of the display panel 100 surrounding the display area AA of the display panel 100 to illustrate some embodiments of this disclosure.

[0093] For example, a gate driving circuit (e.g., Gate driver On Array, or GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) may be disposed in the peripheral area AN of the display panel 100. However, the function of the peripheral area AN of the display panel 100 includes, but is not limited to, these.

[0094] In some embodiments, as shown in FIG3, when the display panel 100 is a thin film transistor liquid crystal display (TFT-LCD) panel, the display panel 100 may include an array substrate 10, an opposing substrate 20, and a liquid crystal layer 30. The opposing substrate 20 and the array substrate 10 are disposed opposite to each other and spaced apart, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposing substrate 20.

[0095] For example, please continue to refer to FIG3, the opposing substrate 20 in the display panel 100 can be a color filter substrate.

[0096] For example, the liquid crystal layer includes liquid crystal material located in the display area AA. The display panel also includes a sealant (not shown) surrounding the liquid crystal material, which serves to connect the array substrate 10 and the opposing substrate 20.

[0097] In one possible embodiment, the display panel is a liquid crystal display panel, the display device including the display panel is a liquid crystal display device, and the liquid crystal display device further includes a backlight panel located on the side of the array substrate 10 away from the opposing substrate 20. Exemplarily, the liquid crystal display panel may be an Advanced Super Dimension Switch (ADS) liquid crystal display panel, or a High-Aperture Ratio and High-Advanced Dimension Switch (HADS) liquid crystal display panel. Exemplarily, the liquid crystal display device further includes a backlight panel and a power supply circuit; the backlight panel is located on the backlight surface of the display panel and is used to provide a light source for the liquid crystal display panel, and the power supply circuit is used to supply power to the display panel.

[0098] For example, the display area AA of the display panel 100 includes a plurality of sub-pixels, each sub-pixel may include a pixel electrode and a common electrode. The pixel electrode and the common electrode are disposed opposite to each other, and a pixel capacitor may be formed between the pixel electrode and the common electrode.

[0099] For example, the material of the pixel electrode may include a transparent conductive material. For instance, the material of the pixel electrode may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0100] The material of the common electrode can also include transparent conductive materials. For example, the material of the common electrode can include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0101] An electric field can be generated within the display panel 100, causing the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect under the influence of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 within the display panel 100, the degree of deflection of the liquid crystal molecules within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted in the area where the liquid crystal molecules are located within the liquid crystal layer 30, thus enabling the display panel 100 to display images.

[0102] For example, the electric field that drives the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect can be generated when a voltage is applied to the pixel electrode and the common electrode within the sub-pixel.

[0103] Figure 4 is a cross-sectional structural diagram of a liquid crystal display device in the related art. As shown in Figure 4, in the related art, the liquid crystal display device includes a liquid crystal display panel 100' and a circuit board 200'. The liquid crystal display panel includes an array substrate 10' and an opposing substrate 20', and a liquid crystal layer 30' located between the array substrate 10' and the opposing substrate 20'. The array substrate 10' includes a substrate 1' and multiple data lines 2' located on the substrate 1'. The substrate 1' has a display area A' and a fan-out area B' located outside the display area. The orthographic projection of the multiple data lines 2' onto the substrate 1' overlaps with the fan-out area B', and at least part of the fan-out area B' is located outside the orthographic projection of the opposing substrate 2' onto the substrate 1'. Part of the circuit board 200' is located in the fan-out area B' in the orthographic projection of the substrate 1', and the circuit board 200' is electrically connected to the data lines 2'. It should be noted that only one data line 2' is shown in Figure 1 as an example.

[0104] It should be noted that as the contrast requirements for liquid crystal display panels in the display field gradually increase, in addition to reducing the problem of light leakage in dark states, it is also necessary to reduce the reflectivity of external light hitting the liquid crystal display panel. In order to reduce the reflectivity, the above-mentioned liquid crystal display device removes the grounding electrode layer located on the side of the opposing substrate 20' away from the array substrate 10'. However, in practical applications, human hands inevitably touch the surface of the liquid crystal display device, and static electricity is generated due to friction. After the electrode layer is removed, the surface of the opposing substrate 20' loses its ability to conduct static electricity, resulting in a weakening of the electrostatic protection capability of the entire liquid crystal display device. External static electricity will enter the liquid crystal display panel along the edge of the opposing substrate 20' near the fan-out area B', and then flow to the fan-out area, causing the data line 2' to be damaged by static electricity. As shown in Figure 4, the liquid crystal display panel also includes an adhesive structure 5', which is located in the fan-out area B' and between the array substrate 10' and the opposing substrate 20'. In actual production, the side of the adhesive structure 5' closest to the opposing substrate 20' may be recessed, resulting in a gap between the adhesive structure 5' and the opposing substrate 20'. This can cause external static electricity to enter the liquid crystal display panel along the gap. The path of static electricity entering the liquid crystal display panel is shown by the arrow in Figure 4. After the static current reaches part of the data line 2' located in the fan-out area B', it may flow further along the data line 2' towards the display area A', or further along the data line 2' away from the display area A' to the circuit board 200', thus affecting the display function.

[0105] In other related technologies, to improve the electrostatic discharge (ESD) protection capability of the display device, a full-layer grounding electrode layer is fabricated on the side of the opposing substrate 20' away from the array substrate 10'. This electrode layer is located in the display area A' and the fan-out area B'. However, in this approach, the full-layer electrode layer results in a high reflectivity of the display panel to ambient light. If the display panel is a liquid crystal display (LCD), this full-layer electrode layer also has a high reflectivity to the backlight emitted by the backlight panel. Therefore, the full-layer grounding electrode layer reduces the contrast of the display panel, resulting in insufficient brightness in dark conditions, which does not meet the needs of users of products such as televisions.

[0106] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel, and a display device. By setting an electrostatic protection structure and without setting an electrode layer for grounding covering the entire display area, the aforementioned poor display problems can be avoided. At the same time, the electrostatic protection capability of the display device can be improved, the reflectivity can be reduced, and the contrast and reliability of the display device can be improved.

[0107] The array substrate, display panel and display device provided in this disclosure will be described in detail below.

[0108] In some embodiments, as shown in Figures 2 and 3, the array substrate 10 provided in this disclosure includes a display area AA and a fan-out area BB located on one side of the display area AA. The array substrate 10 includes a substrate 1, multiple data lines 2 and multiple fan-out lines 3 disposed on the substrate 1, an electrostatic discharge (ESD) protection structure 4 and a grounding structure 5 disposed on the fan-out area BB. The multiple fan-out lines 3 are located in the fan-out area BB, and each fan-out line 3 is connected to at least one data line 2. The ESD protection structure 4 is located on the side of the multiple fan-out lines 3 away from the substrate 1, and the ESD protection structure 4 is electrically connected to the grounding structure 5. As shown in Figure 5A, the fan-out line 3 includes a target trace segment 31. The multiple target trace segments 31 of the multiple fan-out lines 3 are arranged at intervals along a first direction X, and the first direction X is parallel to the boundary line J1 between the fan-out area BB and the display area AA. In the thickness direction of the substrate 1, the ESD protection structure 4 covers the multiple target trace segments 31 of the multiple fan-out lines 3.

[0109] For example, the substrate 1 can be a flexible substrate 1, such as a polyethylene terephthalate (PET) film, a polyethylene naphthalate (PEN) film, a polyimide (PI) film, etc.; or it can be a rigid substrate 1, such as a glass substrate 1.

[0110] For example, referring to Figure 2, multiple fan-out lines 3 are located in the fan-out area BB. Each fan-out line 3 is connected to at least one data line 2. That is, one fan-out line 3 can be connected to one data line 2, and one fan-out line 3 can also be connected to multiple data lines 2. The multiple data lines 2 are located in the display area AA, and the multiple data lines 2 are used to connect the sub-pixels in the display area AA.

[0111] In some embodiments, referring to FIG2, the opposing substrate 20 includes a first boundary B1, which is located in the region where multiple target trace segments 31 of multiple fan-out lines 3 of the array substrate 10 are located, and the first boundary B1 intersects with the multiple target trace segments 31.

[0112] It should be noted that, referring to Figure 2, the first boundary B1 is the boundary where static electricity generated by a human hand touching the surface of the liquid crystal display device enters the display panel 100. This first boundary B1 is close to the fan-out area BB. The area where multiple target trace segments 31 are located, i.e., the fan-out lines 3, are easily damaged under static electricity, affecting the display, is called the target area C. The first boundary B1 is located in the area where multiple target trace segments 31 of the multiple fan-out lines 3 of the array substrate 10 are located. That is, the first boundary B1 is located within the target area C. The first boundary B1 intersects with multiple target trace segments 31, meaning that the two ends of each target trace segment 31 are located on both sides of the first boundary B1 in the second direction Y. The second direction Y is perpendicular to the first direction X. The plane formed by the first direction X and the second direction Y is parallel to the surface of the array substrate 10 near the opposing substrate 20, and both the second direction Y and the first direction X are perpendicular to the thickness direction.

[0113] Compared with related technologies, referring to Figures 2 and 3, this application sets the electrostatic discharge (ESD) protection structure 4 on the side of the multiple fan-out lines 3 away from the substrate 1, and the ESD protection structure 4 covers multiple target trace segments 31 of the multiple fan-out lines 3. That is, the ESD protection structure 4 covers the target area C. The ESD protection structure 4 overlaps with the first boundary B1. During the process of static electricity generated by the friction between the human hand and the surface of the liquid crystal display device entering the display panel 100 along the first boundary B1, the static electricity will be attracted to the ESD protection structure 4 and transmitted to the grounding structure 5 electrically connected to the ESD protection structure 4. The static electricity is discharged through the grounding structure 5, which can prevent the static electricity from being released on the target trace segments 31 in the target area C, causing damage to the target trace segments 31. It can also improve the ESD protection capability without affecting the contrast of the display device, thereby improving the service life and reliability of the display device.

[0114] It should be noted that the electrostatic protection structure 4 covers multiple target trace segments 31 of multiple fan-out lines 3. In addition to the electrostatic protection function of multiple target trace segments 31, the electrostatic protection structure 4 can also protect multiple target trace segments 31 from being scratched. Since the electrostatic protection structure 4 overlaps with the first boundary B1, the first boundary B1 needs to be cut during the formation of the opposing substrate 20. During the cutting process, the electrostatic protection structure 4 can prevent cutting debris from damaging multiple target trace segments 31.

[0115] In some embodiments, referring to Figures 5A and 5C, the grounding structure 5 includes a first grounding electrode 51 disposed on at least one side of the multiple fan-out lines 3 on opposite sides in the first direction X; the electrostatic protection structure 4 includes a connected connecting line 41 and at least one shielding portion 42, the connecting line 41 extending along the first direction X and connected to the first grounding electrode 51; referring to Figures 6A, 7A, 8, 9A and 10, and in conjunction with Figure 3, in the thickness direction of the substrate 1, each shielding portion 42 covers at least one target trace segment 31 of at least one fan-out line 3.

[0116] It should be noted that, referring to Figures 5A and 5C, in some embodiments, the portion of the connecting line 41 near the grounding structure 5 in Figure 5C is a bent structure. According to Figure 5C, the bent structure of the connecting line 41 is a right-angle bend, that is, the extension direction of the connecting line 41 bends from the first direction X to the second direction Y, and then bends from the second direction Y back to the first direction X, and finally connects to the grounding structure 5 in the first direction X. This arrangement is to avoid interference between the connecting line 41 and other components on the array substrate, and at the same time, to avoid interference between signals transmitted between other lines arranged on the same layer as the connecting line 41, thereby improving the quality of the display device.

[0117] It is understandable that, referring to Figure 5D, the position of the connection between the connecting line 41 and the grounding structure 5 in the second direction Y is set slightly below the grounding structure 5. This is based on the wiring method of the connecting line 41. In other words, based on the arrangement of the connecting line 41, the grounding structure 5 is located slightly below the grounding structure 5 in the second direction Y, making it easier to connect the connecting line 41 to the grounding structure 5. Therefore, this setting not only follows the principle of proximity but also simplifies the wiring and avoids wire detours.

[0118] For example, the first grounding electrode 51 is disposed on at least one of the opposite sides of the plurality of fan-out lines 3 in the first direction X. That is, the first grounding electrode 51 is disposed on any one of the opposite sides of the plurality of fan-out lines 3 in the first direction X, or the first grounding electrode 51 is disposed on both opposite sides of the plurality of fan-out lines 3 in the first direction X. Referring to FIG5A, the first grounding electrode 51 shown in FIG5A is disposed on both opposite sides of the plurality of fan-out lines 3 in the first direction X. With this arrangement, static electricity can be grounded simultaneously through the first grounding electrodes 51 on both sides, thereby achieving the effect of rapid release of static electricity.

[0119] In some embodiments, referring to Figures 6A, 7A, 8 and 9A, the electrostatic protection structure 4 includes a plurality of shielding parts 42, which are arranged along a first direction X, and each shielding part 42 covers a target routing segment 31 of a fan-out line 3; the connecting line 41 is located on one side of the plurality of shielding parts 42 in a second direction Y, which is perpendicular to the first direction X.

[0120] For example, referring to Figures 6A, 7A, 8, and 9A, the connecting line 41 is located on one side of the plurality of shielding portions 42 in the second direction Y. Referring to Figure 2, the connecting line 41 can be located on the side of the plurality of shielding portions 42 closer to the display area AA, or it can be located on the side of the plurality of shielding portions 42 farther from the display area AA. The connection line 41 shown in Figures 6A, 7A, 8, and 9A, which can be located on the side of the plurality of shielding portions 42 closer to the display area AA, is merely an example and is not specifically limited here.

[0121] In some embodiments, referring to Figures 7B and 8, Figure 7B is a partial enlarged view of Figure 7A. The shielding portion 42 includes a first sub-portion 42a and a second sub-portion 42b connected to each other. The width W1 of the first sub-portion 42a is greater than the width W2 of the second sub-portion 42b. The width of the first sub-portion 42a or the second sub-portion 42b is the dimension of the first sub-portion 42a or the second sub-portion 42b in the width direction of the shielding portion 42.

[0122] It is understood that the first sub-part 42a includes a first side c1 and a second side c2 opposite to each other in a set direction, where the set direction is perpendicular to the width direction. The width of the first sub-part 42a is the distance between the first side c1 and the second side c2, which is also the dimension of the shielding part 42 in the width direction. This width direction can be the same as or intersect with the first direction X. The width W2 of the second sub-part 42b is explained in the same way as above, and will not be repeated here.

[0123] With the above configuration, during the process of static electricity being transferred to the shielding part 42, since the width W1 of the first sub-part 42a is greater than the width W2 of the second sub-part 42b, for example, referring to FIG2, the first sub-part 42a overlaps with the first boundary B1 of the opposing substrate 20. During the process of static electricity entering the fan-out line 3 along the first boundary B1, the first sub-part 42a covering the target trace segment 31 of the fan-out line 3 is closer to the static electricity generation position than the second sub-part 42b, which can quickly attract the charge of static electricity, accelerate the discharge of static electricity, and thus improve the reliability of the display device.

[0124] In some embodiments, referring to FIG7B, the difference between the width W1 of the first sub-part 42a and the width W2 of the second sub-part 42b ranges from 3μm to 6μm.

[0125] For example, the width W1 of the first sub-part 42a is 23 μm and the width W2 of the second sub-part 42b is 20 μm. This is just an example. Specifically, the width W1 of the first sub-part 42a and the width W2 of the second sub-part 42b only need to satisfy the above-mentioned difference range.

[0126] In some embodiments, referring to Figures 7B and 8, the shielding portion 42 includes two second sub-portions 42b, and a first sub-portion 42a is connected between the two second sub-portions 42b.

[0127] It is understood that the shielding portion 42 includes two second sub-portions 42b, one of which is located on the side of the first sub-portion 42a closer to the display area AA, and the other is located on the side of the first sub-portion 42a away from the display area AA. In other words, the first sub-portion 42a can be connected to any position between the two second sub-portions 42b, meaning the two second sub-portions 42b can have different dimensions in the length direction. For example, the length direction is the second direction Y.

[0128] For example, the shielding part 42 includes two second sub-parts 42b, and the two second sub-parts 42b are not equal in size in the length direction. Since the first sub-part 42a of the shielding part 42 is wider than the other sub-parts, this arrangement can attract static electricity over a larger range in the length direction to avoid discharge on the target routing segment 31 of the fan-out line 3.

[0129] In some embodiments, referring to FIG7B, the midpoint of the first sub-part 42a in the length direction of the shielding part 42 coincides with the midpoint of the shielding part 42 in the length direction.

[0130] For example, referring to FIG7B, with the length direction being the second direction Y, the midpoint of the first sub-part 42a in the length direction of the shielding part 42 coincides with the midpoint of the shielding part 42 in the length direction. That is, the distance between the first sub-part 42a and the end of the two second sub-parts 42b that is away from the first sub-part 42a is equal.

[0131] In some embodiments, referring to FIG8, the fan-out line 3 includes a first sub-fan-out line 301 and a second sub-fan-out line 302 connected to each other. The first sub-fan-out line 301 is closer to the display area AA than the second sub-fan-out line 302. The second sub-fan-out line 302 extends along the second direction Y. The extension direction of the first sub-fan-out line 301 intersects the extension direction of the second sub-fan-out line 302. The distance from the intersection point of the first sub-fan-out line 301 and the second sub-fan-out line 302 of at least two fan-out lines 3 to the connecting line 41 is not equal. The connecting line 41 is located on the side of the plurality of shielding parts 42 close to the display area AA. The distance between the first sub-part 42a of the shielding part 42 and the connecting line 41 is positively correlated with the distance from the intersection point of the first sub-fan-out line 301 and the second sub-fan-out line 3 of the fan-out line 3 corresponding to the shielding part 42 to the connecting line 41.

[0132] For example, as shown in Figure 8, the extension direction of the first sub-fan line 301 intersects the extension direction of the second sub-fan line 302. That is, the first sub-fan line 301 and the second sub-fan line 302 can form a certain angle, and the vertex is the intersection point of the first sub-fan line 301 and the second sub-fan line 302. Taking the leftmost fan-out line 3 and the last fan-out line 3 in Figure 8 as examples, the distance d1 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 to the connecting line 41 is less than the distance d2 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 to the connecting line 41. Figure 8 is just one example. Here, it is only necessary to satisfy that the distance d1 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 to the connecting line 41 is not equal to the distance d2 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 to the connecting line 41. For example, the distance d1 from the intersection of the first sub-fan line 301 and the second sub-fan line 302 of the leftmost fan line 3 to the connecting line 41 can also be greater than the distance d2 from the intersection of the first sub-fan line 301 and the second sub-fan line 302 of the rightmost fan line 3 to the connecting line 41.

[0133] For example, when the connecting line 41 is located on the side of the plurality of shielding portions 42 close to the display area AA, as described above, the distance d1 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 in FIG8 to the connecting line 41 is less than the distance d2 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 to the connecting line 41. Continuing to refer to FIG8, the distance between the first sub-part 42a of the corresponding shielding portion 42 of the leftmost fan-out line 3 and the connecting line 41 is d3, and the distance between the first sub-part 42a of the corresponding shielding portion 42 of the rightmost fan-out line 3 and the connecting line 41 is d4, where d3 < d4. For example, d3 = 0 μm.

[0134] It should be noted that at the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3, charge is more easily accumulated due to tip discharge. Therefore, to improve electrostatic protection and better protect the fan-out line 3, the distance between the first sub-part 42a of the shielding part 42 and the connecting line 41 is positively correlated with the distance between the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3 corresponding to the shielding part 42 and the connecting line 41. That is, referring to Figure 2, during the process of static electricity entering the target trace segment 31 of the fan-out line 3 along the first boundary B1 of the opposing substrate 20, the first sub-part 42a of the shielding part 42 covering the target trace segment 31 is closer to the charge accumulation position. Moreover, since the first sub-part 42a of the shielding part 42 is wider than the other sub-parts, it can better attract charge, thereby preventing discharge at the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3.

[0135] For example, the target routing segment 31 of the fan-out line 3 can be part of the first sub-fan-out line 301 or part of the second sub-fan-out line 302, without limitation. This application provides a detailed description with the target routing segment 31 being part of the second sub-fan-out line 302, and the target routing segment 31 being part of the first sub-fan-out line 301, referring to the description with the target routing segment 31 being part of the second sub-fan-out line 302.

[0136] In some embodiments, referring to FIG6B, the width W3 of the connecting line 41 is equal to the width W4 of the shielding portion 42.

[0137] For example, referring to FIG6B, setting the width W3 of the connecting line 41 to be equal to the width W4 of the shielding portion 42 can simplify the process of forming the electrostatic protection structure. For example, the process of forming the electrostatic protection structure is an etching process.

[0138] In some embodiments, referring to Figures 9A and 9B, the electrostatic protection structure 4 includes a plurality of shielding parts 42, which are arranged along a first direction X, and each shielding part 42 covers a target routing segment 31 of a fan-out line 3; the connecting line 41 is arranged to intersect with the plurality of shielding parts 42, and the two ends of each shielding part 42 are located on both sides of the connecting line 41 in a second direction Y, which is perpendicular to the first direction X.

[0139] For example, referring to Figures 9A and 9B, the connecting line 41 is intersected with a plurality of shielding parts 42. The two ends of each shielding part 42 are located on both sides of the connecting line 41 in the second direction Y. That is, the connecting line 41 is located in the area where the target trace segment 31 is located, and the two ends of each shielding part 42 are at the edge of the area where the target trace segment 31 is located. Since the connecting line 41 is continuous and there is no interruption in the middle, when static electricity flows to the connecting line 41, the connecting line 41 can quickly attract the charge and transfer it along the first direction X, thereby improving the static electricity protection capability of the static protection structure.

[0140] In some embodiments, referring to Figures 9A and 9B, the shielding portion 42 includes a first portion 421 and a second portion 422 located on both sides of the connecting line 41 in the second direction Y, the lengths of the first portion 421 and the second portion 422 are equal; the length of the first portion 421 or the second portion 422 is the dimension of the first portion 421 or the second portion 422 in the length direction of the shielding portion 42.

[0141] For example, referring to Figures 9A and 9B, the first part 421 and the second part 422 are located on both sides of the connecting line 41 in the second direction Y, and the lengths of the first part 421 and the second part 422 are equal. That is, the distance between the connecting line 41 and the side of the first part 421 away from the second part 422 is equal to the distance between the connecting line 41 and the side of the second part 422 away from the first part 421.

[0142] It should be noted that the length direction here refers to the extension direction of the first part 421 or the second part 422. The extension direction of the first part 421 or the second part 422 shown in Figures 9A and 9B is the second direction Y. This is only one example. The extension direction of the first part 421 or the second part 422 can also be any direction that intersects the second direction Y and is not perpendicular to the second direction Y.

[0143] In some embodiments, as shown in Figures 9A and 9B, the width W3 of the connecting line 41 is greater than the width W4 of the shielding portion 42.

[0144] For example, referring to Figures 9A and 9B, setting the width W3 of the connecting line 41 to be greater than the width W4 of the shielding part 42 can increase the electrostatic adsorption area and reduce the impedance during signal transmission of the connecting line 41.

[0145] In some embodiments, referring to Figures 6B, 7B, 8, 9B and 10, the width W4 of the shielding portion 42 is greater than or equal to the width W5 of the target trace segment 31 of the fan-out line 3.

[0146] For example, when a shielding part 42 covers a target trace segment 31, as shown in Figures 6B and 9B, the width W4 of the shielding part 42 is greater than the width W5 of the target trace segment 31 of the fan-out line 3. As shown in Figures 7B and 8, the width W1 of the first sub-part and the width W2 of the second sub-part of the shielding part 42 are both greater than the width W5 of the target trace segment 31 of the fan-out line 3.

[0147] For example, when a shielding portion 42 covers multiple target trace segments 31, referring to FIG10, the width W4 of the shielding portion 42 is greater than the width W5 of the target trace segment 31 of the fan-out line 3.

[0148] The above figure only illustrates an example where the width W4 of the shielding portion is greater than the width W5 of the target trace segment 31 of the fan-out line 3. In other embodiments, the width W4 of the shielding portion is equal to the width W5 of the target trace segment 31 of the fan-out line 3. This width setting allows the target trace segment 31 to be completely covered by the shielding portion 42. In other words, the shielding portion 42 can attract and conduct away static charge located above the target trace segment 31, protecting the target trace segment 31 from the effects of static electricity.

[0149] In some embodiments, as shown in FIG10, the electrostatic protection structure 4 includes a shielding portion 42 extending along a first direction X, the shielding portion 42 covering at least two target routing segments 31 of at least two fan-out lines 3; the connecting line 41 is located on one side of the shielding portion 42 in a second direction Y, the second direction Y being perpendicular to the first direction X.

[0150] For example, referring to FIG10, the shielding part 42 covers multiple target routing segments 31 of multiple fan-out lines 3. This arrangement can increase the electrostatic adsorption area, improve the electrostatic attraction efficiency, and facilitate the rapid discharge of static electricity.

[0151] In some embodiments, referring to FIG6B in conjunction with FIG2, the size of the shielding portion 42 in the second direction Y is greater than or equal to 400 μm, and the second direction Y is perpendicular to the first direction X.

[0152] For example, the dimension d5 of the shielding part 42 in the second direction Y is greater than or equal to 400 μm. The minimum dimension of the shielding part 42 in the second direction Y is defined here based on the position of the first boundary B1 of the opposing substrate 20. Since the opposing substrate 20 needs to be cut during the manufacturing process, the first boundary B1 after cutting is located in the area where multiple target trace segments 31 are located. That is to say, during the process of static electricity entering the display panel 100 along the first boundary B1, the area where the target trace segments 31 are located are all places where static electricity may be easily released. Performing static electricity protection in this area can ensure that static electricity is effectively adsorbed and discharged. The minimum dimension of the shielding part 42 in the second direction Y can also be the dimension of the area where the target trace segments 31 are located in the second direction Y.

[0153] In some embodiments, referring to FIG2, the first boundary B1 of the opposing substrate 20 passes through the midpoint of the multiple target trace segments 31 of the multiple fan-out lines 3 in the length direction.

[0154] It should be noted that since the first boundary B1 of the opposing substrate 20 is the boundary for static electricity to enter the display panel 100, and the first boundary B1 passes through the midpoint of multiple target trace segments 31 of multiple fan-out lines 3 in the length direction, setting the static discharge position at the midpoint of the target trace segment 31 in the length direction, i.e., the static discharge position is located in the middle of the static protection structure 4, can ensure that all static electricity can be absorbed by the static protection structure 4 and transferred to the grounding structure 5, thereby protecting the target trace segment 31, improving the static protection capability of the display panel 100, and thus improving the service life of the display panel 100.

[0155] For example, the first boundary B1 of the opposing substrate 20 passes through the midpoint of the multiple target trace segments 31 of the multiple fan-out lines 3 in the length direction. Since the first boundary B1 of the opposing substrate 20 is the cutting position of the opposing substrate 20, that is, the cutting position of the opposing substrate 20 is located at the midpoint of the multiple target trace segments 31 in the length direction, with this configuration, the electrostatic protection structure 4 can better protect the multiple target trace segments 31 of the multiple fan-out lines 3, and avoid damage to the multiple target trace segments 31 of the multiple fan-out lines 3 caused by cutting debris generated during the cutting process of the opposing substrate 20.

[0156] The following is a detailed description of the arrangement of each film layer on the array substrate 10.

[0157] In some embodiments, referring to Figures 6C, 6D, and 6E, where Figure 6E is a cross-sectional view obtained by taking a section along the cross-section line EE' in Figure 5B, according to Figure 6E, the array substrate 10 further includes a gate conductive layer 101, a gate dielectric layer 102, a source / drain conductive layer 103, a passivation layer 104, and a transparent conductive layer 105 sequentially stacked along a direction away from the substrate 1. The first ground electrode 51 is located on the gate conductive layer 101, and the electrostatic discharge protection structure 4 is located on the source / drain conductive layer 103 and / or the transparent conductive layer 105.

[0158] For example, the gate dielectric layer 102 and the passivation layer 104 can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and can be a single layer, double layer or multilayer structure to achieve the effect of blocking water and oxygen and blocking alkaline ions. They can be deposited by plasma enhanced chemical vapor deposition (PECVD) process.

[0159] For example, the material of the transparent conductive layer 105 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0160] The following section uses the electrostatic discharge protection structure 4 located in the source / drain conductive layer 103 as an example to introduce the specific structure and connection of the electrostatic discharge protection structure 4.

[0161] In some embodiments, referring to Figures 5A, 5B, and 6E, where Figure 5B is a partially enlarged view of Figure 5A and Figure 6E is a cross-sectional view of Figure 5B obtained by taking a section along the cross-section line EE', the transparent conductive layer 105 includes a first transition electrode 1051 disposed on at least one side of the multiple fan-out lines 3 on opposite sides in the first direction X; the electrostatic discharge protection structure 4 is located in the source / drain conductive layer 103; the first transition electrode 1051 is connected to the first ground electrode 51 through a first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104, and the first transition electrode 1051 is connected to the connection line 41 of the electrostatic discharge protection structure 4 through a second via G2 penetrating the passivation layer 104.

[0162] For example, referring to FIG5A, the first transition electrode 1051 shown in FIG5A is located in the transparent conductive layer 105, and the first transition electrode 1051 is disposed on opposite sides of the multiple fan-out lines 3 in the first direction X. Referring to FIG6E, the first transition electrode 1051 is connected to the first ground electrode 51 through the first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104, and the first transition electrode 1051 is connected to the connection line 41 of the electrostatic protection structure 4 through the second via G2 penetrating the passivation layer 104. That is to say, the first transition electrode 1051 can play the role of connecting the connection line 41 of the electrostatic protection structure 4 and the first ground electrode 51. It should be noted that the depths of the first via G1 and the second via G2 are different.

[0163] In some embodiments, referring to FIG5A, the multiple fan-out lines 3 are divided into multiple fan-out line groups 310, and each fan-out line group 310 includes at least one fan-out line 3; referring to FIG11A, the electrostatic protection structure 4 further includes a shielded connection part 43, which is disposed between two adjacent fan-out line groups 310, and the shielded connection part 43 is connected to the connecting line 41.

[0164] For example, each fan-out line group 310 includes at least one fan-out line 3, that is, each fan-out line group 310 may include one fan-out line 3 or multiple fan-out lines 3; as shown in FIG5A, the fan-out line group 310 shown in FIG5A includes multiple fan-out lines 3.

[0165] It should be noted that, referring to Figure 11A, a shielding connection part 43 is provided. The shielding connection part 43 is connected between two adjacent fan-out line groups 310, and the shielding connection part 43 is connected to the connecting line 41, as shown in Figure 11A. The shielding connection part 43 is a whole surface, which can increase the electrostatic adsorption area of ​​the electrostatic protection structure 4, so that more static electricity is distributed in the area between the two adjacent fan-out line groups 310. At the same time, it can reduce the static electricity distribution above the target routing segment 31 of multiple fan-out lines 3, so as to reduce the risk of damage to the target routing segment 31 of multiple fan-out lines 3.

[0166] In some embodiments, referring to FIG11A, the shielding connection portion 43 is located on the source-drain conductive layer 103, and the shielding connection portion 43 is provided with a plurality of hollow holes 431 penetrating the shielding connection portion 43.

[0167] For example, referring to FIG11A, the shielding connection portion 43 in FIG11A is provided with a plurality of hollow holes 431. This is provided to improve light transmittance while ensuring that the curing of the adhesive layer provided between the array substrate 10 and the opposing substrate 20 is not affected.

[0168] In some embodiments, continuing to refer to FIG11C, a plurality of perforations 431 also penetrate the gate dielectric layer 102 and the passivation layer 104.

[0169] For example, referring to FIG11C, which shows a cross-sectional structural view of the shielding connection portion 43, multiple perforations 431 also penetrate the gate dielectric layer 102 and the passivation layer 104, which can further improve the light transmittance.

[0170] In some embodiments, referring to FIG11A, the dimension of the shielding connection portion 43 in the second direction Y is greater than the length of the shielding portion 42, and the second direction Y is perpendicular to the first direction X.

[0171] For example, the dimension of the shielding connection part 43 in the second direction Y is L1, and the length of the shielding part 42 is L2. The setting of L1 > L2 is mainly to transfer most of the static electricity to the shielding connection part 43, so as to avoid the accumulation of static electricity and thereby improve the speed of static electricity discharge.

[0172] In some embodiments, referring to FIG12, the array substrate 10 further includes a plurality of bonding pin groups 110, each bonding pin group 110 including at least one bonding pin 111, each bonding pin 111 being connected to a fan-out line 3; the grounding structure 5 includes a second grounding electrode 52 disposed on at least one side of the bonding pin group 110 in the first direction X, and the second grounding electrode 52 being connected to the shielding connection portion 43.

[0173] For example, referring to FIG12 in conjunction with FIG11A, the array substrate 10 includes a plurality of bonding pin groups 110. The plurality of bonding pin groups 110 are disposed on the side of the fan-out line group 310 away from the display area AA. Each bonding pin group 110 is correspondingly connected to one fan-out line group 310. Each bonding pin group 110 may include one bonding pin 111 or may include multiple bonding pins 111. When a bonding pin group 110 includes one bonding pin 111, one bonding pin 111 is correspondingly connected to one fan-out line 3. When a bonding pin group 110 includes multiple bonding pins 111, each fan-out line group 310 also includes multiple fan-out lines 3, and the number of bonding pins 111 and fan-out lines 3 is the same. One bonding pin 111 is correspondingly connected to one fan-out line 3.

[0174] Referring to Figure 11B, a second ground electrode 52 is provided in the source / drain conductive layer 103 of Figure 11B. Referring to Figures 11A and 12, the second ground electrode 52 is provided on at least one side of the bonding pin group 110 in the first direction X. That is, the second ground electrode 52 can be provided on any side of the bonding pin group 110 in the first direction, or it can be provided on both sides of the bonding pin group 110 in the first direction. The position of the second ground electrode 52 in Figure 12 is only one example. As can be seen from Figure 12, in the multiple bonding pin groups 110, along the first direction X, the second ground electrode 52 of the two outermost bonding pin groups 110 is located on one side of the bonding pin group 110, and the second ground electrode 52 is located on the side adjacent to the shielding connection portion 43; except for the two outermost bonding pin groups 110, the other bonding pin groups 110 are provided with second ground electrodes 52 on both sides in the first direction X.

[0175] It should be noted that the above-mentioned second grounding electrode 52 is connected to the corresponding shielding connection part 43, which can conduct the static electricity adsorbed by the shielding connection part 43 through the second grounding electrode 52, so as to realize that the static electricity can be released along the shortest path, thereby improving the static electricity release efficiency.

[0176] In some embodiments, referring to FIG12, two second ground electrodes 52 are provided between two adjacent bonding pin groups 110, one of the second ground electrodes 52 is disposed near one of the bonding pin groups 110, and the other second ground electrode 52 is disposed near the other bonding pin group 110; the shielding connection portion 43 is connected to the two second ground electrodes 52 at both ends in the first direction X.

[0177] For example, referring to FIG12, two second ground electrodes 52 are provided between two adjacent bonding pin groups 110, and each second ground electrode 52 overlaps with the bonding pin group 110 adjacent to it.

[0178] It should be noted that the shielding connection part 43 is connected to two second grounding electrodes 52 at both ends in the first direction X. In other words, during the process of the shielding connection part 43 adsorbing static electricity, the second grounding electrodes 52 can quickly discharge the static electricity of the shielding connection part 43 near the target routing segment 31 of the multiple fan-out lines 3, so as to avoid the accumulation of static electricity above the target routing segment 31 of the multiple fan-out lines 3 and improve the electrostatic protection capability.

[0179] In some embodiments, referring to FIG11A, the bonding pin group 110 includes a ground pin 112; a second ground electrode 52 is located on the side of the ground pin 112 away from the substrate 1, and the second ground electrode 52 and the ground pin 112 overlap in the thickness direction of the substrate 1; the second ground electrode 52 is connected to the ground pin 112.

[0180] For example, continuing to refer to FIG11A, the second ground electrode 52 and the ground pin 112 overlap in the thickness direction of the substrate 1, that is, the ground pin 112 is also located on both sides of the bonding pin group 110 in the first direction X.

[0181] For example, referring to FIG2, the bonding pin group 110 is provided with a plurality of connection holes 1101. The bonding pin group 110 is bonded to the flip-chip thin film 300 through the plurality of connection holes 1101. As an example, the bonding pin group 110 is located in the gate conductive layer 101, and the plurality of connection holes 1101 penetrate the passivation layer 104 and the gate dielectric layer 102.

[0182] In some embodiments, referring to FIG11B, the ground pin 112 is located in the gate conductive layer 101, and the second ground electrode 52 is located in the source-drain conductive layer 103; the transparent conductive layer 105 includes a second transition electrode 1052, which is disposed on the side of the second ground electrode 52 away from the substrate 1; the second transition electrode 1052 is connected to the second ground electrode 52 and the ground pin 112 through a third via G3 that penetrates the passivation layer 104, the second ground electrode 52 and the gate dielectric layer 102.

[0183] For example, referring to FIG11B in conjunction with FIG11A, the second transition electrode 1052 is connected to the ground pin 112 through the third via G3 that penetrates the passivation layer 104, the second ground electrode 52 and the gate dielectric layer 102. Due to the setting of the third via G3, the side of the second ground electrode 52 is exposed and is electrically connected to the second transition electrode 1052 on the side wall of the third via G3. The connection between the second ground electrode 52 and the ground pin 112 is further realized through the second transition electrode 1052.

[0184] The following describes the specific connection between the electrostatic protection structure 4 and the first grounding electrode 51 and the second grounding electrode 52 when the structure is located in the transparent conductive layer 105.

[0185] In some embodiments, the first ground electrode 51 is located on the gate conductive layer 101, and the electrostatic discharge (ESD) protection structure 4 is located on the transparent conductive layer 105. In this case, the first transfer electrode 1051 located on the transparent conductive layer 105 can be directly connected to the connection line 41 of the ESD protection structure 4 located on the transparent conductive layer 105. That is, the connection line of the ESD protection structure 4 can be connected to the first ground electrode 51 through the first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104 via the first transfer electrode 1051. The connection between the ESD protection structure 4 and the first ground electrode 51 can be achieved without setting a second via G2, which can simplify the process to a certain extent. Alternatively, the connection line located on the ESD protection structure 4 can be directly connected to the first ground electrode 51 through the first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104. In this case, the connection with the first ground electrode 51 can be achieved without setting a first transfer electrode 1051.

[0186] In other embodiments, the second ground electrode 52 is located in the source / drain conductive layer 103, and the electrostatic discharge protection structure 4 is located in the transparent conductive layer 105. In this case, the shielding connection portion 43 included in the electrostatic discharge protection structure 4 is also located in the transparent conductive layer 105. Based on this, the second transfer electrode 1052 located in the transparent conductive layer 105 can be directly connected to the shielding connection portion 43 of the electrostatic discharge protection structure 4. That is, the shielding connection portion 43 of the electrostatic discharge protection structure 4 can be connected to the second ground electrode 52 through the third via G3 of the second transfer electrode 1052 penetrating the gate dielectric layer 102 and the passivation layer 104.

[0187] In some embodiments, the second grounding electrode 52 can be located in the same layer as the electrostatic protection structure 4, and the second grounding electrode 51 and the electrostatic protection structure 4 can both be located in the transparent conductive layer 105. In this case, the shielding connection portion 43 included in the electrostatic protection structure 4 is also located in the transparent conductive layer 105. In this case, the second grounding electrode 52 located in the transparent conductive layer 105 can directly contact and connect with the shielding connection portion 43 of the electrostatic protection structure 4. That is, when the second grounding electrode 52 can be located in the same layer as the electrostatic protection structure 4, the second transfer electrode 1052 located in the transparent conductive layer 105 as described above does not need to be provided, thus simplifying the process. It should be noted that "same layer" here refers to the same material being formed using the same patterning process.

[0188] For example, when the second ground electrode 52 and the electrostatic discharge protection structure 4 are both located in the transparent conductive layer 105, and the ground pin 112 is located in the gate conductive layer 101, the second ground electrode 52 can be connected to the ground pin 112 through a via penetrating the passivation layer 104 and the gate dielectric layer 102. With this configuration, the second ground electrode 52 and the ground pin 112 can directly contact each other without needing to be connected via the second adapter electrode 1052. Furthermore, compared to the case where the second ground electrode 52 is located in the source / drain conductive layer 103, the contact area between the second ground electrode 52 and the ground pin 112 is increased.

[0189] The following describes the specific connection between the electrostatic protection structure 4, with part of it located in the source / drain conductive layer 103 and part of it located in the transparent conductive layer 105, and the first grounding electrode 51 and the second grounding electrode 52.

[0190] In some embodiments, the shielding portion 42 and the connecting line 41 in the electrostatic discharge (ESD) protection structure 4 are located on the transparent conductive layer 105, and the shielding connection portion 43 is located on the source / drain conductive layer 103. The shielding connection portion 43 can be electrically connected to the connecting line 41 through a via penetrating the passivation layer 104. In this case, the specific connection between the connecting line 41 of the ESD protection structure 4 and the first grounding electrode 51 is described above in the description of the ESD protection structure 4 located on the transparent conductive layer 105. The specific connection between the shielding connection portion 43 of the ESD protection structure 4 and the second grounding electrode 52 is described above in the description of the ESD protection structure 4 located on the source / drain conductive layer 103, and will not be repeated here.

[0191] In other embodiments, the shielding portion 42 and the connecting line 41 in the electrostatic discharge (ESD) protection structure 4 are located in the source / drain conductive layer 103, and the shielding connection portion 43 is located in the transparent conductive layer 105. The shielding connection portion 43 can be electrically connected to the connecting line 41 through a via penetrating the passivation layer 104. In this case, the specific connection between the connecting line 41 of the ESD protection structure 4 and the first ground electrode 51 is as described above regarding the ESD protection structure 4 located in the source / drain conductive layer 103. The specific connection between the shielding connection portion 43 of the ESD protection structure 4 and the second ground electrode 52 is as described above regarding the ESD protection structure 4 located in the transparent conductive layer 105, and will not be repeated here.

[0192] In some embodiments of this disclosure, the grounding structure 5 may include a first grounding electrode 51 and a second grounding electrode 52, which may be provided simultaneously or only one of the first grounding electrode 51 and the second grounding electrode 52 may be provided, as long as the electrostatic protection structure 4 and the grounding structure 5 can be electrically connected.

[0193] Some embodiments of this disclosure provide a display panel 100, as shown in FIG2. The display panel 100 includes an array substrate 10 and an opposing substrate 20 provided in any of the above embodiments. Therefore, the display panel 100 provided by this invention has all the beneficial effects of the array substrate 10 provided in any of the above embodiments, which will not be elaborated here.

[0194] In some embodiments, as shown in FIG2, the opposing substrate 20 is recessed within the array substrate 10 on both the left and right sides of the display panel 100. In other possible embodiments, the edges of the opposing substrate 20 and the array substrate 10 may be flush on both the left and right sides of the display panel 100, or the array substrate 10 may be recessed within the opposing substrate 20. This application embodiment does not limit this.

[0195] In some embodiments, referring to FIG3, the display panel further includes an adhesive structure 50. The adhesive structure 50 is located between the array substrate 10 and the opposing substrate 20. At least a portion of the orthographic projection of the adhesive structure 50 onto the substrate 1 is located in the fan-out region BB, and the orthographic projection of the adhesive structure 50 onto the substrate 1 overlaps with the orthographic projection of the opposing substrate 20 onto the substrate 1. Exemplarily, the orthographic projection of the adhesive structure 50 onto the substrate 1 is located on one side of the orthographic projection of the sealant onto the substrate 1. The adhesive structure 50 can protect the fan-out lines 3 located in the fan-out region BB. Optionally, the material of the adhesive structure 50 is a UV-curable adhesive.

[0196] In some embodiments, referring to FIG3, the display panel 100 further includes an active layer (not shown) disposed between the gate dielectric layer 102 and the source / drain conductive layer 103. The active layer includes an active pattern, and the active pattern is made of silicon. Exemplarily, the gate conductive layer 101 includes a gate pattern, and the source / drain conductive layer 103 includes a source / drain pattern. The gate pattern and the source / drain pattern are made of metallic materials, such as single metal materials like aluminum, copper, molybdenum, chromium, and titanium, or alloys.

[0197] For example, the active layer material includes any one of cryogenic polycrystalline silicon, indium gallium zinc oxide, or cryogenic polycrystalline oxide.

[0198] It should be noted that the above materials are merely examples and this disclosure does not impose any limitations. Furthermore, Figure 3 illustrates an array substrate with a bottom-gate thin-film transistor (TFT) as an example; in other embodiments, the array substrate may also employ a top-gate TFT.

[0199] In some embodiments, the display panel 100 further includes a pixel electrode pattern and a common electrode pattern. The pixel electrode pattern may be located on the side of the common electrode pattern away from the substrate 1, or the pixel electrode pattern and the common electrode pattern may be located on the same layer. For example, the pixel electrode pattern and the common electrode pattern may both be located on the transparent conductive layer 105. Alternatively, the pixel electrode pattern and the common electrode pattern may both be located on the array substrate of the display panel. Alternatively, the pixel electrode pattern may be located on the opposing substrate of the display panel 100, and the common electrode pattern may be located on the opposing substrate 20 of the display panel 100. In the embodiments of this application, the pixel electrode pattern and the common electrode pattern are both located on the array substrate 10 of the display panel 100.

[0200] For example, the materials of the pixel electrode pattern and the common electrode pattern are transparent conductive materials such as indium tin oxide (ITO), which can reduce the impact on light emission.

[0201] Some embodiments of this disclosure provide a display device 1000, as shown in FIG13. This display device may be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), in-vehicle computer, wearable display device, etc. This disclosure does not impose any special limitations on the specific form of the above-described display device. As shown in FIG13, the display device 1000 includes the display panel 100 provided in any of the above embodiments, and the display panel 100 includes a display side 100a and a non-display side 100b. Therefore, the display device 1000 provided by this invention has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated upon here.

[0202] As exemplarily shown in FIG13, the display device 1000 in this embodiment of the present disclosure is exemplified as a liquid crystal display device. Referring to FIG13, in some embodiments, the main structure of the liquid crystal display device 1000 includes a frame 500, a cover plate 600, a display panel 100, and other electronic components.

[0203] The frame 500 surrounds an accommodating space, in which the display panel 100 and other electronic components are housed, and the cover plate 600 is located on the open side of the frame 500.

[0204] For example, referring to FIG13, the display panel 100 includes a liquid crystal layer 30 between an array substrate 10 and an opposing substrate 20. The array substrate 10 and the opposing substrate 20 can be bonded together by an adhesive 40, thereby confining the liquid crystal layer 30 within the area enclosed by the adhesive 40.

[0205] In some embodiments, referring to FIG2, the display device 1000 includes a driving circuit board 200, the driving circuit board 200 includes a ground terminal 201, the ground terminal 201 is electrically connected to the ground pin 112 to realize the connection between the grounding structure 5 and the ground terminal 201, so that after static electricity enters the display panel from the outside of the display panel and reaches the electrostatic protection structure 4, it can be transmitted to the ground terminal 201 in sequence through the electrostatic protection structure 4, the grounding structure 5, and the ground pin 112 to realize grounding.

[0206] It should be noted that, since the ground pin 112 is located in the gate conductive layer 101, for example, the ground pin 112 can be electrically connected to the flip-chip film 300 through the passivation layer 104 and the gate dielectric layer 102, and the flip-chip film 300 is electrically connected to the driving circuit board 200. In other words, the ground pin 112 can be connected to the ground terminal 201 in the driving circuit board 200 through the flip-chip film 300.

[0207] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0208] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising a display area and a fan-out area located on one side of the display area, the array substrate comprising: Substrate; Multiple data lines and multiple fan-out lines are disposed on the substrate, the multiple fan-out lines are located in the fan-out area, and each fan-out line is connected to at least one data line; An electrostatic discharge (ESD) protection structure and a grounding structure are disposed in the fan-out area. The ESD protection structure is located on the side of the multiple fan-out lines away from the substrate, and the ESD protection structure is electrically connected to the grounding structure. The fan-out line includes target trace segments, and the multiple target trace segments of the multiple fan-out lines are arranged at intervals along a first direction, which is parallel to the boundary line between the fan-out area and the display area; in the thickness direction of the substrate, the electrostatic protection structure covers the multiple target trace segments of the multiple fan-out lines.

2. The array substrate according to claim 1, wherein, The grounding structure includes a first grounding electrode, which is disposed on at least one side of the multiple fan-out lines on opposite sides in the first direction; The electrostatic protection structure includes a connecting wire and at least one shielding part, the connecting wire extending along the first direction and connected to the first grounding electrode; In the thickness direction of the substrate, each of the shielding portions covers at least one target trace segment of at least one of the fan-out lines.

3. The array substrate according to claim 2, wherein, The electrostatic protection structure includes a plurality of shielding parts, which are arranged along the first direction, and each shielding part covers a target routing segment of one fan-out line. The connecting line is located on one side of the plurality of shielding portions in a second direction, which is perpendicular to the first direction.

4. The array substrate according to claim 3, wherein, The shielding portion includes a first sub-part and a second sub-part connected to each other, wherein the width of the first sub-part is greater than the width of the second sub-part; The width of the first sub-part or the second sub-part is the dimension of the first sub-part or the second sub-part in the width direction of the shielding part.

5. The array substrate according to claim 4, wherein, The shielding portion includes two second sub-parts, and the first sub-part is connected between the two second sub-parts.

6. The array substrate according to claim 5, wherein, The two second sub-parts have different dimensions in the length direction.

7. The array substrate according to claim 5, wherein, The midpoint of the first sub-part in the length direction of the shielding part coincides with the midpoint of the shielding part in the length direction.

8. The array substrate according to any one of claims 4 to 7, wherein, The fan-out line includes a first sub-fan-out line and a second sub-fan-out line connected together. The first sub-fan-out line is closer to the display area than the second sub-fan-out line. The second sub-fan-out line extends along the second direction. The extension direction of the first sub-fan-out line intersects the extension direction of the second sub-fan-out line. The distances from the intersection of the first and second sub-fan lines of at least two of the said fan lines to the connecting line are not equal; The connecting line is located on the side of the plurality of shielding parts near the display area. The distance between the first sub-part of the shielding part and the connecting line is positively correlated with the distance between the intersection of the first sub-fan line and the second sub-fan line of the fan line corresponding to the shielding part and the connecting line.

9. The array substrate according to claim 8, wherein, The difference between the width of the first sub-part and the width of the second sub-part ranges from 3μm to 6μm.

10. The array substrate according to claim 3, wherein, The width of the connecting line is equal to the width of the shielding part.

11. The array substrate according to claim 2, wherein, The electrostatic protection structure includes a plurality of shielding parts, which are arranged along the first direction, and each shielding part covers a target routing segment of one fan-out line. The connecting line is arranged to intersect with the plurality of shielding parts, and the two ends of each shielding part are respectively located on both sides of the connecting line in a second direction, the second direction being perpendicular to the first direction.

12. The array substrate according to claim 11, wherein, The shielding portion includes a first portion and a second portion located on both sides of the connecting line in the second direction, and the first portion and the second portion are of equal length. The length of the first part or the second part is the dimension of the first part or the second part in the length direction of the shield.

13. The array substrate according to claim 11 or 12, wherein, The width of the connecting line is greater than the width of the shielding part.

14. The array substrate according to any one of claims 3 to 13, wherein, The width of the shielding part is greater than or equal to the width of the target routing segment of the fan-out line.

15. The array substrate according to claim 2, wherein, The electrostatic protection structure includes a shielding part that extends along the first direction and covers at least two target trace segments of at least two fan-out lines. The connecting line is located on one side of the shielding part in a second direction, which is perpendicular to the first direction.

16. The array substrate according to any one of claims 2 to 15, wherein, The shielding part has a dimension greater than or equal to 400 μm in the second direction, which is perpendicular to the first direction.

17. The array substrate according to any one of claims 2 to 16, wherein, The array substrate further includes a gate conductive layer, a source / drain conductive layer, and a transparent conductive layer that are sequentially stacked along a direction away from the substrate; The first grounding electrode is located in the gate conductive layer, and the electrostatic protection structure is located in the source / drain conductive layer and / or the transparent conductive layer.

18. The array substrate according to claim 17, wherein, The array substrate further includes a gate dielectric layer located between the gate conductive layer and the source / drain conductive layer, and a passivation layer located between the source / drain conductive layer and the transparent conductive layer; The transparent conductive layer includes a first transition electrode, which is disposed on at least one of the opposite sides of the plurality of fan-out lines in the first direction; The electrostatic protection structure is located in the source and drain conductive layer; The first transition electrode is connected to the first ground electrode through a first via penetrating the gate dielectric layer and the passivation layer, and the first transition electrode is connected to the connection line of the electrostatic protection structure through a second via penetrating the passivation layer.

19. The array substrate according to claim 17 or 18, wherein, The multiple fan-out lines are divided into multiple fan-out line groups, and each fan-out line group includes at least one fan-out line. The electrostatic protection structure also includes a shielded connection part disposed between two adjacent fan-out line groups, and the shielded connection part is connected to the connecting line.

20. The array substrate according to claim 19, wherein, The shielding connection is located in the source and drain conductive layer, and the shielding connection has multiple hollow holes that penetrate the shielding connection.

21. The array substrate according to claim 20, wherein, The plurality of perforations also penetrate the gate dielectric layer and the passivation layer.

22. The array substrate according to any one of claims 19 to 21, wherein the dimension of the shielding connection portion in the second direction is greater than the length of the shielding portion, and the second direction is perpendicular to the first direction.

23. The array substrate according to any one of claims 19 to 22, wherein, The array substrate further includes multiple bonding pin groups, each bonding pin group including at least one bonding pin, and each bonding pin being connected to a fan-out line; The grounding structure includes a second grounding electrode disposed on at least one side of the bonding pin group in the first direction, and the second grounding electrode is connected to the shielding connection portion.

24. The array substrate according to claim 23, wherein, Two second ground electrodes are provided between two adjacent bonding pin groups, one of which is located close to one of the bonding pin groups and the other is located close to the other bonding pin group; The shielded connection is connected to two second grounding electrodes at both ends in the first direction.

25. The array substrate according to claim 23 or 24, wherein, The bonding pin group includes a ground pin; The second ground electrode is located on the side of the ground pin away from the substrate, and the second ground electrode and the ground pin overlap in the thickness direction of the substrate; The second grounding electrode is connected to the grounding pin.

26. The array substrate according to claim 25, wherein, The grounding pin is located on the gate conductive layer, and the second grounding electrode is located on the source-drain conductive layer; The transparent conductive layer includes a second transfer electrode, which is disposed on the side of the second ground electrode away from the substrate; The second transfer electrode is connected to the second ground electrode and the ground pin through a third via that passes through the passivation layer, the second ground electrode and the gate dielectric layer.

27. A display panel, comprising: The array substrate as described in any one of claims 1 to 26; Opposite substrate disposed opposite to the array substrate; The opposing substrate includes a first boundary, which is located in the region where multiple target trace segments of multiple fan-out lines of the array substrate are located, and the first boundary intersects with the multiple target trace segments.

28. The display panel according to claim 27, wherein, The first boundary of the opposing substrate passes through the midpoint of the multiple target trace segments of the multiple fan-out lines in the length direction.

29. A display device, comprising: The display panel as described in claim 27 or 28; The driver circuit board is connected to the display panel.

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