Photovoltaic module, photovoltaic system, and solar cell and preparation method therefor

Abstract

The present application discloses a solar cell. The solar cell comprises a bottom cell and a top cell which are stacked; the bottom cell is provided with a substrate; a confined space recessed into the substrate is formed in the side of the substrate close to the top cell; and at least the side surface of the top cell close to the bottom cell is located in the confined space. The present application further provides a preparation method for the solar cell, a photovoltaic module, and a photovoltaic system. In the solar cell provided by the present application, a confined space is formed in the side of the substrate close to a top cell, and at least some areas of the top cell are stacked in the confined space, so that the confined space can play a role in confined growth of a light absorption layer in the top cell, thereby reducing the requirements of the light absorption layer on the substrate roughness.

Description

A photovoltaic module, a photovoltaic system, a solar cell, and a method for manufacturing the same.

[0001] This application claims priority to Chinese Patent Application No. 2024105088597, filed on April 25, 2024, entitled "A photovoltaic module, a photovoltaic system, a solar cell and a method for preparing the same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of photovoltaics, specifically to a photovoltaic module, a photovoltaic system, a solar cell, and a method for preparing the same. Background Technology

[0003] Currently, the efficiency of crystalline silicon solar cells is approaching its limit, and tandem solar cells are an effective way to improve photovoltaic cell efficiency. Current crystalline silicon tandem solar cells mainly include perovskite / crystalline silicon tandem solar cells, III-V group crystalline silicon tandem solar cells, and organic / crystalline silicon tandem solar cells. However, in perovskite and organic solar cells fabricated using solution methods, the size difference between the crystalline silicon textured pyramid structure and the thickness of the tandem structure is significant. This results in uneven film layer uniformity and poor coverage on the surface of the crystalline silicon textured pyramid structure, leading to poor cell performance and low efficiency. If a planar structure is used, insufficient friction during solution-based fabrication of the upper layer will result in poor film uniformity and low coverage. Specifically: The pyramid structure has significant height variations, ranging from micrometers (around 5 micrometers), with face angles of 53-55°. The perovskite thin film is micro-nano in size. During coating, due to the pyramid's slope angle and the ductility of the solution in crystalline silicon, the coating material tends to deposit thicker at the base of the pyramid, while the film layer at the tip is very thin or even discontinuous, affecting surface coverage (the tip may not even be fully covered). If the surface is too smooth, the slurry cannot effectively cover the surface, and the slurry's surface tension will cause it to shrink, leading to agglomeration and clumping.

[0004] Application content

[0005] To address the problems existing in the prior art, this application provides a solar cell in which a defined space is provided on the side of the substrate near the top cell. This defined space can confine the growth of the light-absorbing layer of the top cell, reducing the requirements for substrate roughness.

[0006] Specifically, this application relates to the following aspects:

[0007] This application provides a solar cell including a bottom cell and a top cell stacked together. The bottom cell has a substrate and a defined space recessed into the substrate on the side of the substrate near the top cell. In the top cell, at least one surface near the bottom cell is located within the defined space.

[0008] In some embodiments, the depth of the defined space is 200 nm-1 μm, and / or,

[0009] Within the defined space, the surface roughness of the substrate is less than or equal to one-third of the depth of the defined space.

[0010] In some embodiments, the defined space has a bottom surface, and the edge region of the substrate has an edge-limiting outer wall disposed around the edge of the bottom surface.

[0011] In some embodiments, the defined space has a bottom surface, and the middle region of the base is provided with a spaced-out limiting wall protruding from the bottom surface.

[0012] In some embodiments, the thickness of the outer wall of the edge confinement is less than or equal to 50 μm, preferably 15 μm-30 μm, and the thickness of the spacer confinement wall is less than or equal to 50 μm, preferably 15 μm-30 μm.

[0013] In some embodiments, the bottom battery further includes a second passivation layer located within the defined space, the defined space having a bottom surface and sidewalls, the second passivation layer including a middle portion and side portions located at both ends of the middle portion, the side portions being stacked on the inner sidewalls of the defined space.

[0014] In some embodiments, the substrate is a silicon substrate, and the second passivation layer is stacked adjacent to the silicon substrate; and / or

[0015] The bottom cell further includes a second doped layer located on the side surface of the second passivation layer away from the silicon substrate.

[0016] In some embodiments, an intermediate layer is stacked within the defined space, the intermediate layer being located between the bottom battery and the top battery.

[0017] The intermediate layer includes a TCO layer and first dielectric material particles.

[0018] The first dielectric material particles are dispersed within the TCO layer, or

[0019] The first dielectric material particles are dispersed on the surface of the TCO layer near the top cell.

[0020] In some embodiments, the projected area of ​​all the first dielectric material particles on the TCO layer is less than or equal to 20% of the surface area of ​​the TCO layer, and the projection direction is the stacking direction of the bottom and top cells; and / or

[0021] The average particle size of the first dielectric material particles is 5-30 nm, preferably 10-15 nm; and / or

[0022] The material of the first dielectric material particle can be silicon dioxide, aluminum oxide, or silicon nitride.

[0023] In some embodiments, the top battery further includes an antireflective layer that at least partially covers the outer wall of the edge confinement of the defined space.

[0024] In some embodiments, the top battery further includes an antireflective layer located within the defined space.

[0025] In some embodiments, the antireflective layer has second dielectric material particles on the surface facing away from or near the bottom battery; and / or

[0026] The projected area of ​​all second dielectric material particles on the antireflection layer is less than or equal to 40% of the surface area of ​​the antireflection layer, and the projection direction is the stacking direction of the bottom and top cells; and / or

[0027] The average particle size of the second dielectric material particles is 5-30 nm, preferably 10-15 nm; and / or

[0028] The material of the second dielectric material particle can be silicon dioxide, aluminum oxide, or silicon nitride.

[0029] This application also provides a method for preparing a solar cell, comprising the following steps:

[0030] A bottom battery is prepared, wherein the bottom battery includes a substrate, and a defined space is formed in the substrate that is recessed into the interior of the substrate;

[0031] Prepare a top cell such that at least one surface of the top cell near the bottom cell lies within the space defined by the space.

[0032] In some embodiments, the defined space is formed by laser etching or mask-plus-solution etching.

[0033] In some implementations, an intermediate layer is formed within the defined space prior to the formation of the top cell;

[0034] The method for preparing the intermediate layer includes the following steps:

[0035] Form a transparent conductive layer;

[0036] The raw material of the first dielectric material particles is sprayed onto the transparent conductive layer by spraying, thereby forming an intermediate layer containing the first dielectric material particles.

[0037] In some implementations, an intermediate layer is formed within the defined space prior to the formation of the top cell;

[0038] The method for preparing the intermediate layer includes the following steps:

[0039] Forming a transparent conductive layer;

[0040] The raw material of the first dielectric material particles is sprayed onto the transparent conductive layer by spraying, thereby forming the first dielectric material particles;

[0041] A second transparent conductive layer is formed, and the second transparent conductive layer covers the first dielectric material particles.

[0042] In some embodiments, the prepared solar cell is the aforementioned solar cell.

[0043] This application provides a photovoltaic module, which includes a solar cell as described above; or a solar cell prepared by the aforementioned method.

[0044] This application provides a photovoltaic system, which includes the aforementioned photovoltaic modules.

[0045] The solar cell provided in this application has a space defined inside the substrate on the side of the substrate near the top cell, and at least a portion of the top cell is stacked within the defined space. Therefore, the defined space can play a role in confining the growth of the light absorption layer of the top cell, thereby reducing its requirement for substrate roughness.

[0046] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 is a partial structural diagram of the solar cell provided in this application.

[0049] Figure 2 is a structural diagram of the solar cell provided in this application.

[0050] Figure 3 is a partial structural diagram of the solar cell provided in this application.

[0051] Figure 4 is a structural diagram of the solar cell provided in this application.

[0052] Figure 5 is a structural diagram of the solar cell provided in this application.

[0053] Explanation of reference numerals in the attached figures: 1-Antireflection layer, 2-Second carrier transport layer, 3-Perovskite absorber layer, 4-First carrier transport layer, 5-Intermediate layer, 6-Second doped layer, 7-Second passivation layer, 8-Silicon substrate, 9-First passivation layer, 10-First doped layer, 11-Second dielectric material particle, 12-Electrode, 13-First dielectric material particle, 14-Edge confinement outer wall, 15-Spacer confinement wall, 16-Backside TCO layer, 17-Heavily doped crystalline silicon region, 18-Backside antireflection layer, 19-Silicon oxide passivation layer. Specific Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] This application provides a solar cell including a bottom cell and a top cell stacked together. The bottom cell has a substrate and a defined space recessed into the substrate on the side of the substrate near the top cell. In the top cell, at least one surface near the bottom cell is located within the defined space.

[0056] The solar cell provided in this application has a defined space on the side of the substrate near the top cell, and at least a portion of the top cell is stacked within the defined space. Therefore, the defined space can play a role in confining the growth of the light absorption layer of the top cell, thereby reducing its requirements for substrate roughness.

[0057] In some implementations, the substrate has a defined space on the side near the top cell.

[0058] In some embodiments, the side of the substrate near the top cell has multiple defined spaces arranged in an array. For example, the number of defined spaces can be 2, 3, 4, 5, or more.

[0059] The number of spaces can be determined based on actual needs.

[0060] The surface of the substrate near the top cell includes an edge region and a central region. The edge region surrounds the central region and is flush with or lower than the central region.

[0061] In some embodiments, the defined space may be a groove structure; the defined space has a bottom surface, and the edge region of the base has an edge-limiting outer wall 14 disposed around the edge of the bottom surface.

[0062] In some embodiments, a spacer wall 15 protruding from the bottom surface is provided in the middle region of the substrate.

[0063] As shown in Figure 1, the substrate has an edge-confining outer wall 14 surrounding the edge of the substrate on the side surface near the top cell. Multiple crisscrossing spaced-spaced confinement walls 15 are also present on the substrate surface. The side surface of the substrate near the top cell, the edge-confining outer wall 14, and the spaced-spaced confinement walls 15 constitute multiple arrayed confined spaces. Specifically, the edge-confining outer wall 14 is perpendicular to the horizontal surface of the substrate and extends towards one side of the top cell, within which the light-absorbing layer of the top cell is located. With this design, when fabricating the top cell, the confined space can confine the liquid raw material of the light-absorbing layer, improving the quality of the light-absorbing layer and reducing non-uniformity caused by large-area coating. Furthermore, the arrayed structure can reduce reflection, enhancing the cell's light absorption.

[0064] Specifically, the thickness of the outer wall 14 of the edge confinement is less than or equal to 50 μm, preferably 15-30 μm, and can be, for example, 50 μm, 49 μm, 48 μm, 47 μm, 46 μm, 45 μm, 44 μm, 43 μm, 42 μm, 41 μm, 40 μm, 39 μm, 38 μm, 37 μm, 36 μm, 35 μm, 34 μm, 33 μm, 32 μm, 31 μm, 30 μm, 29 μm, 28 μm, 27 μm, 26 μm, 25 μm, 24 μm, 23 μm, 22 μm, 21 μm, 20 μm, 19 μm, 18 μm, 17 μm, 16 μm, 15 μm, 14 μm, 13 μm, 12 μm, 11 μm, 10 μm, etc.

[0065] In some embodiments, the thickness of the edge-limiting outer wall 14 is less than or equal to 40 μm.

[0066] In some embodiments, the thickness of the edge-confined outer wall 14 is less than or equal to 30 μm.

[0067] In some embodiments, the thickness of the edge-limiting outer wall 14 is less than or equal to 20 μm.

[0068] In some embodiments, the thickness of the edge-limiting outer wall 14 is less than or equal to 15 μm.

[0069] In some embodiments, the thickness of the edge-limiting outer wall 14 is less than or equal to 10 μm.

[0070] In some embodiments, the thickness of the outer wall 14 of the edge confinement is greater than or equal to 1 μm.

[0071] In some embodiments, the thickness of the outer wall 14 of the edge confinement is greater than or equal to 1 and less than or equal to 50 μm.

[0072] Specifically, the thickness of the spacer wall 15 is less than or equal to 50 μm, preferably 15-30 μm, and can be, for example, 50 μm, 49 μm, 48 μm, 47 μm, 46 μm, 45 μm, 44 μm, 43 μm, 42 μm, 41 μm, 40 μm, 39 μm, 38 μm, 37 μm, 36 μm, 35 μm, 34 μm, 33 μm, 32 μm, 31 μm, 30 μm, 29 μm, 28 μm, 27 μm, 26 μm, 25 μm, 24 μm, 23 μm, 22 μm, 21 μm, 20 μm, 19 μm, 18 μm, 17 μm, 16 μm, 15 μm, 14 μm, 13 μm, 12 μm, 11 μm, 10 μm, etc.

[0073] In some embodiments, the thickness of the spacer wall 15 is less than or equal to 40 μm.

[0074] In some embodiments, the thickness of the spacer wall 15 is less than or equal to 30 μm.

[0075] In some embodiments, the thickness of the spacer wall 15 is less than or equal to 20 μm.

[0076] In some embodiments, the thickness of the spacer wall 15 is less than or equal to 15 μm.

[0077] In some embodiments, the thickness of the spacer wall 15 is less than or equal to 10 μm.

[0078] In some embodiments, the thickness of the spacer wall 15 is greater than or equal to 1 μm.

[0079] In some embodiments, the thickness of the spacer wall 15 is greater than or equal to 1 and less than or equal to 50 μm.

[0080] In some embodiments, the thickness of the edge confinement outer wall 14 is equal to the thickness of the spacer confinement wall 15.

[0081] In some implementations, the height of the edge confinement outer wall 14 is equal to the height of the spacer confinement wall 15.

[0082] In this application, the bottom battery also includes a second passivation layer located within a defined space. The defined space has a bottom surface and sidewalls. The second passivation layer 7 includes a middle portion and side portions located at both ends of the middle portion. The side portions are stacked on the inner sidewalls of the defined space.

[0083] In some embodiments, the substrate is a silicon substrate 8, and a second passivation layer 7 is stacked adjacent to the surface of the silicon substrate 8 on the side near the top cell.

[0084] The second passivation layer 7 can passivate defects on the surface of the silicon substrate 8, thereby reducing charge recombination on the surface of the silicon substrate 8. In addition, the second passivation layer 7 can also prevent the silicon substrate 8 from contacting the second doped layer 6 and the top cell on one side of the second passivation layer 7, thus preventing a short circuit.

[0085] In this application, the length of the defined space is 1cm-5cm, preferably 1.5cm-3.5cm, and its width is 1cm-5cm, preferably 1.5cm-3.5cm.

[0086] The length of the defined space can be 1cm, 1.5cm, 2cm, 2.5cm, 3cm, 3.5cm, 4cm, 4.5cm, 5cm, etc., and its width can be 1cm, 1.5cm, 2cm, 2.5cm, 3cm, 3.5cm, 4cm, 4.5cm, 5cm, etc.

[0087] If the size of the confined space is too small, it will result in excessively high grid line density, causing shading and affecting cell efficiency; if the size is too large, it will lead to a decrease in the quality of thin film fabrication in the top cell. If the thickness of the spacer confining wall 15 and the outer wall of the edge confining space 14 are too large, it will lead to a reduction in the area of ​​the top cell and a deterioration in the stacking effect.

[0088] In this application, an intermediate layer is stacked within a defined space. The intermediate layer includes a TCO layer and first dielectric material particles 13. The intermediate layer is located between the bottom cell and the top cell.

[0089] In some embodiments, the first dielectric material particles 13 are dispersed within the TCO layer.

[0090] In some embodiments, first dielectric material particles 13 are dispersed on the surface of the TCO layer near the top cell.

[0091] In some embodiments, the projected area of ​​all the first dielectric material particles 13 on the TCO layer accounts for less than or equal to 20% of the surface area of ​​the TCO layer, for example, it can be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, etc. The projection direction is the stacking direction of the bottom cell and the top cell.

[0092] In some embodiments, the projected area of ​​all the first dielectric material particles 13 on the TCO layer is less than or equal to 15% of the surface area of ​​the TCO layer.

[0093] In some embodiments, the projected area of ​​all the first dielectric material particles 13 on the TCO layer is less than or equal to 10% of the surface area of ​​the TCO layer.

[0094] In this paper, the percentage of the positive projection area of ​​all the first dielectric material particles 13 on the TCO layer can be detected by methods such as AFM and SEM.

[0095] In some embodiments, a second doped layer 6 is stacked between the intermediate layer and the second passivation layer 7. That is, the bottom cell includes a silicon substrate 8, a second passivation layer 7, and a second doped layer 6 stacked on one side.

[0096] In this application, the bottom cell can be a silicon-based cell, and the top cell can be a perovskite cell or an organic cell. The silicon-based cell can be PERC, TOPCon, HJT, or a hybrid cell structure modified from PERC, TOPCon, and HJT, etc.

[0097] In some embodiments, as shown in FIG2, when the bottom cell is an HJT, the bottom cell includes a back electrode (electrode 12), a back TCO layer 16, a first doped layer 10, a first passivation layer 9, a silicon substrate 8, a second passivation layer 7, and a second doped layer 6 stacked sequentially. The top cell includes a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and a front electrode (electrode 12) stacked sequentially. That is, from bottom to top, the solar cell includes an electrode 12, a back TCO layer 16, a first doped layer 10, a first passivation layer 9, a silicon substrate 8, a second passivation layer 7, a second doped layer 6, an intermediate layer, a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and an electrode 12 stacked sequentially. The silicon substrate 8 has multiple arrayed defined spaces on the side near the top cell. A second passivation layer 7 uniformly covers these defined spaces. The second passivation layer 7 includes a central portion and side portions located at both ends of the central portion. The central portion is located on the surface of the silicon substrate 8 opposite to the first passivation layer 9, and the side portions are located on the inner sidewalls of the defined spaces. A second doped layer 6 is located on the side surface of the central portion opposite to the silicon substrate 8. Multiple first dielectric material particles 13 are distributed within the central layer.

[0098] The silicon substrate 8 can be either a p-type doped silicon substrate 8 or an n-type doped silicon substrate 8.

[0099] The surface of the silicon substrate 8 near the top cell can be either smooth or rough.

[0100] The top of the confined space is flush with the second carrier transport layer.

[0101] The depth of the space is limited to 200nm-1μm, for example, it can be 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.

[0102] Within the defined space, the surface roughness of the substrate is less than or equal to one-third of the depth of the defined space. Specifically, the surface roughness of the silicon substrate 8 on the side closest to the top cell is less than or equal to one-third of the depth of the defined space. This design does not adversely affect the fabrication of the top cell and can also trap light. Excessive surface roughness will affect the fabrication of the upper thin films, especially the perovskite absorber layer and the organic absorber layer, resulting in reduced film quality and performance.

[0103] When the depth of the confined space is h, the surface roughness of the silicon substrate 8 can be 0, 0.01h, 0.02h, 0.03h, 0.04h, 0.05h, 0.06h, 0.07h, 0.08h, 0.09h, 0.1h, 0.11h, 0.12h, 0.13h, 0.14h, 0.15h, 0.16h, 0.17h, 0.18h, 0.19h, 0.2h, 0.21h, 0.22h, 0.23h, 0.24h, 0.25h, 0.26h, 0.27h, 0.28h, 0.29h, 0.3h, 0.31h, 0.32h, 0.33h, etc.

[0104] In this text, surface roughness refers to the distance between the lowest and highest points on the surface of the silicon substrate 8.

[0105] The surface roughness in this paper can be measured by electron microscopy of the groove interior using methods such as SEM and TEM, thus revealing its roughness.

[0106] The first doped layer 10 has the opposite doping type to the second doped layer 6.

[0107] When the first doped layer 10 is p-type doped and the second doped layer 6 is n-type doped.

[0108] When the first doped layer 10 is n-type doped and the second doped layer 6 is p-type doped.

[0109] Both the first doped layer 10 and the second doped layer 6 can be crystalline silicon doped layers, amorphous silicon doped layers, amorphous silicon carbide doped layers, crystalline silicon carbide doped layers, amorphous silicon oxide doped layers, or crystalline silicon oxide doped layers.

[0110] In some embodiments, the silicon substrate 8, the first passivation layer 9, the first doped layer 10, the second passivation layer 7, and the second doped layer 6 all have a textured surface.

[0111] The first passivation layer 9 is intrinsic hydrogenated amorphous silicon with a thickness of 1nm-20nm, for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm.

[0112] The second passivation layer 7 is intrinsic hydrogenated amorphous silicon with a thickness of 1nm-20nm, for example, it can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm.

[0113] The first passivation layer 9 and the second passivation layer 7 can be the same or different layers, for example, they can have different hydrogen content, thickness and process.

[0114] The thickness of the first doped layer 10 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm, 200nm, etc.

[0115] The thickness of the second doped layer 6 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm, 200nm, etc.

[0116] The TCO layer can be a transparent conductive film, specifically fluorine-doped tin oxide (FTO), indium tin oxide (ITO), or aluminum-doped zinc oxide (AZO), etc.; its thickness can be 1-20nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, or 20nm.

[0117] The back TCO layer 16 can be a transparent conductive film, specifically fluorine-doped tin oxide (FTO), indium tin oxide (ITO), or aluminum-doped zinc oxide (AZO), with a thickness of 30nm-120nm, for example, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, etc.

[0118] Electrode 12 can be made of gold, silver, copper, or other materials, but is not limited to these.

[0119] In some embodiments, as shown in FIG4, when the bottom cell is PERC, the bottom cell includes a back electrode (electrode 12), a first passivation layer 9, a silicon substrate 8, a second passivation layer 7, and a second doped layer 6 stacked sequentially. The silicon substrate 8 has multiple heavily doped crystalline silicon regions 17 on the side near the first passivation layer 9. The back electrode penetrates the first passivation layer 9 and connects to the heavily doped crystalline silicon regions 17. The top cell includes a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and a front electrode stacked sequentially. That is, from bottom to top, the solar cell includes an electrode, a first passivation layer 9, a silicon substrate 8, a second passivation layer 7, a second doped layer 6, an intermediate layer 5, a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and a front electrode (electrode 12) stacked sequentially. The top of the defined space is flush with the second carrier transport layer.

[0120] The first passivation layer 9 is a silicon nitride layer (SiN). x layer)

[0121] In some embodiments, the orthographic projection of the heavily doped crystalline silicon region 17 onto the first passivation layer 9 overlaps with the orthographic projection of the back electrode onto the first passivation layer 9.

[0122] The doping type of the heavily doped region is opposite to that in the first doped layer 10.

[0123] When the first doped layer 10 is p-type doped, the heavily doped crystalline silicon region 17 is n-type doped.

[0124] When the first doped layer 10 is n-type doped, the heavily doped crystalline silicon region 17 is p-type doped.

[0125] The descriptions of electrode 12, second passivation layer 7, second doped layer 6, intermediate layer 5, first carrier transport layer 4, light absorption layer, and second carrier transport layer 2 can be found in the description of the battery structure in Figure 2 above. The above structure is not limited to the PERC battery structure of this embodiment, and does not exclude conventional and other modified PERC battery structures. For example, the second passivation layer 7 may not be provided; instead, it may be provided on the second doped layer 6, and the second passivation layer 7 may have an opening that contacts the intermediate layer 5.

[0126] In some embodiments, as shown in FIG5, when the bottom cell is TOPCon, the bottom cell includes a back electrode (electrode 12), a back antireflection layer 18, a first doped layer 10, a silicon oxide passivation layer 19, a silicon substrate 8, a second passivation layer 7, and a second doped layer 6 stacked sequentially. The top cell includes a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and a front electrode (electrode 12) stacked sequentially. That is, from bottom to top, the solar cell includes an electrode 12, a back antireflection layer 18, a first doped layer 10, a silicon oxide passivation layer 19, a silicon substrate 8, a second passivation layer 7, a second doped layer 6, an intermediate layer 5, a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and an electrode 12 stacked sequentially.

[0127] The descriptions of electrode 12, second passivation layer 7, second doped layer 6, intermediate layer 5, first carrier transport layer 4, light absorption layer, and second carrier transport layer 2 can be found in the description of the battery structure in Figure 2 above. The above structure is not limited to the TOPCon battery structure of this embodiment, and does not exclude conventional and other modified TOPCon battery structures. For example, the second passivation layer 7 may not be provided; instead, it may be provided on the second doped layer 6, and the second passivation layer 7 may have an opening that contacts the intermediate layer 5.

[0128] In this application, the material of the first dielectric material particle 13 can be a dielectric material such as silicon dioxide, aluminum oxide, or silicon nitride, including but not limited to these.

[0129] For a two-terminal stacked cell, electron-hole recombination occurs at the interface between the second doped layer 6 and the first carrier transport layer 4. Therefore, longitudinal electron / hole transport should be maximized within the second doped layer 6 and the first carrier transport layer 4, while lateral carrier transport should be minimized. Lateral transport cannot effectively reach the interface, increasing ineffective carrier recombination and causing cell efficiency loss. The first dielectric material particles 13 can effectively block the second doped layer 6 and the first carrier transport layer 4 laterally, reducing the possibility of lateral carrier transport. Simultaneously, the first dielectric material particles 13 can increase the interface roughness to facilitate the fabrication of the light-absorbing layer in the top cell and also act as an anti-reflection agent, avoiding optical losses caused by the high reflectivity of the planar silicon substrate 8. In some embodiments, the presence of the first dielectric material particles 13 can form small protrusions on the surface of the first carrier transport layer 4 away from the bottom cell, creating an undulating microstructure, which is beneficial for the fabrication of the perovskite layer or organic absorber layer in the top cell.

[0130] When the bottom cell is a crystalline silicon cell, the refractive index of the first dielectric material particle 13 is less than that of crystalline silicon, and the difference in refractive index between the two can promote anti-reflection and enhanced absorption.

[0131] The average particle size of the first dielectric material particles 13 is 10-15 nm, for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, etc.

[0132] In this paper, the average particle size is the D90 particle size, which can be detected by methods such as AFM and SEM. The D90 particle size refers to the diameter of 90% of the particles in a sample volume that is less than or equal to this value.

[0133] If the size of the first dielectric material particle 13 is too large, the top cell and bottom cell will split, which is not conducive to charge extraction and transmission; if the size of the first dielectric material particle 13 is too small, the first dielectric material particle 13 will accumulate, resulting in increased contact resistance.

[0134] In this application, the top battery also includes an antireflection layer 1, which is stacked together with a second carrier transport layer 2.

[0135] In some embodiments, the surface of the antireflective layer 1 closest to the bottom battery is located within a defined space, while the surface of the antireflective layer 1 furthest from the bottom battery completely covers the defined space.

[0136] In some implementations, the antireflective layer 1 has its surface near the bottom cell completely covering the entire defined space.

[0137] In some implementations, the antireflective layer 1 is located within a defined space.

[0138] In some embodiments, the antireflective layer 1 has second dielectric material particles 11 on the side surface facing away from the bottom battery.

[0139] In some embodiments, as shown in FIG3, the antireflective layer 1 has second dielectric material particles 11 on the surface of the side near the bottom battery.

[0140] The material of the second dielectric material particle 11 can be a dielectric material such as silicon dioxide, aluminum oxide, or silicon nitride, including but not limited to these.

[0141] The projected area of ​​all second dielectric material particles 11 on the antireflection layer 1 accounts for less than or equal to 40% of the surface area of ​​the antireflection layer 1. For example, it can be 40%, 39%, 38%, 37%, 36%, 35%, 34%, 33%, 32%, 31%, 30%, 29%, 28%, 27%, 26%, 25%, 24%, 23%, 22%, 21%, 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, etc. The projection direction is the stacking direction of the bottom and top cells.

[0142] The average particle size of the second dielectric material particles 11 is 5-30 nm, preferably 10-15 nm, and can be, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm. This average particle size is D90, and its definition and detection method can be found in the foregoing description.

[0143] In this paper, the percentage of the positive projection area of ​​all the second dielectric material particles 11 on the antireflection layer 1 can be detected by methods such as AFM and SEM.

[0144] If the size of the second dielectric material particles 11 is too large, it will disrupt the contact between the antireflective layer 1 and the top cell, which is detrimental to the stability of the cell; if the size of the second dielectric material particles 11 is too small, the particles will easily accumulate, resulting in large particle clusters in the contact between the antireflective layer 1 and the top cell.

[0145] By setting the second dielectric material particles 11, the reflection of light on the battery can be reduced.

[0146] In this application, when the top cell is a perovskite cell, it includes a first carrier transport layer 4, a perovskite absorber layer 3, a second carrier transport layer 2, and an electrode 12 stacked sequentially. The surface of the first carrier transport layer 4 facing away from the perovskite absorber layer 3 is stacked with the functional layer.

[0147] The first carrier transport layer 4 can be either a hole transport layer or an electron transport layer, and the conductivity type of the first carrier transport layer 4 is opposite to that of the second carrier transport layer 2. When the first carrier transport layer 4 is a hole transport layer, it can be a molybdenum oxide layer, a [bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA) layer, a copper iodide layer, or a Spiro-OMeTAD (2,2',7,7'-Tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene) layer, a PEDOT layer, a PEDOT:PSS layer, a P3HT layer, a P3OHT layer, a P3ODDT layer, or a NiO layer. x The first layer is a CuSCN layer. The second carrier transport layer 2 is an electron transport layer, which can be a titanium oxide layer, a tin oxide layer, or a C layer. 60 Layer or C 60 -PCBM layer,

[0060] PCBM([6,6]-phenyl-C 61 butyric acid methyl ester, Chinese name [6,6]-phenyl-C 61 -Isomethyl butyrate) layer,

[0070] PCBM([6,6]-Phenyl-C 71 -butyric acid methyl ester, Chinese name is [6,6]-phenyl-C 71 - Isomethyl butyrate) layer, bis

[0060] PCBM(Bis(1-[3-(methoxycarbonyl)propyl]-1-phenyl)-[6,6]C 62 Layers such as

[0060] ICBA(1',1”,4',4”-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2”,3”][5,6]fullerene-C60) and others, including but not limited to these, as long as they can achieve the functions in this application.

[0148] When the first carrier transport layer 4 is an electron transport layer, it can be a titanium oxide layer, a tin oxide layer, or a C layer. 60 Layer or C 60 -PCBM layer,

[0060] PCBM([6,6]-phenyl-C 61 butyric acid methyl ester, Chinese name [6,6]-phenyl-C 61-Isomethyl butyrate) layer,

[0070] PCBM([6,6]-Phenyl-C 71 -butyric acid methyl ester, Chinese name is [6,6]-phenyl-C 71 - Isomethyl butyrate) layer, bis

[0060] PCBM(Bis(1-[3-(methoxycarbonyl)propyl]-1-phenyl)-[6,6]C 62 Layers such as

[0060] ICBA(1',1”,4',4”-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2”,3”][5,6]fullerene-C60) and ... The second carrier transport layer 2 is a hole transport layer, which can be a molybdenum oxide layer, a [bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA) layer, a copper iodide layer, or a Spiro-OMeTAD (2,2',7,7'-Tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene) layer, a PEDOT layer, a PEDOT:PSS layer, a P3HT layer, a P3OHT layer, a P3ODDT layer, or a NiO layer. x A layer or a CuSCN layer. This includes, but is not limited to, anything that achieves the functionality described in this application.

[0149] The thickness of the first carrier transport layer 4 is 10-15 nm, for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm.

[0150] The thickness of the second carrier transport layer 2 is 10-15 nm, for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm.

[0151] The perovskite absorber layer 3 can be an organic-inorganic hybrid halide perovskite layer, an all-inorganic halide perovskite layer, a lead-free perovskite layer, etc., including but not limited to these. Its thickness is 350nm-700nm, for example, it can be 350nm, 360nm, 370nm, 380nm, 390nm, 400nm, 410nm, 420nm, 430nm, 440nm, 450nm, 460nm, 470nm, 480nm, 490nm, 500nm, 600nm, 650nm or 700nm.

[0152] Electrode 12 can be made of one or more of the following materials: metallic materials such as Ag, Au, Cu, Al, Ni, C materials, and polymer conductive materials.

[0153] In this application, when the top cell is an organic cell, it includes a first carrier transport layer 4, a light absorption layer, a second carrier transport layer 2, and an electrode 12 stacked sequentially. The surface of the intermediate layer 5 facing away from the first carrier transport layer 4 is stacked together with the intermediate connecting layer.

[0154] The light-absorbing layer is made of organic materials, with a thickness ranging from 50nm to 500nm. Optional materials include P3HT, PCBM, PTB7, PM6, and Y7.

[0155] This application provides a method for preparing a solar cell, comprising the following steps:

[0156] Step 1: Prepare a bottom cell, which includes a substrate, and form a defined space recessed into the substrate.

[0157] Step 2: Prepare the top cell such that at least one side of the top cell's surface, near the bottom cell, is located within a defined space.

[0158] Taking HJT as the bottom battery as an example, the details are as follows:

[0159] Step one specifically includes the following steps:

[0160] Step 1.1 Silicon substrate treatment

[0161] A single-crystal silicon wafer (N-type or P-type) with a flat front side is used. The wafer is cleaned using the standard RCA (Radio Corporation of America) cleaning process, then repeatedly rinsed with deionized water and dried with nitrogen gas before use.

[0162] Step 1.2 Preparation of the confined space

[0163] The confined space is prepared by methods such as laser etching or mask + solution etching.

[0164] In some embodiments, laser etching refers to the formation of a defined space on a silicon substrate 8 using laser ablation. This defined space is formed by controlling known parameters such as the laser spot size, focal length, laser wavelength, pulse width, and energy. The laser source is preferably a short-wavelength ultrafast laser, such as a violet picosecond laser or a green picosecond laser. The laser spot is a square or circular spot with a side length or diameter of 20-200 μm, and the laser energy density is greater than or equal to 1.5 mJ / mm².

[0165] In some embodiments, cleaning is performed after laser etching. The cleaning method can include two approaches: the first approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and then cleaning with deionized water; the second approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with deionized water, then alkaline washing, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and finally cleaning with deionized water. After cleaning using either of these methods, the surface roughness of the silicon substrate 8 within the defined space is less than or equal to one-third of the depth of the defined space.

[0166] In some implementations, when using photolithography to prepare the defined space, the specific operations are as follows:

[0167] Photolithography: A layer of photoresist is coated onto the cleaned silicon substrate 8. A spin coater is used to form a uniform thin film of photoresist, which is then dried. The photoresist is exposed using a mask, and then developed to create a rectangular pattern of photoresist on the silicon substrate 8.

[0168] Etching: The photolithographically etched silicon substrate 8 is etched to form a rectangular structure corresponding to the mask pattern on the silicon substrate 8 by active ion etching (RIE).

[0169] Photoresist Removal: After etching, the remaining photoresist needs to be removed using an organic solvent to expose the defined space of the multiple arrays on the silicon substrate 8. Cleaning is then performed for battery fabrication.

[0170] Step 1.3 Preparation of the first passivation layer 9 and the second passivation layer 7

[0171] Intrinsic amorphous silicon layers were deposited on the light-receiving and back-light-receiving surfaces of the silicon substrate using PECVD (chemical vapor deposition) to cover the entire array structure. The specific fabrication process is existing technology and will not be described in detail here.

[0172] Step 1.4 Fabrication of the second doped layer 6 (light-receiving surface):

[0173] The second doped layer 6 is deposited on the surface of the intrinsic amorphous silicon layer (second passivation layer 7) on the light-receiving surface in the horizontal direction using PECVD. The specific preparation process is existing technology and will not be described in detail here.

[0174] Step 1.5 Fabrication of the first doped layer 10 (backlight side):

[0175] The first doped layer 10 is deposited on the intrinsic amorphous silicon layer (first passivation layer 9) on the backlight side using PECVD. The specific preparation process is existing technology and will not be described in detail here.

[0176] Step 1.6 Preparation of Backside TCO

[0177] A transparent conductive film layer on the back side is prepared on the first doped layer 10 by PVD. The target material used for the transparent conductive film layer on the back side includes, but is not limited to, ITO, AZO, and IWO. The specific preparation process is existing technology and will not be described in detail here.

[0178] Before forming the top cell, step 1.7 is included. Step 1.7 is to form an intermediate layer within a defined space.

[0179] In this paper, since there are two types of intermediate layer structures, the following preparation methods are used:

[0180] The first preparation method is as follows:

[0181] Step 1.71a: The first dielectric material is dispersed in acetone solvent to form a sol.

[0182] Step 1.72a: A transparent conductive layer (TCO layer) is prepared on the side of the second doped layer away from the second passivation layer 7 using PVD. Then, a sol is sprayed onto the transparent conductive layer to form a TCO layer with first dielectric material particles 13 on the surface, which is the intermediate layer.

[0183] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0184] The second preparation method is as follows:

[0185] Step 1.71b: Disperse the first dielectric material in acetone solvent to form a sol.

[0186] Step 1.72b involves preparing a transparent conductive layer one on the surface of the second doped layer away from the second passivation layer 7 using PVD. Then, a sol-gel is sprayed onto the transparent conductive layer one to form first dielectric material particles 13. Next, a second transparent conductive layer is prepared on the surface of the first dielectric material particles 13 away from the transparent conductive layer one using PVD, thus forming an intermediate layer where the first dielectric material particles are located within the TCO layer.

[0187] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0188] Step two includes the following steps:

[0189] Step 2.1 Fabrication of the first carrier transport layer 4

[0190] A first carrier transport layer 4 is formed on the surface of the intermediate layer 5 facing away from the second doped layer 6 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0191] Step 2.2 Preparation of the light-absorbing layer

[0192] A precursor solution for preparing the light-absorbing layer is coated onto the first carrier transport layer 4 and dried to form the light-absorbing layer. Due to the limiting effect of the array structure, the growth of the precursor solution is reduced, thereby reducing the requirement for substrate roughness, which helps to simplify the thin film coating process, and the prepared surface coverage is high and the film thickness is uniform.

[0193] Step 2.3 Fabrication of the second carrier transport layer 2

[0194] A second carrier transport layer 2 is formed on the surface of the light absorption layer opposite to the first carrier transport layer 4 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0195] Step 2.4 Preparation of Antireflection Layer 1

[0196] Using a template, an antireflection layer 1 is formed on the surface of the second carrier transport layer 2 facing away from the light absorption layer using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0197] Before or after the formation of the antireflection layer 1, a sol (a sol made by dispersing the second dielectric material in acetone solvent) is sprayed onto the second carrier transport layer 2 or the antireflection layer by spraying, thereby forming particles of the second dielectric material.

[0198] Step 2.5 Preparation of Electrode 12

[0199] The solar cell was fabricated by screen printing silver electrodes on the front and back sides and drying them at 180 degrees Celsius. The front electrode was burned through the antireflection layer 1 and connected to the second carrier transport layer 2.

[0200] This application provides a method for preparing a solar cell, comprising the following steps:

[0201] Step 1: Prepare a bottom cell, which includes a substrate, and form a defined space recessed into the substrate.

[0202] Step 2: Prepare the top cell such that at least one side of the top cell's surface, near the bottom cell, is located within a defined space.

[0203] Taking PERC batteries as an example, the details are as follows:

[0204] Step one specifically includes the following steps:

[0205] Step 1.1 Silicon substrate treatment

[0206] A single-crystal silicon wafer (N-type or P-type) with a flat front side is used. The wafer is cleaned using the standard RCA (Radio Corporation of America) cleaning process, then repeatedly rinsed with deionized water and dried with nitrogen gas before use.

[0207] Step 1.2 Preparation of the confined space

[0208] The confined space is prepared by methods such as laser etching or mask + solution etching.

[0209] In some embodiments, laser etching refers to the formation of a defined space on a silicon substrate 8 using laser ablation. This defined space is formed by controlling known parameters such as the laser spot size, focal length, laser wavelength, pulse width, and energy. The laser source is preferably a short-wavelength ultrafast laser, such as a violet picosecond laser or a green picosecond laser. The laser spot is a square or circular spot with a side length or diameter of 20-200 μm, and the laser energy density is greater than or equal to 1.5 mJ / mm².

[0210] In some embodiments, cleaning is performed after laser etching. The cleaning method can include two approaches: the first approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and then cleaning with deionized water; the second approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with deionized water, then alkaline washing, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and finally cleaning with deionized water. After cleaning using either of these methods, the surface roughness of the silicon substrate 8 within the defined space is less than or equal to one-third of the depth of the defined space.

[0211] In some implementations, when using photolithography to prepare the defined space, the specific operations are as follows:

[0212] Photolithography: A layer of photoresist is coated onto the cleaned silicon substrate 8. A spin coater is used to form a uniform thin film of photoresist, which is then dried. The photoresist is exposed using a mask, and then developed to create a rectangular pattern of photoresist on the silicon substrate 8.

[0213] Etching: The photolithographically etched silicon substrate 8 is etched to form a rectangular structure corresponding to the mask pattern on the silicon substrate 8 by active ion etching (RIE).

[0214] Photoresist Removal: After etching, the remaining photoresist needs to be removed using an organic solvent to expose the defined space of the multiple arrays on the silicon substrate 8. Cleaning is then performed for battery fabrication.

[0215] Step 1.3 Preparation of the second passivation layer 7

[0216] An intrinsic amorphous silicon layer is deposited on the light-receiving surface of the silicon substrate using PECVD (chemical vapor deposition) to cover the entire inner surface of the defined space. The specific preparation process is existing technology and will not be described in detail here.

[0217] Step 1.4 Fabrication of the second doped layer 6 (light-receiving surface):

[0218] The second doped layer 6 is deposited on the surface of the intrinsic amorphous silicon layer (second passivation layer 7) on the light-receiving surface in the horizontal direction using PECVD. The specific preparation process is existing technology and will not be described in detail here.

[0219] Step 1.5 Fabrication of heavily doped crystalline silicon region 17 (backlight side):

[0220] A heavily doped crystalline silicon region 17 is formed on the side of the silicon substrate 8 away from the second passivation layer 7. The specific preparation process is the existing technology, such as the diffusion of metal elements into the silicon substrate to form a localized heavily doped region.

[0221] Step 1.6 Preparation of the first passivation layer 9

[0222] A first passivation layer 9 is formed on the side of the silicon substrate 8 facing away from the second passivation layer 7. The specific preparation process is existing technology, for example, an aluminum oxide passivation layer can be prepared by using the ALD method.

[0223] Before forming the top cell, step 1.7 is included. Step 1.7 is to form an intermediate layer within a defined space.

[0224] In this paper, since there are two types of intermediate layer structures, the following preparation methods are used:

[0225] The first preparation method is as follows:

[0226] Step 1.71a: The first dielectric material is dispersed in acetone solvent to form a sol.

[0227] Step 1.72a: A transparent conductive layer (TCO layer) is prepared on the side of the second doped layer away from the second passivation layer 7 using PVD. Then, a sol is sprayed onto the transparent conductive layer to form a TCO layer with first dielectric material particles 13 on the surface, which is the intermediate layer.

[0228] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0229] The second preparation method is as follows:

[0230] Step 1.71b: Disperse the first dielectric material in acetone solvent to form a sol.

[0231] Step 1.72b involves preparing a transparent conductive layer one on the surface of the second doped layer away from the second passivation layer 7 using PVD. Then, a sol-gel is sprayed onto the transparent conductive layer one to form first dielectric material particles 13. Next, a second transparent conductive layer is prepared on the surface of the first dielectric material particles 13 away from the transparent conductive layer one using PVD, thus forming an intermediate layer where the first dielectric material particles are located within the TCO layer.

[0232] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0233] Step two includes the following steps:

[0234] Step 2.1 Fabrication of the first carrier transport layer 4

[0235] A first carrier transport layer 4 is formed on the surface of the intermediate layer 5 facing away from the second doped layer 6 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0236] Step 2.2 Preparation of the light-absorbing layer

[0237] A precursor solution for preparing the light-absorbing layer is coated onto the first carrier transport layer 4 and dried to form the light-absorbing layer. Due to the limiting effect of the array structure, the growth of the precursor solution is reduced, thereby reducing the requirement for substrate roughness, which helps to simplify the thin film coating process, and the prepared surface coverage is high and the film thickness is uniform.

[0238] Step 2.3 Fabrication of the second carrier transport layer 2

[0239] A second carrier transport layer 2 is formed on the surface of the light absorption layer opposite to the first carrier transport layer 4 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0240] Step 2.4 Preparation of Antireflection Layer 1

[0241] Using a template, an antireflection layer 1 is formed on the surface of the second carrier transport layer 2 facing away from the light absorption layer using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0242] Before or after the formation of the antireflection layer 1, a sol (a sol made by dispersing the second dielectric material in acetone solvent) is sprayed onto the second carrier transport layer 2 or the antireflection layer by spraying, thereby forming particles of the second dielectric material.

[0243] The step numbers above are not necessarily in a specific order.

[0244] Step 2.5 Preparation of Electrode 12

[0245] The solar cell was fabricated by screen printing front and back silver electrodes and drying them at 180 degrees Celsius. The front electrode was burned through to connect with the antireflective layer 1 and the second carrier transport layer 2.

[0246] This application provides a method for preparing a solar cell, comprising the following steps:

[0247] Step 1: Prepare a bottom cell, which includes a substrate, and form a defined space recessed into the substrate.

[0248] Step 2: Prepare the top cell such that at least one side of the top cell's surface, near the bottom cell, is located within a defined space.

[0249] Taking the TOPCon battery as an example, the details are as follows:

[0250] Step one specifically includes the following steps:

[0251] Step 1.1 Silicon substrate treatment

[0252] A single-crystal silicon wafer (N-type or P-type) with a flat front side is used. The wafer is cleaned using the standard RCA (Radio Corporation of America) cleaning process, then repeatedly rinsed with deionized water and dried with nitrogen gas before use.

[0253] Step 1.2 Preparation of the confined space

[0254] The confined space is prepared by methods such as laser etching or mask + solution etching.

[0255] In some embodiments, laser etching refers to the formation of a defined space on a silicon substrate 8 using laser ablation. This defined space is formed by controlling known parameters such as the laser spot size, focal length, laser wavelength, pulse width, and energy. The laser source is preferably a short-wavelength ultrafast laser, such as a violet picosecond laser or a green picosecond laser. The laser spot is a square or circular spot with a side length or diameter of 20-200 μm, and the laser energy density is greater than or equal to 1.5 mJ / mm².

[0256] In some embodiments, cleaning is performed after laser etching. The cleaning method can include two approaches: the first approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and then cleaning with deionized water; the second approach involves acid washing with a mixture of hydrochloric acid and hydrofluoric acid, followed by cleaning with deionized water, then alkaline washing, followed by cleaning with an organic solvent such as acetone or ethyl ketone, and finally cleaning with deionized water. After cleaning using either of these methods, the surface roughness of the silicon substrate 8 within the defined space is less than or equal to one-third of the depth of the defined space.

[0257] In some implementations, when using photolithography to prepare the defined space, the specific operations are as follows:

[0258] Photolithography: A layer of photoresist is coated onto the cleaned silicon substrate 8. A spin coater is used to form a uniform thin film of photoresist, which is then dried. The photoresist is exposed using a mask, and then developed to create a rectangular pattern of photoresist on the silicon substrate 8.

[0259] Etching: The photolithographically etched silicon substrate 8 is etched to form a rectangular structure corresponding to the mask pattern on the silicon substrate 8 by active ion etching (RIE).

[0260] Photoresist Removal: After etching, the remaining photoresist needs to be removed using an organic solvent to expose the defined space of the multiple arrays on the silicon substrate 8. Cleaning is then performed for battery fabrication.

[0261] Step 1.3 Preparation of the second passivation layer 7

[0262] An intrinsic amorphous silicon layer was deposited on the light-receiving surface of the silicon substrate using PECVD (chemical vapor deposition) to cover the entire array structure. The specific fabrication process is existing technology and will not be described in detail here.

[0263] Step 1.4 Preparation of silicon oxide passivation layer 19

[0264] A silicon oxide passivation layer 19 is formed on the side of the silicon substrate 8 facing away from the second passivation layer 7. The specific preparation process of the silicon oxide passivation layer 19 is existing technology, such as obtaining the silicon oxide passivation layer through thermal oxidation preparation and ultraviolet ozone preparation processes.

[0265] Step 1.5 Fabrication of the second doped layer 6 (light-receiving surface):

[0266] The second doped layer 6 is deposited on the surface of the intrinsic amorphous silicon layer (second passivation layer 7) on the light-receiving surface in the horizontal direction using PECVD. The specific preparation process is existing technology and will not be described in detail here.

[0267] Step 1.6 Fabrication of the first doped layer 10 (backlight side):

[0268] A first doped layer 10 is formed on the side of the silicon oxide passivation layer 19 away from the silicon substrate 8 using PECVD. The specific preparation process of the first doped layer 10 is existing technology and will not be described in detail here.

[0269] Step 1.7 Preparation of the back antireflection layer 11

[0270] A back-side antireflection layer was prepared on the first doped layer 10 using PVD. The specific preparation process is existing technology and will not be described in detail here.

[0271] Before forming the top cell, step 1.8 is included. Step 1.8 is to form an intermediate layer within a defined space.

[0272] In this paper, since there are two types of intermediate layer structures, the following preparation methods are used:

[0273] The first preparation method is as follows:

[0274] Step 1.81a: The first dielectric material is dispersed in acetone solvent to form a sol.

[0275] Step 1.82a: A transparent conductive layer (TCO layer) is prepared on the side of the second doped layer away from the second passivation layer 7 using PVD. Then, a sol is sprayed onto the transparent conductive layer to form a TCO layer with first dielectric material particles 13 on the surface, which is the intermediate layer.

[0276] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0277] The second preparation method is as follows:

[0278] Step 1.81b: Disperse the first dielectric material in acetone solvent to form a sol.

[0279] Step 1.82b involves preparing a first transparent conductive layer using PVD on the surface of the second doped layer away from the second passivation layer 7. Then, a sol-gel is sprayed onto the first transparent conductive layer to form first dielectric material particles 13. Next, a second transparent conductive layer is prepared using PVD on the surface of the first dielectric material particles 13 away from the first transparent conductive layer, thus forming an intermediate layer where the first dielectric material particles are located within the TCO layer.

[0280] The specific preparation process of the transparent conductive layer is existing technology and will not be described in detail here.

[0281] Step two includes the following steps:

[0282] Step 2.1 Fabrication of the first carrier transport layer 4

[0283] A first carrier transport layer 4 is formed on the surface of the intermediate layer 5 facing away from the second doped layer 6 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0284] Step 2.2 Preparation of the light-absorbing layer

[0285] A precursor solution for preparing the light-absorbing layer is coated onto the first carrier transport layer 4 and dried to form the light-absorbing layer. Due to the limiting effect of the array structure, the growth of the precursor solution is reduced, thereby reducing the requirement for substrate roughness, which helps to simplify the thin film coating process, and the prepared surface coverage is high and the film thickness is uniform.

[0286] Step 2.3 Fabrication of the second carrier transport layer 2

[0287] A second carrier transport layer 2 is formed on the surface of the light absorption layer opposite to the first carrier transport layer 4 using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0288] Step 2.4 Preparation of Antireflection Layer 1

[0289] Using a template, an antireflection layer 1 is formed on the surface of the second carrier transport layer 2 facing away from the light absorption layer using the ALD method. The specific fabrication process is existing technology and will not be described in detail here.

[0290] Before or after the formation of the antireflection layer 1, a sol (a sol made by dispersing the second dielectric material in acetone solvent) is sprayed onto the second carrier transport layer 2 or the antireflection layer by spraying, thereby forming particles of the second dielectric material.

[0291] Step 2.5 Preparation of Electrode 12

[0292] The solar cell was fabricated by screen printing silver electrodes on the front and back sides and drying them at 180 degrees Celsius. The front electrode was burned through the antireflection layer 1 and connected to the second carrier transport layer 2.

[0293] In the preparation method of this application, the steps of forming the first dielectric material particles and the second dielectric material particles may or may not be included. The specific step can be determined according to actual needs.

[0294] The step numbers above are not necessarily in a specific order.

[0295] This application also provides a photovoltaic module, which includes the aforementioned solar cell; or a solar cell prepared by the aforementioned method.

[0296] This application also provides a photovoltaic system, which includes the aforementioned photovoltaic modules.

[0297] Example

[0298] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0299] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0300] Example 1

[0301] The solar cell of this embodiment, as shown in Figure 2, includes the following steps:

[0302] Step 1.1 Silicon wafer cleaning

[0303] The silicon wafer is an N-type single crystal silicon wafer with a flat front side (M2 silicon wafer, with a thickness of 130μm). The substrate is cleaned using the standard RCA cleaning process, then repeatedly rinsed with deionized water, and dried with nitrogen gas before use.

[0304] Step 12. Preparation of the confined space

[0305] Multiple arrays of confined spaces are fabricated using photolithography. The dimensions (length × width × height) of each confined space are 3cm × 3cm × 800nm. The thickness of the spacer confining wall 15 and the edge confining outer wall 14 are the same, and both are 20μm.

[0306] Photolithography: A layer of photoresist is coated onto the cleaned silicon substrate 8. A spin coater is used to form a uniform thin film of photoresist, which is then dried. The photoresist is exposed using a mask, and then developed to create a rectangular pattern of photoresist on the silicon substrate 8.

[0307] Etching: The photolithographically etched silicon substrate 8 is etched to form a defined spatial structure on the silicon substrate 8 corresponding to the mask pattern through active ion etching (RIE).

[0308] Remove photoresist: After etching, place the silicon wafer with photoresist in the above-mentioned organic solvent and soak for 5 minutes; then clean the silicon wafer with deionized water and blow it dry with nitrogen to expose the defined space of the array arrangement on the silicon substrate 8.

[0309] The organic solvent is a mixed solution of sodium hydroxide and methanol, with a pH of approximately 11.

[0310] Step 1.3 Preparation of the first passivation layer 9 and the second passivation layer 7

[0311] On the light-receiving and back-light-receiving surfaces of the silicon substrate 8, intrinsic amorphous silicon layers with a thickness of 5 nm are deposited as the second passivation layer 7 and the first passivation layer 9, respectively, using PECVD (chemical vapor deposition). The first passivation layer 9 is located on the back-light-receiving surface, and the second passivation layer 7 is located on the light-receiving surface. The second passivation layer 7 includes a central portion and side portions located on both sides of the central portion. The side portions are located on the inner sidewall of the defined space, and the central portion is located in the horizontal direction of the defined space.

[0312] Step 1.4 Fabrication of the second doped layer 6 (light-receiving surface):

[0313] A second doped layer 6 with a thickness of 10 nm is deposited on the surface of the second passivation layer 7 on the side opposite to the silicon substrate 8 using PECVD. The doping element in the second doped layer 6 is phosphorus.

[0314] Step 1.5 Fabrication of the first doped layer 10 (backlight side):

[0315] A first doped layer 10 with a thickness of 15 nm was deposited on the intrinsic amorphous silicon layer using PECVD on the first passivation layer 9. The dopant element in the first doped layer 10 is boron.

[0316] Step 1.6 Preparation of Backside TCO

[0317] A transparent conductive film with a thickness of 80 nm was prepared on the first doped layer 10 using PVD.

[0318] Step 1.7 Preparation of intermediate layer 5

[0319] Silica sol was prepared by dispersing silica particles with a particle size of 10 nm in acetone solvent, and the concentration of silica sol was 0.3 wt%.

[0320] An ITO layer with a thickness of 20 nm is prepared on the first doped layer 10 by PVD. Then, silica sol is sprayed onto the ITO layer and dried at 70 °C to form an intermediate layer with first dielectric material particles 13 with a particle size of 10 nm.

[0321] Step 2.1 Fabrication of the first carrier transport layer 4

[0322] A nickel oxide layer (first carrier transport layer 4) with a thickness of approximately 30 nm was prepared using the ALD method. The precursor was dimethylcyclopentadienyl nickel, which reacted with oxygen plasma to generate nickel oxide. The reaction temperature was 75 °C, with a dimethylcyclopentadienyl nickel pulse for 3 seconds, nitrogen purging for 4 seconds, oxygen plasma for 3 seconds, and purging for 1 second.

[0323] Step 2.2 Preparation of the perovskite absorber layer 3

[0324] 206.4 mg of FAI, 27.0 mg of MABr, 608.6 mg of PbI₂, and 88.2 mg of PbBr₂ were dissolved in 1 ml of precursor solvent, and then 52.2 μl of CsI in DMSO (dimethyl sulfoxide) solution (390 mg / ml) was added. The mixture was heated and stirred at 60°C for 2 hours to obtain a perovskite precursor solution. The product obtained in step 2.1 was transferred into a nitrogen glove box (water content less than 1 ppm, oxygen content less than 1 ppm). The perovskite precursor solution was coated onto the first carrier transport layer 4, and after drying, a perovskite absorber layer 3 was prepared.

[0325] Step 2.3 Fabrication of the second carrier transport layer

[0326] A second carrier transport layer with a thickness of 30 nm was prepared using the ALD method at a deposition temperature of 200 °C. The precursors were diethylzinc and deionized water. The diethylzinc was pulsed for 0.2 seconds and purged with nitrogen for 10 seconds, while the deionized water was pulsed for 0.2 seconds and purged with nitrogen for 10 seconds. The surface of the second carrier transport layer away from the silicon substrate was flush with the top of the edge confinement outer wall 14 and the spacer confinement wall 15.

[0327] Step 2.4 Preparation of the antireflective layer

[0328] Using a template, a 30 nm thick aluminum oxide layer was deposited on the second carrier transport layer using the ALD method, with the aluminum oxide layer covering the defined space. The precursors were triethylaluminum and deionized water, the reaction temperature was 200 °C, and the cycle consisted of a 0.2 sec trimethylaluminum pulse followed by a 10 sec nitrogen purge, a 0.2 sec deionized water pulse, and a 10 sec nitrogen purge.

[0329] Step 2.5 Electrode Preparation

[0330] Silver electrodes on the front and back sides are screen-printed and dried at 180 degrees Celsius to complete the fabrication of the solar cell. The parameters of the solar cell in this embodiment are shown in Table 1.

[0331] The difference between Examples 2-5 and Example 1 lies in the dimensions (length × width) of the space defined on the silicon substrate surface; all other parameters are the same. The parameters of the solar cell in this example are shown in Table 1.

[0332] The difference between Examples 6-11 and Example 1 is the thickness of the outer wall of the edge confinement zone; all other parameters are the same. The parameters of the solar cell in this example are shown in Table 1.

[0333] The difference between Examples 12-14 and Example 1 is that the proportion of the projected area of ​​the first dielectric material particles on the TCO layer to the surface area of ​​the TCO is different; all other parameters are the same. The parameters of the solar cell in this example are shown in Table 1.

[0334] The difference between Examples 15-19 and Example 1 is that the average particle size of the first dielectric material particles is different, while all other parameters are the same. The parameters of the solar cell in this example are shown in Table 1.

[0335] The difference between Examples 20 and 21 and Example 1 is the roughness of the silicon substrate; all other parameters are the same. The parameters of the solar cell in this example are shown in Table 1.

[0336] The difference between Comparative Example 1 and Example 1 is that there is no defined space on the silicon substrate; all other parameters are the same. The parameters of the solar cell in this comparative example are shown in Table 1.

[0337] Table 1 shows the parameters of the solar cells in each embodiment and comparative example.

[0338] Summary: As shown in the table above, the solar cell structure of this application can effectively improve the quality of tandem cells, thereby achieving excellent cell efficiency. However, excessively large confined space dimensions make it difficult to control the uniformity of the top cell fabrication, leading to reduced tandem cell performance. Larger thicknesses of the edge confining outer walls and spacer walls result in a smaller top cell area, further reducing cell performance. Excessive roughness at the bottom of the confined space reduces the uniformity of the light absorption layer of the top cell, limiting the effectiveness of the confined space and ultimately degrading cell performance.

[0339] Although the embodiments of this application have been described above in conjunction with the accompanying drawings, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

[0340] The terms "some implementations," "one embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the phrase "in one embodiment" does not necessarily refer to the same embodiment in all instances.

[0341] Those skilled in the art should understand that, in the disclosure of this application, the terms "first," "second," "third," "fourth," "fifth," etc., are only used to distinguish different structures and do not limit the number of specific structures, connection relationships, etc.; in addition, the orientation or positional relationship indicated by "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc., is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limitations on this application.

Claims

1. A solar cell, wherein, The device includes a bottom battery and a top battery stacked together. The bottom battery has a base and a defined space recessed into the base on the side of the base near the top battery. In the top battery, at least one surface near the bottom battery is located within the defined space.

2. The solar cell according to claim 1, wherein, The depth of the defined space is 200nm-1μm, or, Within the defined space, the surface roughness of the substrate is less than or equal to one-third of the depth of the defined space.

3. The solar cell according to claim 1, wherein, The defined space has a bottom surface, and the edge region of the base has an edge-limiting outer wall disposed around the edge of the bottom surface.

4. The solar cell according to claim 3, wherein, The length of the defined space is 1cm-5cm, and the width of the defined space is 1cm-5cm.

5. The solar cell according to claim 1, wherein, The defined space has a bottom surface, and the middle region of the base is provided with a spaced-out limiting wall protruding from the bottom surface.

6. The solar cell according to claim 4, wherein, The thickness of the outer wall of the edge confinement is less than or equal to 50 μm.

7. The solar cell according to claim 5, wherein, The thickness of the spacer wall is less than or equal to 50 μm.

8. The solar cell according to claim 1, wherein, The bottom battery also includes a second passivation layer located within the defined space, the defined space having a bottom surface and sidewalls, the second passivation layer including a middle portion and side portions located at both ends of the middle portion, the side portions being stacked on the inner sidewalls of the defined space.

9. The solar cell according to claim 8, wherein, The substrate is a silicon substrate, and the second passivation layer is stacked adjacent to the silicon substrate; or The bottom cell further includes a second doped layer located on the side surface of the second passivation layer away from the silicon substrate.

10. The solar cell according to claim 1 or 9, wherein, An intermediate layer is stacked within the defined space, and the intermediate layer is located between the bottom battery and the top battery. The intermediate layer includes a TCO layer and first dielectric material particles. The first dielectric material particles are dispersed within the TCO layer, or The first dielectric material particles are dispersed on the surface of the TCO layer near the top cell.

11. The solar cell according to claim 10, wherein, The projected area of ​​all first dielectric material particles on the TCO layer is less than or equal to 20% of the surface area of ​​the TCO layer, and the projection direction is the stacking direction of the bottom and top cells; or The average particle size of the first dielectric material particles is 5-30 nm; or The material of the first dielectric material particle can be silicon dioxide, aluminum oxide, or silicon nitride.

12. The solar cell according to claim 3, wherein, The top battery also includes an anti-reflective layer, in which at least partially covers the outer wall of the edge confinement of the defined space.

13. The solar cell according to claim 1, wherein, The top battery also includes an anti-reflective layer located within the defined space.

14. The solar cell according to claim 12, wherein, The antireflective layer has second dielectric material particles on its surface facing away from or near the bottom battery; the projected area of ​​all the second dielectric material particles on the antireflective layer is less than or equal to 40% of the surface area of ​​the antireflective layer, and the projection direction is the stacking direction of the bottom and top batteries; or The average particle size of the second dielectric material particles is 5-30 nm; or The material of the second dielectric material particle can be silicon dioxide, aluminum oxide, or silicon nitride.

15. A method for preparing a solar cell, wherein, Includes the following steps: A bottom battery is prepared, wherein the bottom battery includes a substrate, and a defined space is formed in the substrate that is recessed into the interior of the substrate; A top cell is prepared such that at least one surface of the top cell near the bottom cell lies within the defined space.

16. The preparation method according to claim 15, wherein, The defined space is formed by laser etching or mask and solution etching.

17. The preparation method according to claim 15, wherein, An intermediate layer is formed within the defined space prior to the formation of the top cell; The method for preparing the intermediate layer includes the following steps: Form a transparent conductive layer; The raw material of the first dielectric material particles is sprayed onto the transparent conductive layer by spraying, thereby forming an intermediate layer containing the first dielectric material particles.

18. The preparation method according to claim 15, wherein, An intermediate layer is formed within the defined space prior to the formation of the top cell; The method for preparing the intermediate layer includes the following steps: Forming a transparent conductive layer; The raw material of the first dielectric material particles is sprayed onto the transparent conductive layer by spraying, thereby forming the first dielectric material particles; A second transparent conductive layer is formed, and the second transparent conductive layer covers the first dielectric material particles.

19. A photovoltaic module, wherein, The photovoltaic module includes the solar cell as described in any one of claims 1-14.

20. A photovoltaic system, wherein, The photovoltaic system includes the photovoltaic module as described in claim 19.

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