Serial peripheral interface, beam control chip and data transmission method

Abstract

Provided in the embodiments of the present disclosure are a serial peripheral interface, a beam control chip and a data transmission method. The serial peripheral interface comprises a shift register module, a data parsing module and a plurality of memory cells, wherein the shift register module is configured to receive an external data frame and transmit the data frame to the data parsing module, a complete data frame structure comprises a frame header, a control bit, an address bit and a data bit, and the received data frame comprises an incomplete data frame structure and / or a merged complete data frame structure; and the data parsing module is configured to acquire the data frame, determine a structure type of the acquired data frame, determine a parsing mode for the acquired data frame on the basis of the determined structure type, parse the acquired data frame on the basis of the determined parsing mode, and operate the memory cells. In this way, the serial peripheral interface can provide corresponding parsing processing modes on the basis of different data frame structures, such that the data transmission rate is increased.

Description

Serial digital interface, beam control chip and data transmission method

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202410505934.4, filed on April 25, 2024, entitled "Serial Digital Interface, Beam Control Chip and Data Transmission Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit technology, and in particular to a serial digital interface, a beam control chip, and a data transmission method. Background Technology

[0004] The Serial Peripheral Interface (SPI) is a full-duplex, synchronous communication bus used for data exchange between a master and peripheral devices. The SPI bus uses a master-slave communication mechanism, where the master is the master and the peripheral device is the slave.

[0005] One application of the SPI interface is programming beamforming chips. Beamforming is used to focus radio frequency signal strength to overcome path loss. To achieve beamforming, the amplitude and phase settings of each of multiple beamforming chips are programmed. Each time the amplitude and phase settings of a chip are programmed, the amplitude and phase control information needs to be rewritten into the corresponding memory cell in the SPI, which takes several hundred bits of transmission time, impacting the speed of beamforming control. Summary of the Invention

[0006] This disclosure provides a serial digital interface, a beam control chip, and a data transmission method that can improve the speed of data transmission and beam control.

[0007] In a first aspect, embodiments of this disclosure provide a serial digital interface, including a shift register module, a data parsing module, and multiple storage units, wherein the storage units are used to store data;

[0008] The shift register module is used to receive external data frames and transmit the data frames to the data parsing module; wherein, the complete data frame structure includes a frame header, control bits, address bits and data bits, and the received data frame includes an incomplete data frame structure and / or a merged complete data frame structure, wherein the merged data frame structure has the same address bits;

[0009] The data parsing module is used for:

[0010] Acquire the data frame;

[0011] Determine the structure type of the acquired data frame;

[0012] Based on the determined structure type, determine the parsing method for the acquired data frame;

[0013] The acquired data frame is parsed according to the determined parsing method, and the storage unit is operated on.

[0014] In some embodiments, the incomplete data frame structure includes at least one of the following types:

[0015] The data frame structure of the first type includes the frame header, the control bits, and the data bits;

[0016] The second type of data frame structure includes the frame header, the control bits, and the address bits;

[0017] The third type of data frame structure has the data bits;

[0018] The fourth type of data frame structure includes the frame header and the control bits;

[0019] The merged complete data frame structure includes the frame header, the control bits, the address bits, and multiple data bits;

[0020] The step of parsing the acquired data frame and operating the storage unit includes:

[0021] For the data frame structure of the first type, the data parsing module determines the operation mode based on the content of the control bits; when the operation mode is a write operation, the data in the data bits is written into the default storage unit.

[0022] For the data frame structure of the second type, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a write operation, the data in the default storage unit is written into the storage unit corresponding to the address bit, or when the operation mode is a read operation, the data is read from the storage unit corresponding to the address bit.

[0023] For the data frame structure of the third type, the data parsing module determines the operation mode based on the data in the default storage unit; when the operation mode is a write operation, the data of the data bits is written into the default storage unit.

[0024] For the data frame structure of the fourth type, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a read operation, data is read from the default storage unit, or when the operation mode is a write operation, default data is written to the default storage unit.

[0025] For the merged complete data frame structure, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a write operation, the data in the data bit is written sequentially to the multiple storage units, starting from the address indicated by the address bit.

[0026] In some embodiments, the data in the storage unit is used to send to the corresponding receiving module;

[0027] When the data of the same receiving module is changed continuously, the data frame of the first type is selected;

[0028] When writing periodic data to the receiving module, the data frame of the second type is selected;

[0029] When the data of all the receiving modules is changed, the data frame of the third type is selected;

[0030] When reading temperature data from the default storage unit, the fourth type of data frame is selected;

[0031] When the data of a portion of the receiving module is changed, the merged complete data frame is selected.

[0032] In some embodiments, the serial digital interface further includes: a frame type register for storing the structure type of the current data frame;

[0033] The data parsing module is further configured to: obtain the structure type stored in the frame type register, wherein the stored structure type is the structure type of the current data frame.

[0034] In some embodiments, the current data frame further includes the structure type of the next data frame;

[0035] The data parsing module is also used to: write the structure type of the next data frame into the frame type register.

[0036] In some embodiments, the control bit includes the structure type of the next data frame; or, the address bit includes the structure type of the next data frame.

[0037] In some embodiments, the serial digital interface further includes: a buffer register module, configured to acquire data from the storage unit and output the data from the storage unit in parallel to the corresponding receiving module.

[0038] In some embodiments, the shift register module is further configured to serially output the data of the storage unit based on the parsing result.

[0039] In some embodiments, the serial digital interface further includes:

[0040] Input side includes input data signal interface, input clock signal interface, and temperature code interface;

[0041] Output clock signal interface and output data signal interface on the output side.

[0042] In a second aspect, embodiments of this disclosure provide a beam control chip, the beam control chip including multiple radio frequency channels and a serial digital interface as described in any one of the first aspects;

[0043] The serial digital interface is used to control the phase and / or amplitude of the radio frequency channel; the address of the storage unit corresponds to different radio frequency channels.

[0044] Thirdly, embodiments of this disclosure provide a data transmission method for a beam control chip, comprising:

[0045] Define a data frame, wherein the defined data frame includes an incomplete data frame structure and / or a merged complete data frame structure, wherein the complete data frame structure includes a frame header, control bits, address bits and data bits, and the merged data frame structure has the same address bits;

[0046] The data frame is acquired using the data transmission pin of the beam control chip;

[0047] Determine the structure type of the acquired data frame;

[0048] Based on the determined structure type, determine the parsing method for the acquired data frame;

[0049] The acquired data frame is parsed according to the determined parsing method, and the storage unit is operated.

[0050] This disclosure provides a serial digital interface, including a shift register module, a data parsing module, and multiple storage units for parsing data frames. The shift register module receives data frames that include incomplete data frame structures and / or merged complete data frame structures. Different parsing methods are used when the data frame structure type differs, allowing for the use of different data frame structure types in different application scenarios. Flexible access to storage units is achieved by flexibly setting the data frame structure. Furthermore, using different data frame structure types in different application scenarios eliminates the need to use complete data frames every time, saving parsing time and improving the transmission speed of the serial digital interface.

[0051] Furthermore, this serial digital interface can be used in a beam control chip to control the phase and / or amplitude of the beam control chip. The addresses of the storage units correspond to different radio frequency channels (transmit channels and / or receive channels). By writing data to multiple storage units and simultaneously outputting the data from multiple storage units to the corresponding radio frequency channels, the phase and / or amplitude of multiple radio frequency channels can be controlled simultaneously, so that there is no time difference in the control of different radio frequency channels. Attached Figure Description

[0052] Figure 1 is a schematic diagram of a beam control chip and baseband provided in an embodiment of this disclosure;

[0053] Figure 2 is a schematic diagram of a serial digital interface provided in an embodiment of this disclosure;

[0054] Figure 3 is a schematic diagram of the structure of a data frame provided in an embodiment of this disclosure;

[0055] Figure 4 is a schematic diagram of the structure of a data frame provided in an embodiment of this disclosure;

[0056] Figure 5 is a schematic diagram of a serial digital interface provided in an embodiment of this disclosure;

[0057] Figure 6 is a schematic diagram of a serial digital interface provided in an embodiment of this disclosure;

[0058] Figure 7 is a schematic diagram of a beam control chip provided in an embodiment of this disclosure. Detailed Implementation

[0059] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0061] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0062] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0063] Beam control chips (also known as phased array chips) are one of the core components of phased array systems and are currently widely used in broadband satellite communication, millimeter-wave 5G communication, and other fields. Figure 1 is a schematic diagram of a beam control chip and baseband provided in an embodiment of this disclosure. As shown in Figure 1, the beam control chip may include multiple radio frequency (RF) channels, where each RF channel is a transmission channel for RF signals, including a transmitting channel and a receiving channel. Figure 1 uses the receiving channel as an example. Each RF channel is coupled to an antenna and can receive RF signals from the antenna. Each RF channel includes a corresponding phase shifter and / or amplitude modulator. The phase shifter is used to shift the phase of the signal, and the amplitude modulator is used to adjust the amplitude of the signal. The amplitude modulator can be an attenuator or an amplifier. When the phased array system needs to point in a specific direction to achieve a beam in that direction, the corresponding RF signal can be phase-shifted by the phase shifter in the phased array, and / or the corresponding RF signal can be amplitude-adjusted by the amplitude modulator, thereby obtaining a radiation pattern in that specific direction and thus a corresponding beam. The beam control chip may also include a combiner, which combines signals from multiple radio frequency channels and sends the combined signal to the baseband. The baseband processor modulates the combined signal to obtain a digital signal.

[0064] Data controlling the phase shifters and amplitude modulators can be sent from the baseband to the beam control chip and then transmitted to each phase shifter and amplitude modulator respectively to adjust the phase of each phase shifter and the amplitude of each amplitude modulator. Data transmission between the baseband and the beam control chip can use an SPI interface. The baseband includes an SPI master, and the beam control chip includes an SPI slave. The SPI master sends data frames to the SPI slave, which parses the data frames and sends the parsed data to the corresponding phase shifter and amplitude modulator. Since the phase of the phase shifter and / or the amplitude of the amplitude modulator need to be changed each time the beam is adjusted, the control data needs to be rewritten to the SPI slave's memory. This data writing process has a significant impact on the beam control speed.

[0065] To improve beam control speed, this disclosure provides a serial digital interface including a shift register module, a data parsing module, and multiple storage units. The shift register module receives external data frames and transmits them to the data parsing module. A complete data frame structure includes a frame header, control bits, address bits, and data bits. The received data frames may include incomplete data frame structures and / or merged complete data frame structures. The data parsing module is used to: acquire data frames; determine the structure type of the acquired data frames; determine the parsing method for the acquired data frames based on the determined structure type; and, after parsing the acquired data frames according to the determined parsing method, operate on the storage units. Because the data frames received by the shift register module include incomplete data frame structures and / or merged complete data frame structures, different parsing methods are used when the data frame structure type is different. This allows different data frame structure types to be used in different application scenarios, enabling flexible access to storage units through flexible data frame structure settings. Furthermore, using different data frame structure types in different application scenarios eliminates the need to use complete data frames every time, saving parsing time and improving the transmission speed of the serial digital interface.

[0066] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0067] In one embodiment of this disclosure, as shown in FIG2, the serial digital interface 10 mainly includes an input interface, an output interface, and an internal structure (not shown in FIG2, but the internal structure can be referred to FIG5). The input interface mainly includes a receive reset signal interface RST, a chip select signal interface CSB, an input clock signal interface CKI, an input data signal interface SDI, and a temperature code interface TEMP, etc. The output interface mainly includes a transmit output clock signal interface CKO, an output data signal interface SDO, a phase shifter (PS) / digital step attenuator (DSA) signal interface for amplitude and phase control of the RF channel within the beam control chip PS / DSA, and multiple enable signal interfaces XX_EN1-XX_ENn, etc. The output data signal interface SDO is used to transmit signals from inside the beam control chip to outside the chip. The PS / DSA interface and the XX_EN1-XX_ENn interfaces are internal interfaces for the serial digital interface 10 to transmit data to the chip's internal components, and can connect to the chip's internal data bus to send data to devices inside the chip, such as the RF channel. The internal structure may include temperature sensors, etc. Among the signals transmitted through the input and output interfaces, the reset signal, chip select signal, input clock signal, and input data signal are signals provided externally to the chip; the temperature code is a signal generated by the internal temperature sensor of the chip; the output clock signal, output data signal, PS / DSA signal, and multiple enable signals are signals generated by the serial digital interface 10 based on the input data, and are located inside the beam control chip.

[0068] It should be noted that in some application scenarios, the reset signal and output clock signal can be omitted, thereby further reducing the number of interfaces of the serial digital interface 10 and reducing the occupation of chip pin resources, but there is no specific limitation on this.

[0069] The serial digital interface 10 typically includes two modes: master and slave. In SPI communication, the master is responsible for controlling the initiation and termination of communication and timing, and sending data frames to the slave to write data; the slave passively responds to the master's instructions to perform data transmission. The serial digital interface in Figure 2 is illustrated using the slave mode.

[0070] As shown in Figure 3, in some embodiments, the complete data frame structure includes a frame header, control bits, address bits, and data bits. The frame header is a set of specific bit patterns or signal sequences used to identify and mark the start and end of a frame (i.e., a data frame), typically consisting of a clock signal and the status of the master select line. In some embodiments, the frame header may contain the following information: slave selection, data transmission mode, acknowledgment and verification information, etc. The acknowledgment and verification information is used to confirm the actual occurrence of data transmission or to perform error detection and verification between data frames; if the frame header is incorrect, the SPI will not respond.

[0071] Control bits are used to control the operation or mode of data transmission. Control bits can include control information (such as instructions) for the memory cell. The control information determines what operation to perform on the SPI in this frame, such as writing to the memory cell or reading information from the SPI.

[0072] The address bits are used to indicate the destination or source of data transmission. They are used for addressing in memory cells and determine where in the SPI data is operated on, such as which memory cell within the serial digital interface 10 is operated on.

[0073] Data bits are the part used to transmit actual data. The data in the data bits is new data passed to the SPI, such as data written to the memory cell within the serial digital interface 10.

[0074] In the embodiment shown in Figure 3, the frame header, control bits, address bits, and data bits are arranged sequentially in the data frame. In other embodiments, the order of the control bits, address bits, and data bits can be interchanged. In addition, the data frame structure may also include a frame tail, which is a set of specific bit patterns or signal sequences used to identify the end of the frame. The frame header, control bits, address bits, and data bits can each include one or more bits.

[0075] The serial digital interface 10 can parse data frames in the following four steps:

[0076] Step 1: The data parsing module 12 parses the frame header to confirm whether it matches the preset frame header. If the frame header matches the preset frame header, the data parsing module 12 continues to parse the data frame. If the frame header does not match the preset frame header, the data parsing module 12 stops parsing the data frame and waits for the next frame to be received before parsing. Here, the preset frame header is stored in any one or more storage units.

[0077] Step 2: The data parsing module 12 identifies the control bits and determines the function of the current data frame based on the content of the control bits (e.g., instructions). For example, the function of the current data frame is to read data from a certain memory cell in the SPI (data from the memory cell can be read from the SDO interface), write data to a certain memory cell in the SPI, or output the data of the memory cell through the cache register module 14, etc.

[0078] Step 3: The data parsing module 12 identifies the address bits and determines which memory cell in the SPI to operate based on the content of the address bits;

[0079] Step 4: The data parsing module 12 identifies the data bits and transmits the new data contained in the data bits to the storage unit corresponding to the address bits.

[0080] To save on data frame transmission and parsing time, this solution improves the data frame structure. In different scenarios, some structures can be omitted, such as omitting one or more of the frame header, control bits, address bits, and data bits, to reduce the length of the data frame and thus improve processing speed; or, a data frame can include multiple data bits, allowing data to be written to multiple storage units at once, thereby improving processing speed.

[0081] The improved data frame structure is shown in Figure 4. The improved data frame structure may include at least one of the first type, the second type, the third type, the fourth type, or the fifth type (i.e., the merged complete data frame structure).

[0082] The first type of data frame structure includes: a frame header, control bits, and data bits; the first type of data frame structure does not include address bits, and the positions of control bits and data bits can be interchanged;

[0083] The second type of data frame structure includes: a frame header, control bits, and address bits; the second type of data frame structure does not include data bits, and the positions of the control bits and address bits can be interchanged;

[0084] The third type of data frame structure includes only data bits; the third type of data frame structure does not include frame headers, control bits, and address bits.

[0085] The fourth type of data frame structure includes a frame header and control bits; the fourth type of data frame structure does not include address bits and data bits.

[0086] The fifth type of data frame structure includes: a frame header, control bits, address bits, and at least two data bits, such as data bits 1 to data bits m; wherein the positions of the control bits, address bits, and at least two data bits can be interchanged.

[0087] The first to fourth types of data frames are incomplete data frame structures. These incomplete structures lack one or more of the following: frame header, control bits, address bits, and data bits. The length of an incomplete data frame is shorter than that of a complete data frame, resulting in shorter transmission and parsing times. The fifth type of data frame is a merged complete data frame structure. This merged structure shares the same address bits and includes a frame header, control bits, address bits, and at least two data bits. These at least two data bits share the frame header, control bits, and address bits. Therefore, a single fifth-type data frame can write data to multiple storage units, eliminating the need for multiple data frames and saving transmission and parsing time. In summary, this solution allows for the use of different data frame structures in different application scenarios, providing flexibility in setting the data frame structure and avoiding the need to use a complete data frame structure every time, thus saving data transmission time.

[0088] The following describes the processing of the serial digital interface for the aforementioned incomplete data frame structure and the merged complete data frame structure, in conjunction with the internal structure of the serial digital interface. Those skilled in the art will understand that the serial digital interface of this solution can also process the complete data frame structure shown in Figure 3.

[0089] In some embodiments, referring to FIG5, a second schematic diagram of the structure of a serial digital interface provided in this disclosure is shown. As shown in FIG5, the serial digital interface 10 may include a shift register module 11, a data parsing module 12, and multiple storage units 13 (for clarity, multiple storage units are shown as storage units 13 in FIG5). The data parsing module 12 is connected to the shift register module 11 and the storage units 13 respectively. The shift register module 11 can receive data frames from outside the serial digital interface 10 through the SDI interface; the data parsing module 12 is used to parse the data frames and send the parsed data to the storage units 13; the storage units 13 are used to store data, such as data bits, and the storage units can be registers. Each storage unit has an address, as shown in FIG6, addresses 0x00, 0x01, ..., 0xFE, which represent the positions of storage units 131 to 13n respectively. In FIG6, n, x, E, and F are natural numbers.

[0090] As shown in Figure 6, in some embodiments, the serial digital interface 10 may further include a buffer register module 14 for sending data from multiple storage units 131-13n to a receiving module outside the serial digital interface 10. The receiving module and the serial digital interface 10 are located within the same chip. The serial digital interface 10 is used to write data to the receiving module, which may be an amplitude modulator or a phase shifter. The data in the storage units may be data parsed from a data frame or default data pre-stored in the storage units. It should be noted that the buffer register module 14 waits for all bits of the data to arrive before simultaneously outputting the data to the receiving module to prevent signal timing discrepancies. Furthermore, the buffer register module 14 may include multiple registers to store all bits of the data; this is not specifically limited.

[0091] Referring to Figure 6, the shift register module 11 receives data frames from the serial digital interface 10 and sends the data frames to the data parsing module 12. The shift register module 11 has the ability to shift data bit by bit, allowing data to be transmitted between the master and slave devices in bit units. For example, the shift register module 11 temporarily stores newly received data for subsequent data processing. To avoid occupying too much space, the old data is immediately shifted out bit by bit after the new data arrives. During the input data storage period, the data parsing module 12 parses the data in the shift register module 11. The shift register module 11 can also serially output the data to be output from the SDO interface through a shifting method. The data output from the SDO interface comes from the parsing result of the data parsing module 12. In one case, the shift register module 11 directly shifts out the input data; in another case, the shift register module 11 serially outputs some data from storage units 131-13n from the SDO interface based on the parsing result.

[0092] The data parsing module 12 is used to acquire data frames sent by the shift register module 11 and determine the structure type of the acquired data frames. The data parsing module 12 can know the structure type of the data frame before receiving it, so as to correctly parse the data frame. It should be noted that the serial digital interface 10 can process data frames of different lengths and structures simultaneously. Therefore, as shown in Figure 6, the serial digital interface 10 may include a frame type register to store the structure type of the current data frame, i.e., which type of data frame is shown in Figure 3 or Figure 4. In Figure 6, 0xFF represents the address of the frame type register. The frame type register can also be read and written, thereby changing the currently stored frame type information and identifying whether the current frame structure is correct.

[0093] The data parsing module 12 can read the contents of the frame type register to obtain the structure type stored in the frame type register, which is the structure type of the current data frame. The structure type of the current data frame in the frame type register can be written by the previous data frame, so that the data parsing module 12 can determine the structure type of the current data frame. Furthermore, the current data frame can also include the structure type of the next data frame, so that when the serial digital interface 10 receives the next data frame, the data parsing module 12 can determine the structure type of the next data frame. In some embodiments, when the data frame includes control bits, the control bits can include the structure type of the next data frame; for example, one or more bits in the control bits can be used to indicate the structure type of the next data frame. In some embodiments, when the data frame includes address bits, the address bits can include the structure type of the next data frame; for example, one or more bits in the address bits can be used to indicate the structure type of the next data frame. If the current data frame includes the structure type of the next data frame, the data parsing module 12 is also used to write the structure type of the next data frame into the frame type register for correct parsing of the next data frame. In the initial state, the frame type register stores a default value, such as 001 representing the first type. After parsing the data frame of the first type, the data value stored in the frame type register can be adjusted by the control bits or address bits of the data frame, for example, adjusted to 011 representing the second type according to the parsing result.

[0094] After determining the data frame structure type, the data parsing module 12 determines the parsing method for that data frame based on its structure type. The data frame type includes a complete data frame structure and any one of the first to fifth types. The parsing method refers to parsing the data frame to extract one or more of the following: frame header, control bits, address bits, and data bits. Different data frame structures have different parsing methods; using the parsing method corresponding to the data frame structure ensures correct parsing of the data frame.

[0095] According to the determined parsing method, the data parsing module 12 parses the data frame. The parsing process includes: the data parsing module 12 identifying the data frame from the shift register module 11 and extracting one or more of the following: frame header, control bits (instructions), address bits, and data bits. The data parsing module 12 can distinguish different data frames based on the chip select signal. When the chip select signal is low, it indicates the start of a data frame transmission; when the data frame transmission is complete, the chip select signal goes high. The data parsing module 12 begins parsing each bit when the chip select signal is low.

[0096] After parsing, the data parsing module 12 can also operate on the storage unit. For example, according to instructions, the data parsing module 12 may address the storage unit, write data to the corresponding storage unit, send the data in the storage unit back to the shift register module 11 for serial output, output the data in the storage unit to the buffer register module 14 for output to the receiving module, or perform other operations. In some embodiments, the data parsing process can be controlled by a reset signal, an input clock signal, and an input chip select signal. During the temporary storage of input data in the shift register module 11, the data parsing module 12 parses the data in the shift register module 11 to improve data transmission efficiency.

[0097] The following details the data parsing module 12's process of parsing data frames and operating on storage units for different types of data frame structures:

[0098] For the first type of data frame structure, as shown in Figure 4, the data frame structure includes a frame header, control bits, and data bits. This data frame has no address bits, and all data in the data bits is written to a default storage unit, thereby reducing the transmission time of address bits. As shown in Figure 6, the data parsing module 12 determines the operation mode, such as a write operation, based on the content of the control bits (e.g., instructions). When the operation mode is a write operation, the data in the data bits is written to the default storage unit (e.g., the first default storage unit). Specifically, in some embodiments, when the data parsing module 12 performs parsing, it first determines the frame parsing method according to the frame type register. The data parsing module 12 selects a fixed-length frame header from the data input by the shift register module 11 for comparison. Then, the data parsing module 12 selects a fixed-length control bit to determine whether to read data from the default storage unit, write data to the default storage unit, or perform other operations. Finally, the data parsing module 12 selects a fixed-length data as the data to be interacted with the default storage unit.

[0099] For the second type of data frame structure, as shown in Figure 4, the data frame structure includes a frame header, control bits, and address bits. This data frame does not include data bits; the data is pre-stored in a default memory unit. After addressing, the data is directly output to the buffer register module, thereby outputting to the external SPI, which can reduce the data bit transmission time. As shown in Figure 6, the data parsing module 12 determines the operation mode, such as a read operation or a write operation, based on the content of the control bits. When the operation mode is a write operation, the data in the default memory unit (e.g., the second default memory unit) is written to the memory unit corresponding to the address bit; or, when the operation mode is a read operation, the data is read from the memory unit corresponding to the address bit. Specifically, in some embodiments, when the data parsing module 12 performs parsing, it first determines the frame parsing method according to the frame type register. The data parsing module 12 selects a fixed-length frame header from the data input by the shift register module 11 for comparison. Then, the data parsing module 12 selects a fixed-length control bit to determine whether to read data from the storage unit, write data to the storage unit, or perform other operations. Subsequently, the data parsing module 12 selects a fixed-length address bit for addressing in the storage unit to determine which storage unit to write data to or read data from.

[0100] For the third type of data frame structure, as shown in Figure 4, the data frame only retains the data bits, eliminating the need for transmission and parsing of the frame header, control bits, and address bits. This results in faster transmission speeds, and the data in the data bits can be written to the default storage unit. As shown in Figure 6, the data parsing module 12 determines the operation mode based on the data in the default storage unit (e.g., the third default storage unit). The data in the default storage unit may include instructions from the control bits, and the operation mode can be determined based on these instructions. When the operation mode is a write operation, the data in the data bits is written to the default storage unit (e.g., the fourth default storage unit). The default storage unit is a pre-defined storage unit, and its location can be obtained without address bits. Specifically, in some embodiments, when the data parsing module 12 performs parsing, it first determines the frame parsing method based on the frame type register. The data parsing module 12 directly selects data from the data input by the shift register module 11 as the data to be interacted with in the default storage unit (e.g., the fourth default storage unit).

[0101] For the fourth type of data frame structure, as shown in Figure 4, the data frame structure includes a frame header and control bits. The data frame does not include address bits and data bits, as both address and data are default values. Therefore, the address bits and data bits do not need to be transmitted, saving transmission and parsing time. As shown in Figure 6, the data parsing module 12 determines the operation mode based on the content of the control bits. When the operation mode is a read operation, data is read from the default storage unit (e.g., the fifth default storage unit), or when the operation mode is a write operation, default data is written to the default storage unit. Specifically, in some embodiments, when the data parsing module 12 performs parsing, it first determines the frame parsing method based on the frame type register. The data parsing module 12 selects a fixed-length frame header from the data input by the shift register module 11 for comparison. Then, the data parsing module 12 selects a fixed-length control bit to determine whether to read data from the default storage unit, write data to the default storage unit, or perform other operations.

[0102] For the merged complete data frame structure, namely the fifth type of data frame structure, as shown in Figure 4, the data frame structure includes a frame header, control bits, address bits, and at least two data bits. The fifth type of data frame merges multiple data frames into one data frame. As long as the starting address is given, subsequent data is written sequentially into the storage units corresponding to the starting address and subsequent addresses, saving transmission and parsing time. As shown in Figure 6, the data parsing module 12 determines the operation mode based on the content of the control bits. When the operation mode is a write operation, the data is written sequentially into the data bits of multiple storage units, starting from the address indicated by the address bits. Specifically, in some embodiments, when the data parsing module 12 performs parsing, it first determines the frame parsing method according to the frame type register. The data parsing module 12 selects a fixed-length frame header from the data input by the shift register module 11 for comparison, and then selects a fixed-length control bit to determine whether to read data from the storage unit, write data to the storage unit, or perform other operations. After that, the data parsing module 12 selects a fixed-length address bit for addressing in the storage unit. The address bit is a starting address, corresponding to the memory unit where data 1 is to be written (its address is the starting address); the address to be addressed for data 2 is the starting address + X (X can be negative), that is, the address of the memory unit to be written for data 2 is the starting address + X; and so on, the address to be addressed for data n is the starting address + (n-1)X, and the address of the memory unit to be written for data n is the starting address + (n-1)X. The value of X can be stored in a specific memory unit (e.g., the sixth default memory unit), in the control bits of the frame, or permanently stored in the circuit. The value of X can be 1, 2, 3, etc., or -1, -2, -3, etc.

[0103] It should be noted that the serial digital interface 10 also has a readback function, which can detect whether the incoming data frame has errors. If an error is detected in the incoming data frame, it needs to be rewritten. Therefore, error correction can be performed through the readback function.

[0104] The aforementioned serial digital interface 10 is used in the beam control chip shown in Figure 1. As an SPI slave, the serial digital interface 10 receives data frames from the baseband. It parses the data frames and, based on the parsing results, sends the data to the amplitude modulators and / or phase shifters of multiple RF channels to simultaneously control the amplitude and / or phase of multiple RF channels, such as simultaneously controlling 16 or more RF channels. The serial digital interface 10 can be used and process different types of data frames in different scenarios. Different types of data frames have different lengths, allowing flexible access to the memory unit and improving data transmission capabilities, such as data transmission rates of 125 MHz and above. It can also correct SPI operating status errors by reading back data.

[0105] In some embodiments, the data transmission method of the beam control chip in FIG1 may include the following steps:

[0106] Step 1: Define the data frame. The defined data frame includes incomplete data frame structures and / or merged complete data frame structures (e.g., the five types of data frames shown in Figure 4). The data frame can be predefined. The correspondence between the data frame type and the decoding method is pre-stored in the serial digital interface 10, and the correspondence between the data frame type and the scene is pre-stored in the baseband processor. Based on the current scene, the processor selects a structure from the first to the fifth type of data frame and sends it to the beam control chip. Specific scenes are explained in detail below with reference to Figure 7.

[0107] Step 2: Acquire data frames using the data transmission pins of the beam control chip. The baseband processor sends data frames to the data transmission pins of the beam control chip via the SPI host. These data transmission pins can be independent of the input data signal interface SDI of the serial digital interface 10, but can also be connected to the input data signal interface SDI of the serial digital interface 10, sending the data frames to the input data signal interface SDI. Alternatively, the data transmission pin can also be the input data signal interface SDI of the serial digital interface 10, and the serial digital interface 10 acquires the data frames through these pins.

[0108] Step 3: Determine the structure type of the acquired data frame. Specifically, the serial digital interface 10 can determine the structure type of the acquired data frame through the data parsing module 12 in Figure 5, in order to correctly parse the data frame.

[0109] Step 4: Determine the parsing method for the acquired data frame based on the determined structure type. Specifically, the data parsing module 12 of the serial digital interface 10 can determine the parsing method for the data frame based on its structure type.

[0110] Step 5: According to the determined parsing method, parse the acquired data frame and operate on the storage unit. Specifically, the data parsing module 12 of the serial digital interface 10 can parse the acquired data frame. After parsing, the data parsing module 12 can also operate on the storage unit. For example, the data parsing module 12 can address the storage unit, write data to the corresponding storage unit, send the data in the storage unit back to the shift register module 11 in Figure 5 for serial output, or output the data in the storage unit to the buffer register module 14 in Figure 6 for output to the receiving module, or perform other operations.

[0111] The beam control chip will be explained in detail below with reference to Figure 7.

[0112] Referring to Figure 7, the beam control chip 40 may include a serial digital interface 10 and multiple radio frequency (RF) channels 21 as described in any of the preceding embodiments. The serial digital interface 10 is used to control the phase and / or amplitude of the RF channels 21. The RF channels 21 are RF signal transmission channels, including RF signal receiving channels 211 and RF signal transmitting channels 212, which are respectively connected between the antenna and the baseband. Each receiving channel 211 includes a phase shifter and an amplitude modulator. The phase shifter can be a receiver phase shifter (PS), and the amplitude modulator can be a receiver digital step attenuator (DSA). Each transmitting channel 212 includes a phase shifter and an amplitude modulator. The phase shifter can be a transmitter phase shifter (PS), and the amplitude modulator can be a transmitter digital step attenuator (DSA). The digital step attenuator (DSA) is used to adjust the signal strength; it can achieve signal attenuation by changing the resistor network. The phase shifter (PS) is used to change the signal phase; it can adjust the signal phase by shifting the phase of the input signal. The digital step attenuator (DSA) and phase shifter (PS) belonging to the same RF channel 21 are connected in series to attenuate and shift the signal.

[0113] Additionally, as shown in Figure 7, multiple RF channels 21 correspond to multiple antennas 0 to n (n is a positive integer). For example, antenna 0 is connected to the receiver digital step attenuator DSA 0 and the receiver phase shifter PS 0 to transmit the received signal, after modulation by the receiver digital step attenuator DSA 0 and the receiver phase shifter PS 0, to the baseband modem, etc. Simultaneously, antenna 0 is connected to the transmitter digital step attenuator DSA 0 and the transmitter phase shifter PS 0. The signal transmitted by the baseband modem, etc., is modulated by the transmitter digital step attenuator DSA 0 and the transmitter phase shifter PS 0 and then transmitted outward by antenna 0.

[0114] The beam control chip 40 also includes multiple selection (T / R selection) modules 22 for receiving selection signals and data transmitted by the serial digital interface 10 (not shown in Figure 7). It should be noted that the selection signals can specifically be transmit / receive (T / R) selection signals. The T / R selection signal refers to the selection signal between the receive channel 211 and the transmit channel 212; it is essentially a control signal that sends SPI data to the receive channel 211 or the transmit channel 212 according to different level states of the T / R selection signal.

[0115] In this embodiment, each T / R multiplexing module 22 corresponds to one RF channel 21. The T / R multiplexing module 22 is a receiving module that receives data from the serial digital interface 10 and is the object to which the serial digital interface 10 writes data. That is, the serial digital interface 10 is used to write data (including phase and amplitude) to the T / R multiplexing module 22. The T / R multiplexing module 22 sends the phase and amplitude to the receiving channel 211 and the transmitting channel 212. When the multiplexing signal is in the first level state, the phase and amplitude are output to the receiver phase shifter PS and the receiver digital step attenuator DSA of the receiving channel 211; when the multiplexing signal is in the second level state, the phase and amplitude are output to the transmitter phase shifter PS and the transmitter digital step attenuator DSA of the transmitting channel 212. The address of the storage unit corresponds to different RF channels 21. For example, the address of the storage unit is used to indicate which multiplexing module 22 to write data to.

[0116] In this embodiment, the data received by the T / R multiplexing module 22 includes information on two control signals, namely phase and amplitude. These two types of information can be sent to the phase shifter PS and the digital step attenuator DSA respectively using the following methods: The T / R multiplexing module 22 can be configured through two registers respectively. For example, 0x00 can be defined as the phase data (PS) of channel 0, and 0x01 can be defined as the amplitude data (DSA) of channel 0; or, it can be configured according to different bits. For example, 0x00 stores the phase and amplitude of channel 0, the first 8 bits are the phase data, and the last 8 bits are the amplitude data, but there is no limitation on this.

[0117] Here, the first level state can be a high level state, such as logic 1; the second level state can be a low level state, such as logic 0, but there is no specific limitation on this.

[0118] In this embodiment, the address of the storage unit corresponds to different radio frequency channels 21. For example, the storage unit with address 0x00 stores the amplitude and phase data of channel 0, the storage unit with address 0x01 stores the amplitude and phase data of channel 1, and so on.

[0119] The following section explains how beam control chips modify amplitude and phase information via SPI, using different scenarios as examples.

[0120] In some embodiments, as shown in FIG7, a first type of data frame structure is selected in the first scenario. The first scenario involves continuously changing the data of the same receiving module, writing different data to the amplitude and phase information of a certain RF channel 21 and immediately outputting it to the RF channel 21 (i.e., the phase shifter and attenuator). This can be achieved by continuously reading and writing to the memory unit corresponding to the same address (i.e., the default memory unit). In the first type of data frame structure, when the content of the control bit indicates a write operation, the data parsing module 12 writes the data in the data bits to the default memory unit and sends the data written to the default memory unit to the corresponding T / R multiplexing module 22. By changing the data in the data bits, the amplitude and phase information in the corresponding RF channel 21 can be continuously changed.

[0121] In the second scenario, a second type of data frame structure is selected. This second scenario involves writing periodic data to the receiving module, continuously writing periodic data to the amplitude and phase information of a certain RF channel 21. The second type of data frame structure does not include data bits; the periodic data (i.e., the default data) can be pre-stored in multiple storage units, eliminating the need to send data bits and reducing data bit transmission and parsing time. The data parsing module 12 parses the address bits in the data frame and sends the data from the storage unit corresponding to that address bit to the predetermined RF channel 21 via the T / R multiplexing module 22. The predetermined RF channel 21 is the default RF channel in the second scenario, i.e., the system's default RF channel when no specification is required. By changing the address bits, periodic data from multiple storage units can be sequentially written to the predetermined RF channel 21, thereby continuously writing periodic data to the amplitude and phase information of a certain RF channel 21.

[0122] In the third scenario, a third type of data frame structure is selected. This third scenario involves changing the data of all receiving modules, continuously writing different data to the amplitude and phase information of all RF channels 21. The third type of data frame structure does not include a frame header, control bits, or address bits, eliminating the need for transmission and parsing of these elements, thus saving transmission and parsing time. The data parsing module 12 writes the data bits into the default storage unit and sends the written data to all RF channels 21 via the T / R multiplexing module 22 to change the amplitude and phase information of all RF channels 21. By changing the data bits, the amplitude and phase information of all RF channels 21 can be continuously changed.

[0123] In the fourth scenario, the fourth type of data frame structure is selected. This fourth scenario involves reading temperature data from the default storage unit to continuously monitor the internal temperature data of the SPI. The temperature data is collected by the internal temperature sensor of the SPI and stored in one or more default storage units. Since only data is read from the default storage units in the SPI, the data frame structure does not need to include data bits. Because the data frame does not include data bits, there is no need to transmit and parse data bits, thus improving the reading speed. When the data frame structure is of type fourth, the content of the control bits indicates a read operation. The data parsing module 12 reads the temperature data from the default storage unit and outputs the read temperature data. At this time, the temperature data in the default storage unit can be transmitted to the shift register module 11 and serially output through the SDO interface.

[0124] In the fifth scenario, the fifth type of data frame structure is selected. This fifth scenario involves modifying data from a portion of the receiving module, specifically modifying only the amplitude and phase information of a portion of the RF channels 21. Because it involves rewriting the data (amplitude and / or phase information) of a portion of the RF channels 21, multiple data frames can be merged into one. By selecting only the starting address of the amplitude and phase information to be modified and writing the data to be changed, the data of a portion of the RF channels 21 can be modified, reducing the number of data frame transmissions and saving data frame resources. Specifically, the control bit indicates a write operation, writing data 1 to data n to multiple storage units respectively, and the address bit indicates the starting address of the multiple storage units. The data parsing module 12, based on the starting address, sequentially writes data 1 to data n to the multiple storage units and sequentially sends the written data to the multiple RF channels 21 corresponding to the multiple storage units to modify the data of a portion of the RF channels.

[0125] In some embodiments, the buffer register module 14 includes multiple registers, each of which obtains multiple data from the storage unit. When multiple data are stored in the buffer register module 14, the multiple data are output in parallel to multiple radio frequency channels 21, so that the amplitude and phase information of the radio frequency channels 21 change simultaneously, thereby synchronously modifying the beam information of each radio frequency channel 21 and preventing the generation of beam signal time differences.

[0126] It should be noted that this embodiment is not limited to these five application scenarios and five data frame types.

[0127] It should also be noted that the serial digital interface 10 can simultaneously write amplitude and phase information for no less than 16 channels, and operates normally at a clock rate of 125MHz or higher.

[0128] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0129] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0130] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0131] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0132] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0133] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0134] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0135] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A serial digital interface, characterized in that, It includes a shift register module, a data parsing module, and multiple storage units, wherein the storage units are used to store data; The shift register module is used to receive external data frames and transmit the data frames to the data parsing module; wherein, the complete data frame structure includes a frame header, control bits, address bits and data bits, and the received data frame includes an incomplete data frame structure and / or a merged complete data frame structure, wherein the merged data frame structure has the same address bits; The data parsing module is used for: Acquire the data frame; Determine the structure type of the acquired data frame; Based on the determined structure type, determine the parsing method for the acquired data frame; The acquired data frame is parsed according to the determined parsing method, and the storage unit is operated on.

2. The serial digital interface according to claim 1, characterized in that, The incomplete data frame structure includes at least one of the following types: The data frame structure of the first type includes the frame header, the control bits, and the data bits; The second type of data frame structure includes the frame header, the control bits, and the address bits; The third type of data frame structure has the data bits; The fourth type of data frame structure includes the frame header and the control bits; The merged complete data frame structure includes the frame header, the control bits, the address bits, and multiple data bits; The plurality of data bits are used to write data to the plurality of storage units; The step of parsing the acquired data frame and operating the storage unit includes: For the data frame structure of the first type, the data parsing module determines the operation mode based on the content of the control bits; when the operation mode is a write operation, the data in the data bits is written into the default storage unit. For the data frame structure of the second type, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a write operation, the data in the default storage unit is written into the storage unit corresponding to the address bit, or when the operation mode is a read operation, the data is read from the storage unit corresponding to the address bit. For the data frame structure of the third type, the data parsing module determines the operation mode based on the data in the default storage unit; when the operation mode is a write operation, the data of the data bits is written into the default storage unit. For the data frame structure of the fourth type, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a read operation, data is read from the default storage unit, or when the operation mode is a write operation, default data is written to the default storage unit. For the merged complete data frame structure, the data parsing module determines the operation mode according to the content of the control bit; when the operation mode is a write operation, the data in the data bit is written sequentially to the multiple storage units, starting from the address indicated by the address bit.

3. The serial digital interface according to claim 2, characterized in that, The data in the storage unit is used to send to the corresponding receiving module; When the data of the same receiving module is changed continuously, the data frame of the first type is selected; When periodic data is written to the receiving module, the data frame of the second type is selected; When the data of all the receiving modules is changed, the data frame of the third type is selected; When reading temperature data from the default storage unit, the fourth type of data frame is selected; When the data of a portion of the receiving module is changed, the merged complete data frame is selected.

4. The serial digital interface according to any one of claims 1 to 3, characterized in that, Also includes: The frame type register is used to store the structure type of the current data frame. The data parsing module is further configured to: obtain the structure type stored in the frame type register, wherein the stored structure type is the structure type of the current data frame.

5. The serial digital interface according to claim 4, characterized in that, The current data frame also includes the structure type of the next data frame; The data parsing module is also used to: write the structure type of the next data frame into the frame type register.

6. The serial digital interface according to claim 5, characterized in that, The control bit includes the structure type of the next data frame; or, the address bit includes the structure type of the next data frame.

7. The serial digital interface according to any one of claims 1 to 3, characterized in that, Also includes: A cache register module is used to acquire data from the storage unit and output the data from the storage unit in parallel to the corresponding receiving module.

8. The serial digital interface according to any one of claims 1 to 3, characterized in that, The shift register module is also used to serially output the data of the storage unit according to the parsing result.

9. The serial digital interface according to any one of claims 1 to 3, characterized in that, Also includes: Input side includes input data signal interface, input clock signal interface, and temperature code interface; Output clock signal interface and output data signal interface on the output side.

10. A beam control chip, characterized in that, The beam control chip includes multiple radio frequency channels and a serial digital interface as described in any one of claims 1-9; The serial digital interface is used to control the phase and / or amplitude of the radio frequency channel; the address of the storage unit corresponds to different radio frequency channels.

11. A data transmission method for a beam control chip, characterized in that, include: Define a data frame, which includes an incomplete data frame structure and / or a merged complete data frame structure, wherein the complete data frame structure includes a frame header, control bits, address bits, and data bits; The data frame is acquired using the data transmission pin of the beam control chip; Determine the structure type of the acquired data frame; Based on the determined structure type, determine the parsing method for the acquired data frame; The acquired data frame is parsed according to the determined parsing method, and the storage unit is operated.

12. The data transmission method according to claim 11, characterized in that, When the structure type of the acquired data frame is the merged complete data frame structure, the step of parsing the acquired data frame and operating the storage unit includes: Based on the content of the control bit, the operation mode is determined; when the operation mode is a write operation, the data in the data bit is written sequentially to the multiple storage cells, starting from the address indicated by the address bit.

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