Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus and system. Specifically, data processing including QPSK mapping is performed on p RS-coded first data streams to obtain multiple DP-QPSK symbol streams, wherein each DP-QPSK symbol stream comprises a QPSK symbol stream in a first polarization direction and a QPSK symbol stream in a second polarization direction. Compared with a cascaded FEC transmission scheme, the embodiments of the present application do not require cascaded FEC coding before data processing including QPSK mapping, such that multiple DP-QPSK symbol streams to be transmitted have a lower bit rate and a lower baud rate. Thus, the data processing method provided by the embodiments of the present application has the advantages of low complexity, low power consumption, and low latency, etc., and can be applied in multiple transmission scenarios, especially in future coherent transmission scenarios exceeding 800 Gbps (such as 1.6 Tbps).

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese Patent Application No. 202410511318.X, filed on April 25, 2024, entitled “A Data Processing Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information.

[0004] Forward error correction (FEC) coding is used to correct transmission errors, resolving transmission errors and recovering the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, performs symbol mapping on the bit sequence resulting from the second FEC encoding to generate a corresponding symbol sequence, and finally transmits the generated symbol sequence to the receiving end via optical fiber. The second FEC encoding typically uses soft-decision decoding, which has high complexity and power consumption. Furthermore, convolutional interleaving is performed between the first and second FEC encodings to improve the overall performance of the cascaded FEC scheme, but this results in higher latency. Existing cascaded FEC coding schemes cannot meet the requirements of low complexity, low power consumption, and low latency coherent scenarios with speeds of 800Gbps or higher (such as 1.6Tbps), which is an urgent problem to be solved in the future. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system. These methods offer advantages such as low complexity, low power consumption, and low latency, making them applicable to a wide range of transmission scenarios, particularly suitable for future coherent transmission scenarios exceeding 800Gbps (e.g., 1.6Tbps).

[0006] In a first aspect, embodiments of this application provide a data processing method. Specifically, p first data streams encoded by Reed-Solomon (RS) are first acquired, where p is a positive integer multiple of 4 and p is an integer power of 2. Then, the p first data streams are subjected to data processing including quadrature phase shift keying (QPSK) to obtain multiple dual-polarization (DP) QPSK symbol streams, each DP-QPSK symbol stream including a QPSK symbol stream in a first polarization direction and a QPSK symbol stream in a second polarization direction.

[0007] In this embodiment, p RS-encoded first data streams undergo data processing including QPSK mapping to obtain multiple DP-QPSK symbol streams. Compared to the concatenated FEC encoding scheme, this embodiment does not require concatenated FEC encoding before the QPSK mapping data processing, resulting in lower bit rates and baud rates for the multiple DP-QPSK symbol streams to be transmitted. Furthermore, since concatenated FEC encoding typically uses soft-decoding for the internal code, requiring soft value information, the overall power consumption of this embodiment is lower. Additionally, compared to differential quadrature phase shift keying (DQPSK) modulation, the QPSK modulation used in this embodiment has better performance. It can be seen that the data processing method provided by this embodiment has advantages such as low complexity, low power consumption, and low latency, and can be applied to many transmission scenarios, especially suitable for future coherent transmission scenarios above 800Gbps (e.g., 1.6Tbps).

[0008] In some possible implementations, performing data processing including QPSK mapping on p first data streams to obtain multiple DP-QPSK symbol streams includes: performing data processing including QPSK mapping and framing on p first data streams to obtain multiple DP-QPSK symbol streams. It should be understood that framing here can also be referred to as DSP framing. This application does not limit the order in which QPSK mapping and framing are performed. If QPSK mapping is performed first and then framing, the target symbol sequence is inserted through framing. If framing is performed first and then QPSK mapping, the target bit sequence is inserted through framing, and the target bit sequence is then processed by QPSK mapping to obtain the target symbol sequence. It should be understood that adding framing operations helps improve the signal quality recovered by the receiver.

[0009] In some possible implementations, data processing involving QPSK mapping and framing of the p first data streams includes: performing QPSK mapping and framing on every two first data streams to obtain one DP-QPSK symbol stream. Specifically, two consecutive bits from each data stream participating in the QPSK mapping are mapped to obtain one QPSK symbol. It should be understood that the four bits mapped to one DP-QPSK symbol come from two data streams, which helps to combat colored noise.

[0010] In some possible implementations, QPSK mapping and framing of every two first data streams in p first data streams includes one of the following methods, enriching the implementation options of this scheme. Method 1: Perform QPSK mapping on one of the two first data streams to obtain a first QPSK symbol stream, and insert a target symbol sequence into the first QPSK symbol stream to obtain a DP-QPSK symbol stream in one polarization direction. Method 2: Insert a target bit sequence into one of the two first data streams to obtain a second data stream, and perform QPSK mapping on the second data stream to obtain a DP-QPSK symbol stream in one polarization direction, wherein the target bit sequence is QPSK mapped to obtain the target symbol sequence. Method 3: Perform QPSK mapping on one of the two first data streams to obtain the I component data stream and Q component data stream of the first QPSK symbol stream. Insert the I component of the target symbol sequence into the I component data stream and insert the Q component of the target symbol sequence into the Q component data stream to obtain a DP-QPSK symbol stream in one polarization direction.

[0011] In some possible implementations, data processing involving QPSK mapping on p first data streams includes: interleaving every two first data streams from the p first data streams, wherein each interleaved first data stream includes bits from one of the first data streams before interleaving and bits from the other first data stream before interleaving. That is, the interleaving here is an operation of shuffling the bit order of the two first data streams, not an independent interleaving of each first data stream to shuffle the order. Then, QPSK mapping and framing are performed on every two interleaved first data streams to obtain one DP-QPSK symbol stream. It should be understood that interleaving before QPSK mapping and framing helps to reduce the impact of polarization-determined loss (PDL) in the X and Y polarization directions.

[0012] In some possible implementations, interleaving every two first data streams in p first data streams includes one of the following methods. Interleaving Method 1: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams; interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0c1d1d2a2b3c3 and 8 bits c0d0a1b1b2c2d3a3, where the 8 bits a0b0c1d1d2a2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0a1b1b2c2d3a3 correspond to 4 QPSK symbols in the other polarization direction. Interleaving Method 2: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams; interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0d1a1c2d2b3c3 and 8 bits c0d0b1c1a2b2d3a3, where the 8 bits a0b0d1a1c2d2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0b1c1a2b2d3a3 correspond to 4 QPSK symbols in the other polarization direction. It should be understood that the above interleaving method enables consecutive bits in each first data stream to be uniformly mapped to QPSK symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0013] In some possible implementations, for scenarios where QPSK mapping is performed before framing: Based on interleaving method 1, the four QPSK symbols corresponding to the eight bits a0b0c1d1d2a2b3c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0a1b1b2c2d3a3 are consecutive in one DP-QPSK symbol stream. Based on interleaving method 2, the four QPSK symbols corresponding to the eight bits a0b0d1a1c2d2b3c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0b1c1a2b2d3a3 are consecutive in one DP-QPSK symbol stream.

[0014] In some possible implementations, data processing involving QPSK mapping and framing of the p first data streams includes: performing QPSK mapping and framing on every four first data streams to obtain one DP-QPSK symbol stream, wherein two bits from each of the two data streams involved in the QPSK mapping are mapped to obtain one QPSK symbol. It should be understood that the four bits mapped to one DP-QPSK symbol come from four data streams, which helps to combat colored noise.

[0015] In some possible implementations, QPSK mapping and framing of every four first data streams in p first data streams includes one of the following methods, enriching the implementation options of this scheme. Method 1: Perform QPSK mapping on two of the four first data streams to obtain a second QPSK symbol stream. Insert a target symbol sequence into the second QPSK symbol stream to obtain a DP-QPSK symbol stream in one polarization direction. Method 2: Insert a target bit sequence into two of the four first data streams to obtain two third data streams. Perform QPSK mapping on the two third data streams to obtain a DP-QPSK symbol stream in one polarization direction, wherein the target bit sequence is QPSK mapped to obtain the target symbol sequence. Method 3: Perform QPSK mapping on two of the four first data streams to obtain the I component data stream and Q component data stream of the second QPSK symbol stream. Insert the I component of the target symbol sequence into the I component data stream and insert the Q component of the target symbol sequence into the Q component data stream to obtain a DP-QPSK symbol stream in one polarization direction.

[0016] In some possible implementations, data processing involving QPSK mapping on the p first data streams includes: interleaving every four first data streams from the p first data streams, performing QPSK mapping and framing on every four interleaved first data streams to obtain one DP-QPSK symbol stream. It should be understood that interleaving before QPSK mapping and framing helps to reduce the impact of polarization-determined loss (PDL) in the X and Y polarization directions.

[0017] In some possible implementations, interleaving every four first data streams in p first data streams includes one of the following methods: Interleaving Method 1: Obtain four consecutive bits a0a1a2a3 from the first first data stream, four consecutive bits b0b1b2b3 from the second first data stream, four consecutive bits c0c1c2c3 from the third first data stream, and four consecutive bits d0d1d2d3 from the fourth first data stream; Interleave the four consecutive bits a0a1a2a3 and the four consecutive bits b0b1b2... b3. Four consecutive bits c0c1c2c3 and four consecutive bits d0d1d2d3 are interleaved to obtain four bits a0c1d2b3, four bits b0d1a2c3, four bits c0a1b2d3 and four bits d0b1c2a3. The four bits a0c1d2b3 and four bits b0d1a2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0a1b2d3 and four bits d0b1c2a3 correspond to four QPSK symbols in another polarization direction. Interleaving method 2: Obtain 4 consecutive bits a0a1a2a3 from the first data stream of the 4 first data streams, 4 consecutive bits b0b1b2b3 from the second data stream of the 4 first data streams, 4 consecutive bits c0c1c2c3 from the third data stream of the 4 first data streams, and 4 consecutive bits d0d1d2d3 from the fourth data stream of the 4 first data streams. Four consecutive bits a0a1a2a3, four consecutive bits b0b1b2b3, four consecutive bits c0c1c2c3, and four consecutive bits d0d1d2d3 are interleaved to obtain four bits a0d1c2b3, four bits b0a1d2c3, four bits c0b1a2d3, and four bits d0c1b2a3. The four bits a0d1c2b3 and four bits b0a1d2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0b1a2d3 and four bits d0c1b2a3 correspond to four QPSK symbols in the other polarization direction. It should be understood that this interleaving method ensures that consecutive bits in each first data stream are uniformly mapped to QPSK symbols in both the X and Y polarization directions, which is beneficial for combating PDL impairments.

[0018] In some possible implementations, for scenarios where QPSK mapping is performed before framing: Based on interleaving method 1, the four QPSK symbols corresponding to 4 bits a0c1d2b3 and 4 bits b0d1a2c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to 4 bits c0a1b2d3 and 4 bits d0b1c2a3 are consecutive in one DP-QPSK symbol stream. Based on interleaving method 2, the four QPSK symbols corresponding to 4 bits a0d1c2b3 and 4 bits b0a1d2c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to 4 bits c0b1a2d3 and 4 bits d0c1b2a3 are consecutive in one DP-QPSK symbol stream.

[0019] In some possible implementations, each DP-QPSK symbol stream includes multiple DP-QPSK symbol sequences, and a fixed position in each DP-QPSK symbol sequence includes a target symbol sequence inserted by framing. The target symbol sequence includes at least one of frame synchronization symbol sequences, training symbol sequences, reserved symbol sequences, and pilot symbol sequences, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0020] In some possible implementations, the target symbol sequence includes a pilot symbol sequence, where each DP-QPSK symbol sequence is N times the number of QPSK symbol sequences in any polarization direction. G Each symbol includes one pilot symbol, where N G = 32, 64, 128, 35, 41, 69, 86, 171, 341, or 681. It should be understood that if N... G The integer power of 2, such as 32, 64, or 128, facilitates the hardware implementation of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). If N... G The baud rates are 35, 41, 69, 86, 171, 341, or 681, with a clock frequency of 156.25MHz. The baud rate is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, and can perform fast phase locking. The phase-locked loop (PLL) has low complexity and low jitter.

[0021] In some possible implementations, each DP-QPSK symbol stream includes an I-path component of the QPSK symbol stream in a first polarization direction, a Q-path component of the QPSK symbol stream in a second polarization direction, and an I-path component of the QPSK symbol stream in a second polarization direction. It should be understood that the four component signals of the QPSK symbol stream are processed by a DAC to obtain four analog signals to be transmitted.

[0022] In some possible implementations, performing data processing including QPSK mapping on p first data streams to obtain multiple DP-QPSK symbol streams includes: performing data processing including QPSK mapping on p first data streams to obtain q DP-QPSK symbol streams, where q = p / 2 or q = p / 4. That is, it can be that every two first data streams undergo data processing including QPSK mapping to obtain one DP-QPSK symbol stream, or every four first data streams undergo data processing including QPSK mapping to obtain one DP-QPSK symbol stream, thus adapting to various different scenarios.

[0023] In some possible implementations, p = 8, q = p / 2 = 4; or p = 16, q = p / 4 = 4 or q = p / 2 = 8; or p = 32, q = p / 4 = 8. This provides multiple correspondences between the values ​​of p and q, expanding the application scenarios of this scheme.

[0024] In some possible implementations, each a in each first data stream RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS The RS code length is a power of 2 greater than or equal to 4. For example, in each first data stream, every four adjacent RS symbols come from four RS codewords. The code length of the RS code is counted in units of symbols, and the symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code, which has a code length of 544 RS symbols, meaning that an RS codeword includes 544 RS symbols, and one RS symbol contains 10 bits. The fact that every four adjacent RS symbols in each first data stream come from four RS codewords provides good resistance to colored noise.

[0025] In some possible implementations, the p first data streams are obtained by processing 16 fourth data streams through a symbol-multiplexed Physical Media Attachment (PMA) layer. These 16 fourth data streams are obtained by processing the service data to be transmitted through a Physical Coding Sublayer (PCS) including RS encoding. This provides a specific implementation method for processing the service data to be transmitted to obtain the p first data streams, improving the completeness of this solution.

[0026] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing, and t signals are obtained from 16 fourth data streams through 16:t PMA processing, where t is a positive integer multiple of 4. This provides a scheme for obtaining p first data streams by performing two-step PMA processing on the second data stream after PCS processing, which is well compatible with the application scenario shown in Figure 2. One step of the PMA processing is performed by the sending device, and the other step is performed by the sending processing module.

[0027] In some possible implementations, p first data streams are obtained by processing 16 fourth data streams through 16:p PMA. Here, a scheme is provided to obtain p first data streams by performing a one-step PMA process on the second data stream after PCS processing, which is well compatible with the application scenario shown in Figure 3. This PMA process is performed by the sending device.

[0028] In some possible implementations, the p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing. That is, for the application scenario shown in Figure 2, the sending processing module obtains the p first data streams by performing t:p PMA processing based on symbol multiplexing on t signals from the sending device, thus improving the data processing flow of the sending processing module.

[0029] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 8, p = 16; or t = 16, p = 16. Several possible implementations of the t:p PMA processing are given here, which improves the scalability of this solution.

[0030] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding. This provides a method to directly obtain p first data streams by PCS processing of the service data to be sent, without requiring PMA processing, allowing for flexible selection of different implementation methods according to actual needs.

[0031] In some possible implementations, the data processing method provided in this application is applied to scenarios including Ethernet, optical transport networks, and space optical communication.

[0032] Secondly, embodiments of this application provide a data processing apparatus, comprising an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2. The processing unit is configured to perform data processing on the p first data streams, including orthogonal phase shift keying (QPSK) mapping, to obtain multiple dual-polarization DP-QPSK symbol streams, each DP-QPSK symbol stream including a QPSK symbol stream in a first polarization direction and a QPSK symbol stream in a second polarization direction.

[0033] In some possible implementations, the processing unit is specifically used to perform data processing, including QPSK mapping and framing, on p first data streams to obtain multiple DP-QPSK symbol streams.

[0034] In some possible implementations, the processing unit is specifically used to perform QPSK mapping and framing on every two first data streams in p first data streams to obtain one DP-QPSK symbol stream. Specifically, two consecutive bits from each data stream participating in the QPSK mapping are mapped to obtain one QPSK symbol.

[0035] In some possible implementations, the processing unit is specifically configured to perform one of the following methods: Method 1: Perform QPSK mapping on one of the two first data streams to obtain a first QPSK symbol stream, and insert a target symbol sequence into the first QPSK symbol stream to obtain a DP-QPSK symbol stream in one polarization direction. Method 2: Insert a target bit sequence into one of the two first data streams to obtain a second data stream, and perform QPSK mapping on the second data stream to obtain a DP-QPSK symbol stream in one polarization direction, wherein the target bit sequence is QPSK mapped to obtain a target symbol sequence. Method 3: Perform QPSK mapping on one of the two first data streams to obtain an I-component data stream and a Q-component data stream of the first QPSK symbol stream, insert the I-component of the target symbol sequence into the I-component data stream and insert the Q-component of the target symbol sequence into the Q-component data stream to obtain a DP-QPSK symbol stream in one polarization direction.

[0036] In some possible implementations, the processing unit is specifically used to interleave every two first data streams from p first data streams, wherein each interleaved first data stream includes bits from one of the first data streams before interleaving and bits from the other first data stream before interleaving. Then, QPSK mapping and framing are performed on every two interleaved first data streams to obtain one DP-QPSK symbol stream.

[0037] In some possible implementations, the processing unit is specifically used to combine every two first data streams in p first data streams and perform one of the following interleaving methods. Interleaving Method 1: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams; interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0c1d1d2a2b3c3 and 8 bits c0d0a1b1b2c2d3a3, where the 8 bits a0b0c1d1d2a2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0a1b1b2c2d3a3 correspond to 4 QPSK symbols in the other polarization direction. Interleaving Method 2: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams; interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0d1a1c2d2b3c3 and 8 bits c0d0b1c1a2b2d3a3, where the 8 bits a0b0d1a1c2d2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0b1c1a2b2d3a3 correspond to 4 QPSK symbols in the other polarization direction.

[0038] In some possible implementations, based on interleaving mode 1, the four QPSK symbols corresponding to the eight bits a0b0c1d1d2a2b3c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0a1b1b2c2d3a3 are consecutive in one DP-QPSK symbol stream; based on interleaving mode 2, the four QPSK symbols corresponding to the eight bits a0b0d1a1c2d2b3c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0b1c1a2b2d3a3 are consecutive in one DP-QPSK symbol stream.

[0039] In some possible implementations, the processing unit is specifically used to perform data processing on p first data streams, including QPSK mapping and framing, by: performing QPSK mapping and framing on every four first data streams in the p first data streams to obtain one DP-QPSK symbol stream. Specifically, two bits from each of the two data streams participating in the QPSK mapping are mapped to obtain one QPSK symbol.

[0040] In some possible implementations, the processing unit is specifically configured to perform one of the following methods: Method 1: Perform QPSK mapping on two of the four first data streams to obtain a second QPSK symbol stream, and insert a target symbol sequence into the second QPSK symbol stream to obtain a DP-QPSK symbol stream in one polarization direction. Method 2: Insert a target bit sequence into two of the four first data streams to obtain two third data streams, and perform QPSK mapping on the two third data streams to obtain a DP-QPSK symbol stream in one polarization direction, wherein the target bit sequence is QPSK mapped to obtain a target symbol sequence. Method 3: Perform QPSK mapping on two of the four first data streams to obtain the I-component data stream and the Q-component data stream of the second QPSK symbol stream, insert the I-component of the target symbol sequence into the I-component data stream and insert the Q-component of the target symbol sequence into the Q-component data stream to obtain a DP-QPSK symbol stream in one polarization direction.

[0041] In some possible implementations, the processing unit is specifically used to interleave every 4 first data streams in p first data streams, and to perform QPSK mapping and framing on every 4 interleaved first data streams to obtain 1 DP-QPSK symbol stream.

[0042] In some possible implementations, the processing unit is specifically used to combine every two first data streams in p first data streams and perform one of the following interleaving methods. Interleaving method 1: Obtain four consecutive bits a0a1a2a3 from the first first data stream of the four first data streams, four consecutive bits b0b1b2b3 from the second first data stream of the four first data streams, four consecutive bits c0c1c2c3 from the third first data stream of the four first data streams, and four consecutive bits d0d1d2d3 from the fourth first data stream of the four first data streams; and interleave the four consecutive bits a0a1a2a3 and the four consecutive bits b0b1b2... b3. Four consecutive bits c0c1c2c3 and four consecutive bits d0d1d2d3 are interleaved to obtain four bits a0c1d2b3, four bits b0d1a2c3, four bits c0a1b2d3 and four bits d0b1c2a3. The four bits a0c1d2b3 and four bits b0d1a2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0a1b2d3 and four bits d0b1c2a3 correspond to four QPSK symbols in another polarization direction. Interleaving method 2: Obtain 4 consecutive bits a0a1a2a3 from the first data stream of the 4 first data streams, 4 consecutive bits b0b1b2b3 from the second data stream of the 4 first data streams, 4 consecutive bits c0c1c2c3 from the third data stream of the 4 first data streams, and 4 consecutive bits d0d1d2d3 from the fourth data stream of the 4 first data streams. Four consecutive bits a0a1a2a3, four consecutive bits b0b1b2b3, four consecutive bits c0c1c2c3, and four consecutive bits d0d1d2d3 are interleaved to obtain four bits a0d1c2b3, four bits b0a1d2c3, four bits c0b1a2d3, and four bits d0c1b2a3. The four bits a0d1c2b3 and four bits b0a1d2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0b1a2d3 and four bits d0c1b2a3 correspond to four QPSK symbols in another polarization direction.

[0043] In some possible implementations, based on interleaving mode 1, the four QPSK symbols corresponding to 4 bits a0c1d2b3 and 4 bits b0d1a2c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to 4 bits c0a1b2d3 and 4 bits d0b1c2a3 are consecutive in one DP-QPSK symbol stream. Based on interleaving mode 2, the four QPSK symbols corresponding to 4 bits a0d1c2b3 and 4 bits b0a1d2c3 are consecutive in one DP-QPSK symbol stream, and the four QPSK symbols corresponding to 4 bits c0b1a2d3 and 4 bits d0c1b2a3 are consecutive in one DP-QPSK symbol stream.

[0044] In some possible implementations, each DP-QPSK symbol stream includes multiple DP-QPSK symbol sequences, and a fixed position in each DP-QPSK symbol sequence includes a target symbol sequence inserted by framing. The target symbol sequence includes at least one of frame synchronization symbol sequences, training symbol sequences, reserved symbol sequences, and pilot symbol sequences, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0045] In some possible implementations, the target symbol sequence includes a pilot symbol sequence, where each DP-QPSK symbol sequence is N times the number of QPSK symbol sequences in any polarization direction. G Each symbol includes one pilot symbol, where N G =32, 64, 128, 35, 41, 69, 86, 171, 341 or 681.

[0046] In some possible implementations, each DP-QPSK symbol stream includes an I-path component of the QPSK symbol stream in a first polarization direction, a Q-path component of the QPSK symbol stream in a first polarization direction, an I-path component of the QPSK symbol stream in a second polarization direction, and a Q-path component of the QPSK symbol stream in a second polarization direction.

[0047] In some possible implementations, the processing unit is specifically used to perform data processing, including QPSK mapping, on p first data streams to obtain q DP-QPSK symbol streams, where q = p / 2 or q = p / 4.

[0048] In some possible implementations, p = 8, q = p / 2 = 4; or, p = 16, q = p / 4 = 4 or q = p / 2 = 8; or, p = 32, q = p / 4 = 8.

[0049] In some possible implementations, each a in each first data stream RS The adjacent RS symbols are respectively from a RSOne RS codeword, a RS An integer power greater than or equal to 4 and equal to 2. For example, in each first data stream, every four adjacent RS symbols come from four RS codewords.

[0050] In some possible implementations, p first data streams are obtained by PMA processing based on symbol multiplexing from 16 fourth data streams, and the 16 fourth data streams are obtained by PCS processing including RS encoding from the service data to be sent.

[0051] In some possible implementations, p first data streams are obtained by processing t signals through t:p PMA, and t signals are obtained by processing 16 fourth data streams through 16:t PMA, where t is a positive integer multiple of 4.

[0052] In some possible implementations, p first data streams are obtained by processing 16 fourth data streams through 16:p PMA.

[0053] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing.

[0054] In some possible implementations, t = 8, p = 8; or, t = 16, p = 8; or, t = 8, p = 16; or, t = 16, p = 16.

[0055] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding.

[0056] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0057] Thirdly, embodiments of this application provide a chip for performing the method as described in any of the embodiments of the first aspect.

[0058] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0059] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0060] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to execute the method described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0061] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0062] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0063] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0064] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0065] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0066] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0067] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0068] Figure 5(a) is a data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0069] Figure 5(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0070] Figure 5(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0071] Figure 5(d) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0072] Figure 5(e) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0073] Figure 6(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application;

[0074] Figure 6(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0075] Figure 6(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0076] Figure 7 is a schematic diagram of several implementation methods for QPSK mapping and framing of the first data stream in the embodiments of this application;

[0077] Figure 8(a) is a schematic diagram of an implementation method for QPSK mapping and DSP framing of p first data streams in this application;

[0078] Figure 8(b) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application embodiment;

[0079] Figure 9(a) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application embodiment;

[0080] Figure 9(b) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application embodiment;

[0081] Figure 10(a) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0082] Figure 10(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0083] Figure 11(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application;

[0084] Figure 11(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0085] Figure 12 is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0086] Figure 13 is a schematic diagram of a data processing device in an embodiment of this application;

[0087] Figure 14 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0088] Figure 15 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0089] This application provides a data processing method, apparatus, and system. These methods offer advantages such as low complexity, low power consumption, and low latency, making them applicable to a wide range of transmission scenarios, particularly suitable for future coherent transmission scenarios exceeding 800Gbps (e.g., 1.6Tbps).

[0090] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0091] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting end device 01, transmitting end processing module 02, channel transmission medium 03, receiving end processing module 04, and receiving end device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0092] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs Reed-Solomon (RS) encoding on the data and then transmits the RS-encoded data to the transmitting processing module 02. The transmitting processing module 02 performs quadrature phase shift keying (QPSK) mapping on the RS-encoded data to obtain q dual-polarization (DP) QPSK symbol streams (DP-QPSK signals). The q DP-QPSK symbol streams are transmitted to the receiving processing module 04 via the channel transmission medium 03. The receiving processing module 04 performs DP-QPSK demapping on the received q DP-QPSK symbol streams and transmits the demapping data to the receiving device 05. The receiving device 05 decodes the received data.

[0093] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs RS encoding and QPSK mapping to obtain q DP-QPSK symbol streams and sends them to the transmission medium 03. The receiving device 05 performs DP-QPSK demapping and decoding on the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0094] It should be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0095] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0096] 101. Obtain p first data streams after RS ​​encoding.

[0097] In this embodiment, all p first data streams are RS-encoded data streams. It should be noted that the code length of the RS code in this embodiment is counted in units of symbols; the symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, meaning that an RS codeword includes 544 RS symbols, and one RS symbol contains 10 bits. Specifically, in each first data stream, every four adjacent RS symbols come from four RS codewords, where p is an integer multiple of 4 and a power of 2. Typically, p is 4, 8, 16, or 32, etc.

[0098] For example, in service transmissions applied to 1.6T Ethernet (1.6Terabit Ethernet, abbreviated as 1.6TE), the integer p is 8 or 16. As another example, in service transmissions applied to 3.2T Ethernet, the integer p is 16 or 32.

[0099] 102. Perform data processing, including QPSK mapping, on p first data streams to obtain q DP-QPSK symbol streams.

[0100] It should be understood that a DP-QPSK symbol stream contains one QPSK symbol stream in the X-polarization direction and one QPSK symbol stream in the Y-polarization direction, where the X-polarization and Y-polarization directions are orthogonal. The X-polarization direction can also be referred to as the first polarization direction, and the Y-polarization direction as the second polarization direction. For example, q DP-QPSK symbol streams to be transmitted are represented by 2×q QPSK symbol streams, where each pair of QPSK symbol streams represents the X-polarization and Y-polarization directions of one DP-QPSK symbol stream, respectively. For example, q DP-QPSK symbol streams to be transmitted are represented by 4×q QPSK symbol stream components, where each of the 4 QPSK symbol stream components represents the I-path component, Q-path component, I-path component, and Q-path component of the QPSK symbol stream in the X-polarization direction, respectively, in one DP-QPSK symbol stream.

[0101] In some applications, data processing involving DP-QPSK mapping is performed on every two first data streams from p first data streams to obtain one DP-QPSK symbol stream to be transmitted, resulting in a total of q = p / 2 DP-QPSK symbol streams to be transmitted. Two consecutive bits from each data stream participating in the QPSK mapping are mapped to obtain one QPSK symbol. It should be understood that the four bits mapped to one DP-QPSK symbol come from two data streams, which helps to combat colored noise.

[0102] In other applications, the first data processing performs DP-QPSK mapping on every four first data streams from the p first data streams to obtain one DP-QPSK symbol stream to be transmitted, resulting in a total of q = p / 4 DP-QPSK symbol streams to be transmitted. Two bits from each of the two data streams participating in the QPSK mapping are mapped to obtain one QPSK symbol. It should be understood that the four bits mapped to one DP-QPSK symbol come from four data streams, which helps to combat colored noise.

[0103] It should be noted that the combination of QPSK mapping oriented towards the X polarization direction and QPSK mapping oriented towards the Y polarization direction can also be called DP-QPSK mapping.

[0104] It should be noted that in some specific applications, to further improve performance, the data processing mentioned above, including QPSK mapping, also includes FEC encoding. In this case, FEC encoding combined with RS coding is called concatenated FEC encoding, where RS coding is called the outer code of the concatenated FEC encoding scheme, and FEC encoding is called the inner code. More specifically, FEC encoding is performed on p first data streams to obtain p encoded data streams, and then data processing including QPSK mapping is performed on the p encoded data streams to obtain q DP-QPSK symbol streams. The inner code can use a Single Parity Check Code (SPC) or Hamming code, etc. Typically, FEC encoding (i.e., the inner code) uses soft-decoding, requiring soft value information, resulting in higher overall power consumption for the concatenated FEC encoding scheme. In other words, the concatenated FEC encoding scheme has better performance, but also higher power consumption and complexity.

[0105] Considering 1.6T Ethernet service transmission, the total bit rate of p first data streams is 106.25 × 2 × 8 = 1700 Gbits per second. It should also be understood that the bit rates in this application are nominal rates; in practical applications, the bit rate will have a certain offset range, for example, ±V0 (ppm) error, where V0 can be 20, 25, 50, or 100, etc. Each first data stream contains four consecutive RS symbols from four different RS codewords; each first data stream is also called a 4-symbol-quartet stream. In some specific applications, the first data stream is further processed by a Physical Media Attachment (PMA) layer based on symbol multiplexing, also known as PMA-S. More specifically, the first data stream is obtained through PMA processing based on 4-symbol-quartet multiplexing. It should be noted that, in the embodiments of this application, m0:m1 PMA means that m0 input data streams are symbolically multiplexed to obtain m1 output data streams. In some other specific applications, the first data stream is also processed by a Physical Coding Sublayer (PCS).

[0106] Figure 5(a) is a data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are then subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is granular with 10 bits. Each of the 4 adjacent RS symbols in the 16 PCS Lanes comes from 4 different RS codewords. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6T AUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation, with a corresponding baud rate (also known as symbol rate) of 106.25 GBaud. Therefore, the total bit rate of the eight 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called the 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also called the 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 8 1.6T AUI-8 signals. The 8 1.6T AUI-8 signals are first processed by 1.6T 8:8PMA to obtain p = 8 first data streams. Then, data processing including QPSK mapping is performed to obtain q = p / 2 = 4 DP-QPSK symbol streams to be sent.

[0107] Figure 5(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(b), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. Each of the 16 1.6T AUI-16 signals has a bit rate of 106.25 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 53.125 G Baud. Therefore, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first processes them through 1.6T 16:8PMA to obtain p = 8 first data streams, and then performs data processing including QPSK mapping to obtain q = p / 2 = 4 DP-QPSK symbol streams to be transmitted.

[0108] Figure 5(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(c), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p = 8 first data streams, and data processing including QPSK mapping is performed to obtain q = p / 2 = 4 DP-QPSK symbol streams to be sent. The 1.6TPCS processing, 1.6T 16:8PMA, and data processing including QPSK mapping are implemented in the transmitting device 01.

[0109] Figure 6(a) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6T AUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation, with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the eight 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called the 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also called the 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 8 1.6T AUI-8 signals, first processes them through 1.6T8:16PMA to obtain p=16 first data streams, and then performs data processing including QPSK mapping to obtain q=p / 4=4 DP-QPSK symbol streams to be transmitted.

[0110] Figure 6(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(b), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. The 16 PCS Lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. Each of the 16 1.6T AUI-16 signals has a bit rate of 106.25 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 53.125 G Baud. Therefore, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first processes them through 1.6T 16:16PMA to obtain p = 16 first data streams, and then performs data processing including QPSK mapping to obtain q = p / 4 = 4 DP-QPSK symbol streams to be transmitted.

[0111] Figure 6(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(c), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol distributed and interleaved to obtain 16 PCS Lanes. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are used as p = 16 first data streams, and data processing including QPSK mapping is performed to obtain q = p / 4 = 4 DP-QPSK symbol streams to be sent. The 1.6T PCS processing and the data processing including QPSK mapping are implemented in the transmitting device 01.

[0112] It should be noted that in the scenarios for 1.6T services shown in Figures 5(a), 5(b), and 5(c), p = 8 first data streams participate in QPSK mapping. In the scenarios for 1.6T services shown in Figures 6(a), 6(b), and 6(c), p = 16 first data streams participate in QPSK mapping. The data processing involving p = 8 first data streams participating in QPSK mapping is applicable not only to the 1.6T service scenarios described above but also to other service scenarios with a total rate of 1.6T, such as two 800G services or four 400G services.

[0113] Figure 5(d) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(d), consider two 800G service scenarios, where each 800G service data is processed by an 800G PCS to obtain 32 PCS Lanes. Specifically, each 800G PCS process includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain 32 PCS Lanes. The symbol distribution is granular with 10 bits. The 32 PCS Lanes are processed by 800G 32:4PMA based on 4-symbol multiplexing to obtain four 800G AUI-4 signals. The two 800G service data, after the above 800G PCS and 800G 32:4PMA, obtain a total of two sets of 800G AUI-4 signals, totaling eight signal streams. Each of the two 800G AUI-4 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the two 800G AUI-4 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the two 800G AUI-4 signals. Each 800G AUI-4 signal is processed by 800G 4:4 PMA to obtain four first data streams, resulting in a total of p = 8 first data streams. These eight first data streams then undergo data processing including QPSK mapping to obtain q = p / 2 = 4 DP-QPSK symbol streams to be transmitted.

[0114] Figure 5(e) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(e), consider four 400G service scenarios, where each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS process includes two RS encoding processing units. For example, the 400G PCS process in the figure may include RS-A and RS-B, and the 400G PCS process may also include RS-C and RS-D. The encoded data streams obtained after the two RS encoding processing units are then symbol-distributed and interleaved to obtain 16 PCS Lanes. The symbol distribution is granular with 10 bits. The 16 PCS Lanes are processed by 400G 16:2PMA based on 4-symbol multiplexing to obtain two 400G AUI-2 signals. The four 400G service data are processed by the above 400G PCS and 400G 16:2PMA to obtain a total of four sets of 400G AUI-2 signals, totaling eight signal streams. Each of the four 400G AUI-2 signals has a bit rate of 212.5 Gbits per second, uses PAM4 modulation, and has a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the four 400G AUI-2 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the four 400G AUI-2 signals. Each 400G AUI-2 signal is processed by 400G 2:2PMA to obtain two first data streams, resulting in a total of p = 8 first data streams. These 8 first data streams then undergo data processing including QPSK mapping to obtain q = p / 2 = 4 DP-QPSK symbol streams to be transmitted.

[0115] It should be noted that, to improve the signal quality recovered at the receiving end, the data to be transmitted is typically framed at the transmitting end. This framing can also be called DSP framing. Specifically, the DP-QPSK symbol stream to be transmitted contains multiple DP-QPSK symbol sequences. Framing is used to insert the target symbol sequence at a fixed position in each DP-QPSK symbol sequence. The DP-QPSK symbol sequence is also called a DSP frame. Consider that a DSP frame contains a total of N... DSP DP-QPSK symbols, meaning the DSP frame contains N in the X polarization direction. DSP The DSP frame contains N QPSK symbols in the Y polarization direction. DSP The target symbol sequence contains a total of N1 QPSK symbols. These symbols are inserted into the DSP frame along both the X and Y polarization directions. Considering the total bit rate of the data stream before framing is W1, the total bit rate of the data stream after framing is W2 = W1 × N. DSP / (NDSP -N1). At this point, taking q=4 as an example, the baud rate corresponding to each of the 4 DP-QPSK symbol streams to be sent is W. s =W2 / 16.

[0116] It should be understood that the values ​​of the target symbol sequence inserted in the X-polarization direction may not be exactly the same as those inserted in the Y-polarization direction; they are collectively referred to as target symbol sequences without specific distinction. For example, the target symbol sequence includes at least one of the following: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence. Optionally, reserved symbols may also be called fixed stuff (FS), and frame alignment symbols may also be called multi-frame alignment signal (MFAS).

[0117] In some specific applications, taking the pilot symbol sequence as an example where the target symbol sequence inserted by the DSP frame is a pilot symbol sequence, in either the X-polarization direction or the Y-polarization direction, every N in the DSP frame... G One symbol at a fixed position among the symbols is the pilot symbol, and the remaining N G -1 symbol is the pre-framing symbol (also known as the payload symbol). As an example, every N... G The first symbol in the set is the pilot symbol. Several specific implementations are given below.

[0118] Consider N G =32, at this time, the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1)G Baud≈109.6774G Baud. N G It is an integer power of 2, which facilitates the hardware implementation of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

[0119] Consider N G=64, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1)G Baud≈107.9365G Baud. N G It is an integer power of 2, which facilitates the hardware implementation of ADC and DAC.

[0120] Consider N G =128, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1)G Baud≈107.0866G Baud. N G It is an integer power of 2, which facilitates the hardware implementation of ADC and DAC.

[0121] Consider N G =35, at this time, the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1) G Baud = 109.375 G Baud. At this point, considering a clock frequency of 156.25 MHz, the baud rate 109.375 G = 156.25 M × 700 is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, can perform fast phase locking, and has low PLL complexity and low jitter.

[0122] Consider N G =41, at this time, the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G-1) G Baud = 108.90625 G Baud. At this point, considering a clock frequency of 156.25MHz, the baud rate 108.90625G = 156.25M × 697 is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, and can perform fast phase locking. The PLL has low complexity and low jitter.

[0123] Consider N G =69, at this time, the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1) G Baud = 107.8125 G Baud. At this point, considering a clock frequency of 156.25MHz, the baud rate 107.8125G = 156.25M × 690 is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, and can perform fast phase locking. The PLL has low complexity and low jitter.

[0124] Consider N G =86, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1)G Baud = 107.5G Baud. At this time, considering a clock frequency of 156.25MHz, the baud rate 107.5G = 156.25M × 688 is an integer multiple of the clock frequency value, which is beneficial for serdes hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, can perform fast phase locking, and has low PLL complexity and low jitter.

[0125] Consider N G =171, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G-1) G Baud = 106.875 G Baud. At this point, considering a clock frequency of 156.25 MHz, the baud rate 106.875 G = 156.25 M × 684 is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, and can perform fast phase locking. The PLL has low complexity and low jitter.

[0126] Consider N G =341, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1) G Baud = 106.5625 G Baud. At this point, considering a clock frequency of 156.25 MHz, the baud rate 106.5625 G = 156.25 M × 682 is an integer multiple of the clock frequency value, which is beneficial for SERDES hardware implementation. It can simplify the way the receiver extracts and synchronizes the clock, and can perform fast phase locking. The PLL has low complexity and low jitter.

[0127] Consider N G =681, at this time the baud rate corresponding to each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud=106.25×N G / (N G -1) G Baud = 106.40625 G Baud. At this point, considering a clock frequency of 156.25MHz, the baud rate 106.40625G = 156.25M × 681 is an integer multiple of the clock frequency value, which is beneficial for SERDE hardware implementation. It simplifies the clock extraction and synchronization process at the receiver, allows for fast phase locking, and results in low PLL complexity and low jitter. It should be noted that the baud rate without DSP framing is 106.25G = 156.25M × 680, N G =681 corresponds to a baud rate of 106.40625G = 156.25M × 681Baud, which is closest to the 106.25Gbaud baud rate without DSP framing. The solution has a lower baud rate.

[0128] In other specific applications, the baud rate of the DP-QPSK symbol stream to be transmitted is W. s=W2 / 16 is an integer multiple of the clock frequency used. In this case, the clock extraction and synchronization at the receiver can be simplified, fast phase locking can be performed, and the PLL has low complexity and low jitter.

[0129] It should also be understood that the baud rates in this application are all nominal rates. In actual applications, the baud rates of DP-QPSK symbol streams will have a certain error range. For example, the baud rate may have an error of ±V1 (ppm), where V1 can be 20, 25, 50 or 100, etc.

[0130] Figure 7 is a schematic diagram of several implementation methods for QPSK mapping and framing of the first data stream in the embodiments of this application.

[0131] As shown in example 7(a), DSP framing is performed after QPSK mapping, and DSP framing operates on symbols. QPSK mapping is performed on two first data streams respectively. One of the QPSK-mapped QPSK symbol streams is inserted into the target symbol sequence in the X-polarization direction to obtain a DP-QPSK symbol stream in the X-polarization direction. The other QPSK-mapped QPSK symbol stream is inserted into the target symbol sequence in the Y-polarization direction to obtain a DP-QPSK symbol stream in the Y-polarization direction. In this example, QPSK mapping takes two consecutive bits from the input first data stream and maps them to obtain a QPSK symbol.

[0132] As shown in example (b) of Figure 7, DSP framing is performed before QPSK mapping, and DSP framing operates on a bit-by-bit basis. A target bit sequence in the X-polarization direction is inserted into one of the two first data streams, and then QPSK mapping is performed to obtain a DP-QPSK symbol stream in the X-polarization direction. A target bit sequence in the Y-polarization direction is inserted into the other of the two first data streams, and then QPSK mapping is performed to obtain a DP-QPSK symbol stream in the Y-polarization direction. Specifically, the target bit sequence in the X-polarization direction is QPSK mapped to obtain the target symbol sequence in the X-polarization direction, and the target bit sequence in the Y-polarization direction is QPSK mapped to obtain the target symbol sequence in the Y-polarization direction.

[0133] As shown in example (c) of Figure 7, DSP framing is performed after QPSK mapping, and DSP framing operates on symbols. Two of the four first data streams are QPSK mapped, and then a target symbol sequence in the X-polarization direction is inserted to obtain a DP-QPSK symbol stream in the X-polarization direction. The other two of the four first data streams are QPSK mapped, and then a target symbol sequence in the Y-polarization direction is inserted to obtain a DP-QPSK symbol stream in the Y-polarization direction. In this example, QPSK mapping obtains one bit from each of the two input first data streams, resulting in a total of two bits. These two bits are then mapped to obtain a QPSK symbol.

[0134] As shown in example (d) of Figure 7, DSP framing is performed before QPSK mapping, and DSP framing operates on a bit-by-bit basis. The target bit sequence, i.e., target bit sequence X, is inserted into the four input first data streams respectively. I Target bit sequence X Q Target bit sequence Y I Target bit sequence Y Q Then, QPSK mapping is performed on two of the four first data streams from which the target bit sequence is inserted to obtain a DP-QPSK symbol stream in the X-polarization direction. Similarly, QPSK mapping is performed on the other two of the four first data streams from which the target bit sequence is inserted to obtain a DP-QPSK symbol stream in the Y-polarization direction. The target bit sequence is obtained by QPSK mapping to form the target symbol sequence. It should be noted that the target bit sequence X... I The target symbol sequence is the in-phase component in the X-polarization direction, and the target bit sequence X is... Q The target symbol sequence is represented by the Q-path component (quadrature-phase component) in the X-polarization direction, and the target bit sequence Y... I The target symbol sequence is the I-phase component in the Y-polarization direction, and the target bit sequence is Y. Q This refers to the Q-path component (quadrature-phase component) of the target symbol sequence in the Y-polarization direction. In other words, the target bit sequence X... I and target bit sequence X Q After QPSK mapping, the target symbol sequence in the X polarization direction and the target bit sequence Y are obtained. I and target bit sequence Y Q After QPSK mapping, the target symbol sequence in the Y polarization direction is obtained.

[0135] As shown in example (e) of Figure 7, DSP framing is performed after QPSK mapping, and DSP framing is performed on symbols. QPSK mapping is performed on one of the two first data streams to obtain the symbol stream in the X-polarization direction. The symbol stream in the X-polarization direction is represented by two component data streams, one of which is the I component data stream (denoted as X). I One is a data stream, and the other is a Q-component data stream (denoted as X). Q (Data stream). QPSK mapping is performed on the other of the two first data streams to obtain the symbol stream in the Y-polarization direction. The symbol stream in the Y-polarization direction is represented by two component data streams, one of which is the I-component data stream (denoted as Y). I One is a data stream, and the other is a Q-component data stream (denoted as Y). Q Data stream). The four component data streams are framed using DSP, i.e., X... I The data stream inserts the I component of the target symbol sequence in the X polarization direction, for X Q The data stream inserts the Q component of the target symbol sequence in the X-polarization direction, and the Y-polarization direction... I The data stream inserts the I component of the target symbol sequence in the Y polarization direction, for Y Q The data stream is inserted with the Q component of the target symbol sequence in the Y polarization direction to obtain a DP-QPSK symbol stream to be transmitted.

[0136] As shown in example (f) of Figure 7, DSP framing is performed after QPSK mapping, and DSP framing is performed on symbols. Two of the four first data streams are QPSK mapped to obtain the symbol stream in the X-polarization direction. The symbol stream in the X-polarization direction is represented by two component data streams, one of which is the I component data stream (denoted as X). I One is a data stream, and the other is a Q-component data stream (denoted as X). Q (Data Stream). QPSK mapping is performed on two of the four first data streams to obtain the symbolic data stream in the Y-polarization direction. The symbolic data stream in the Y-polarization direction is represented by two component data streams, one of which is the I-component data stream (denoted as Y). I One is a data stream, and the other is a Q-component data stream (denoted as Y). Q Data stream). The four component data streams are framed using DSP, i.e., X... I The data stream inserts the I component of the target symbol sequence in the X polarization direction, for X Q The data stream inserts the Q component of the target symbol sequence in the X-polarization direction, and the Y-polarization direction... I The data stream inserts the I component of the target symbol sequence in the Y polarization direction, for Y QThe data stream is inserted with the Q component of the target symbol sequence in the Y polarization direction to obtain a DP-QPSK symbol stream to be transmitted.

[0137] The following section details how to process the p first data streams, taking into account the possible values ​​of p.

[0138] For scenarios where p=8, for example, as shown in Figure 5(a), eight first data streams are obtained from 1.6T 8:8PMA. As shown in Figures 5(b) and 5(c), eight first data streams are obtained from 1.6T 16:8PMA. As shown in Figure 5(d), a total of eight first data streams are obtained from two groups of 800G 32:4PMA. As shown in Figure 5(e), a total of eight first data streams are obtained from four groups of 400G 16:2PMA. It should be noted that this method of processing eight first data streams with p=8 is applicable to service scenarios with a total rate of 1.6T, including one 1.6T service, two 800G services, and four 400G services, and can be applied to a wider range of scenarios.

[0139] Figure 8(a) is a schematic diagram of one implementation of QPSK mapping and DSP framing of p first data streams in this application. As shown in Figure 8(a), taking p=8 as an example, every two first data streams in the eight first data streams (i.e., first data streams 0-7) are processed by DP-QPSK mapping and DSP framing to obtain a DP-QPSK symbol stream. In some specific applications, DP-QPSK mapping and DSP framing are implemented as shown in examples (a), (b), or (e) of Figure 7.

[0140] It should be noted that the QPSK mapping obtains two consecutive bits (A, B) from each input data stream i (0≤i≤7) and obtains a QPSK symbol according to a preset mapping rule. Bit A is mapped to the I-phase component of the QPSK symbol, and bit B is mapped to the Q-phase component of the QPSK symbol. A specific mapping rule is shown in Table 1 below.

[0141] Table 1

[0142] It should be noted that, considering the different effects of polarization-dependent loss (PDL) on the X and Y polarization directions, interleaving can also be performed before DP-QPSK mapping and DSP framing.

[0143] Figure 8(b) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application. As shown in Figure 8(b), 8 bits are obtained from each of the two input first data streams and interleaved, for a total of 16 bits, and then interleaved to shuffle the order. Each interleaved first data stream includes bits from one of the first data streams before interleaving and bits from the other first data stream before interleaving. That is, the interleaving here is a combined operation of shuffling the bit order of the two first data streams, rather than interleaving each first data stream independently to shuffle the order.

[0144] One specific interleaving method is as follows: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams. Interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0c1d1d2a2b3c3 and 8 bits c0d0a1b1b2c2d3a3. In this DP-QPSK symbol stream, the 8 bits a0b0c1d1d2a2b3c3 correspond to 4 QPSK symbols in one polarization direction, with a0b0, c1d1, d2a2, and b3c3 each mapped to one QPSK symbol. Similarly, the 8 bits c0d0a1b1b2c2d3a3 correspond to 4 QPSK symbols in another polarization direction, with c0d0, a1b1, b2c2, and d3a3 each mapped to one QPSK symbol. In some possible scenarios, the 4 QPSK symbols corresponding to the 8 bits a0b0c1d1d2a2b3c3 are consecutive in the DP-QPSK symbol stream after removing the inserted target symbol sequence, and the 4 QPSK symbols corresponding to the 8 bits c0d0a1b1b2c2d3a3 are also consecutive in the DP-QPSK symbol stream after removing the inserted target symbol sequence. It should be understood that the above interleaving method enables consecutive bits in each first data stream to be uniformly mapped to QPSK symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0145] Another specific interleaving method is as follows: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams. Interleave the 8 consecutive bits a0b0a1b1a2b2a3b3 and the 8 consecutive bits c0d0c1d1c2d2c3d3 to obtain 8 bits a0b0d1a1c2d2b3c3 and 8 bits c0d0b1c1a2b2d3a3. In this DP-QPSK symbol stream, the 8 bits a0b0d1a1c2d2b3c3 correspond to 4 QPSK symbols in one polarization direction, with a0b0, d1a1, c2d2, and b3c3 each mapped to one QPSK symbol. Similarly, the 8 bits c0d0b1c1a2b2d3a3 correspond to 4 QPSK symbols in another polarization direction, with c0d0, b1c1, a2b2, and d3a3 each mapped to one QPSK symbol. In some possible scenarios, the 4 QPSK symbols corresponding to the 8 bits a0b0d1a1c2d2b3c3 are consecutive in the DP-QPSK symbol stream after removing the inserted target symbol sequence, and the 4 QPSK symbols corresponding to the 8 bits c0d0b1c1a2b2d3a3 are also consecutive in the DP-QPSK symbol stream after removing the inserted target symbol sequence. It should be understood that the above interleaving method enables consecutive bits in each first data stream to be uniformly mapped to QPSK symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0146] For the scenario where p=16, for example, as shown in Figure 6(a), 16 first data streams are obtained from 1.6T 8:16PMA. Another example, as shown in Figure 6(b), 16 first data streams are obtained from 1.6T 16:16PMA. Yet another example, as shown in Figure 6(c), 16 first data streams are obtained from 1.6T PCS.

[0147] Figure 9(a) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application. As shown in Figure 9(a), taking p=16 as an example, every 4 first data streams in the 16 first data streams (i.e., first data streams 0-15) are processed by DP-QPSK mapping and DSP framing to obtain a DP-QPSK symbol stream. In some specific applications, DP-QPSK mapping and DSP framing are implemented as shown in examples (c), (d), or (f) in Figure 7.

[0148] It should be noted that the QPSK mapping obtains one bit from each of the two input first data streams, for a total of two bits (A, B), and obtains a QPSK symbol according to the mapping rules shown in Table 1. Bit A is mapped to the I-phase component of the QPSK symbol, and bit B is mapped to the Q-phase component of the QPSK symbol.

[0149] It should be noted that, considering the different effects of polarization-dependent loss (PDL) on the X and Y polarization directions, interleaving can also be performed before DP-QPSK mapping and DSP framing.

[0150] Figure 9(b) is a schematic diagram of another implementation of QPSK mapping and DSP framing of p first data streams in this application. As shown in Figure 9(b), four bits are obtained from each of the four input first data streams and interleaved, for a total of 16 bits, and then interleaved to shuffle the order. That is to say, the interleaving here is a bit order shuffling operation combined with the four first data streams, rather than interleaving each first data stream independently to shuffle the order.

[0151] A specific interleaving method is as follows: Obtain four consecutive bits a0a1a2a3 from the first of the four first data streams; obtain four consecutive bits b0b1b2b3 from the second of the four first data streams; obtain four consecutive bits c0c1c2c3 from the third of the four first data streams; and obtain four consecutive bits d0d1d2d3 from the fourth of the four first data streams. Interleave the four consecutive bits a0a1a2a3, b0b1b2b3, c0c1c2c3, and d0d1d2d3 to obtain four bits a0c1d2b3, four bits b0d1a2c3, four bits c0a1b2d3, and four bits d0b1c2a3. In this DP-QPSK symbol stream, four bits a0c1d2b3 and four bits b0d1a2c3 correspond to four QPSK symbols in one polarization direction, with a0b0, c1d1, d2a2, and b3c3 each mapped to one QPSK symbol. Similarly, four bits c0a1b2d3 and four bits d0b1c2a3 correspond to four QPSK symbols in another polarization direction, with c0d0, a1b1, b2c2, and d3a3 each mapped to one QPSK symbol. In some possible scenarios, the four QPSK symbols corresponding to the four bits a0c1d2b3 and four bits b0d1a2c3 are continuous after removing the inserted target symbol sequence from a single DP-QPSK symbol stream, and the four QPSK symbols corresponding to the four bits c0a1b2d3 and four bits d0b1c2a3 are also continuous after removing the inserted target symbol sequence from a single DP-QPSK symbol stream. It should be understood that the above interleaving method enables consecutive bits in each first data stream to be uniformly mapped to QPSK symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0152] Another specific interleaving method is as follows: Obtain four consecutive bits a0a1a2a3 from the first of the four first data streams; obtain four consecutive bits b0b1b2b3 from the second of the four first data streams; obtain four consecutive bits c0c1c2c3 from the third of the four first data streams; and obtain four consecutive bits d0d1d2d3 from the fourth of the four first data streams. Interleave the four consecutive bits a0a1a2a3, b0b1b2b3, c0c1c2c3, and d0d1d2d3 to obtain four bits a0d1c2b3, four bits b0a1d2c3, four bits c0b1a2d3, and four bits d0c1b2a3. In this DP-QPSK symbol stream, four bits (a0d1c2b3) and four bits (b0a1d2c3) correspond to four QPSK symbols in one polarization direction, with a0b0, d1a1, c2d2, and b3c3 each mapped to one QPSK symbol. Similarly, four bits (c0b1a2d3) and four bits (d0c1b2a3) correspond to four QPSK symbols in another polarization direction, with c0d0, b1c1, a2b2, and d3a3 each mapped to one QPSK symbol. In some possible scenarios, the four QPSK symbols corresponding to the four bits (a0d1c2b3 and b0a1d2c3) are continuous after removing the inserted target symbol sequence from a single DP-QPSK symbol stream, and the four QPSK symbols corresponding to the four bits (c0b1a2d3 and d0c1b2a3) are also continuous after removing the inserted target symbol sequence from a single DP-QPSK symbol stream. It should be understood that the above interleaving method enables consecutive bits in each first data stream to be uniformly mapped to QPSK symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0153] In some possible scenarios, for the scenarios shown in Figures 8(b) and 9(b) above, each first data stream can be FEC encoded before interleaving, which is beneficial to improving data transmission performance.

[0154] It should be noted that, using the data processing method provided in this application embodiment, as shown in Figures 8(a), 8(b), 9(a), and 9(b), the bit rate corresponding to the data stream after processing 1.6T PCS is W1 = 1700 Gbits per second. After data processing including QPSK mapping and DSP framing, it yields 4 DP-QPSK symbol streams. Considering that the data processing includes DSP framing, each DSP frame contains a total of N... DSP DP-QPSK symbols, which contain N DSP-N1 pre-framing DP-QPSK symbols and N1 inserted DP-QPSK symbols. The pre-framing DP-QPSK symbols are also called payload symbols. At this point, the total bit rate of the data stream after DSP framing is W2 = W1 × N. DSP / (N DSP -N1)=1700×N DSP / (N DSP -N1)Gbps, the baud rate of each signal in the 4 DP-QPSK symbol streams to be transmitted is W. s =W2 / 16 = 106.25 × N DSP / (N DSP -N1)G Baud.

[0155] It should be understood that, compared with existing cascaded FEC schemes, the embodiments of this application do not require cascaded FEC encoding before performing data processing including QPSK mapping, resulting in multiple DP-QPSK symbol streams to be transmitted having lower bit rates and baud rates. Therefore, the data processing method proposed in this application has advantages such as low complexity, low power consumption, and low latency, and can be applied to a wide range of transmission scenarios, especially suitable for future coherent transmission scenarios above 800Gbps (such as 1.6Tbps).

[0156] The above considers the data processing method for 1.6T Ethernet service transmission. The following presents the data processing method for future 3.2T service transmission.

[0157] Figure 10(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. Figure 10(b) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. As shown in Figures 10(a) and 10(b), in some specific applications, p = 16 and q = 8.

[0158] As shown in Figure 10(a), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. Symbol distribution is performed at a 10-bit granularity. The 16 PCS Lanes are then processed by 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and 3.2T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 3.2T 16:16PMA to obtain p=16 first data streams, and then performs data processing including QPSK mapping to obtain q=p / 2=8 DP-QPSK symbol streams to be transmitted.

[0159] As shown in Figure 10(b), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. These 16 PCS Lanes serve as p = 16 first data streams, and undergo data processing including QPSK mapping to obtain q = p / 2 = 8 DP-QPSK symbol streams to be transmitted. The 3.2T PCS processing and the data processing including QPSK mapping are implemented in the transmitting device 01.

[0160] Figure 11(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. Figure 11(b) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. As shown in Figures 11(a) and 11(b), in some specific applications, p = 16 and q = 4.

[0161] As shown in Figure 11(a), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. Symbol distribution is performed at a 10-bit granularity. The 16 PCS Lanes are then processed by 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and 3.2T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 3.2T 16:16PMA to obtain p=16 first data streams, and then performs data processing including QPSK mapping to obtain q=p / 4=4 DP-QPSK symbol streams to be transmitted.

[0162] As shown in Figure 11(b), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. These 16 PCS Lanes serve as p = 16 first data streams, and undergo data processing including QPSK mapping to obtain q = p / 4 = 4 DP-QPSK symbol streams to be transmitted. The 3.2T PCS processing and the data processing including QPSK mapping are implemented in the transmitting device 01.

[0163] Figure 12 is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 12, in some specific applications, p = 32 and q = 8. 3.2T service data is processed by 3.2T PCS to obtain 32 PCS channel data streams, also known as 32 PCS Lanes. The 3.2T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol distributed and interleaved to obtain 32 PCS Lanes. The 32 PCS Lanes serve as the first data stream with p = 32, and undergo data processing including QPSK mapping to obtain q = p / 4 = 8 DP-QPSK symbol streams to be sent. The 3.2T PCS processing and the data processing including QPSK mapping are implemented in the transmitting device 01.

[0164] Figure 13 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 13, the data processing device includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is used to execute the operation of step 101 in the above embodiment, and the processing unit 202 is used to execute the operation of step 102 in the above embodiment. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated unit can be implemented in hardware or in the form of software functional units.

[0165] Figure 14 is a schematic diagram of an optical module structure in an embodiment of this application. As shown in Figure 14, the optical module includes a processor 301 and an interface 302. The processor 301 is used to execute the operation of step 102 in the above embodiment. In one possible implementation, the processor 301 includes the processing unit 202 shown in Figure 13. The interface 302 can be a transceiver or an input / output interface. The interface 302 is used to receive signals from other devices and transmit them to the processor 301 or to send signals from the processor 301 to other devices. As an example, after the processor 301 performs the above data processing including QPSK mapping, it obtains a DP-QPSK symbol stream and sends the DP-QPSK symbol stream through the interface 302. In this example, the interface 202 can specifically refer to an electrical interface. As another example, after the processor 301 performs data processing including QPSK mapping, it obtains a DP-QPSK symbol stream. The modulator in the optical module performs signal processing such as electro-optic conversion according to the DP-QPSK symbol stream to obtain an optical signal, and then sends the optical signal through the interface 302. In this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0166] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0167] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0168] Figure 15 is a schematic diagram of a transmitting device according to an embodiment of this application. As shown in Figure 15, the transmitting device includes a host-side device 401 and an optical module 402. The host-side device 401 is used to send data to the optical module 402, and the optical module 402 generates an optical signal based on the data sent by the host-side device 401 and transmits the optical signal through a channel. For example, the host-side device may specifically be a switch, router, or server. The transmitting device can be a communication device including the host-side device 401 and the optical module 402. It should also be understood that the transmitting device in this embodiment is named based on the data flow direction and does not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0169] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0170] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0171] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0172] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0173] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0174] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0175] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0176] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0177] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0178] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0179] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Obtain p first data streams after Reed-Solomon RS encoding, where p is a positive integer multiple of 4 and p is an integer power of 2; The p first data streams are subjected to data processing including orthogonal phase shift keying (QPSK) mapping to obtain multiple dual-polarization DP-QPSK symbol streams. Each DP-QPSK symbol stream includes a QPSK symbol stream in the first polarization direction and a QPSK symbol stream in the second polarization direction.

2. The method according to claim 1, characterized in that, Data processing, including QPSK mapping, is performed on the p first data streams to obtain multiple DP-QPSK symbol streams, including: The p first data streams are subjected to data processing including QPSK mapping and framing to obtain multiple DP-QPSK symbol streams.

3. The method according to claim 2, characterized in that, The data processing for the p first data streams, including QPSK mapping and framing, includes: QPSK mapping and framing are performed on every two first data streams in the p first data streams to obtain one DP-QPSK symbol stream, wherein two consecutive bits from each data stream participating in QPSK mapping are mapped to obtain one QPSK symbol.

4. The method according to claim 3, characterized in that, Performing QPSK mapping and framing on every two first data streams in the p first data streams includes one of the following methods: Perform QPSK mapping on one of the two first data streams to obtain a first QPSK symbol stream, and insert a target symbol sequence into the first QPSK symbol stream to obtain a QPSK symbol stream of the DP-QPSK symbol stream in one of the polarization directions; or, A target bit sequence is inserted into one of the two first data streams to obtain a second data stream. QPSK mapping is performed on the second data stream to obtain a QPSK symbol stream of the DP-QPSK symbol stream in one of the polarization directions. The target bit sequence is QPSK mapped to obtain a target symbol sequence. or, QPSK mapping is performed on one of the two first data streams to obtain the I component data stream and Q component data stream of the first QPSK symbol stream. The I component of the target symbol sequence is inserted into the I component data stream and the Q component of the target symbol sequence is inserted into the Q component data stream to obtain the QPSK symbol stream of the DP-QPSK symbol stream in one of the polarization directions.

5. The method according to any one of claims 1 to 4, characterized in that, Data processing, including QPSK mapping, for the p first data streams includes: The p first data streams are interleaved with every two first data streams to obtain two interleaved first data streams. Each interleaved first data stream includes bits from one of the first data streams before interleaving and bits from the other first data stream before interleaving. The two interleaved first data streams are QPSK mapped and framed to obtain a DP-QPSK symbol stream.

6. The method according to claim 5, characterized in that, Interleaving every two first data streams from the p first data streams includes: Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams. The consecutive 8 bits a0b0a1b1a2b2a3b3 and the consecutive 8 bits c0d0c1d1c2d2c3d3 are interleaved to obtain 8 bits a0b0c1d1d2a2b3c3 and 8 bits c0d0a1b1b2c2d3a3, wherein the 8 bits a0b0c1d1d2a2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0a1b1b2c2d3a3 correspond to 4 QPSK symbols in another polarization direction; or, Obtain 8 consecutive bits a0b0a1b1a2b2a3b3 from one of the two first data streams, and obtain 8 consecutive bits c0d0c1d1c2d2c3d3 from the other of the two first data streams. The consecutive 8 bits a0b0a1b1a2b2a3b3 and the consecutive 8 bits c0d0c1d1c2d2c3d3 are interleaved to obtain 8 bits a0b0d1a1c2d2b3c3 and 8 bits c0d0b1c1a2b2d3a3, wherein the 8 bits a0b0d1a1c2d2b3c3 correspond to 4 QPSK symbols in one polarization direction, and the 8 bits c0d0b1c1a2b2d3a3 correspond to 4 QPSK symbols in another polarization direction.

7. The method according to claim 6, characterized in that, The four QPSK symbols corresponding to the eight bits a0b0c1d1d2a2b3c3 are consecutive in the DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0a1b1b2c2d3a3 are consecutive in the DP-QPSK symbol stream; or, the four QPSK symbols corresponding to the eight bits a0b0d1a1c2d2b3c3 are consecutive in the DP-QPSK symbol stream, and the four QPSK symbols corresponding to the eight bits c0d0b1c1a2b2d3a3 are consecutive in the DP-QPSK symbol stream.

8. The method according to claim 2, characterized in that, The data processing for the p first data streams, including QPSK mapping and framing, includes: QPSK mapping and framing are performed on every 4 first data streams in the p first data streams to obtain 1 DP-QPSK symbol stream, wherein 2 bits from the 2 data streams participating in the QPSK mapping are mapped to obtain 1 QPSK symbol.

9. The method according to claim 8, characterized in that, Performing QPSK mapping and framing on every four first data streams in the p first data streams includes one of the following methods: Perform QPSK mapping on two of the four first data streams to obtain a second QPSK symbol stream, and insert a target symbol sequence into the second QPSK symbol stream to obtain a QPSK symbol stream of the DP-QPSK symbol stream in one of the polarization directions; or, Two of the four first data streams are respectively inserted with target bit sequences to obtain two third data streams. QPSK mapping is performed on the two third data streams to obtain the QPSK symbol stream of the DP-QPSK symbol stream in one polarization direction. The target bit sequence is QPSK mapped to obtain the target symbol sequence. or, Two of the four first data streams are QPSK mapped to obtain the I-component data stream and Q-component data stream of the second QPSK symbol stream. The I-component data stream is inserted with the I-component data stream and the Q-component data stream is inserted with the Q-component data stream to obtain the QPSK symbol stream of the DP-QPSK symbol stream in one polarization direction.

10. The method according to claim 1, 2, 8 or 9, characterized in that, Data processing, including QPSK mapping, for the p first data streams includes: The p first data streams are interleaved with every 4 first data streams, and then QPSK mapping and framing are performed on every 4 interleaved first data streams to obtain 1 DP-QPSK symbol stream.

11. The method according to claim 10, characterized in that, Interleaving every four first data streams from the p first data streams includes: Obtain four consecutive bits a0a1a2a3 from the first data stream of the four first data streams, four consecutive bits b0b1b2b3 from the second data stream of the four first data streams, four consecutive bits c0c1c2c3 from the third data stream of the four first data streams, and four consecutive bits d0d1d2d3 from the fourth data stream of the four first data streams; The four consecutive bits a0a1a2a3, b0b1b2b3, c0c1c2c3, and d0d1d2d3 are interleaved to obtain four bits a0c1d2b3, four bits b0d1a2c3, four bits c0a1b2d3, and four bits d0b1c2a3. The four bits a0c1d2b3 and four bits b0d1a2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0a1b2d3 and four bits d0b1c2a3 correspond to four QPSK symbols in another polarization direction. or, Obtain four consecutive bits a0a1a2a3 from the first data stream of the four first data streams, four consecutive bits b0b1b2b3 from the second data stream of the four first data streams, four consecutive bits c0c1c2c3 from the third data stream of the four first data streams, and four consecutive bits d0d1d2d3 from the fourth data stream of the four first data streams; The four consecutive bits a0a1a2a3, b0b1b2b3, c0c1c2c3, and d0d1d2d3 are interleaved to obtain four bits a0d1c2b3, four bits b0a1d2c3, four bits c0b1a2d3, and four bits d0c1b2a3. The four bits a0d1c2b3 and b0a1d2c3 correspond to four QPSK symbols in one polarization direction, and the four bits c0b1a2d3 and d0c1b2a3 correspond to four QPSK symbols in another polarization direction.

12. The method according to claim 11, characterized in that, The four QPSK symbols corresponding to the four bits a0c1d2b3 and the four bits b0d1a2c3 are consecutive in the DP-QPSK symbol stream; or, the four QPSK symbols corresponding to the four bits a0d1c2b3 and the four bits b0a1d2c3 are consecutive in the DP-QPSK symbol stream.

13. The method according to claim 4, 5, 6, 7, 9, 10, 11 or 12, characterized in that, Each DP-QPSK symbol stream includes multiple DP-QPSK symbol sequences, and a fixed position in each DP-QPSK symbol sequence includes a target symbol sequence inserted through the framing. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence.

14. The method according to claim 4, 5, 6, 7, 9, 10, 11 or 12, characterized in that, The target symbol sequence includes a pilot symbol sequence, and each DP-QPSK symbol sequence has N elements in the QPSK symbol sequence in any polarization direction. G Each symbol includes one pilot symbol, where N G =32, 64, 128, 35, 41, 69, 86, 171, 341 or 681.

15. The method according to any one of claims 1 to 14, characterized in that, Each of the DP-QPSK symbol streams includes the I-path component of the QPSK symbol stream in the first polarization direction, the Q-path component of the QPSK symbol stream in the first polarization direction, the I-path component of the QPSK symbol stream in the second polarization direction, and the Q-path component of the QPSK symbol stream in the second polarization direction.

16. The method according to any one of claims 1 to 15, characterized in that, Data processing, including QPSK mapping, is performed on the p first data streams to obtain multiple DP-QPSK symbol streams, including: The p first data streams are subjected to data processing including QPSK mapping to obtain q DP-QPSK symbol streams, where q = p / 2 or q = p / 4.

17. The method according to claim 16, characterized in that, p = 8, q = p / 2 = 4; Alternatively, p = 16, q = p / 4 = 4 or q = p / 2 = 8; Alternatively, p = 32, q = p / 4 = 8.

18. The method according to any one of claims 1 to 17, characterized in that, In each of the first data streams, every four adjacent RS symbols come from four RS codewords.

19. The method according to any one of claims 1 to 18, characterized in that, The p first data streams are obtained by processing 16 fourth data streams through a symbol-based physical media adaptation layer (PMA). The 16 fourth data streams are obtained by processing the service data to be sent through a physical coding sublayer (PCS) including RS coding.

20. The method according to claim 19, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA, and the t signals are obtained by processing the 16 fourth data streams through 16:t PMA, where t is a positive integer multiple of 4.

21. The method according to claim 19, characterized in that, The p first data streams are obtained by processing the 16 fourth data streams through 16:p PMA.

22. The method according to any one of claims 1 to 18, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA based on symbol multiplexing.

23. The method according to claim 20 or 22, characterized in that, t = 8, p = 8; or t = 16, p = 8; or t = 8, p = 16; Alternatively, t = 16, p = 16.

24. The method according to any one of claims 1 to 18, characterized in that, The p first data streams are obtained by processing the service data to be sent through a PCS including RS encoding.

25. The method according to any one of claims 1 to 24, characterized in that, The data processing method is applicable to scenarios including Ethernet, optical transport networks, and space optical communication.

26. A data processing apparatus, characterized in that, The data processing device includes: an acquisition unit and a processing unit; The acquisition unit is used to: acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2; The processing unit is used to: perform data processing including quadrature phase shift keying (QPSK) mapping on the p first data streams to obtain multiple dual-polarization DP-QPSK symbol streams, each of the DP-QPSK symbol streams including a QPSK symbol stream in a first polarization direction and a QPSK symbol stream in a second polarization direction.

27. A chip, characterized in that, The chip includes a processor for performing the method as described in any one of claims 1 to 25.

28. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used to perform the method as described in any one of claims 1 to 25 and to transmit and receive signals through the interface.

29. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 28, wherein the optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

30. A communication system, characterized in that, Includes: the transmitting device and the receiving device as described in claim 29, wherein the transmitting device is configured to transmit a signal to the receiving device.

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