Light emitting diode chip, display module, and lighting device

Abstract

A light emitting diode chip, a display module, and a lighting device. The light emitting diode chip comprises a chip body (100) and an adjusting layer (200) arranged on the chip body (100). The adjusting layer (200) is located on a light exit side of the light emitting diode chip, and the refractive index of the adjusting layer (200) is greater than the refractive index of a film layer (114), that is in contact with the adjusting layer (200), in the chip body (100).

Description

LED chips, display modules and lighting devices

[0001] This application claims priority to Chinese Patent Application No. 202410518231.5, filed with the Chinese Patent Office on April 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, such as a light-emitting diode chip, a display module, and a lighting device. Background Technology

[0003] In semiconductor lighting technology, light-emitting diodes (LEDs), as light-emitting devices that convert electrical energy into light energy, have advantages such as energy saving, environmental friendliness, long lifespan, and high luminous efficiency, and are widely used in many fields such as indication, display, decoration, and lighting. However, LEDs have relatively low light extraction efficiency. Summary of the Invention

[0004] This application provides a light-emitting diode chip, a display module, and a lighting device, which can improve the light extraction efficiency of the light-emitting diode chip.

[0005] In a first aspect, embodiments of this application provide a light-emitting diode chip, including a chip body and an adjustment layer disposed on the chip body. The adjustment layer is located on the light-emitting side of the light-emitting diode chip, and the refractive index of the adjustment layer is greater than the refractive index of the film layer in the chip body that is in contact with the adjustment layer.

[0006] Secondly, embodiments of this application provide a display module, including a driving backplane and the aforementioned light-emitting diode chip, wherein the light-emitting diode chip is disposed on the driving backplane and electrically connected to the driving backplane.

[0007] Thirdly, embodiments of this application provide a lighting device, including a circuit board and the aforementioned light-emitting diode chip, wherein the light-emitting diode chip is disposed on the circuit board and electrically connected to the circuit board. Attached Figure Description

[0008] Figure 1 is an optical path diagram of a light-emitting diode chip in some embodiments;

[0009] Figure 2 is an optical path diagram of the packaged light-emitting diode chip in some embodiments;

[0010] Figure 3 is an optical path diagram of the light-emitting diode chip in an embodiment of this application;

[0011] Figure 4 is a first simplified diagram of the light-emitting diode chip in an embodiment of this application;

[0012] Figure 5 is a second simplified diagram of the light-emitting diode chip in an embodiment of this application;

[0013] Figure 6 is a third simplified diagram of the light-emitting diode chip in the embodiments of this application;

[0014] Figure 7 is a fourth simplified diagram of the light-emitting diode chip in the embodiments of this application;

[0015] Figure 8 is a schematic diagram of a first type of photonic crystal in the embodiments of this application;

[0016] Figure 9 is a second schematic diagram of a photonic crystal in an embodiment of this application;

[0017] Figure 10 is a third schematic diagram of the photonic crystal in the embodiments of this application;

[0018] Figure 11 is a fourth schematic diagram of the photonic crystal in the embodiments of this application;

[0019] Figure 12 is a fifth schematic diagram of a photonic crystal in the embodiments of this application;

[0020] Figure 13 is a sixth schematic diagram of a photonic crystal in the embodiments of this application;

[0021] Figure 14 is a seventh schematic diagram of a photonic crystal in the embodiments of this application;

[0022] Figure 15 is an eighth schematic diagram of a photonic crystal in the embodiments of this application;

[0023] Figure 16 is a schematic diagram of a first reflective layer in an embodiment of this application;

[0024] Figure 17 is another schematic diagram of the first reflective layer in an embodiment of this application;

[0025] Figure 18 is a first structural diagram of the light-emitting diode chip in an embodiment of this application;

[0026] Figure 19 is a second structural diagram of the light-emitting diode chip in an embodiment of this application;

[0027] Figure 20 is a third structural diagram of the light-emitting diode chip in the embodiments of this application;

[0028] Figure 21 is a fourth structural diagram of the light-emitting diode chip in the embodiments of this application;

[0029] Figure 22 is a schematic diagram of a display module in an embodiment of this application;

[0030] Figure 23 is another schematic diagram of the display module in an embodiment of this application;

[0031] Figure 24 is a schematic diagram of a lighting device in an embodiment of this application;

[0032] FIG. 25 is a schematic diagram of a display module provided with a packaging layer in an embodiment of the present application;

[0033] FIG. 26 is another schematic diagram of a display module provided with a packaging layer in an embodiment of the present application;

[0034] FIG. 27 is a schematic diagram of a lighting device provided with a packaging layer in an embodiment of the present application.

[0035] Description of reference numerals: 100, chip body; 101, substrate; 102, buffer layer; 103, N-type electrode; 104, N-type semiconductor layer; 105, P-type electrode; 106, light-emitting layer; 107, P-type semiconductor layer; 108, current spreading layer; 109, second reflective layer; 110, first insulating layer; 111, second insulating layer; 112, bonding substrate; 113, bonding layer; 114, film layer; 200, adjustment layer; 201, optical microstructure; 202, photonic crystal; 203, through hole; 300, driving backplane; 301, driving substrate; 302, driving unit; 400, packaging layer; 500, first reflective layer; 600, lighting device; 610, light-emitting diode chip; 620, circuit board. Detailed implementation manners

[0036] The material of the film layer on the light-emitting side of the light-emitting diode chip is usually gallium nitride (GaN), and its refractive index is n1, where n1 is equal to 2.4, and the refractive index of air is n3, where n3 is equal to 1. The refractive index of this film layer differs greatly from that of air, resulting in a small critical angle of the light-emitting diode chip, usually about 22 degrees. Referring to FIG. 1, the light rays equal to or greater than this critical angle undergo total internal reflection, and the light extraction efficiency is low. At the same time, the light rays undergoing total internal reflection are reflected and refracted multiple times inside the light-emitting diode chip, and a large proportion will exit from the sidewall of the light-emitting diode chip, resulting in a large proportion of side light extraction of the light-emitting diode chip, reducing the light extraction efficiency and also causing uneven light extraction distribution.

[0037] Referring to FIG. 2, after the light-emitting diode chip is packaged, epoxy resin and other materials are usually used as the packaging layer 400, and the refractive index of the packaging layer 400 is n4, where n3 < n4 < n1, that is, the refractive index of the packaging layer 400 is less than the refractive index of the corresponding film layer of the light-emitting diode chip and greater than the refractive index of air. In this way, the critical angle of the packaged light-emitting diode chip can be increased, the light extraction efficiency can be improved, and the light extraction distribution will be more uniform. However, as shown in FIG. 2, using the packaging layer, the improvement of the light extraction efficiency and the uniformity of the light extraction distribution of the light-emitting diode chip is limited and the effect is not good.

[0038] The LED chip, display module, and lighting device provided in this application embodiment utilize an adjustment layer disposed on the chip body, allowing the adjustment layer to be directly formed on the chip body, resulting in a simple process and low cost. The adjustment layer is located on the light-emitting side of the LED chip, ensuring that light generated by the chip body passes through the adjustment layer and exits to the outside of the LED chip. The refractive index of the adjustment layer is greater than the refractive index of the film layer in contact with the adjustment layer in the chip body, making the adjustment layer an optically denser medium, while the corresponding film layer in the chip body is an optically less dense medium. When light emitted from the chip body enters the adjustment layer, it transitions from an optically less dense medium to an optically denser medium, resulting in an incident angle greater than the refraction angle. This maximizes the refraction efficiency of the light emitted from the chip body into the adjustment layer, improving the light extraction efficiency from the chip body to the adjustment layer. Furthermore, by processing the surface of the adjustment layer away from the chip body, light can be focused, further improving the light extraction efficiency of the adjustment layer and ultimately enhancing the light extraction efficiency of the LED chip.

[0039] Considering that less light is emitted when light enters from an optically denser medium through an optically less dense medium due to total internal reflection and other effects, only a small proportion of the light entering the adjustment layer from the chip body returns to the chip body. This reduces the number of reflections and refractions within the chip body, significantly reducing side emission, increasing normal emission, shaping the light, improving the light extraction efficiency of the LED chip, and enhancing the uniformity of the light distribution. Furthermore, by using the chip body and adjustment layer to adjust the phase and amplitude distribution of the light, precise control over the light angle and intensity can be achieved.

[0040] In the accompanying drawings, the same or similar reference numerals denote the same or similar parts or parts having the same or similar functions throughout. The described embodiments are some embodiments related to this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without inventive effort are within the scope of protection of this application. The embodiments of this application will be described below with reference to the accompanying drawings.

[0041] This application provides a light-emitting diode (LED) chip that can be used in lighting, display, and other fields. The LED chip can be rectangular, square, circular, elliptical, triangular, rhomboid, parallelogram, or other polygonal shapes.

[0042] The size of a light-emitting diode (LED) chip can range from 0.001 to 200 micrometers, or even larger, depending on the application of the LED. The "size" mentioned above refers to the length of the LED chip in one direction. For example, it could be the length or width of a rectangular LED chip, the major or minor axis of an elliptical LED chip, or the diameter of a circular LED chip, etc.

[0043] The following provides illustrative examples of the size of LED chips in different application scenarios. When the LED chip is used in display products such as home televisions and desktop computers, the chip size can be greater than 100 micrometers. When the LED chip is used in display products such as laptops and tablets, the chip size can be greater than 60 micrometers. When the LED chip is used in display products such as mobile phones and smartwatches, the chip size can be greater than 50 micrometers.

[0044] Referring to Figures 3 to 21, the light-emitting diode (LED) chip includes a chip body 100 and an adjustment layer 200. The adjustment layer 200 is located on the light-emitting side of the LED chip, and the refractive index of the adjustment layer 200 is greater than the refractive index of the film layer 114 in the chip body 100 that is in contact with the adjustment layer 200. The chip body 100 may have multiple film layers, with at least some film layers stacked. The chip body 100 generates and emits light. The light can be white light or light of other colors. The chip body 100 can be electroluminescent (EL), or it can simultaneously possess both electroluminescence and photoluminescence (PL) light emission forms.

[0045] The architecture of the chip body 100 can be configured according to actual needs. The chip body 100 can be a normal structure, a flip structure, a vertical structure, a thin-film normal structure, a thin-film flip structure, a thin-film vertical structure, etc. Among them, the normal structure is shown in Figure 4, the flip structure is shown in Figure 5, and the vertical structure is shown in Figure 6. In this way, the chip body 100 can be fabricated using conventional processes and technologies, and the adjustment layer 200 can be formed directly on the chip body 100, resulting in lower cost and simpler processes.

[0046] An adjustment layer 200 is disposed on one side of the chip body 100, and the light emitted from the chip body 100 passes through the adjustment layer 200 and exits to the outside of the light-emitting diode chip. As shown in Figures 3 and 4, the adjustment layer 200 is located above the chip body 100, and the light-emitting side of the light-emitting diode chip is the upper side. The refractive index of the adjustment layer 200 is n2, the refractive index of the film layer 114 in the chip body 100 that is in contact with the adjustment layer 200 is n1, and the refractive index of air is n3, where n2>n1>n3. Thus, the refractive index of the adjustment layer 200 is relatively large, and the refractive index of the film layer 114 in the chip body 100 that is in contact with the adjustment layer 200 is relatively small. The adjustment layer 200 is an optically denser medium, and the film layer 114 in the chip body 100 that is in contact with the adjustment layer 200 is an optically less dense medium. When light emitted from the chip body 100 enters the adjustment layer 200, it moves from an optically less dense medium to an optically denser medium. This causes the incident angle of the emitted light to be greater than the refraction angle, thereby maximizing the efficiency of the light emitted from the chip body 100 into the adjustment layer 200. This improves the light extraction efficiency from the chip body 100 to the adjustment layer 200. Furthermore, by processing the surface of the adjustment layer 200 away from the chip body 100, the light can be focused, further improving the light extraction efficiency of the adjustment layer 200, and ultimately enhancing the light extraction efficiency of the LED chip.

[0047] Considering that less light is emitted when light enters a less optically denser medium from an optically less dense medium due to total internal reflection and other effects, only a small proportion of the light entering the adjustment layer 200 from the chip body 100 returns to the chip body 100. This reduces the number of reflections and refractions within the chip body 100, significantly reducing side emission, increasing normal emission, and improving the light extraction efficiency of the LED chip. Simultaneously, by using the chip body and adjustment layer to adjust the phase and amplitude distribution of light, precise control over the light angle and intensity is achieved.

[0048] When the light-emitting diode chip also includes an encapsulation layer covering the chip body 100 and the adjustment layer 200, the refractive index of the encapsulation layer is n4, where n2>n1>n4>n3. This increases the critical angle of the light-emitting diode chip, allowing the light emitted from the chip body 100 to be refracted into the air with maximum efficiency, thereby improving the light emission efficiency and making the emitted light distribution more uniform.

[0049] The adjustment layer 200 can be formed using epitaxial processes such as Metal-organic Chemical Vapor Deposition (MOCVD), physical film formation processes such as magnetron sputtering, chemical film formation processes such as Chemical Vapor Deposition (CVD), or other film formation processes. The adjustment layer 200 can be a single-layer structure or a multi-layer structure. A single-layer structure allows for easier control of the adjustment layer 200's thickness, preventing the LED chip from becoming too thick, and also facilitates the fabrication of the adjustment layer 200. A multi-layer structure allows the refractive index of the multiple layers of the adjustment layer 200 to increase sequentially along the direction away from the chip body 100, and all layers are greater than the refractive index of the adjacent film layer 114 of the adjustment layer 200 in the chip body 100. This configuration allows light entering the adjustment layer 200 from the chip body 100 to exit with maximum efficiency, improving the light extraction efficiency of the LED chip.

[0050] Referring to Figures 3 to 7, an optical microstructure 201 is also formed on the surface of the adjustment layer 200 opposite to the film layer 114. The optical microstructure 201 is configured to improve the light extraction efficiency of the adjustment layer 200. By processing the surface of the adjustment layer 200 to form the optical microstructure 201, the light that is refracted and dispersed unevenly within the adjustment layer 200 is converged and uniformly emitted through the optical microstructure 201, refracting into the air with maximum efficiency, thereby improving the light extraction efficiency of the light-emitting diode chip.

[0051] In some embodiments, the height of the optical microstructure 201 is 30%-80% of the thickness of the adjustment layer 200, and the thickness of the adjustment layer 200 is 0.1-10 micrometers. This ensures that, on the one hand, the thinner adjustment layer 200 avoids an excessively large total thickness of the LED chip, which is beneficial for product miniaturization. On the other hand, the appropriate height of the optical microstructure 201 avoids compromising the integrity of the adjustment layer 200 and prevents the chip body 100 from being exposed, while also providing sufficient height to guarantee light extraction efficiency.

[0052] For example, the height of the optical microstructure 201 is 35%-45%, 50%-60%, or 65%-75% of the thickness of the adjustment layer 200, such as 40%, 55%, or 70% of the thickness of the adjustment layer 200. As another example, the thickness of the adjustment layer 200 can be 0.5-1 micrometer, 1.5-5 micrometers, or 6-8 micrometers, such as 1 micrometer, 4 micrometers, or 7 micrometers.

[0053] The height of the optical microstructure 201 is related to the thickness of the adjustment layer 200. When the thickness of the adjustment layer 200 is large, the height of the optical microstructure 201 can be large; when the thickness of the adjustment layer 200 is small, the height of the optical microstructure 201 can be small, which facilitates the fabrication of the optical microstructure 201 while ensuring the integrity of the adjustment layer 200. For example, when the thickness of the adjustment layer 200 is 6-8 micrometers, the height of the optical microstructure 201 can be 65%-75% of the thickness of the adjustment layer 200; when the thickness of the adjustment layer 200 is 0.5-1 micrometer, the height of the optical microstructure 201 is 35%-45% of the thickness of the adjustment layer 200.

[0054] In some embodiments, the optical microstructure 201 may be located on a portion of the surface of the adjustment layer 200 facing away from the chip body 100, or on the entire surface of the adjustment layer 200 facing away from the chip body 100. By selectively performing partial surface treatment on the surface of the adjustment layer 200 facing away from the chip body 100, the formed optical microstructure 201 can be located only in the required area, thereby allowing for flexible adjustment of the position of the optical microstructure 201 to control the light emission range and light emission angle of the light-emitting diode chip.

[0055] Based on the above embodiments, in some possible implementations, referring to Figure 7, the optical microstructure 201 has a concave-convex structure, which is formed through a surface roughening process. In this way, the surface roughening process creates an irregular concave-convex structure on the surface of the adjustment layer 200 away from the chip body 100, reducing or disrupting total internal reflection at the interface between the adjustment layer 200 and the air, thereby improving the light extraction efficiency of the adjustment layer 200 and thus improving the light extraction efficiency of the LED chip. The roughening depth of the surface roughening process is 30%-80% of the thickness of the adjustment layer 200.

[0056] In some embodiments, the surface roughening process can be achieved through physical or chemical methods. Physical methods include manual grinding, while chemical methods include wet etching, dry etching, or a combination of both. Wet etching can be solution etching, electrochemical etching, etc., while dry etching can be reactive ion etching (RIE), high-density plasma (HDP) etching, electron cyclotron resonance (ECR) plasma etching, inductively coupled plasma (ICP) etching, etc. Different methods can be selected depending on the material used in the adjustment layer 200, and different etching solutions or etching gases can be selected depending on the material used in the adjustment layer 200.

[0057] For example, the adjustment layer 200 is made of indium gallium nitride (InGaN) material, and the optical microstructure 201 can be formed by a process of ICP etching, cleaning, potassium hydroxide (KOH) solution etching, and cleaning of the corresponding surface of the adjustment layer 200. As another example, the adjustment layer 200 is made of indium tin oxide (ITO), and the optical microstructure 201 can be formed by a process of coating with photoresist, photomask lithography, and immersion in 98% concentrated sulfuric acid on the corresponding surface of the adjustment layer 200, wherein the immersion in 98% concentrated sulfuric acid is performed at a temperature of 60 degrees Celsius for 8 minutes.

[0058] Based on the above embodiments, referring to Figures 4 to 6, in some possible implementations, the optical microstructure 201 is a photonic crystal 202, which is formed using electron beam lithography, nanoimprint lithography, or holographic exposure. Thus, by forming a regular photonic crystal 202 on the surface of the adjustment layer 200 away from the chip body 100, light can be shaped, facilitating control of the light emission distribution and improving the light emission efficiency of the adjustment layer 200, thereby increasing the light emission efficiency of the light-emitting diode chip.

[0059] In some embodiments, the height (i.e., depth) of the photonic crystal 202 is 30%-80% of the thickness of the adjustment layer 200. The photonic crystals 202 are arranged periodically, with a period of 1-5 micrometers, which is adapted to the dimension of the photonic crystals 202. The height direction of the photonic crystals 202 is aligned with the thickness direction of the adjustment layer 200.

[0060] In some possible examples, referring to Figures 8 to 11, in any three adjacent rows of photonic crystals 202, the photonic crystals 202 in adjacent rows are staggered, and the photonic crystals 202 in every other row are arranged opposite each other. Referring to Figures 12 to 15, the end face of the photonic crystal 202 facing away from the film layer 114 is also provided with a through hole 203. By providing the through hole 203, the light transmittance of the photonic crystal 202 can be improved. The cross-sectional shape of the through hole 203 can be circular, elliptical, triangular, polygonal, etc.

[0061] The photonic crystal 202 can be a two-dimensional or three-dimensional photonic crystal. The surface shape of a two-dimensional photonic crystal can be circular, elliptical, triangular, square, rhomboid, parallelogram, rectangular, or polygonal. The shape of a three-dimensional photonic crystal can be a triangular prism, cube, face-centered cube, hexagonal close-packed structure, or cylinder. As shown in Figure 8, the surface shape of the two-dimensional photonic crystal is square; as shown in Figure 9, the surface shape of the two-dimensional photonic crystal is circular; as shown in Figure 10, the surface shape of the two-dimensional photonic crystal is regular hexagonal; and as shown in Figure 11, the surface shape of the two-dimensional photonic crystal is triangular.

[0062] For example, the photonic crystal 202 has a period of 2 micrometers, a depth of 0.1 micrometers, and a cubic shape. It is formed using nanoimprint lithography, and its process includes template preparation and photonic crystal 202 pattern transfer. The template preparation process involves: fabricating a silicon template, pressing polymer material onto the silicon template, demolding, and obtaining a polymer soft template. The photonic crystal 202 pattern transfer process involves: cleaning the chip body with deionized water (100°C), drying, spin-coating with 150 nm UV imprinting adhesive, pre-baking for 3 minutes, UV soft imprinting, demolding and adhesive removal, dry etching, and adhesive removal. During UV soft imprinting, the polymer soft template is covered on the UV imprinting adhesive, exposed to UV light for 15 minutes, and then exposed to UV light for 10 seconds at a pressure of 35 × 10⁻⁶. 5 Pascal.

[0063] In some embodiments, the soft template may be made of intermediate polymer stamp (IPS) material or polydimethylsiloxane material.

[0064] In this embodiment, the adjustment layer 200 covers at least a portion of the surface of the film layer, and the optical microstructure 201 is disposed on at least a portion of the surface of the adjustment layer 200 facing away from the chip body. By adjusting the size of the adjustment layer 200 and the position of the optical microstructure 201, the light emission range of the light-emitting side of the LED chip is adjusted, thereby controlling the light emission angle of the LED chip. The adjustment layer 200 can be made of a transparent, high-refractive-index material to improve its light transmittance. In some embodiments, the adjustment layer 200 can also be made of conductive material; for example, the adjustment layer 200 can be made of ITO. Thus, in the example where the adjustment layer 200 covers only a portion of the surface of the film layer, the adjustment layer 200 can also reduce the edge effect of the LED chip.

[0065] For example, referring to Figure 3, the adjustment layer 200 can cover the entire surface of the corresponding side of the chip body 100, and the optical microstructure 201 is disposed on the entire surface of the corresponding side of the adjustment layer 200, so that the light-emitting side of the light-emitting diode chip emits light from the entire surface, and the light inside the light-emitting diode chip is concentrated and emitted uniformly, thereby improving the light-emitting efficiency of the diode chip.

[0066] In some embodiments, the light-emitting diode chip may further include a first reflective layer 500. By providing the first reflective layer 500, light is controlled to be emitted uniformly only from a designated area (e.g., the middle area) of the light-emitting diode chip. The first reflective layer 500 is disposed in the same layer as the adjustment layer 200, or the first reflective layer 500 is disposed on the side of the adjustment layer 200 away from the chip body and exposes the optical microstructure 201, so that light is emitted from the area not covered by the first reflective layer 500.

[0067] As a possible example, referring to FIG16, the film layer 114 in the chip body 100 that is in contact with the adjustment layer 200 includes a central region 1140 and an edge region 1141 surrounding the central region 1140. A first reflective layer 500 is located on the edge region 1141 of the film layer 114, and the adjustment layer 200 is located on the central region 1140 of the film layer 114.

[0068] In some embodiments, the edge region of the corresponding film layer 114 in the chip body 100 can completely surround the central region of the film layer 114, that is, the edge region of the film layer 114 surrounds the central region of the film layer 114 for a full circumference. The first reflective layer 500 is disposed on the edge region of the film layer 114, and the adjustment layer 200 is disposed on the central region of the film layer 114, so that the first reflective layer 500 is disposed around the adjustment layer 200, reducing the coverage area of ​​the adjustment layer 200 on the chip body 100. The first reflective layer 500 reflects light back to the chip body, and then, through refraction and reflection in the chip body, the light is uniformly emitted from the central region of the light-emitting diode chip. In this example, the coverage area of ​​the optical microstructure 201 is not limited; for example, the optical microstructure 201 can be disposed on the entire surface of the adjustment layer 200.

[0069] As another possible example, referring to Figure 17, the adjustment layer 200 includes a central region 2000 and an edge region 2001 surrounding the central region 2000. An optical microstructure 201 is located in the central region 2000 of the adjustment layer 200, and a first reflective layer 500 is located on the edge region 2001 of the adjustment layer 200. The adjustment layer 200 can cover the entire surface of the corresponding side of the chip body 100, and the first reflective layer 500 is disposed on the side of the adjustment layer 200 away from the chip body 100; that is, the chip body 100, the adjustment layer 200, and the first reflective layer 500 are stacked sequentially.

[0070] The edge region of the adjustment layer 200 can completely surround the central region of the adjustment layer 200, that is, the edge region of the adjustment layer 200 surrounds the central region of the adjustment layer 200 for a full circumference. The first reflective layer 500 is located on the edge region of the adjustment layer 200, and the optical microstructure 201 is located on the central region of the adjustment layer 200, so that the first reflective layer 500 surrounds the optical microstructure 201, and the first reflective layer 500 reflects the light back to the chip body. Then, through refraction and reflection in the chip body, the light is uniformly emitted from the central region of the light-emitting diode chip.

[0071] Referring to Figures 18 to 20, in some possible embodiments, the chip body 100 includes a buffer layer 102, an N-type electrode 103, a P-type electrode 105, an N-type semiconductor layer 104, a P-type semiconductor layer 107, a light-emitting layer 106, and a first insulating layer 110. The buffer layer 102 and the N-type semiconductor layer 104 are stacked. The light-emitting layer 106 is disposed on the side of the N-type semiconductor layer 104 facing away from the buffer layer 102, and the P-type semiconductor layer 107 is disposed on the side of the light-emitting layer 106 facing away from the buffer layer 102. The N-type electrode 103 is in contact with the N-type semiconductor layer 104, and the P-type electrode 105 is in contact with the P-type semiconductor layer 107. The first insulating layer 110 is disposed on the side of the P-type semiconductor layer 107 facing away from the buffer layer 102. An adjustment layer 200 is disposed on the side of the buffer layer 102 facing away from the N-type semiconductor layer 104, or an adjustment layer 200 is disposed on the side of the first insulating layer 110 facing away from the P-type semiconductor layer 107.

[0072] For example, an N-type semiconductor layer 104 is disposed on one side surface of the buffer layer 102, a light-emitting layer 106 is disposed on the surface of the N-type semiconductor layer 104 facing away from the buffer layer 102, and a P-type semiconductor layer 107 is disposed on the surface of the light-emitting layer 106 facing away from the buffer layer 102. That is, the buffer layer 102, the N-type semiconductor layer 104, the light-emitting layer 106, and the P-type semiconductor layer 107 are stacked sequentially. The N-type semiconductor layer 104 is also in contact with the N-type electrode 103 and conducting, and the P-type semiconductor layer 107 is in contact with the P-type electrode 105 and conducting. In the energized state, an electric field is formed between the N-type electrode 103 and the P-type electrode 105. The light-emitting layer 106 is located in this electric field and is electrically connected to the N-type electrode 103 through the N-type semiconductor layer 104 and to the P-type electrode 105 through the P-type semiconductor layer 107. The first insulating layer 110 is disposed on the side of the P-type semiconductor 107 away from the buffer layer 102. It can be in contact with the P-type semiconductor 107. Other films 114, such as the current spreading layer 108, can also be disposed there.

[0073] In some embodiments, the buffer layer 102 may be made of one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and the thickness of the buffer layer 102 may be 10-40 nanometers. The N-type semiconductor layer 104 may be made of N-type doped gallium nitride, and the P-type semiconductor layer 107 may be made of P-type doped gallium nitride. The first insulating layer 110 may be made of silicon oxide or silicon nitride. The light-emitting layer 106 includes a light-emitting material of at least one wavelength to emit light of a specific wavelength.

[0074] In some embodiments, the buffer layer 102 or the first insulating layer 110 is in contact with the adjustment layer 200, and the refractive index of the adjustment layer 200 is greater than 2.4.

[0075] In some embodiments, the buffer layer 102 or the first insulating layer 110 is in contact with the adjustment layer 200. The material of the adjustment layer 200 can be selected from at least one of indium gallium nitride, gallium arsenide, gallium phosphide, and silicon carbide, for example, using only one of these materials or a combination of multiple materials. The overall refractive index of the adjustment layer 200 is greater than 2.4. Exemplarily, the adjustment layer 200 can adopt a single-layer or multi-layer structure. If it is a multi-layer structure, the materials of each layer can be different, but its overall refractive index must be greater than 2.4.

[0076] Based on the above embodiments, the buffer layer 102 or the first insulating layer 110 is in contact with the adjustment layer 200. The adjustment layer 200 is made of at least one of indium gallium nitride, gallium arsenide, gallium phosphide, or silicon carbide, and its refractive index is greater than 2.4. Specifically, the refractive index of indium gallium nitride is 2.48-2.8, the refractive index of gallium arsenide is 3.927, the refractive index of gallium phosphide is 3.5, and the refractive index of silicon carbide is 2.65. The adjustment layer 200 can also be made of other materials that meet the refractive index requirements.

[0077] The adjustment layer 200 can be disposed on the buffer layer 102 or the first insulating layer 110. As shown in Figure 18, when the chip body 100 is in a forward-mounted structure, the adjustment layer 200 is in contact with the first insulating layer 110. As shown in Figure 19, when the chip body 100 is a flip-chip structure without a substrate 101 (thin-film flip-chip structure), the adjustment layer 200 is in contact with the buffer layer 102. The refractive index of the adjustment layer 200 is greater than the refractive index of the contacting buffer layer 102 or the first insulating layer 110. For example, the adjustment layer 200 is made of indium gallium nitride and is formed by epitaxial growth or vacuum deposition to ensure that the adjustment layer 200 has a high transmittance of light emitted from the chip body 100.

[0078] The chip body 100 also includes a current spreading layer 108 and a second reflective layer 109. The current spreading layer 108 is disposed between the P-type semiconductor layer 107 and the first insulating layer 110, and is in contact with the P-type electrode 105. The second reflective layer 109 is disposed on the side of the buffer layer 102 away from the light-emitting layer 106, or the second reflective layer 109 is disposed on the side of the first insulating layer 110 away from the buffer layer 102, and a second insulating layer 111 is also disposed on the side of the second reflective layer 109 away from the buffer layer 102. When the second reflective layer 109 is disposed on the side of the buffer layer 102 away from the light-emitting layer 106, the adjustment layer 200 is in contact with the first insulating layer 110. The current spreading layer 108 can improve the distribution capability of the P-type electrode 105, allowing holes to be distributed as evenly as possible in the area where the P-type semiconductor layer 107 is located. The material of the current spreading layer 108 can be a transparent conductive material or silver, etc. The reflective layer is configured to adjust the light emission direction of the light-emitting diode chip.

[0079] As an example, referring to Figure 18, a buffer layer 102 and an N-type semiconductor 104 are stacked sequentially. A light-emitting layer 106 is disposed on the side of the N-type semiconductor layer 104 facing away from the buffer layer 102, and a P-type semiconductor layer 107 is disposed on the side of the light-emitting layer 106 facing away from the buffer layer 102. A current spreading layer 108 contacts the side of the P-type semiconductor layer 107 facing away from the buffer layer 102. An N-type electrode 103 contacts the N-type semiconductor layer 104, and a P-type electrode 105 contacts both the P-type semiconductor layer 107 and the current spreading layer 108. A first insulating layer 110 is disposed on the side of the current spreading layer 108 facing away from the buffer layer 102, and a second reflective layer 109 is disposed on the side of the buffer layer 102 facing away from the light-emitting layer 106.

[0080] Based on the above example, a chip body 100 with a positive mounting structure is formed, and the light emission direction of the light-emitting diode chip is in the direction away from the location of the buffer layer 102, that is, the upward arrow direction shown in Figure 18. The adjustment layer 200 is disposed on the side of the first insulating layer 110 away from the buffer layer 102 and is in contact with the first insulating layer 110.

[0081] As another example, referring to Figures 19 and 20, a buffer layer 102 and an N-type semiconductor 104 are stacked sequentially. A light-emitting layer 106 is disposed on the side of the N-type semiconductor layer 104 facing away from the buffer layer 102, and a P-type semiconductor layer 107 is disposed on the side of the light-emitting layer 106 facing away from the buffer layer 102. A current spreading layer 108 contacts the side of the P-type semiconductor layer 107 facing away from the buffer layer 102. An N-type electrode 103 contacts the N-type semiconductor layer 104, and a P-type electrode 105 contacts both the P-type semiconductor layer 107 and the current spreading layer 108. A first insulating layer 110 is disposed on the side of the current spreading layer 108 facing away from the buffer layer 102, and a second reflective layer 109 is disposed on the side of the first insulating layer 110 facing away from the buffer layer 102. A second insulating layer 111 is also disposed on the side of the second reflective layer 109 facing away from the buffer layer 102.

[0082] Based on the above example, a flip-chip body 100 is formed, and the light emission direction of the light-emitting diode chip is towards the buffer layer 102, i.e., the downward arrow direction shown in Figures 19 and 20. The adjustment layer 200 is disposed on the side of the buffer layer 102 away from the light-emitting layer 106 and is in contact with the adjustment layer 200.

[0083] In some embodiments, the chip body 100 further includes a substrate 101, as shown in Figures 18 and 20. The substrate 101 is disposed on the side of the buffer layer 102 facing away from the N-type semiconductor 104. When the adjustment layer 200 is located on the side of the buffer layer 102 facing away from the N-type semiconductor layer 104, the adjustment layer 200 is disposed on the side of the substrate 101 facing away from the N-type semiconductor 104. The material of the substrate 101 may be one of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide.

[0084] In some embodiments, the substrate 101 is in contact with the adjustment layer 200, and the refractive index of the adjustment layer 200 is greater than 1.78.

[0085] In some embodiments, the substrate 101 is in contact with the adjustment layer 200. The material of the adjustment layer 200 can be selected from at least one of indium gallium nitride, gallium arsenide, gallium phosphide, silicon carbide, indium tin oxide, titanium oxide, and tantalum oxide. For example, one of these materials can be selected alone, or a combination of multiple materials can be used, ensuring that the overall refractive index of the adjustment layer 200 is greater than 1.78. Exemplarily, the adjustment layer 200 can adopt a single-layer or multi-layer structure. If it is a multi-layer structure, the materials of each layer can be different, but its overall refractive index must be greater than 1.78.

[0086] As an example, as shown in FIG18, in the chip body 100 with a positive mounting structure, the substrate 101 is disposed between the buffer layer 102 and the second reflective layer 109, and the adjustment layer 200 is in contact with the first insulating layer 110.

[0087] As another example, as shown in Figure 20, in a flip-chip body 100 with a substrate 101, the substrate 101 is disposed between a buffer layer 102 and an adjustment layer 200, i.e., the substrate 101 is in contact with the adjustment layer 200. The adjustment layer 200 is made of at least one of indium tin oxide, titanium oxide, or tantalum oxide, and its refractive index is greater than 1.78. Specifically, indium tin oxide has a refractive index of 1.858, titanium oxide includes titanium dioxide, titanium pentoxide, and titanium trioxide, all with a refractive index of 2.35, and tantalum oxide has a refractive index of 2.1. For example, the adjustment layer 200 is made of ITO and formed by magnetron sputtering, thus providing high transmittance of light emitted from the chip body 100. The adjustment layer 200 can also be made of other materials that meet the refractive index requirements.

[0088] Referring to FIG21, in some possible embodiments, the chip body 100 includes a bonding substrate 112, a bonding layer 113, an N-type semiconductor layer 104, a P-type semiconductor layer 107, an N-type electrode 103, a P-type electrode 105, a light-emitting layer 106, and a first insulating layer 110. A bonding substrate 112 and a bonding layer 113 are sequentially disposed on a P-type electrode 105. A P-type semiconductor layer 107 is disposed on the side of the bonding layer 113 away from the bonding substrate 112 and in contact with the bonding layer 113. A light-emitting layer 106 is disposed on the side of the P-type semiconductor layer 107 away from the bonding substrate 112. An N-type semiconductor layer 104 is disposed on the side of the light-emitting layer 106 away from the bonding substrate 112. A first insulating layer 110 is disposed on the side of the N-type semiconductor layer 104 away from the light-emitting layer 106. The N-type electrode 103 contacts the side of the N-type semiconductor layer 104 away from the bonding substrate 112. An adjustment layer 200 is disposed on the side of the first insulating layer 110 away from the N-type semiconductor layer 104.

[0089] As shown in Figure 21, a bonding substrate 112 is disposed on the surface of the P-type electrode 105, and a bonding layer 113 is disposed on the surface of the bonding substrate 112 facing away from the P-type electrode 105. A P-type semiconductor layer 107 is disposed on the surface of the bonding layer 113 facing away from the bonding substrate 112, and a light-emitting layer 106 is disposed on the surface of the P-type semiconductor layer 107 facing away from the bonding substrate 112. An N-type semiconductor layer 104 is disposed on the surface of the light-emitting layer 106 facing away from the bonding substrate 112, and a first insulating layer 110 is disposed on the surface of the N-type semiconductor layer 104 facing away from the light-emitting layer 106. An adjustment layer 200 is disposed on the surface of the first insulating layer 110 facing away from the N-type semiconductor layer 104, i.e., the adjustment layer 200 is in contact with the first insulating layer 110. The N-type electrode 103 penetrates through the adjustment layer 200 and the first insulating layer 110 to contact the surface of the N-type semiconductor layer 104 facing away from the bonding substrate 112.

[0090] In some embodiments, the adjustment layer 200 is made of at least one of indium gallium nitride, gallium arsenide, gallium phosphide, silicon hydride, chromium oxide, or chromium, and the refractive index of the adjustment layer 200 is greater than 2.4. The chip body 100 also includes a second reflective layer 109, which is disposed between the P-type semiconductor layer 107 and the bonding layer 113. The second reflective layer 109 may be located within the area enclosed by the P-type semiconductor layer 107 and the bonding layer 113.

[0091] For example, the second reflective layer 109 is embedded within the bonding layer 113, and the surface of the second reflective layer 109 facing away from the bonding substrate 112 is flush with the surface of the bonding layer 113 facing away from the bonding substrate 112. By setting the second reflective layer 109, the light emission direction of the light-emitting diode chip can be the upward direction indicated by the arrow in Figure 7, forming a vertically structured light-emitting diode chip.

[0092] In some embodiments, the light-emitting diode (LED) chips provided in this application have a wide range of applicability in terms of structure, wavelength, and size. For example, in terms of structure, they can adopt a conventional, flip-chip, vertical, or thin-film architecture; in terms of wavelength characteristics, they can be single-wavelength or multi-wavelength chips; in terms of size, they can be miniature LED chips, micro LED chips, or conventionally sized chips.

[0093] Referring to Figures 22 and 23, this application embodiment also provides a display module, including a driving backplane 300 and the aforementioned light-emitting diode (LED) chip. The LED chip is disposed on the driving backplane 300 and electrically connected to the driving backplane 300. The driving backplane 300 can be a thin-film transistor (TFT) driving backplane 300 or a complementary metal-oxide-semiconductor (CMOS) driving backplane 300.

[0094] As one possible implementation, a plurality of light-emitting diode (LED) chips can be disposed on the driving backplane 300. These LED chips are arranged in an array on the driving backplane 300, and the driving backplane 300 can provide driving current to the LED chips, thereby driving them to emit light. As shown in Figure 22, LED chips C1, C2, C3, and C4 are arranged on the driving backplane 300. In some examples, there may be five, six, or more LED chips arranged in an array. The number of LED chips can be adjusted.

[0095] As another possible implementation, the driving backplane 300 includes a driving substrate 301 and multiple driving units 302. Each driving unit 302 is electrically connected to a corresponding plurality of light-emitting diode (LED) chips, and all driving units 302 are electrically connected to the driving substrate 301. The driving units 302 and the driving substrate 301 can also be TFT or CMOS. As shown in Figure 23, LED chips C1 and C2 are electrically connected to one driving unit 302, and LED chips C3 and C4 are connected to another driving unit 302. Both driving units 302 are electrically connected to the driving substrate 301. The number of driving units 302 and the number of LED chips connected to each driving unit 302 can be adjusted.

[0096] In some embodiments, depending on the type of light-emitting diode chip used, the display module provided in this application embodiment can be divided into LED display module, Mini LED display module and Micro LED display module.

[0097] This application also provides a full-color display screen, which can be manufactured by packaging the display module described above.

[0098] This application also provides an electronic device including the aforementioned full-color display screen. This electronic device can be a television, electronic watch, e-reader, desktop computer, laptop computer, tablet computer, mobile phone, augmented reality (AR) device, or virtual reality (VR) device, etc. When the light-emitting diode chip of the electronic device includes ultraviolet light pixels, the electronic device can also be an ultraviolet curing lamp or an ultraviolet detection lamp, etc.

[0099] This application also provides a lighting device, including a circuit board and the aforementioned light-emitting diode (LED) chips. The LED chips are disposed on the circuit board and electrically connected to the circuit board. This lighting device can be a lamp, such as a street lamp or decorative lamp. The circuit board can be a printed circuit board (PCB) or a flexible printed circuit board (FPC). Multiple LED chips can be disposed on the circuit board, arranged in an array on the circuit board, and the circuit board drives the multiple LED chips to emit light.

[0100] In some embodiments, FIG24 exemplarily illustrates a schematic diagram of the structure of a lighting device 600. As shown in FIG24, a plurality of light-emitting diode chips 610 are disposed on a circuit board 620, and the plurality of light-emitting diode chips 610 are electrically connected to the circuit board 620.

[0101] In some embodiments, an encapsulation layer may be disposed above the light-emitting diode chip. After the light-emitting diode chip completes electrical connection, an encapsulation material can be applied to the chip surface through an encapsulation process. The encapsulation material may be a polymer material containing a color conversion material or without a color conversion material.

[0102] In some embodiments, Figures 25 and 26 exemplarily illustrate structural schematic diagrams of two different display modules with encapsulation layers. As shown in Figures 25 and 26, an encapsulation layer 400 is disposed above multiple light-emitting diode chips, which is represented by a rectangular dashed line in the figures.

[0103] In some embodiments, FIG27 exemplarily illustrates a schematic diagram of a lighting device 600 with an encapsulation layer. As shown in FIG27, an encapsulation layer 400 is disposed above a plurality of light-emitting diode chips 610, which is represented by a semi-elliptical dashed line in the figure.

[0104] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the meaning of the above terms in this application as appropriate. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. In the description of this application, "multiple" means two or more, unless otherwise specified.

[0105] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion, for example, including, in addition to processes, methods, systems, products, or devices that include the series of steps or units shown in the embodiments of this application, other processes, methods, systems, products, and devices not listed in this series of steps or units, or other steps or units inherent to these processes, methods, systems, products, or devices.

Claims

1. A light-emitting diode chip, comprising a chip body and an adjustment layer disposed on the chip body, the adjustment layer being located on the light-emitting side of the light-emitting diode chip, and the refractive index of the adjustment layer being greater than the refractive index of a film layer in the chip body that is in contact with the adjustment layer.

2. The light-emitting diode chip according to claim 1, wherein, The adjustment layer also has an optical microstructure formed on the surface opposite to the film layer, and the optical microstructure is configured to improve the light output efficiency of the adjustment layer.

3. The light-emitting diode chip according to claim 2, wherein, The optical microstructure is a concave-convex structure, which is formed by a surface roughening process.

4. The light-emitting diode chip according to claim 2, wherein, The optical microstructure is a photonic crystal, which is formed by electron beam lithography, nanoimprint lithography, or holographic exposure.

5. The light-emitting diode chip according to claim 4, wherein, The end face of the photonic crystal facing away from the film layer is also provided with a through hole.

6. The light-emitting diode chip according to claim 4, wherein, The period of the photonic crystal is 1-5 micrometers.

7. The light-emitting diode chip according to claim 4, wherein, The photonic crystal is a two-dimensional photonic crystal, and the planar shape of the two-dimensional photonic crystal is circular, elliptical, triangular, square, rhomboid, parallelogram, rectangle or polygon. Alternatively, the photonic crystal may be a three-dimensional photonic crystal, and the shape of the three-dimensional photonic crystal may be a triangular prism, a cube, a face-centered cube, a hexagonal close-packed structure, or a cylinder.

8. The light-emitting diode chip according to claim 2, wherein, The height of the optical microstructure is 30%-80% of the thickness of the adjustment layer, and the thickness of the adjustment layer is 0.1-10 micrometers.

9. The light-emitting diode chip according to any one of claims 2-8, wherein, The adjustment layer covers at least a portion of the surface of the film, and the optical microstructure is disposed on at least a portion of the surface of the adjustment layer opposite to the chip body.

10. The light-emitting diode chip according to claim 9, further comprising a first reflective layer, wherein the first reflective layer and the adjustment layer are disposed in the same layer; Alternatively, the first reflective layer is disposed on the side of the adjustment layer opposite to the chip body, and exposes the optical microstructure.

11. The light-emitting diode chip according to claim 10, wherein, The film layer in the chip body that is in contact with the adjustment layer includes a central region and an edge region surrounding the central region. The first reflective layer is located on the edge region of the film layer, and the adjustment layer is located on the central region of the film layer.

12. The light-emitting diode chip according to claim 10, wherein, The adjustment layer includes a central region and an edge region surrounding the central region, the optical microstructure is located in the central region of the adjustment layer, and the first reflective layer is located on the edge region of the adjustment layer.

13. The light-emitting diode chip according to claim 1, wherein, The chip body includes a buffer layer, an N-type electrode, a P-type electrode, an N-type semiconductor layer, a P-type semiconductor layer, a light-emitting layer, and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is disposed on the side of the N-type semiconductor layer away from the buffer layer, the P-type semiconductor layer is disposed on the side of the light-emitting layer away from the buffer layer, the N-type electrode is in contact with the N-type semiconductor layer, and the P-type electrode is in contact with both the N-type semiconductor layer and the P-type semiconductor layer. The first insulating layer is disposed on the side of the P-type semiconductor layer away from the buffer layer. The adjustment layer is disposed on the side of the buffer layer away from the N-type semiconductor layer, or the adjustment layer is disposed on the side of the first insulating layer away from the P-type semiconductor layer.

14. The light-emitting diode chip according to claim 1, wherein, The chip body includes a bonding substrate, a bonding layer, an N-type semiconductor layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, a light-emitting layer, and a first insulating layer; The bonding substrate and the bonding layer are sequentially disposed on the P-type electrode. The P-type semiconductor layer is disposed on the side of the bonding layer away from the bonding substrate and is in contact with the bonding layer. The light-emitting layer is disposed on the side of the P-type semiconductor layer away from the bonding substrate. The N-type semiconductor layer is disposed on the side of the light-emitting layer away from the bonding substrate. The first insulating layer is disposed on the side of the N-type semiconductor layer away from the light-emitting layer. The N-type electrode is in contact with the side of the N-type semiconductor layer away from the bonding substrate. The adjustment layer is disposed on the side of the first insulating layer opposite to the N-type semiconductor.

15. The light-emitting diode chip according to claim 13, wherein, The buffer layer or the first insulating layer is in contact with the adjustment layer, and the refractive index of the adjustment layer is greater than 2.

4.

16. The light-emitting diode chip according to claim 15, wherein, The adjustment layer is made of at least one of indium gallium nitride, gallium arsenide, gallium phosphide, or silicon carbide.

17. The light-emitting diode chip according to claim 15, wherein, The chip body also includes a substrate, which is disposed on the side of the buffer layer away from the N-type semiconductor; When the adjustment layer is located on the side of the buffer layer away from the N-type semiconductor layer, the adjustment layer is disposed on the side of the substrate away from the N-type semiconductor.

18. The light-emitting diode chip according to claim 17, wherein, The substrate is in contact with the adjustment layer, and the refractive index of the adjustment layer is greater than 1.

78.

19. The light-emitting diode chip according to claim 18, wherein, The material of the adjustment layer is at least one of indium gallium nitride, gallium arsenide, gallium phosphide, silicon carbide, indium tin oxide, titanium oxide, or tantalum oxide.

20. The light-emitting diode chip according to claim 13, wherein, The chip body further includes a current spreading layer and a second reflective layer. The current spreading layer is disposed between the P-type semiconductor layer and the first insulating layer and is in contact with the P-type electrode. The second reflective layer is disposed on the side of the buffer layer away from the light-emitting layer, or the second reflective layer is disposed on the side of the first insulating layer away from the buffer layer, and the side of the second reflective layer away from the buffer layer is further provided with a second insulating layer; When the second reflective layer is disposed on the side of the buffer layer away from the light-emitting layer, the adjustment layer contacts the first insulating layer.

21. A display module, comprising a driving backplane and a light-emitting diode chip according to any one of claims 1-20, wherein the light-emitting diode chip is disposed on the driving backplane and electrically connected to the driving backplane.

22. A lighting device comprising a circuit board and a light-emitting diode chip according to any one of claims 1-20, wherein the light-emitting diode chip is disposed on the circuit board and electrically connected to the circuit board.

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