Semiconductor device and method for fabricating semiconductor device

Abstract

Provided is a semiconductor device which allows for miniaturization and a higher level of integration. In this semiconductor device, a first insulating layer is located on a first conductive layer, a second insulating layer and a second conductive layer are located on the first insulating layer, and a third conductive layer is located on the second conductive layer. The first insulating layer, the second conductive layer, and the third conductive layer each have an opening portion that reaches the first conductive layer. The opening portion of the second conductive layer has a portion located farther outward than the opening portion of the third conductive layer in a plan view. The second insulating layer covers the lateral surface of the second conductive layer on the opening portion-side. The second insulating layer is located farther outward than the opening portion of the third conductive layer and farther inward than the opening portion of the second conductive layer in a plan view. A semiconductor layer has: a portion covering the area overlapping the opening portion on the top surface of the first conductive layer; a portion covering the lateral surface of the first insulating layer on the opening portion-side; and portions respectively covering the lateral surfaces of the second and third conductive layers on the opening portion-side, with the second insulating layer therebetween.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, metal oxides have also attracted attention as other materials.

[0007] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple overlapping memory cells. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using a metal oxide film. Non-Patent Document 2 also discloses a vertically structured transistor.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53X. Duan et. al, “Novel Vertical Channel-All-Around (CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F2 by Monolithic Stacking”, IEDM Tech. Dig. , 2021, pp. 222-225 Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with low parasitic capacitance.

[0012] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high yield.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high reliability.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is a semiconductor device including: a first conductive layer; a first insulating layer over the first conductive layer; a second insulating layer and a second conductive layer over the first insulating layer; a third conductive layer over the second conductive layer; and a semiconductor layer. The first insulating layer, the second conductive layer, and the third conductive layer have an opening reaching the first conductive layer. In a plan view, a periphery of the opening of the second conductive layer has a portion located outside a periphery of the opening of the third conductive layer. The second insulating layer covers a side surface of the second conductive layer on the opening side. In a plan view, the second insulating layer is located outside the periphery of the opening of the third conductive layer and inside the periphery of the opening of the second conductive layer. The semiconductor layer includes a portion covering a region overlapping with the opening on a top surface of the first conductive layer, a portion covering the side surface of the first insulating layer on the opening side, a portion covering the side surface of the second conductive layer on the opening side with the second insulating layer sandwiched therebetween, and a portion covering the side surface of the third conductive layer on the opening side.

[0015] In the above aspect, it is preferable to have a third insulating layer on the semiconductor layer and a fourth conductive layer on the third insulating layer, and the fourth conductive layer has a portion that faces the side surface of the first insulating layer on the opening side, with the semiconductor layer and the third insulating layer sandwiched therebetween.

[0016] In the above embodiment, the semiconductor layer preferably has a portion covering an upper surface of the third conductive layer.

[0017] Alternatively, one embodiment of the present invention includes a first conductive layer, a first insulating layer over the first conductive layer, a second insulating layer and a second conductive layer over the first insulating layer, a third conductive layer over the second conductive layer, a semiconductor layer, and a third insulating layer over the second insulating layer and the third conductive layer, wherein the first insulating layer, the second conductive layer, the third conductive layer, and the third insulating layer have openings that reach the first conductive layer, and a periphery of the opening of the second conductive layer has a portion located outside a periphery of the opening of the third conductive layer in a plan view, and the second insulating layer has a portion located on the opening side of the second conductive layer. In a plan view, the second insulating layer is located outside the periphery of the opening in the third conductive layer and inside the periphery of the opening in the second conductive layer, and the semiconductor layer has a first portion covering a region overlapping with the opening on the top surface of the first conductive layer, a second portion covering the side surface of the first insulating layer on the opening side, a third portion covering the side surface of the second conductive layer on the opening side with the second insulating layer in between, a fourth portion covering the side surface of the third conductive layer on the opening side, and a fifth portion covering the side surface of the third insulating layer on the opening side.

[0018] In the above aspect, it is preferable to have a fourth insulating layer on the semiconductor layer and a fourth conductive layer on the fourth insulating layer, and the fourth conductive layer has a portion facing the side surface of the first insulating layer on the opening side, with the semiconductor layer and the fourth insulating layer sandwiched therebetween, and a portion facing the side surface of the third insulating layer on the opening side, with the semiconductor layer and the fourth insulating layer sandwiched therebetween.

[0019] In the above aspect, it is preferable that the semiconductor layer has a sixth portion covering an upper surface of the third conductive layer, and the third insulating layer covers an upper surface of the sixth portion of the semiconductor layer.

[0020] Alternatively, one embodiment of the present invention includes forming a first conductive layer; sequentially forming a first insulating layer, a second conductive layer, and a third conductive layer over the first conductive layer; forming a first opening in the third conductive layer that reaches the second conductive layer; forming a second opening in the second conductive layer that reaches the first insulating layer; forming a third opening in the first insulating layer that reaches the first conductive layer; forming a first portion that covers an upper surface of the first conductive layer that overlaps with the second opening, a second portion that covers a side surface of the first insulating layer on the third opening side; and a third portion that covers a side surface of the second conductive layer on the second opening side and is located below the third conductive layer. a fourth portion covering a side surface of the third conductive layer facing the first opening, and a fifth portion covering an upper surface of the third conductive layer; forming a second insulating layer by processing the first insulating film so as to leave the third portion and remove the first portion and the fifth portion; forming a semiconductor layer; forming a third insulating layer on the semiconductor layer; and forming a fourth conductive layer on the third insulating layer; and forming the second opening so that the periphery of the second opening has a portion located outside the periphery of the first opening in a plan view.

[0021] In the above aspect, the second opening in the second conductive layer is preferably formed using isotropic etching conditions.

[0022] Alternatively, one embodiment of the present invention includes forming a first conductive layer; forming a first insulating layer, a second conductive layer, a third conductive layer, a first sacrificial layer, and a second insulating layer in this order over the first conductive layer; providing a first opening in the second insulating layer that reaches the first sacrificial layer; providing a second opening in the first sacrificial layer that reaches the third conductive layer; providing a third opening in the third conductive layer that reaches the second conductive layer; providing a fourth opening in the second conductive layer that reaches the first insulating layer; and providing a fifth opening in the first insulating layer that reaches the first conductive layer. a first portion covering an upper surface of the first conductive layer that overlaps with the second opening, a second portion covering a side surface of the first insulating layer on the fifth opening side, a third portion covering a side surface of the second conductive layer on the fourth opening side and positioned below the third conductive layer, a fourth portion covering a side surface of the third conductive layer on the third opening side, a fifth portion covering a side surface of the first sacrificial layer on the second opening side, a sixth portion covering a side surface of the second insulating layer on the first opening side, and a seventh portion covering an upper surface of the second insulating layer. a semiconductor layer formed on the semiconductor layer; a fourth insulating layer formed on the semiconductor layer; a fourth conductive layer formed on the fourth insulating layer; a fourth opening formed such that, in a plan view, a periphery of the fourth opening has a portion located outside the periphery of the third opening; the semiconductor layer formed to have a portion covering a side surface of the second insulating layer at least in the first opening; the second sacrificial layer formed in the first opening has a portion facing a side surface of the second insulating layer in the first opening with the semiconductor layer sandwiched therebetween; and a height of an upper surface of the second sacrificial layer formed in the first opening is lower than a height of an upper surface of the second insulating layer at the periphery of the first opening.

[0023] In the above aspect, the fourth opening in the second conductive layer is preferably formed using isotropic etching conditions.

[0024] In the above aspect, the second sacrificial layer is preferably made of spin-on-carbon.

[0025] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with low parasitic capacitance can be provided.

[0026] According to one embodiment of the present invention, a method for manufacturing a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with low parasitic capacitance can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a perspective view showing an example of a semiconductor device. FIGS. 1C and 1D are cross-sectional views illustrating an example of a semiconductor device. FIG. 2A is a plan view showing an example of a semiconductor device. FIG. 2B is a perspective view showing an example of a semiconductor device. FIGS. 2C and 2D are cross-sectional views illustrating an example of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIG. 3B is a perspective view showing an example of a semiconductor device. FIGS. 3C and 3D are cross-sectional views illustrating an example of a semiconductor device. FIG. 4A is a plan view showing an example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views illustrating an example of a semiconductor device. FIG. 5A is a plan view showing an example of a semiconductor device. FIG. 5B is a perspective view showing an example of a semiconductor device. FIG. 5C is a cross-sectional view illustrating an example of a semiconductor device. FIG. 6A is a plan view showing an example of a semiconductor device. FIGS. 6B and 6C are perspective views showing an example of a semiconductor device. FIG. 6D is a cross-sectional view illustrating an example of a semiconductor device. FIG. 7A is a plan view showing an example of a semiconductor device. FIG. 7B is a perspective view showing an example of a semiconductor device. FIGS. 7C and 7D are cross-sectional views illustrating an example of a semiconductor device. FIG. 8A is a plan view illustrating an example of a semiconductor device. 8B and 8C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 9A to 9C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 10A to 10C are plan views illustrating an example of a semiconductor device. FIGS. 11A to 11D are cross-sectional views illustrating an example of a semiconductor device. FIG. 12 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 13A to 13D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 14A to 14D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 15A to 15E are cross-sectional views illustrating an example of a semiconductor device. FIG. 16A is a plan view illustrating an example of a semiconductor device. FIG. 16B is a perspective view illustrating an example of a semiconductor device. FIGS. 16C and 16D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 18A to 18C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 19A to 19C are cross-sectional views illustrating an example of a semiconductor device. FIG. 20A is a plan view illustrating an example of a semiconductor device.FIG. 20B is a perspective view showing an example of a semiconductor device. FIGS. 20C and 20D are cross-sectional views illustrating an example of a semiconductor device. FIG. 21A is a plan view showing an example of a semiconductor device. FIG. 21B is a perspective view showing an example of a semiconductor device. FIGS. 21C and 21D are cross-sectional views illustrating an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B and 22C are cross-sectional views illustrating an example of a semiconductor device. FIG. 23A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 23B and 23C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 25B and 25C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 26B and 26C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 27A is a plan view showing an example of a manufacturing method of a semiconductor device. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 31B and 31C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 32A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 32B and 32C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 33A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 33B and 33C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 34B and 34C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 35A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 35B and 35C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 36A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 36B and 36C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 37A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 37B and 37C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 38A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 38B and 38C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 39A is a plan view illustrating an example of a memory device. FIG. 39B is a cross-sectional view illustrating an example of a memory device. FIG. 40A is a plan view illustrating an example of a memory device. FIGS. 40B and 40C are cross-sectional views illustrating an example of a memory device. FIG. 41 is a cross-sectional view illustrating an example of a memory device. FIG. 42 is a cross-sectional view illustrating an example of a memory device. FIG. 43A is a block diagram illustrating a structural example of a semiconductor device. FIGS. 43B and 43C are perspective views illustrating a structural example of a semiconductor device. 44A to 44H are diagrams illustrating an example of a circuit configuration of a memory cell. FIG. 45 is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 46A is a block diagram illustrating a CPU. FIG. 46B is a perspective view of a semiconductor device. FIG. 47 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 48A and 48B are perspective views showing an example of a display device. FIG. 48C is a diagram illustrating an example of a circuit configuration of a pixel. FIGS. 49A and 49B are cross-sectional views showing an example of a display device. FIGS. 50A to 50C are diagrams illustrating an example of a configuration of a display device. FIGS. 51A and 51B are diagrams illustrating an example of a configuration of an electronic component. FIGS. 52A to 52C are diagrams illustrating an example of a mainframe computer. FIG. 52D is a diagram illustrating an example of space equipment. FIG. 52E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 53A to 53F are diagrams illustrating an example of electronic equipment. FIGS. 54A to 54G are diagrams illustrating an example of electronic equipment. FIGS. 55A and 55B are diagrams illustrating the carrier concentration dependence of Hall mobility. Fig. 55C is a cross-sectional view illustrating an indium oxide film. Fig. 56A and Fig. 56B are cross-sectional views showing an example of a semiconductor device.FIG. 57A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 57B and 57C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 58A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 58B and 58C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 59A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 59B and 59C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 60A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 60B and 60C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 61A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 61B and 61C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 62A is a plan view illustrating an example of a semiconductor device. FIGS. 62B and 62C are cross-sectional views illustrating an example of a semiconductor device. FIG. 63A is a plan view illustrating an example of a semiconductor device. FIGS. 63B and 63C are cross-sectional views illustrating an example of a semiconductor device. FIG. 64 is a view showing a result of cross-sectional observation. FIG. 65 is a view showing a result of cross-sectional observation. Fig. 66 is a diagram showing the results of cross-sectional observation. Fig. 67 is a diagram showing the results of cross-sectional observation. Fig. 68 is a diagram showing the results of cross-sectional observation. Fig. 69 is a diagram showing the results of cross-sectional observation. Figs. 70A to 70C are diagrams showing the results of cross-sectional observation. Figs. 71A to 71C are diagrams showing the results of cross-sectional observation. Figs. 72A to 72C are diagrams showing the results of cross-sectional observation. Figs. 73A and 73B are diagrams showing the results of cross-sectional observation. Figs. 74A to 74C are diagrams showing the results of cross-sectional observation. Figs. 75A to 75C are diagrams showing the results of cross-sectional observation. Figs. 76A to 76C are diagrams showing the results of cross-sectional observation.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0036] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0037] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0038] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0039] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0040] In this specification, the term "content" refers to the proportion of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) The content of the metal element X in the metal oxide layer can be expressed as the content not taking into account oxygen, impurities, etc.

[0041] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0042] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0043] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0045] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0046] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0047] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. For example, a path from A to B may have multiple transistors connected via their sources and drains, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." Note that if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply, GND, or the like, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and C are indirectly connected" or "B and C are indirectly connected."

[0048] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0049] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, it can still be said that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0050] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0051] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0052] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0053] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0054] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0055] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0056] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0057] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., vertical directions.

[0058] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0059] In the transistor of one embodiment of the present invention, the source electrode and the drain electrode are located at different heights (for example, heights in a direction perpendicular to a substrate surface or an insulating plane on which the transistor is provided), and a current flows in the height direction through the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0060] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and therefore the area occupied can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0061] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of an insulating layer provided between a source electrode and a drain electrode, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0062] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, high integration and low power consumption of the memory device can be achieved.

[0063] 1A to 1D illustrate a structural example of a semiconductor device according to one embodiment of the present invention. FIG. 1A is a plan view illustrating an example of the semiconductor device. FIG. 1B is a perspective view illustrating the semiconductor device illustrated in FIG. 1A , taken along a plane including dashed-dotted line A1-A2. FIG. 1C is a cross-sectional view corresponding to dashed-dotted line A1-A2 illustrated in FIG. 1A , and FIG. 1D is a cross-sectional view corresponding to dashed-dotted line A3-A4 illustrated in FIG. 1A . Note that some elements are omitted in FIGS. 1A and 1B for clarity. Some elements may also be omitted in subsequent plan views and perspective views. Note that in FIG. 1A and the like, regions where the top surface shapes of the oxide semiconductor layer 230 and the conductive layer 240 are the same are denoted by reference numerals 230 and 240, but the top surface shape of the conductive layer 240 differs from that of the oxide semiconductor layer 230 in that it has an opening 290.

[0064] A semiconductor device of one embodiment of the present invention includes a transistor, an insulating layer 280 , and an insulating layer 278 .

[0065] The transistor includes a conductive layer 240 and an oxide semiconductor layer 230 .

[0066] 1A to 3D, the transistor includes a conductive layer 220, an insulating layer 250, and a conductive layer 260. The conductive layer 220, the insulating layer 250, and the conductive layer 260 will be described with reference to FIG.

[0067] The conductive layer 240 is located on the insulating layer 280 .

[0068] The conductive layer 240 includes a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.

[0069] An opening 290 is provided in the insulating layer 280 and the conductive layer 240. At this time, the opening provided in the insulating layer 280 is referred to as an opening 290a, the opening provided in the conductive layer 240a is referred to as an opening 290b1, and the opening provided in the conductive layer 240b is referred to as an opening 290b2.

[0070] The insulating layer 278 has a portion that is located closer to the interior of the opening 290b1 than the side surface of the conductive layer 240a on the opening 290b1 side. This portion is preferably located below the conductive layer 240b. This portion can also be configured to be located on the insulating layer 280. The insulating layer 278 is preferably in contact with the side surface of the conductive layer 240a on the opening 290b1 side.

[0071] The side surface of the conductive layer 240a on the opening 290b1 side is preferably located outside the side surface of the conductive layer 240b on the opening 290b2 side. For example, in a plan view, the outline (sometimes called the periphery) of the opening 290b1 is preferably located outside the opening 290b2. With this configuration, the insulating layer 278 can have a portion that contacts the side surface of the conductive layer 240a on the opening 290b1 side and is located below the conductive layer 240b. Furthermore, this portion can be configured to be sandwiched between the insulating layer 280 and the conductive layer 240b.

[0072] 1A to 1D , the side surface of conductive layer 240a on the opening 290b1 side is located outside the side surface of insulating layer 280 on the opening 290a side and the side surface of conductive layer 240b on the opening 290b2 side. For example, it can be expressed that the side surface of insulating layer 280 on the opening 290a side, the side surface of conductive layer 240a on the opening 290b1 side, and the side surface of conductive layer 240b on the opening 290b2 side form a continuous surface, and this continuous surface has a recess, and the side surface of conductive layer 240a on the opening 290b1 side forms the bottom of the recess. It can also be expressed that insulating layer 278 is provided so as to fill the recess.

[0073] After forming the opening 290b2 in the conductive layer 240b, the opening 290b1 is formed in the conductive layer 240a. In the etching step for forming the opening 290b1, the side surface of the opening 290b1 is recessed from the side surface of the opening 290b2, so that the side surface of the opening 290b1 can have a shape having a recess in the conductive layer 240a. Here, recessing refers to, for example, processing the side surface of the opening in the direction in which the width of the opening increases.

[0074] Furthermore, by using the same mask to form openings in the conductive layer 240 and the insulating layer 280, or by using the conductive layer 240 as a mask to form openings in the insulating layer 280, it is possible to align the side surface of the insulating layer 280 on the opening 290a side with the side surface of the conductive layer 240b on the opening 290b2 side. Specifically, for example, it is possible to align the positions in the Y direction in the cross-sectional view of Figure 1C, the positions in the X direction in the cross-sectional view of Figure 1D, or the positions in the plan view of Figure 1A.

[0075] Furthermore, after forming an opening in the conductive layer 240b, the shapes of the conductive layer 240b and the insulating layer 280 may change during the process of forming an opening in the insulating layer 280 and the process of recessing the side surface of the opening in the conductive layer 240a. In such cases, for example, the side surface of the conductive layer 240b may not be aligned with the side surface of the insulating layer 280. Specifically, for example, in the Y direction in the cross-sectional view of FIG. 1C , the X direction in the cross-sectional view of FIG. 1D , or the plan view of FIG. 1A , the side surface of the conductive layer 240b may be positioned outward from the side surface of the insulating layer 280. Alternatively, the side surface of the insulating layer 280 may be positioned outward from the side surface of the conductive layer 240b.

[0076] 1A, the outline of opening 290b1 is located outside the outlines of openings 290a and 290b2. Openings 290b1 and 290b2 preferably have an overlapping region, and at least a portion of opening 290b1 is located outside opening 290b2, for example. Opening 290b1 may also have an area located outside opening 290a. Openings 290b1 and 290a preferably have an overlapping region, and openings 290b2 and 290a preferably have an overlapping region.

[0077] 1A shows an example in which the contours of opening 290a and opening 290b2 are the same, but opening 290a and opening 290b2 may have different sizes and shapes. For example, one may be larger than the other. Also, for example, a portion of opening 290b2 may be located outside opening 290a. Also, for example, a portion of opening 290a may be located outside opening 290b2.

[0078] The oxide semiconductor layer 230 has a portion located within the opening 290 .

[0079] The oxide semiconductor layer 230 has a portion along the sidewall of the opening 290. The oxide semiconductor layer 230 has a portion on the bottom surface of the opening 290, a portion along the side surface of the opening 290 of the insulating layer 280, a portion along the side surface of the opening 290 of the conductive layer 240, and a portion on the conductive layer 240. The oxide semiconductor layer 230 is preferably in contact with the top surface of the conductive layer 240 (the top surface of the conductive layer 240b in FIGS. 1B to 1D and the like). The oxide semiconductor layer 230 is preferably in contact with the side surface of the conductive layer 240b. In the structures shown in FIGS. 1A to 1D , the oxide semiconductor layer 230 faces the side surface of the conductive layer 240a on the opening 290b1 side, with the insulating layer 278 sandwiched therebetween.

[0080] The conductive layer 240 functions as an electrode of a transistor. The conductive layer 240 can also function as a wiring of the semiconductor device in addition to the electrode of the transistor. Using a low-resistance material for the conductive layer 240 is preferable because the speed of circuit operation of the semiconductor device can be increased. In the semiconductor device of one embodiment of the present invention, it is preferable to use a low-resistance material for the conductive layer 240a.

[0081] Note that a low-resistance material suitable for the conductive layer 240a may be oxidized by contact with the oxide semiconductor layer 230. Furthermore, contact of the conductive layer 240a with the oxide semiconductor layer 230 may cause defects in the oxide semiconductor layer 230. For example, when tungsten is used as the conductive layer 240a, contact with the oxide semiconductor layer 230 may cause tungsten to extract oxygen from the oxide semiconductor layer 230, which may result in oxidation of the tungsten, generation of oxygen defects in the oxide semiconductor layer 230, and other problems, and there is concern about the effects of these phenomena on transistor characteristics.

[0082] By providing the insulating layer 278 between the side surface of the conductive layer 240a and the oxide semiconductor layer 230, the side surface of the conductive layer 240a can be prevented from contacting the oxide semiconductor layer 230, thereby suppressing the above-described phenomenon. Furthermore, by sandwiching the conductive layer 240b between the top surface of the conductive layer 240a and the oxide semiconductor layer 230, the above-described phenomenon can be suppressed. The conductive layer 240b is preferably made of a material that is not easily oxidized even when in contact with the oxide semiconductor layer 230. Additionally, the conductive layer 240b is preferably made of a material that has good bonding with both the conductive layer 240a and the oxide semiconductor layer 230. By using such a material for the conductive layer 240b and sandwiching the conductive layer 240b between the top surface of the conductive layer 240a and the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 may be reduced, which is preferable.

[0083] The conductive layer 240b can be made of a metal oxide, a metal nitride, or the like.

[0084] The oxide semiconductor layer 230 is preferably in contact with the side surface of the conductive layer 240b on the opening 290b2 side. The oxide semiconductor layer 230 is also preferably in contact with the top surface of the conductive layer 240b.

[0085] Insulating layer 278 may have a portion located inside opening 290b1 of conductive layer 240a, as well as a portion located inside opening 290a of insulating layer 280. Fig. 2A is a plan view showing an example of a semiconductor device, Fig. 2B is a perspective view of the semiconductor device shown in Fig. 2A taken along a plane including dashed dotted line A1-A2, Fig. 2C is a cross-sectional view corresponding to dashed dotted line A1-A2 shown in Fig. 2A, and Fig. 2D is a cross-sectional view corresponding to dashed dotted line A3-A4 shown in Fig. 2A.

[0086] 2A to 2D show an example in which the insulating layer 278 has a first portion located inside the side surface of the conductive layer 240a on the opening 290b1 side, and a second portion located inside the side surface of the insulating layer 280 on the opening 290a side, and the first and second portions are connected to each other. The second portion faces the side surface of the insulating layer 280 on the opening 290a side, with the insulating layer 278 sandwiched therebetween.

[0087] 3A and 3D, a portion located inside the side surface of conductive layer 240a on the opening 290b1 side and a portion located inside the side surface of insulating layer 280 on the opening 290a side may be provided separately. Fig. 3A is a plan view showing an example of a semiconductor device, Fig. 3B is a perspective view of the semiconductor device shown in Fig. 3A taken along a plane including dashed dotted line A1-A2, Fig. 3C is a cross-sectional view corresponding to dashed dotted line A1-A2 shown in Fig. 3A, and Fig. 3D is a cross-sectional view corresponding to dashed dotted line A3-A4 shown in Fig. 3A.

[0088] 3A and 3D, the insulating layer 278 is shown as a portion located inside the side surface of the conductive layer 240a on the opening 290b1 side, and the portion of the insulating layer 280 located inside the side surface of the opening 290a side is shown as the insulating layer 278b. The insulating layer 278b contains, for example, the same elements as the insulating layer 278. The insulating layer 278b is formed by processing the same film as the insulating layer 278. Therefore, the insulating layer 278b contains, for example, the same material as the insulating layer 278. In the semiconductor device, the insulating layer 278b can be configured to contact the side surface of the insulating layer 280 on the opening 290a side.

[0089] 3A to 3D , the insulating layer 278b is sandwiched between the side surface of the insulating layer 280 on the opening 290a side and the oxide semiconductor layer 230. The oxide semiconductor layer 230 has a portion that faces the side surface of the insulating layer 280 on the opening 290a side, with the insulating layer 278b sandwiched therebetween.

[0090] The conductive layer 240 is provided on the insulating layer 280. Note that, as shown in FIGS. 4A to 4C , the conductive layer 240 may have a conductive layer 240c between the insulating layer 280 and the conductive layer 240a. FIG. 4A is a plan view showing an example of a semiconductor device. FIG. 4B is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in FIG. 4A , and differs from FIG. 1C mainly in that the conductive layer 240c is provided between the insulating layer 280 and the conductive layer 240a. FIG. 4C is a view corresponding to the dashed dotted line C3-C4 shown in FIG. 4A , and differs from FIG. 1D mainly in that the conductive layer 240c is provided between the insulating layer 280 and the conductive layer 240a.

[0091] In the opening 290, an opening provided in the conductive layer 240c is referred to as an opening 290b3. In plan view, the openings 290b1 and 290b2 preferably have an overlapping region. In plan view, at least a portion of the opening 290b1 is located outside the opening 290b3, for example.

[0092] In the example shown in FIG. 4A, the contour of the opening 290b3 coincides with the contours of the opening 290b2 and the opening 290a, but the size and shape of each opening may be different.

[0093] The conductive layer 240c can be made of a material that is preferably used for the conductive layer 240b. In addition, the conductive layer 240c can be made of a low-resistance material that is not easily oxidized when in contact with the oxide semiconductor layer 230. For example, the conductive layer 240c can be made of a metal that is not easily oxidized, a metal nitride that is not easily oxidized, or the like.

[0094] The details of suitable materials for the conductive layers 240a, 240b, and 240c will be described later.

[0095] Increasing the thickness of the conductive layer 240a can reduce the resistance when the conductive layer 240 is used as wiring. On the other hand, increasing the thickness of the conductive layer 240a increases the aspect ratio of the opening 290. Here, increasing the aspect ratio means, for example, increasing the ratio of the depth to the width of the opening 290. As the aspect ratio increases, the etching time required to form the opening 290 increases, or etching of deep regions becomes more difficult. Furthermore, as the aspect ratio increases, it is preferable to use conditions with higher coverage, such as conditions with a slow film formation rate, when forming the oxide semiconductor layer 230, the insulating layer 250, the conductive layer 260, and the like in the opening 290, which may result in a longer manufacturing process or a higher level of difficulty.

[0096] The thickness of the conductive layer 240a is, for example, preferably 1 nm to 100 nm, more preferably 3 nm to 50 nm, and may be, for example, 5 nm to 30 nm.

[0097] Since the insulating layer 278 is provided in a recess formed by the upper surface of the insulating layer 280, the side surface of the conductive layer 240a, and the lower surface of the conductive layer 240b (in FIGS. 4A to 4C, the recess formed by the upper surface of the conductive layer 240c, the side surface of the conductive layer 240a, and the lower surface of the conductive layer 240b), it can be formed using a film formation method that easily penetrates into the recess, for example, a method with a slow film formation rate. Furthermore, the width of the recess corresponds to the thickness of the conductive layer 240a in the cross section shown in FIG. 1C, for example.

[0098] The thickness of the insulating layer 278 may be sufficient to fill the recess. When filling the recess, for example, the thickness of the insulating film (e.g., insulating film 278f described later in FIG. 26B etc.) that becomes the insulating layer 278 may be set to about half the thickness of the conductive layer 240a, and the recess may be filled.

[0099] Furthermore, the insulating layer 278 does not need to fill the entire recess, but only needs to be thick enough to provide sufficient insulation when covering the side surfaces of the conductive layer 240a.

[0100] Furthermore, as will be described later, unnecessary portions of the insulating film 278f are removed, so the thickness of the insulating film 278f may be thicker than half the thickness of the conductive layer 240a.

[0101] The thickness of the insulating film 278f is, for example, 0.5 nm to 50 nm, and is, for example, two times or less, less than one time, or less than 0.7 times the thickness of the conductive layer 240a.

[0102] For example, the insulating layer 278 is preferably made of a material having a high etching selectivity with respect to the conductive layer 240b. Here, a high etching selectivity means that the etching rate of the insulating layer 278 is higher than the etching rate of the conductive layer 240b under the etching conditions used to form the insulating layer 278. By increasing the selectivity, it is possible to prevent the conductive layer 240b from disappearing during the formation of the insulating layer 278.

[0103] Furthermore, the insulating layer 278 is preferably made of a material that has a high etching selectivity with respect to a layer that will become the bottom of the opening 290 (for example, the conductive layer 220 described below). Furthermore, if the conductive layer 220 has a layered structure, it is preferably made of a material that has a high etching selectivity with respect to an upper conductive layer. By increasing the selectivity, it is possible to prevent the disappearance of the region of the conductive layer 220 that overlaps with the opening 290 during the formation of the insulating layer 278.

[0104] For example, an insulating oxide film, an insulating nitride film, an insulating oxynitride film, an insulating nitride oxide film, or the like can be used for the insulating layer 278. For example, silicon nitride or silicon nitride oxide is preferably used for the insulating layer 278.

[0105] By using silicon nitride as the insulating layer 278, when a metal oxide is used as the conductive layer 240b, etching with a high selectivity to the conductive layer 240b can be performed when forming the insulating layer 278.

[0106] <Configuration Example 1-2 of Semiconductor Device> As shown in Figures 5A to 5C, the opening 290 provided in the insulating layer 280 may be slit-shaped. The opening 290 shown in Figures 5A to 5C extends in the X direction. The slit-shaped opening 290 is provided in the insulating layer 280, and the longitudinal direction of the slit coincides with the X direction. An opening that extends in one direction may be referred to as a groove portion. The groove may also be referred to as a slit or a trench.

[0107] 5A to 5C illustrate a structural example of a semiconductor device according to one embodiment of the present invention. Fig. 5A is a plan view illustrating the example of the semiconductor device. Fig. 5B is a perspective view of the semiconductor device illustrated in Fig. 5A taken along dashed line B3-B4. Fig. 5C is a cross-sectional view corresponding to dashed line B1-B2 illustrated in Fig. 5A.

[0108] 6A, 6B, and 6D are different from the configurations shown in FIGS. 5A to 5C mainly in that an insulating layer 278b is disposed inside the side surface of the insulating layer 280 on the side of the opening 290a. Fig. 6A is a plan view showing an example of a semiconductor device, Fig. 6B is a perspective view of the semiconductor device shown in Fig. 6A taken along dashed line B3-B4, and Fig. 6D is a cross-sectional view corresponding to dashed line B1-B2 shown in Fig. 6A. In the semiconductor devices shown in Fig. 6A, 6B, and 6D, the insulating layer 278b may be configured to contact the side surface of the insulating layer 280 on the side of the opening 290a.

[0109] The insulating layer 278b is provided to extend in the X direction along the sidewall of the insulating layer 280. In Figures 6A, 6B, and 6D, the insulating layer 278b is sandwiched between the side surface of the insulating layer 280 on the opening 290a side and the oxide semiconductor layer 230. The oxide semiconductor layer 230 has a portion that faces the side surface of the insulating layer 280 on the opening 290a side, with the insulating layer 278b sandwiched therebetween.

[0110] Note that the structure shown in FIG. 6B illustrates an example in which the insulating layer 278 and the insulating layer 278b are processed to have the same shape as the top surface shapes of the conductive layer 240b, the oxide semiconductor layer 230, and the like, while the structure shown in FIG. 6C illustrates an example in which the ends of the insulating layer 278 and the insulating layer 278b are not processed to be aligned with the conductive layer 240b, the oxide semiconductor layer 230, and the like, but are left extending in the X direction.

[0111] 7A to 7D include, in addition to the components of the semiconductor device shown in Figures 1A to 1D, a conductive layer 220, an insulating layer 250, and a conductive layer 260. Figure 7A is a plan view showing an example of the semiconductor device, Figure 7B is a perspective view of the semiconductor device shown in Figure 7A taken along a plane including the dashed-dotted line A1-A2, Figure 7C is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in Figure 7A, and Figure 7D is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in Figure 7A.

[0112] 7A to 7D includes a transistor 200, an insulating layer 280, and an insulating layer 278. The transistor 200 includes a conductive layer 220, a conductive layer 240, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260.

[0113] The insulating layer 280 is provided on the conductive layer 220. An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 and the conductive layer 240.

[0114] The oxide semiconductor layer 230 has a portion over the conductive layer 220, a portion along the side surface of the insulating layer 280 on the opening 290a side, and a portion over the conductive layer 240. The oxide semiconductor layer 230 is preferably in contact with the top surface of the conductive layer 220 and the top surface of the conductive layer 240. It is more preferable that the oxide semiconductor layer 230 be in contact with the side surface of the conductive layer 240.

[0115] The insulating layer 250 and the conductive layer 260 each have a portion located in the opening 290. The insulating layer 250 is provided over the oxide semiconductor layer 230. The conductive layer 260 is provided over the insulating layer 250.

[0116] The conductive layer 260 preferably extends in one direction. In the configurations shown in Figures 7A to 7D, the conductive layer 260 extends in the Y direction.

[0117] It is preferable that one of the conductive layer 240 and the conductive layer 220 extends so as to intersect with the conductive layer 260. In the configurations shown in FIGS. 7A to 7D , the conductive layer 240 extends in the X direction. The conductive layer 260 and the conductive layer 240 can each be used as wiring in a semiconductor device. Furthermore, by intersecting the conductive layer 260 and the conductive layer 240, the overlapping area between the conductive layer 260 and the conductive layer 240 can be reduced, thereby reducing the parasitic capacitance between the two conductive layers. Furthermore, by intersecting the conductive layer 260 and the conductive layer 240, for example, a configuration can be achieved in which a plurality of transistors 200 are arranged in a matrix and a transistor 200 corresponding to the intersecting wiring is selected and a signal is applied.

[0118] 7A to 7D show an example in which an edge of the oxide semiconductor layer 230 on the insulating layer 280 coincides with an edge of the conductive layer 240. For example, when the oxide semiconductor layer 230 is processed using the same mask, the edges may coincide in this way. By processing the oxide semiconductor layer 230 and the conductive layer 240 using the same mask, the manufacturing process of the semiconductor device can be simplified.

[0119] 8A to 8C , an end of the oxide semiconductor layer 230 on the insulating layer 280 does not have to coincide with an end of the conductive layer 240. Fig. 8A is a plan view showing an example of a semiconductor device, Fig. 8B is a cross-sectional view corresponding to the dashed dotted line A1-A2 shown in Fig. 8A , and Fig. 8C is a cross-sectional view corresponding to the dashed dotted line A3-A4 shown in Fig. 8A .

[0120] 8B shows an example in which the edge of the oxide semiconductor layer 230 on the insulating layer 280 is located outside the edge of the conductive layer 240. Here, the "outside" refers to the direction away from the center of the opening 290. In Fig. 8B, the oxide semiconductor layer 230 has, for example, a portion in contact with the top surface of the insulating layer 280 and portions in contact with the side surfaces of the conductive layer 240a and the conductive layer 240b on the outer side as viewed from the center of the opening 290.

[0121] 8C shows an example in which the edge of the oxide semiconductor layer 230 on the insulating layer 280 is located inside the edge of the conductive layer 240. Here, the "inside" refers to the direction approaching the center of the opening 290. In Fig. 8C, the insulating layer 250 has, for example, a portion in contact with the side surface of the oxide semiconductor layer 230 and a portion in contact with the top surface of the conductive layer 240b.

[0122] The conductive layer 220 can function as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240 can function as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 260 can function as a gate electrode of the transistor 200. The insulating layer 250 can function as a gate insulating layer of the transistor 200.

[0123] The oxide semiconductor layer 230 preferably contains a metal oxide (also referred to as an oxide semiconductor). When the oxide semiconductor layer 230 contains a metal oxide, the off-state current of the transistor 200 can be made extremely small.

[0124] The oxide semiconductor layer 230 has a portion facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween. The conductive layer 260 also has a portion facing the side surface of the insulating layer 280 on the opening 290 side, with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. At least part of this portion functions as a channel formation region of the transistor 200. A region of the oxide semiconductor layer 230 near the conductive layer 220 functions as one of the source region and the drain region, and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as the other of the source region and the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0125] The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus current flows vertically. That is, a channel is formed in the oxide semiconductor layer 230 in a region provided along the side surface of the opening 290.

[0126] For example, at least part of a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 240 can function as the other of the source region and the drain region of the transistor.

[0127] For example, at least part of a region of the oxide semiconductor layer 230 that is not in contact with the conductive layer 240 can function as a channel formation region of a transistor.

[0128] The transistor 200 includes the oxide semiconductor layer 230 in a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0129] When oxygen vacancies and impurities exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0130] Oxygen is supplied to the oxide semiconductor layer 230 from each layer included in the transistor 200 (e.g., insulating layers such as the insulating layer 250) and each layer disposed around the transistor 200 (e.g., insulating layers such as the insulating layer 280), thereby reducing oxygen vacancies in the oxide semiconductor layer 230. Consider a case where multiple transistors are arranged in a certain region of a semiconductor device. In this case, when the ratio of the volume of each layer that supplies oxygen to the volume occupied by the transistor 200 decreases, the amount of oxygen supplied per transistor 200 decreases. As the integration density of a circuit increases, the transistors 200 are arranged more densely, and therefore the amount of oxygen supplied per transistor decreases. Therefore, in a highly integrated circuit, there is a concern that the extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240 may have a more significant effect on the characteristics of the transistor 200.

[0131] The semiconductor device of one embodiment of the present invention can achieve excellent transistor characteristics even when applied to a memory device having a memory cell array with high element density, a display device having a high-definition display portion, or the like.

[0132] In the transistor 200, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a display device, the resolution of the display portion can be improved.

[0133] In this specification, a planar transistor refers to a transistor in which the source electrode and the drain electrode are located at the same height or approximately the same height relative to a reference plane, and the current flowing through the semiconductor has a lateral component. Here, the reference plane can be, for example, the substrate surface. Here, the lateral direction refers, for example, to a direction parallel to the substrate surface. In this specification, a VFET refers to a transistor in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor has a vertical component. Since a VFET can have two or more of the source electrode, semiconductor, and drain electrode stacked, it can occupy a significantly smaller area than a planar transistor.

[0134] 9A and 9B show enlarged views of FIGS. 8B and 8C, respectively. Also, as an example, FIGS. 9A and 9B show an example in which the conductive layer 220 has a stacked structure of a conductive layer 220a and a conductive layer 220b over the conductive layer 220a, the insulating layer 280 has a stacked structure of an insulating layer 280a, an insulating layer 280b over the insulating layer 280a, and an insulating layer 280c over the insulating layer 280b, and the conductive layer 260 has a stacked structure of a conductive layer 260a and a conductive layer 260b over the conductive layer 260a. The stacked structures of the conductive layer 220, the conductive layer 260, and the insulating layer 280 will be described later.

[0135] 10A and 10B show cross-sectional views (cross-sectional views from the Z direction) as viewed from above and below, respectively. Fig. 10A is a cross-sectional view including the conductive layer 240b, and Fig. 10B is a cross-sectional view including the conductive layer 240a and the insulating layer 278.

[0136] 8A and other figures, insulating layer 278 is omitted for clarity, but the plan view of FIG. 10C shows the relationship between opening 290b1, opening 290b2, and insulating layer 278. In plan view, the periphery of opening 290b1 has a portion located outside the periphery of opening 290b2. In addition, insulating layer 278 has a portion located outside the periphery of opening 290b2 and inside the periphery of opening 290b1.

[0137] 10A , the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Therefore, the side surface of the conductive layer 260 provided at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the periphery of the oxide semiconductor layer 230 determines the channel width of the transistor 200. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). The channel width W of the transistor 200 is shown in FIGS. 10A and 10B .

[0138] The width of opening 290b2 is represented as width D, and the width of opening 290b1 is represented as width Db. Figures 9A and 9B show an example in which the width of opening 290a is the same as the width of opening 290b2.

[0139] In addition, when the width D is narrow, only the conductive layer 260a may be formed in the opening 290 as shown in FIG. 9C, and the conductive layer 260b may be disposed on the opening 290 filled with the conductive layer 260a.

[0140] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0141] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240b on the opening 290b2 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290b2 in the conductive layer 240b is used as the width D of the opening 290. Alternatively, the width of the opening 290b2 at the highest position in the conductive layer 240b, the width of the opening 290b2 at the lowest position, the width of the opening 290b2 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290b2 in the conductive layer 240b, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290a side can be used as the width D. Furthermore, the width of the opening 290a at the highest position in the insulating layer 280, the width of the opening 290a at the lowest position, the width of the opening 290a at the midpoint between these, or the average value of these three widths may be used as the width D.

[0142] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, and more preferably 20 nm to 100 nm. It is also preferably 5 nm to 60 nm, more preferably 10 nm to 60 nm, and more preferably 20 nm to 60 nm. It is also preferably 5 nm to 50 nm, more preferably 10 nm to 50 nm, and more preferably 20 nm to 50 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0143] The insulating layer 278 is provided in a recess defined by the upper surface of the insulating layer 280, the side surface of the conductive layer 240a, and the lower surface of the conductive layer 240b. The depth of the recess corresponds to the thickness of the conductive layer 240a. The depth of the recess is, for example, about half the difference between the width Db and the width D.

[0144] If the difference between width Db and width D is too large, conductive layer 240a will be positioned farther away from the center of opening 290, increasing the area occupied by transistor 200. On the other hand, it is preferable that the difference between width Db and width D is large enough to bury insulating layer 278.

[0145] The width Db is preferably, for example, 2 nm or more larger than the width D. To reduce the area occupied by the transistor 200, the difference between the width Db and the width D is preferably set to be less than 0.5 times the width of the opening D.

[0146] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 9B , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L can be considered to be the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 face each other and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240b face each other in a cross-sectional view. In this case, the channel length L corresponds to the sum of the length of the side surface of the insulating layer 280 on the opening 290 side and the length of the side surface of the insulating layer 278 in a cross-sectional view.

[0147] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made extremely fine, below the exposure limit of photolithography. This increases the on-state current of the transistor 200, thereby improving frequency characteristics. The channel length of the transistor 200 is, for example, 0.1 nm to 60 nm, 0.1 nm to 50 nm, 0.1 nm to 40 nm, 0.1 nm to 30 nm, 0.1 nm to 20 nm, or 0.1 nm to 10 nm. Alternatively, the channel length is, for example, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. Alternatively, for example, it is 5 nm or more and 60 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 40 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 20 nm or less, or 5 nm or more and 10 nm or less.

[0148] Note that the channel length of the transistor 200 corresponds to the thickness of the insulating layer 280 over the conductive layer 220 and does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0149] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0150] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0151] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 1A and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0152] 9A to 10B, the top surface of the insulating layer 210 can be approximately parallel to the substrate surface, and the top surface of the conductive layer 220 can be approximately parallel to the substrate surface.

[0153] <First Modification of Semiconductor Device> FIGS. 56A and 56B show a modification of FIGS. 9A and 9B, which differs from FIGS. 9A and 9B mainly in the configuration and shape of an insulating layer 280a.

[0154] 56A and 56B, the insulating layer 280a has a layered structure of an insulating layer 280a1 with high coverage and an insulating layer 280a2 with high flatness. The insulating layer 280a1 can be formed using a film formation method with high coverage, such as an ALD method. The insulating layer 280a2 can be formed using a method with high film formation rate, such as a sputtering method.

[0155] The insulating layer 280a1 and the insulating layer 280a2 may be made of the same material, or may be made of different materials.

[0156] By forming the insulating layer 280a with the above-described layered structure, the planarity and coverage of the insulating layer 280 can be improved.

[0157] By flattening the top surface of the insulating layer 280a, the planarity of the insulating layers 280b and 280c formed over the insulating layer 280a can be improved.

[0158] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0159] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0160] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0161] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. ＯH) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0162] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0163] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for an oxide semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0164] For example, examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide, also referred to as indium oxide). Examples of the metal oxide include zinc oxide (Zn oxide, also referred to as zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium. Examples of the usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0165] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0166] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0167] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0168] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0169] For example, the oxide semiconductor layer of one embodiment of the present invention includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC structure, a polycrystalline (poly-crystalline) structure, and an nc structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0170] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0171] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0172] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0173] Indium oxide that can be used for the oxide semiconductor layer of one embodiment of the present invention will be described below.

[0174] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0175] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0176] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 55A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ), and FIG. 55B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0177] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 55B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 55A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 55A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 55A.

[0178] 55A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0179] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0180] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0181] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0182] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 55A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0183] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0184] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0185] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0186] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0187] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0188] The channel formation region may refer to, for example, a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between a region in contact with the source electrode and a region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0189] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0190] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0191] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0192] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 55C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0193] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0194] Furthermore, as shown in FIG. 55C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２) or reacts with oxygen contained in the membrane and is released as water molecules.

[0195] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0196] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0197]

[0198] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0199] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0200] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0201] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0202] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0203] <Second Modification of Semiconductor Device> Fig. 11A shows a modification of Fig. 9B . In the configuration example shown in Fig. 9B , the side surface of insulating layer 278 forms a continuous surface with the side surface of conductive layer 240b on the opening 290b2 side and the side surface of insulating layer 280 on the opening 290a side, whereas in the configuration example shown in Fig. 11A , the side surface of insulating layer 278 is located more outward from the side surface of conductive layer 240b on the opening 290b2 side and the side surface of insulating layer 280 on the opening 290a side when viewed from the inside of the opening. It may also be expressed that the side surface of insulating layer 278 is located in a recess in the plane formed by the side surface of insulating layer 278, the side surface of conductive layer 240b on the opening 290b2 side, and the side surface of insulating layer 280 on the opening 290a side.

[0204] Fig. 11B shows an enlarged view of the area surrounded by the two-dot chain line in Fig. 11A. In the cross section shown in Fig. 11B, the side surface of insulating layer 278 is located outward by a width d1 from the side surface of conductive layer 240b or the side surface of insulating layer 280. Here, "outward" refers to, for example, the outward side as seen from the inside of opening 290b1.

[0205] 11A , the oxide semiconductor layer 230 can be in contact with the bottom surface of the conductive layer 240b in addition to the top and side surfaces thereof, thereby increasing the contact area. Increasing the contact area can increase the on-state current of the transistor. Furthermore, increasing the contact area can suppress peeling of the oxide semiconductor layer 230. Furthermore, the region in contact with the conductive layer 240b can function as a drain region, for example. Increasing the thickness of the oxide semiconductor layer 230 at the interface between the drain region and the channel formation region can improve the reliability of the transistor 200 in some cases.

[0206] <Variation 3 of Semiconductor Device> Figure 11C shows an example of an enlarged view including insulating layer 278 and its surrounding components. In the configuration shown in Figure 11C, insulating layer 278 has a recess. If the thickness of the insulating film (insulating film 278f described later in Figure 26B and other figures) that becomes insulating layer 278 is less than half the thickness of conductive layer 240a, for example, not all of the space between the upper surface of insulating layer 280 and the lower surface of conductive layer 240b will be filled, resulting in the configuration shown in Figure 11C.

[0207] 9B . As described above with reference to FIGS. 3A to 3D , the semiconductor device of one embodiment of the present invention may include an insulating layer 278b so as to cover the side surface of the opening 290a of the insulating layer 280. In FIG. 11D , the insulating layer 278b is provided in contact with the side surface of the insulating layer 280 on the opening 290a side.

[0208] 11D shows an example in which the insulating layer 278b covers the side surfaces of the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c, but the insulating layer 278b may not cover the insulating layer 280c. Alternatively, the insulating layer 278b may cover only the insulating layer 280a.

[0209] The circumferential width of the oxide semiconductor layer 230 in the portion facing the opening 290a is defined as width Da. The width Da is smaller than the width D by, for example, the thickness of the insulating layer 278b.

[0210] 12 , in a semiconductor device of one embodiment of the present invention, a transistor 200 may include a conductive layer 255. The conductive layer 255 can function as a second gate electrode of the transistor 200.

[0211] An insulating layer is provided between the conductive layer 255 and the oxide semiconductor layer 230, and the insulating layer can function as a second gate insulating layer. In FIG. 12, an insulating layer 278b is used as the insulating layer.

[0212] 12 can also be expressed as a structure having a stacked structure of an insulating layer 280_1, a conductive layer 255, and an insulating layer 280_2 instead of the insulating layer 280 in the structure shown in Fig. 11D. An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280_1, the conductive layer 255, the insulating layer 280_2, and the conductive layer 240 instead of the insulating layer 280.

[0213] An insulating layer 280_1, a conductive layer 255, and an insulating layer 280_2 are sequentially disposed between the conductive layer 220 and the conductive layer 240. The insulating layer 280_1 is disposed between the conductive layer 220 and the conductive layer 255, and the insulating layer 280_2 is disposed between the conductive layer 255 and the conductive layer 240. In FIG. 12 , an opening provided in the insulating layer 280_1, the conductive layer 255, and the insulating layer 280_2 is an opening 290a, an opening provided in the conductive layer 240a is an opening 290b1, and an opening provided in the conductive layer 240b is an opening 290b2.

[0214] The insulating layer 278b has a portion that covers the side surface of the conductive layer 255. The oxide semiconductor layer 230 has a portion that faces the side surface of the conductive layer 255, with the insulating layer 278b sandwiched therebetween.

[0215] In the transistor 200, the potential applied to the conductive layer 260 functioning as the first gate electrode is changed independently of the potential applied to the conductive layer 255 functioning as the second gate electrode, thereby reducing the threshold voltage V ｔｈ When the transistor 200 is an n-channel transistor, the V ｔｈcan be increased, thereby reducing the drain current when the potential applied to the first gate electrode is 0 V. Note that the conductive layer 260 may function as the second gate electrode, and the conductive layer 255 may function as the first gate electrode.

[0216] Alternatively, the conductive layer 260 may be connected to the conductive layer 255. Connecting the conductive layer 255 and the conductive layer 260 and applying the same potential thereto makes it possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress variations in threshold voltage caused by DIBL (Drain Induced Barrier Lowering).

[0217] <Variation 5 of Semiconductor Device> Fig. 13A shows a variation of Fig. 9B . Fig. 13B shows an enlarged view of the region surrounded by a two-dot chain line in Fig. 13A . As described above with reference to Figs. 2A to 2D , in the semiconductor device of one embodiment of the present invention, the insulating layer 278 may have a portion that covers the side surface of the opening 290a of the insulating layer 280. In Fig. 13A , the insulating layer 278 has a first portion that is located inside the side surface of the conductive layer 240a on the opening 290b1 side, and a second portion that is located inside the side surface of the insulating layer 280 on the opening 290a side, and the first and second portions are connected to each other.

[0218] The width Da is smaller than the width D by, for example, the thickness of the insulating layer 278 (here, for example, the thickness of the portion covering the side surface of the insulating layer 280).

[0219] 13C and 13D each show a modification of FIG. 13B. Fig. 13C shows an example in which the height of the top surface of a region of the insulating layer 278 extending from the end of the conductive layer 240b toward the inside of the opening (also referred to as a protruding region) is lower than the height of the top surface of a region located under the conductive layer 240b. Fig. 13D shows an example in which the height of the top surface of a region of the insulating layer 278 extending from the end of the conductive layer 240b toward the inside of the opening (also referred to as a protruding region) is higher than the height of the top surface of a region located under the conductive layer 240b.

[0220] The configurations of FIGS. 13C and 13D can be fabricated, for example, by forming the configurations of FIGS. 26A to 26C described below and then changing the amount of etching of the insulating film that will become the insulating layer 278.

[0221] <Sixth Modification of Semiconductor Device> As shown in FIGS. 14A and 14B, an oxide semiconductor layer 230 or the like may be provided so as to cover the side surface of a recessed portion of a conductive layer 220.

[0222] 14A and 14B, for example, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220b, and the sidewall of the opening 290 includes the side surface of the recess of the conductive layer 220b.

[0223] 14A shows an example of a configuration in which the conductive layer 220 in FIG. 9B has a recess, and FIG. 14B shows an example of a configuration in which the conductive layer 220 in FIG. 13A has a recess.

[0224] The conductive layer 220 having the recessed portion can increase the area where the oxide semiconductor layer 230 and the conductive layer 220 are in contact with each other. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced. In addition, in Figures 14A and 14B, the conductive layer 260 and the conductive layer 220 have portions that face each other with the oxide semiconductor layer 230 sandwiched therebetween, which may increase the on-state current of the transistor.

[0225] 14B , the insulating layer 278 is disposed so as to be embedded in the recessed portion of the conductive layer 220. Note that in the example shown in Fig. 14B , the height of the lower end of the insulating layer 278 and the lower end of the oxide semiconductor layer 230 are the same, but as shown in Fig. 14C , the insulating layer 278 may be embedded in the recessed portion of the conductive layer 220, and the height of the lower end of the insulating layer 278 may be higher than the height of the lower end of the oxide semiconductor layer 230. Alternatively, as shown in Fig. 14D , the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 may be embedded in the recessed portion of the conductive layer 220, and the insulating layer 278 may be in contact with the upper surface outside the recessed portion of the conductive layer 220 without being embedded in the recessed portion of the conductive layer 220.

[0226] <Configuration example 3-1 of semiconductor device> The semiconductor device shown in Figures 15A to 15D has a conductive layer 220, an insulating layer 250, and a conductive layer 260 in addition to the semiconductor device shown in Figures 5A to 5C. Figure 15A is a plan view showing an example of the semiconductor device. Figure 15B is a cross-sectional view of the semiconductor device shown in Figure 15A taken along dash-dotted line B1-B2. Figure 15C is a plan view including dash-two-dotted line B5-B6 shown in Figure 15B. Figure 15D is a cross-sectional view corresponding to dash-dotted line B7-B8 shown in Figure 15A.

[0227] The insulating layer 250 has a portion located inside the opening 290 and a portion on the insulating layer 280 that covers the upper surface of the oxide semiconductor layer 230 .

[0228] The conductive layer 260 is located within the opening 290. Preferably, the conductive layer 260 extends in a direction parallel to the direction in which the opening 290 extends within the opening 290. By providing the conductive layer 260 so as to fill the opening 290, the conductive layer 260 can be provided so as to extend in a direction parallel to the direction in which the opening 290 extends.

[0229] The top surface of the conductive layer 260 can be lower than the top surface of a region of the insulating layer 250 which is provided in the insulating layer 280. Alternatively, the top surface of the oxide semiconductor layer 230 which is provided in the insulating layer 280. The top surface of the conductive layer 260 may be lower than the top surface of the conductive layer 240b. The top surface of the conductive layer 260 may be lower than the top surface of the conductive layer 240a and is preferably higher than the bottom surface of the conductive layer 240a. The top surface of the conductive layer 260 is preferably higher than the height of the periphery of the opening 290a in the insulating layer 280.

[0230] The conductive layer 260 may have a portion located outside the opening 290 a in a plan view and located on the insulating layer 280 .

[0231] 15A to 15D , the conductive layer 260 extends in the X direction. The conductive layer 240 extends in the Y direction and is divided in the region overlapping with the opening 290.

[0232] Note that FIG. 15D shows an example in which the end of the insulating layer 278 is aligned with the end of the conductive layer 240 b. However, as shown in FIG. 15E , the insulating layer 278 may be left extending in the X direction without being processed so as to be aligned with the end of the conductive layer 240 b, the oxide semiconductor layer 230, etc.

[0233] 15C , in the opening 290, an insulating layer 250 is provided to cover the oxide semiconductor layer 230, and a conductive layer 260 is provided to cover the insulating layer 250. The conductive layer 260 and the oxide semiconductor layer 230 are provided to face each other with the insulating layer 250 interposed therebetween in the opening 290. In the example shown in FIG. 15C , the channel width of the transistor 200 is determined by the width Wa of the oxide semiconductor layer 230 in the X direction. The channel width of the transistor 200 can be expressed as "2×Wa."

[0234] Increasing the width Wa can increase the channel width per unit area of ​​the transistor 200 and increase the on-state current. On the other hand, decreasing the width Wa can reduce the area occupied by the transistor 200 and increase the integration density of the semiconductor device.

[0235] When the opening 290a is slit-shaped, the width of the opening 290a in the Y direction can be, for example, 5 nm to 300 nm, 5 nm to 200 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, or 5 nm to 30 nm. Alternatively, it can be, for example, 10 nm to 300 nm, 10 nm to 200 nm, 10 nm to 100 nm, 10 nm to 60 nm, 10 nm to 50 nm, 10 nm to 40 nm, or 10 nm to 30 nm. Alternatively, it can be, for example, 20 nm to 300 nm, 20 nm to 200 nm, 20 nm to 100 nm, 20 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm.

[0236] <Configuration example 4-1 of semiconductor device> The semiconductor device shown in Figures 16A to 16D is different from the semiconductor device shown in Figures 7A to 7D mainly in that it has an insulating layer 281 on an insulating layer 280 and the oxide semiconductor layer 230 has a portion along the side surface of the opening of the insulating layer 281.

[0237] Fig. 16A is a plan view showing an example of a semiconductor device. Fig. 16B is a perspective view of the semiconductor device shown in Fig. 16A. Fig. 16C is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in Fig. 16A, and Fig. 16D is a cross-sectional view corresponding to the dashed dotted line C3-C4 shown in Fig. 16A.

[0238] 16B and 16C , the insulating layer 281 is located over the insulating layer 280, the conductive layer 240, and the oxide semiconductor layer 230. An opening 289 is provided in the insulating layer 281.

[0239] The insulating layer 250 and the conductive layer 260 each have a region located within the opening 290 and a region located within the opening 289 .

[0240] In the semiconductor device of one embodiment of the present invention, the insulating layer 280, the conductive layer 240, and the insulating layer 281 can be opened simultaneously using the same mask. Alternatively, after an opening is formed in the insulating layer 281, the conductive layer 240 and the insulating layer 280 can be opened using the insulating layer 281 as a mask. Alternatively, after the insulating layer 281 and the conductive layer 240 are opened simultaneously using the same mask, the insulating layer 280 can be opened using the conductive layer 240 or the insulating layer 281 as a mask. By making the openings, an opening 290a can be formed in the insulating layer 280, an opening 290b2 can be formed in the conductive layer 240b, and an opening 289 can be formed in the insulating layer 281. After making the openings, the side surfaces of the conductive layer 240a can be recessed to form an opening 290b1 in the conductive layer 240a.

[0241] By providing the insulating layer 281 on the conductive layer 240, the conductive layer 240 and a conductive layer provided above the conductive layer 240 can be separated by a distance at least equal to the thickness of the insulating layer 281 on the conductive layer 240. An example of a conductive layer provided above the conductive layer 240 is a wiring connected to the conductive layer 260. The distance can reduce parasitic capacitance between the conductive layer 240 and the conductive layer above it. Furthermore, leakage current between the conductive layer 240 and the conductive layer above it can be reduced. The insulating layer 281 preferably has a thickness sufficient to sufficiently reduce parasitic capacitance between the conductive layer 240 and other conductive layers, and the equivalent oxide thickness (EOT) of the insulating layer 281 is preferably at least greater than the equivalent oxide thickness of the insulating layer 250. In this specification, the equivalent oxide thickness refers to a value obtained by converting a physical film thickness into an electrical film thickness equivalent to silicon oxide or silicon oxynitride. The thickness of the insulating layer 281 can be determined by referring to the thickness of the insulating layer 280, for example.

[0242] 16A to 16D, a conductive layer 265 is provided on an insulating layer 281 above the conductive layer 240. The conductive layer 265 is connected to the conductive layer 260 and extends in the Y direction.

[0243] 17A and 17B show enlarged views of Fig. 16C and 16D, respectively. Also, Fig. 17A and 17B show an example in which the conductive layer 220 has a stacked structure of a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, the insulating layer 280 has a stacked structure of an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b, and the conductive layer 260 has a stacked structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a.

[0244] The oxide semiconductor layer 230 has a portion 279 as a portion in contact with the top surface of the conductive layer 240. The portion 279 is located between the conductive layer 240 and the insulating layer 281. The insulating layer 281 is located over the portion 279.

[0245] 16C and 16D , the conductive layer 260 has a columnar shape. The oxide semiconductor layer 230 has a portion facing the side surface of the conductive layer 260 with the insulating layer 250 sandwiched therebetween, and a portion (portion 279) located on the conductive layer 240 and surrounding the conductive layer 260 with the insulating layer 250 sandwiched therebetween. The portion 279 can be formed by forming a void sandwiched between the insulating layers 280 and 281 and then filling the void with a semiconductor layer. The oxide semiconductor layer 230 having the portion 279 can be configured to be in contact with the top surface of the conductive layer 240b in addition to the side surface of the conductive layer 240b. This increases the contact area between the oxide semiconductor layer 230 and the conductive layer 240. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0246] A region of the oxide semiconductor layer 230 located within the opening 289 does not contribute to a channel formation region and overlaps with the conductive layer 260 with the insulating layer 250, which is thinner than the insulating layer 281, sandwiched therebetween, and thus significant parasitic capacitance might be generated between the oxide semiconductor layer 230 and the conductive layer 260. Therefore, in the semiconductor device of one embodiment of the present invention, it is preferable to reduce the area where the oxide semiconductor layer 230 and the conductive layer 260 overlap within the opening 289.

[0247] In the opening 289, the upper end of the oxide semiconductor layer 230 is preferably lower than the upper end of the conductive layer 260. This can reduce the area where the oxide semiconductor layer 230 overlaps with the conductive layer 260 with the insulating layer 250 sandwiched therebetween, thereby reducing parasitic capacitance that causes a delay in the operating speed of the semiconductor device.

[0248] On the other hand, if the height of the upper end of the oxide semiconductor layer 230 within the opening 289 is lower than the height of the upper surface of the oxide semiconductor layer 230 located on the conductive layer 240b, the oxide semiconductor layer 230 will be discontinuous between within the opening 289 and above the conductive layer 240b, which may hinder conduction between the oxide semiconductor layer 230 and the conductive layer 240 or may reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Therefore, it is preferable that the height of the upper end of the oxide semiconductor layer 230 within the opening 289 is higher than the upper surface of the portion of the oxide semiconductor layer 230 located on the conductive layer 240b and lower than the height of the upper surface of the outer periphery of the opening 289 in the insulating layer 281. This can improve the reliability and operating speed of the semiconductor device.

[0249] If the difference in height between the upper surface of the oxide semiconductor layer 230 covering the upper surface of the conductive layer 240 and the upper surface of the conductive layer 260 within the opening 289 is H1, and the difference in height between the upper surface of the oxide semiconductor layer 230 covering the upper surface of the conductive layer 240 and the upper end of the oxide semiconductor layer 230 within the opening 289 is H2, then H2 is preferably, for example, ½ or less of H1, and more preferably ⅓ or less of H1.

[0250] <Angle of Side Surface of Opening> FIG. 18A shows an example in which the angle formed by the side surface of opening 290 in insulating layer 280 and conductive layer 240 and the reference plane is different in the configuration shown in FIG. 9B.

[0251] It is preferable that the side surface of the opening 290b2 in the conductive layer 240b and the side surface of the opening 290a in the insulating layer 280 be perpendicular to the reference plane, which can increase the integration degree of the transistor 200. Alternatively, tapering the side surface improves coverage with the oxide semiconductor layer 230, the insulating layer 250, the conductive layer 260, and the like.

[0252] The inclinations of the side surface of the insulating layer 280a on the opening 290a side, the side surface of the insulating layer 280b on the opening 290a side, the side surface of the insulating layer 280c on the opening 290a side, and the side surface of the conductive layer 240b on the opening 290b2 side are defined as angles d_1, d_2, d_3, and d_4, respectively. Each angle is an angle with respect to a plane that serves as a reference plane in a cross-sectional view, for example. The reference plane can be, for example, the top surface of the conductive layer 220. Alternatively, the top surface of the insulating layer 210 can be used as the reference plane. Alternatively, the substrate surface can be used as the reference plane.

[0253] Preferably, angles d_1, d_2, d_3, and d_4 are each 45 degrees or greater and less than 90 degrees. Specifically, angles d_1, d_2, d_3, and d_4 are 80 degrees or greater and less than 90 degrees, which allows for miniaturization or high integration of the semiconductor device, as described above, and are therefore preferred. Furthermore, angles d_1, d_2, d_3, and d_4 are 45 degrees or greater or 50 degrees or greater and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, which improves the coverage of the film formed in opening 290 and are therefore preferred.

[0254] 18A , angle d_4 may be smaller than angle d_2. In such a configuration, coverage of the side surface of conductive layer 240 may be improved. Furthermore, for example, angle d_3 may be smaller than angle d_2. In such a configuration, the upper end of opening 290a may be widened, thereby improving coverage of the side surface of insulating layer 280.

[0255] FIG. 18B shows an example in which the angle formed by the side surface of the opening 289 of the insulating layer 281 and the reference plane is different from that in the configuration shown in FIG. 17B.

[0256] Making the side surface of the opening 289 of the insulating layer 281 perpendicular to the reference plane is preferable because it can increase the integration density of the transistor 200. Alternatively, making the side surface tapered improves coverage with the insulating layer 250, the conductive layer 260, and the like.

[0257] The angle of the side surface of the opening 289 of the insulating layer 281 is preferably, for example, 45 degrees or more and less than 90 degrees. Specifically, if the angle is 80 degrees or more and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, which is preferable. Furthermore, if the angle is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, which is preferable.

[0258] The angle of the side surface of the opening 289 is, for example, the angle formed with a plane serving as a reference plane in a cross-sectional view. For example, the upper surface of the conductive layer 220 can be used as the reference plane. Alternatively, the upper surface of the insulating layer 210 can be used as the reference plane. Alternatively, the substrate surface can be used as the reference plane.

[0259] 18B shows an example in which angle d_6 of the side surface of insulating layer 281 at and near the upper end of opening 289 is smaller than angle d_5 below that. Fig. 18C shows an enlarged view of the area surrounded by the two-dot chain line in Fig. 18B. In Fig. 18B, the side surface of opening 289 in insulating layer 281 tapers toward the upper end.

[0260] By making the angle d_6 smaller than the angle d_5, the coverage of the side surface of the opening 289 with the insulating layer 250, the conductive layer 260, etc. can be improved.

[0261] <Semiconductor Device Variation 7> The oxide semiconductor layer 230 can have a stacked structure of multiple layers. Fig. 19A shows an example in which the oxide semiconductor layer 230 in Fig. 17A has three layers: an oxide layer 230a, an oxide layer 230b, and an oxide layer 230c. Fig. 19B is an enlarged view of the region surrounded by a two-dot chain line in Fig. 19A.

[0262] 19A and 19B , the portion of the oxide semiconductor layer 230 that is located on the conductive layer 240b and that is sandwiched between the upper surface of the conductive layer 240b and the insulating layer 281 is formed so as to fill a region 288 that is a space formed by removing a sacrificial layer, as shown in, for example, Figures 33A to 34C described later. Thus, the oxide layers 230b are provided so as to sandwich the oxide layer 230c from above and below, and the oxide layers 230a are provided so as to sandwich the oxide layer 230c from above and below with the oxide layer 230b sandwiched therebetween.

[0263] 19C shows a modification of Fig. 19B. Fig. 19C shows an example in which an oxide layer 230c is not provided in a portion of the oxide semiconductor layer 230 that is located over the conductive layer 240b and sandwiched between the top surface of the conductive layer 240b and the insulating layer 281, and oxide layers 230a are provided to sandwich the oxide layer 230b from above and below. When the thickness of the sacrificial layer for forming the region 288 is thin, for example, the configuration shown in Fig. 19C is formed.

[0264] <Configuration Example 4-2 of Semiconductor Device> The semiconductor device illustrated in FIGS. 20A to 20D is different from that illustrated in FIGS. 16A to 16D mainly in that the oxide semiconductor layer 230 does not have the portion 279 .

[0265] Fig. 20A is a plan view showing an example of a semiconductor device, Fig. 20B is a perspective view of the semiconductor device shown in Fig. 20A, Fig. 20C is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in Fig. 20A, and Fig. 20D is a cross-sectional view corresponding to the dashed dotted line C3-C4 shown in Fig. 20A.

[0266] In the structures shown in FIGS. 20A to 20D, the step of forming the portion 279 of the oxide semiconductor layer 230 can be omitted, and therefore the process can be simplified.

[0267] 21A to 21D differ from those of Figures 16A to 16D mainly in that an insulating layer 250 and a conductive layer 260 are also provided on an insulating layer 281. The conductive layer 260 extends in the Y direction on the insulating layer 281 and can be used as wiring for the semiconductor device.

[0268] Fig. 21A is a plan view showing an example of a semiconductor device. Fig. 21B is a perspective view of the semiconductor device shown in Fig. 21A. Fig. 21C is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in Fig. 21A, and Fig. 21D is a cross-sectional view corresponding to the dashed dotted line C3-C4 shown in Fig. 21A.

[0269] 21A to 21D, the process of removing the conductive layer 260 and the insulating layer 250 on the insulating layer 281 is not necessary, which may allow for simplification of the process.

[0270] 22A to 22C are different from those of FIGS. 16A to 16D mainly in that an insulating layer 250 and an insulating layer 282 are provided in this order outside the columnar conductive layer 260 in an opening 289 of the insulating layer 281, and that the insulating layer 282 is provided between the top surface of the insulating layer 281 and the conductive layer 265. In addition, in FIGS. 16A to 16D , the diameter of the conductive layer 260 increases above the upper end of the oxide semiconductor layer 230 in the opening 289, whereas in FIGS. 22A to 22C , the diameter of the conductive layer 260 is constant in the opening 289.

[0271] The insulating layer 282 is located on the oxide semiconductor layer 230 in the opening 289 and has a portion corresponding to the side surface of the conductive layer 260 with the insulating layer 250 sandwiched therebetween.

[0272] <Example 1 of Manufacturing Method of Semiconductor Device> Thin films (insulating films, semiconductor films, conductive films, and the like) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0273] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF-superimposed DC sputtering, which superimposes RF and DC, is also available. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used when forming films using conductive targets. DC sputtering can also form insulating films by reactive sputtering, in addition to forming conductive films. Pulsed DC sputtering is primarily used when depositing films of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows for control of ion energy and target potential during film formation. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Furthermore, high-quality films can be obtained.

[0274] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is achieved by self-bias or the like. In addition, long-throw sputtering can form anisotropic films by increasing the distance between the sputtering target and the substrate.

[0275] CVD methods can be classified into PECVD, thermal CVD (TCVD) using heat, photo CVD (Photo CVD) using light, etc. They can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0276] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0277] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0278] Furthermore, the ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The PEALD (Plasma Enhanced ALD) method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using XPS.

[0279] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0280] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0281] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0282] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0283] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0284] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0285] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0286] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0287] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0288] As an etching gas for the dry etching process, for example, a gas containing halogen can be used.

[0289] The halogen-containing gas may be, for example, an etching gas containing one or more of fluorine, chlorine, and bromine, such as a fluorocarbon gas, a hydrofluorocarbon gas, or SF ６ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３ The fluorocarbon gas may be a single gas or a mixture of two or more gases. ｘ F ｙ A gas represented by (y≦2x+2) can be used. An example of a fluorocarbon gas that satisfies y=2x+2 is CF. ４ , C ２ F ６ , C ３ F ８ , C ４ F １０ , C ５ F １２ Examples of fluorocarbon gases that satisfy the condition y<2x+2 include saturated fluorocarbon compounds such as C ２ F ４ , C ２ F ２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ Examples of hydrofluorocarbon gases include unsaturated fluorocarbon compounds such as CHF ３ Gas, CH ２ F ２Gas, etc.

[0290] When a gas containing halogen is used as an etching gas, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ ) gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate.

[0291] Alternatively, a gas containing no halogen gas but containing hydrocarbon gas or hydrogen gas can be used as the etching gas.

[0292] Examples of hydrocarbon gases include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ ) can be used.

[0293] When a hydrocarbon gas is used as the etching gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like may be added as appropriate.

[0294] Furthermore, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0295] 23A to 27C , an example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. In each figure, A is a plan view of the semiconductor device, a figure marked with B corresponds to the dashed dotted line A1-A2 in A, and a figure marked with C corresponds to the dashed dotted line A3-A4 in A.

[0296] First, an insulating layer 210 is formed on a substrate.

[0297] Next, a conductive layer 220 is formed on the insulating layer 210 .

[0298] Next, the insulating layer 280 is formed over the insulating layer 210 and the conductive layer 220. After the insulating layer 280 is formed, a top surface thereof may be planarized by planarization treatment.

[0299] Next, a stacked structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a is formed over the insulating layer 280. After that, a mask 274 is formed over the conductive layer 240b and the insulating layer 280, and an opening 290b2 is formed in the conductive layer 240b by removing a portion of the conductive layer 240b that is not covered with the mask 274 (FIGS. 23A to 23C).

[0300] The mask may be a laminated structure of, for example, SOC (Spin On Carbon), SOG (Spin On Glass) on the SOC, and resist on the SOG. The SOG may be, for example, a layer containing polysiloxane.

[0301] First, a resist is processed into a desired shape using lithography, and then the SOG is processed using the resist as a mask. Next, the SOC is processed using the SOG as a mask. It is preferable that the resist is removed during the SOC processing.

[0302] 23B and 23C has a laminated structure of an SOC layer and an SOG layer of the SOC layer, and the thickness of the SOG layer is thinner than before the opening 290b2 is formed.

[0303] Next, an opening 290b1 is formed in the conductive layer 240a using the mask 274 and the conductive layer 240b as a mask (FIGS. 24A to 24C).

[0304] The opening 290b1 is preferably formed in the conductive layer 240a by isotropic etching, which allows the side surface of the opening 290b1 to be recessed further than the side surface of the opening 290b2.

[0305] Dry etching or wet etching can be used as an isotropic etching condition. Alternatively, a combination of dry etching and wet etching can be used. Here, an example is shown in which tungsten is used as the conductive layer 240a and dry etching is performed to form the opening 290b1. In addition, SF is used as the gas for dry etching. ６ A gas containing the following can be used.

[0306] Next, using the mask 274 and the conductive layer 240b as a mask, an opening 290a is formed in the insulating layer 280 (FIGS. 25A to 25C). Subsequently, the mask 274 is removed.

[0307] Anisotropic etching conditions are preferably used to form the opening 290a in the insulating layer 280. Because dry etching allows for anisotropic etching, it is suitable for forming a finely structured laminate including an opening with a high aspect ratio and side surfaces perpendicular to the surface of the insulating layer 280 where the opening is to be formed.

[0308] Note that when forming the opening 290a in the insulating layer 280 using the mask 274, removing the SOG at the same time simplifies the step of removing the mask 274 after forming the opening 290a, which is preferable. In such a case, since only the SOC needs to be removed in the step of removing the mask 274, damage to the conductive layer 240, the insulating layer 280, and the exposed upper surface of the conductive layer 220 in the step of removing the mask 274 is likely to be reduced, for example.

[0309] For example, the insulating layer 280 may be made of silicon oxide, silicon oxynitride, or the like, and a polymer containing silicon and oxygen may be used as the SOG, so that the layers can be removed simultaneously.

[0310] Next, an insulating film 278f is formed so as to cover the upper surface of the conductive layer 220, the side surface of the opening 290a of the insulating layer 280, the side surface of the opening 290b1 of the conductive layer 240a, the lower surface of the conductive layer 240b, the side surface of the opening 290b2 of the conductive layer 240b, the upper surface of the conductive layer 240b, and the upper surface of the insulating layer 280 (FIGS. 26A to 26C). The insulating film 278f is preferably provided in contact with each of the side surface of the insulating layer 280 on the opening 290a side, the side surface of the conductive layer 240a on the opening 290b1 side, and the side surface of the conductive layer 240b on the opening 290b2 side, and preferably in contact with at least the side surface of the opening 290b1. The insulating film 278f has, for example, a portion covering the top surface of the conductive layer 220, a portion covering the side surface of the opening 290a of the insulating layer 280, a portion covering the side surface of the opening 290b1 of the conductive layer 240a and located below the conductive layer 240b, a portion covering the side surface of the opening 290b2 of the conductive layer 240b, and a portion covering the top surface of the conductive layer 240b.

[0311] The insulating film 278f is an insulating film that becomes the insulating layer 278, and can be made of a material that can be used for the insulating layer 278. Here, as an example, a silicon nitride film is formed by a PEALD method.

[0312] The thickness of the insulating film 278f may be, for example, greater than or equal to 0.5 nm and less than or equal to 50 nm, and may be, for example, less than or equal to twice the thickness of the conductive layer 240a, less than 1 time, or less than 0.7 times the thickness of the conductive layer 240a.

[0313] Next, a part of the insulating film 278f is removed to form the insulating layer 278 (FIGS. 27A to 27C).

[0314] Anisotropic etching can be used to form the insulating layer 278. As an example, the insulating layer 278 can be formed by anisotropic dry etching using the conductive layer 240b as a mask, leaving a portion of the insulating film 278f that covers the side surface of the opening 290b1 of the conductive layer 240a and is located under the conductive layer 240b, and removing the other portions. Note that an example is shown here in which the portion of the insulating film 278f that covers the top surface of the conductive layer 220, the portion that covers the side surface of the opening 290a of the insulating layer 280, the portion that covers the side surface of the opening 290b2 of the conductive layer 240b, and the portion that covers the top surface of the conductive layer 240b are removed. As will be described later, the portion that covers the side surface of the opening 290a of the insulating layer 280, the portion that covers the side surface of the opening 290b2 of the conductive layer 240b, and the like can also be left.

[0315] Alternatively, the insulating layer 278 can be formed using isotropic etching conditions.

[0316] In addition, when forming the insulating layer 278, depending on the etching conditions, the side surface of the insulating layer 278 may be located outside the side surface of the conductive layer 240b or the side surface of the insulating layer 280, as shown in Figures 11A and 11B, etc.

[0317] Next, an oxide semiconductor layer 230 is formed so as to cover the top surface of the conductive layer 220, the side surfaces of the opening 290 a of the insulating layer 280, the side surfaces of the insulating layer 278, the side surfaces of the conductive layer 240 b, and the top surface of the conductive layer 240 b. Subsequently, an insulating layer 250 and a conductive layer 260 are formed in this order over the oxide semiconductor layer 230, whereby the semiconductor device illustrated in FIGS. 9A to 9C , etc. can be manufactured.

[0318] 11C, 13A, etc. can be fabricated by processing the insulating film 278f so as to leave the portion covering the side surface of the opening 290a of the insulating layer 280, and the configuration shown in Fig. 13D can be fabricated by leaving a portion of the portion covering the side surface of the opening 290b2 of the conductive layer 240b. Also, the configuration shown in Fig. 11A, etc. can be fabricated by recessing the sidewall in processing the insulating film 278f.

[0319] 28A to 36C , an example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. In each figure, A is a plan view of the semiconductor device, a drawing marked with B corresponds to the dashed dotted line C1-C2 in A, and a drawing marked with C corresponds to the dashed dotted line C3-C4 in A.

[0320] Note that detailed explanation of the content common to the manufacturing method described above may be omitted.

[0321] First, an insulating layer 210 is formed on a substrate. Next, a conductive layer 220 is formed on the insulating layer 210. Next, an insulating layer 280 is formed on the insulating layer 210 and the conductive layer 220.

[0322] Next, a stacked structure of a conductive layer 240a, a conductive layer 240b on the conductive layer 240a, and a sacrificial layer 276 on the conductive layer 240b is formed on the insulating layer 280. Subsequently, an insulating layer 281 is formed on the insulating layer 280 and the sacrificial layer 276 (FIGS. 28A to 28C).

[0323] The sacrificial layer 276 is provided in a region where the oxide semiconductor layer 230 will be formed later. Therefore, the thickness of the sacrificial layer 276 determines the thickness of the oxide semiconductor layer 230 that will be formed later.

[0324] The sacrificial layer 276 is preferably made of a material that can be etched with a wet etching solution. Wet etching allows etching with a high selectivity, and when etching the sacrificial layer 276, the etching selectivity with respect to the conductive layer 220, the conductive layer 240, etc. is high. Here, a high etching selectivity means that the etching rate of the conductive layer 220, the conductive layer 240, etc. is lower than the etching rate of the sacrificial layer 276, and etching of the conductive layer 220, the conductive layer 240 can be suitably suppressed.

[0325] The sacrificial layer 276 may be any of the insulating layers listed above. The sacrificial layer 276 may also be any of the metal oxides listed above. The sacrificial layer 276 may also be a metal film or an alloy film. The sacrificial layer 276 may also be made of a combination of two or more materials selected from these materials.

[0326] For example, aluminum oxide can be used as the sacrificial layer 276. Alternatively, In—Ga—Zn oxide can be used as the sacrificial layer 276.

[0327] Next, a mask 275 is formed on the insulating layer 281, and openings are formed in the insulating layer 281, the sacrificial layer 276, and the conductive layer 240b in this order (FIGS. 29A to 29C). An opening 289 is formed in the insulating layer 281, and an opening 290b2 is formed in the conductive layer 240b.

[0328] Next, an opening 290b1 is formed in the conductive layer 240a using the mask 275, the conductive layer 240b, etc. (FIGS. 30A to 30C). For the formation of the opening 290b1, the description of FIGS. 24A to 24C can be referred to.

[0329] Next, using the mask 275, the conductive layer 240b, etc. as a mask, an opening 290a is formed in the insulating layer 280. Subsequently, an insulating film 278f is formed so as to cover the upper surface of the conductive layer 220, the side surface of the opening 290a in the insulating layer 280, the side surface of the opening 290b1 in the conductive layer 240a, the side surface of the opening 290b2 in the conductive layer 240b, the lower surface of the conductive layer 240b, the side surface of the opening in the sacrificial layer 276, the side surface of the opening 289 in the insulating layer 281, and the upper surface of the insulating layer 281 ( FIGS. 31A to 31C ). The insulating film 278f is preferably provided in contact with each of the side surface of the insulating layer 280 on the opening 290a side, the side surface of the conductive layer 240a on the opening 290b1 side, the side surface of the conductive layer 240b on the opening 290b2 side, the side surface of the sacrificial layer 276 on the opening side, and the side surface of the insulating layer 281 on the opening 289 side, and preferably in contact with at least the side surface of the opening 290b1. The insulating film 278f has, for example, a portion covering the top surface of the conductive layer 220, a portion covering the side surface of the opening 290a of the insulating layer 280, a portion covering the side surface of the opening 290b1 of the conductive layer 240a and located below the conductive layer 240b, a portion covering the side surface of the opening 290b2 of the conductive layer 240b, a portion covering the side surface of the opening of the sacrificial layer 276, a portion covering the side surface of the opening 289 of the insulating layer 281, and a portion covering the top surface of the insulating layer 281.

[0330] Next, the insulating layer 278 is formed by removing a portion of the insulating film 278f (FIGS. 32A to 32C). Note that FIGS. 32A to 32C show an example in which the portion of the insulating film 278f that covers the side surface of the opening 290b1 of the conductive layer 240a and that is located under the conductive layer 240b is left, and the portion that covers the top surface of the conductive layer 220, the portion that covers the side surface of the opening 290a of the insulating layer 280, and the portion that covers the side surface of the opening 290b2 of the conductive layer 240b are removed. Alternatively, the portion of the insulating film 278f that covers the side surface of the opening 290b2 of the conductive layer 240b may remain.

[0331] Next, the sacrificial layer 276 is etched away to form regions 288, which may be voids, for example (FIGS. 33A-33C).

[0332] The sacrificial layer 276 can be etched by, for example, wet etching. In addition, as a chemical solution for wet etching the sacrificial layer 276, a developing solution, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a chemical solution using a mixture of these liquids can be used.

[0333] Next, the oxide semiconductor layer 230 is formed to fill the region 288. The oxide semiconductor layer 230 is formed to cover the top surface of the conductive layer 220, the side surface of the insulating layer 280 on the opening 290a side, the side surface of the insulating layer 278 side, the side surface of the conductive layer 240b on the opening 290b2 side, the side surface of the insulating layer 282 on the opening 289, and the top surface of the insulating layer 281 ( FIGS. 34A to 34C ).

[0334] Here, compared with the depth of the opening in the Y direction of the region 288, the height of the opening (height in the Z direction) is extremely thin, being approximately the thickness of the sacrificial layer 276. Therefore, the region 288 where the oxide semiconductor layer 230 is to be formed can be said to be a region with a high aspect ratio. When the oxide semiconductor layer 230 is formed so as to fill such a region with a high aspect ratio, it is preferable to use the ALD method as a method for forming the oxide semiconductor layer 230.

[0335] Next, a sacrificial layer 277 is formed on the oxide semiconductor layer 230 (FIGS. 34A to 34C). The sacrificial layer 277 is formed so as to fill the openings 290 and 289. In addition, in FIG. 34A to 34C, the sacrificial layer 277 has a portion that overlaps with the top surface of the insulating layer 281, with the oxide semiconductor layer 230 sandwiched therebetween.

[0336] The sacrificial layer 277 may be, for example, SOC.

[0337] It can be expressed that the sacrificial layer 277 functions as a protective film or a mask when the oxide semiconductor layer 230 is processed. By providing the sacrificial layer 277, for example, a region of the oxide semiconductor layer 230 that is not covered with the sacrificial layer 277 can be selectively removed.

[0338] Next, etching is used to remove the portion of the sacrificial layer 277 that overlaps the upper surface of the insulating layer 281. Also, part of the sacrificial layer 277 is removed so that the height of the upper surface of the sacrificial layer 277 in the opening 289 is lower than the height of the upper surface of the insulating layer 281 on the periphery of the opening 289 (FIGS. 35A to 35C).

[0339] Next, a portion of the oxide semiconductor layer 230 that overlaps with the top surface of the insulating layer 281 is removed by etching. In addition, part of the oxide semiconductor layer 230 is removed so that the height of the oxide semiconductor layer 230 in the opening 289 is lower than the height of the top surface of the insulating layer 281 on the periphery of the opening 289 ( FIGS. 36A to 36C ).

[0340] For example, isotropic etching conditions can be used for the etching of the oxide semiconductor layer 230. By using isotropic etching conditions, the portion of the oxide semiconductor layer 230 that covers the top surface and the portion that covers the side surface of the insulating layer 281 can be removed at approximately the same etching rate, and film residue in the region that covers the side surface of the insulating layer 281 can be suppressed.

[0341] The oxide semiconductor layer may be etched under anisotropic etching conditions, or a combination of isotropic etching conditions and anisotropic etching conditions may be used.

[0342] The etching conditions for the oxide semiconductor layer 230 can be appropriately selected from dry etching and wet etching.

[0343] When wet etching is used, for example, diluted hydrofluoric acid or the like can be used as the wet etching chemical.

[0344] Alternatively, dry etching and wet etching may be combined. For example, after a portion of the oxide semiconductor layer 230 over the insulating layer 281 is removed by dry etching, a portion of the insulating layer 281 along a side surface of the opening 289 can be removed by wet etching.

[0345] The oxide semiconductor layer 230 has a recess, and is provided along the sidewalls of the opening 290 and the opening 289 and the top surface of the conductive layer 220, which is the bottom of the opening 290. The sacrificial layer 277 is provided to fill the recess in the oxide semiconductor layer 230, and a portion of the oxide semiconductor layer 230 that is covered with the sacrificial layer 277 is protected by etching and is not removed. Therefore, as shown in FIGS. 36A to 36C , a portion of the oxide semiconductor layer 230 above the portion where the sacrificial layer 277 is buried is removed.

[0346] However, as shown in Figures 36A to 36C, the upper surface of the portion of the oxide semiconductor layer 230 that is provided along the opening 289 is not covered with the sacrificial layer 277, and therefore, the height may be slightly lower than the height of the upper end of the sacrificial layer 277, especially when isotropic etching is used.

[0347] In this manner, the sacrificial layer 277 can function as a protective film or a mask in processing the oxide semiconductor layer 230. The height of the upper end of the oxide semiconductor layer 230 in the opening 289 depends on the height of the upper surface of the sacrificial layer 277.

[0348] As the height of the upper end of the oxide semiconductor layer 230 in the opening 289 increases, the area overlapping with the conductive layer 260 with the insulating layer 250 sandwiched therebetween increases. A larger overlapping area increases parasitic capacitance, which may result in a decrease in the operating speed of the semiconductor device. On the other hand, if the height of the upper end of the oxide semiconductor layer 230 in the opening 289 is lower than the height of the upper surface of the oxide semiconductor layer 230 located on the conductive layer 240b, the oxide semiconductor layer 230 may be discontinuous between the opening 289 and the conductive layer 240b, which may impair electrical continuity between the oxide semiconductor layer 230 and the conductive layer 240 or reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Therefore, it is preferable that the height of the upper end of the oxide semiconductor layer 230 in the opening 289 be higher than the upper surface of the portion of the oxide semiconductor layer 230 located on the conductive layer 240b and lower than the height of the upper surface of the outer periphery of the opening 289 in the insulating layer 281. This improves the reliability and operating speed of the semiconductor device.

[0349] Next, the sacrificial layer 277 is removed. When SOC is used as the sacrificial layer 277, the sacrificial layer 277 can be removed by, for example, an ashing process using oxygen.

[0350] Next, an insulating layer 250 and a conductive layer 260 are formed in this order over the oxide semiconductor layer 230. The insulating layer 250 and the conductive layer 260 are provided to cover the top surface of the conductive layer 220, the side surface on the opening 290 side, and the side surface on the opening 289 side, with the oxide semiconductor layer 230 sandwiched therebetween. The conductive layer 260 is provided over the insulating layer 250 so as to fill the openings 290 and 289, for example.

[0351] The openings 290 and 289 do not have to be embedded in the conductive layer 260. When the film thickness of the conductive layer 260 is thin, the conductive layer 260 is provided so as to cover the side walls of the openings 290 and 289 and the upper surface of the conductive layer 220, which is the bottom of the opening 290, and may have a recess.

[0352] Planarization treatment can be used to form the insulating layer 250 and the conductive layer 260. When the insulating layer 250 and the conductive layer 260 are formed over the insulating layer 281, the portions over the insulating layer 281 can be removed by planarization treatment after the formation of the insulating layer 250 and the conductive layer 260.

[0353] Next, a conductive layer 265 is formed over the insulating layer 281 and the conductive layer 260, and the semiconductor device shown in FIGS. 16A to 16D can be manufactured.

[0354] 37A to 38C , an example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. In each figure, A is a plan view of the semiconductor device, a drawing marked with B corresponds to the dashed-dotted line C1-C2 in A, and a drawing marked with C corresponds to the dashed-dotted line C3-C4 in A.

[0355] First, with reference to FIGS. 28A to 33C, the structure shown in FIGS. 33A to 33C is fabricated.

[0356] Next, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260 are formed in this order (FIGS. 37A to 37C). For the formation of the oxide semiconductor layer 230, reference can be made to FIGS. 34A to 34C.

[0357] Next, part of the conductive layer 260, part of the insulating layer 250, and part of the oxide semiconductor layer 230 over the insulating layer 281 are sequentially removed by planarization treatment. By the planarization treatment, the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 over the insulating layer 281 are removed, and the top surface of the insulating layer 281 is exposed. Furthermore, by the planarization treatment, the conductive layer 260, the insulating layer 250, and the oxide semiconductor layer 230 located outside the opening 289 in a planar view are removed. Chemical mechanical polishing (CMP) treatment can be used for the planarization.

[0358] Next, a portion of the oxide semiconductor layer 230 provided in the opening 289, including a portion located at the upper end of the opening 289, is removed by etching, so that the height of the upper end of the oxide semiconductor layer 230 is lower than the height of the outer periphery of the opening 289 in the insulating layer 281 ( FIGS. 38A and 38B ). The removed region of the oxide semiconductor layer 230 is indicated as region 273. The region 273 is, for example, a void.

[0359] Next, an insulating layer 282 is formed over the insulating layer 281. The insulating layer 282 is preferably provided so as to bury the region 273.

[0360] Next, a conductive layer 266 is formed so as to be embedded in the insulating layer 282. Subsequently, a conductive layer 265 is formed over the insulating layer 282 and the conductive layer 266, whereby the semiconductor device shown in FIGS.

[0361] 57A to 62C , an example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. In each figure, A is a plan view of the semiconductor device, a drawing marked with B corresponds to the dashed dotted line A1-A2 in A, and a drawing marked with C corresponds to the dashed dotted line A3-A4 in A.

[0362] First, an insulating layer 210, a conductive layer 220 on the insulating layer 210, an insulating layer 280 on the insulating layer 210 and the conductive layer 220, a conductive film 240af on the insulating layer 280, and a conductive film 240bf on the conductive film 240af are formed on a substrate.

[0363] Next, a mask is formed over the conductive film 240bf (FIGS. 57A to 57C). Here, a structure in which SOC, SOG, and resist are stacked is used as the mask. FIGS. 57A to 57C show a state in which a resist mask 274c is formed on the SOC layer 274a and the SOG layer 274b. After this, the SOG layer 274b and the SOC layer 274a are processed using the resist mask 274c as a mask. The resist mask 274c is removed, for example, when the SOC layer 274a is processed.

[0364] 57A to 57C show an example in which the insulating layer 280a has a stacked structure of insulating layers 280a1 and 280a2. The insulating layer 280a1 is formed using a method with high coverage, for example. The upper surface of the insulating layer 280a2 is planarized using a planarization treatment, for example.

[0365] Next, using the SOC layer 274a as a mask, part of the conductive film 240bf and part of the conductive film 240af are removed to form a stacked structure of a conductive layer 240a having an opening 290b1 and a conductive layer 240b having an opening 290b2 (Figures 58A to 58C).

[0366] Next, an insulating film 278f is formed while leaving the SOC layer 274a (FIGS. 59A to 59C). The insulating film 278f is formed so as to cover the top surface of the SOC layer 274a, the side surfaces of the SOC layer 274a, the side surfaces of the openings 290b2 and 290b1 of the conductive layer 240b, and the exposed top surface of the insulating layer 280. At this time, the SOG layer 274b may remain on the SOC layer 274a.

[0367] Next, a portion of the insulating film 278f is removed to form the insulating layer 278. Subsequently, the SOG layer 274a is used as a mask to form an opening 290a in the insulating layer 280 (FIGS. 60A to 60C). Anisotropic etching can be used to form the insulating layer 278. Isotropic etching can also be used. Note that, if the SOG layer 274b remains before the insulating film 278f is removed, for example, the SOG layer 274b will be removed during the etching that forms the opening 290a in the insulating layer 280.

[0368] The SOC layer 274a is then removed. By leaving the SOC layer 274a on the conductive layer 240b and processing the insulating film 278f and the insulating layer 280 using the SOC layer 274a as a mask, the shape of the insulating layer 278 and the shape of the side surface of the opening in the insulating layer 280 can be improved. Furthermore, when processing the insulating film 278f and the insulating layer 280, the top of the conductive layer 240b can be protected by the SOC layer 274a.

[0369] Next, a film that becomes the oxide semiconductor layer 230 is formed so as to cover the top surface of the conductive layer 220, the side surfaces of the opening 290a in the insulating layer 280, the side surfaces of the insulating layer 278, the side surfaces of the conductive layer 240b, and the top surface of the conductive layer 240b. Subsequently, a mask is used to remove parts of the oxide semiconductor layer 230, the conductive layer 240b, and the conductive layer 240a (FIGS. 61A to 61C). This allows the conductive layer 240 to function as a wiring extending in the X direction, for example.

[0370] Subsequently, an insulating layer 250 and a conductive layer 260 are formed in this order over the oxide semiconductor layer 230, whereby the semiconductor device illustrated in FIGS. 62A to 62C can be manufactured.

[0371] <Configuration Example 5 of Semiconductor Device> Fig. 62A is a plan view showing an example of a semiconductor device, Fig. 62B is a cross-sectional view corresponding to the dashed dotted line A1-A2 shown in Fig. 62A, and Fig. 62C is a cross-sectional view corresponding to the dashed dotted line A3-A4 shown in Fig. 62A.

[0372] 62A to 62C show an example in which the side surface of insulating layer 278 is positioned further outward than the side surface of insulating layer 280 when viewed from the opening, similarly to FIGS. 11B and 11C.

[0373] 63A to 63C show an example of a semiconductor device that does not include an insulating layer 278. In the structures shown in Fig. 63A to 63C, the side surfaces of the conductive layer 240b, the conductive layer 240a, and the insulating layer 280 are approximately aligned. Furthermore, the insulating layer 278 is not disposed between the conductive layer 240a and the oxide semiconductor layer 230, and the side surface of the conductive layer 240a and the oxide semiconductor layer 230 are in contact with each other.

[0374] Materials that can be used in the semiconductor device of this embodiment will be described below.

[0375] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 278, insulating layer 281, insulating layer 282, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0376] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0377] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0378] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0379] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms may be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0380] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0381] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0382] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0383] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0384] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0385] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0386] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0387] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0388] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0389] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0390] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0391] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0392] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0393] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0394] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0395] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0396] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0397] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0398] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0399] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0400] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0401] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0402] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0403] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0404] The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0405] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0406] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0407] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0408] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0409] The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIGS. 9A and 9B , the insulating layer 280 can have a three-layer structure including an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b. In this case, it is preferable to use a material with a low dielectric constant as the insulating layer 280b, and to use barrier insulating layers against oxygen as the insulating layers 280a and 280c. This can suppress oxidation of the conductive layer 220 and the conductive layer 240 and prevent high resistance.

[0410] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 280a and the insulating layer 280c, and a silicon oxide film as the insulating layer 280b. Note that each of the insulating layer 280a and the insulating layer 280c may have a stacked structure of two or more layers.

[0411] The insulating layer 281 preferably contains a material with a low relative dielectric constant. The insulating layer 281 may be made of any material, structure, or the like that can be used for the insulating layer 280.

[0412] Alternatively, the insulating layer 281 may have a laminated structure of a material with a low relative dielectric constant and a material having a barrier property against hydrogen.

[0413] When the insulating layer 281 has a barrier property against hydrogen, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0414] The insulating layer 282 preferably contains a material with a low relative dielectric constant. The insulating layer 282 may be made of any material, structure, or the like that can be used for the insulating layer 280.

[0415] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0416] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0417] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0418] The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0419] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0420] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0421] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0422] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0423] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0424] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0425] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0426] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0427] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0428] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0429] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0430] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0431] [Conductive Layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. Alternatively, nitrides of alloys containing the above-mentioned metal elements or oxides of such alloys may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0432] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon (ITSO), indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0433] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0434] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0435] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0436] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0437] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even when it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even when it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing silicon (In—Sn—Si oxide, also referred to as ITSO), In—Zn oxide, or the like.

[0438] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0439] The conductive layer 240 preferably includes a conductive layer 240a and a conductive layer 240b over the conductive layer 240a. It is preferable that the conductive layer 240b be made of an oxide conductor, and the conductive layer 240a be made of a material having higher conductivity than the conductive layer 240b.

[0440] The conductive layer 240a can be made of, for example, any of the metal elements listed above, alloys containing the metal elements listed above, or alloys combining the metal elements listed above. Also usable are tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Also usable are semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0441] The conductive layer 240b can be, for example, a conductive material containing oxygen, a conductive material containing nitrogen, a material containing a metal element such as titanium, tantalum, or ruthenium, or a metal oxide, metal nitride, or the like.

[0442] More specifically, the conductive layer 240b is preferably made of ITO, ITSO, or In—Zn oxide. The conductive layer 240a is preferably made of tungsten, copper, aluminum, or an alloy containing aluminum. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a.

[0443] 4B and 4C, the conductive layer 240 may include a conductive layer 240c between the insulating layer 280 and the conductive layer 240a. The conductive layer 240c can be made of a material that can be used for the conductive layer 240b.

[0444] Alternatively, the conductive layer 240a can be made of a material that is resistant to oxidation, such as a metal element, an alloy containing the above-mentioned metal element, or an alloy combining the above-mentioned metal elements.

[0445] The conductive layer 220 can have a stacked structure of two or more layers. Examples such as Figures 9A and 9B show examples in which the conductive layer 220 has a stacked structure of a conductive layer 220a and a conductive layer 220b on the conductive layer 220a. The conductive layer 220a can be made of, for example, the material applicable to the conductive layer 240a described above. The conductive layer 220b can be made of, for example, the material applicable to the conductive layer 240b described above.

[0446] The conductive layer 220a can also have a stacked structure of two or more layers. When the conductive layer 220a has a two-layer stacked structure, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion can be used as the lower layer of the conductive layer 220a, and a highly conductive material can be used as the upper layer of the conductive layer 220a. Specifically, titanium nitride can be used as the lower layer of the conductive layer 220a, and tungsten can be used as the upper layer of the conductive layer 220a. In this case, the titanium nitride film is in contact with the insulating layer 210. By using a material that is resistant to oxidation as the lower layer of the conductive layer 220a, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed when an oxide insulating layer is used for the insulating layer 210. Furthermore, by using a metal material (here, tungsten) that has a higher conductivity than an oxide conductor and titanium nitride as the upper layer of the conductive layer 220a, the conductivity of the conductive layer 220 can be increased.

[0447] The conductive layer 260 has a region that functions as a gate wiring. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0448] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0449] 9A and 9B, etc., has a two-layer structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. The conductive layer 260a is preferably formed under conditions that provide high coverage. For example, a film having a barrier property against oxygen, hydrogen, and the like may be used as the conductive layer 260a. For the conductive layer 260b, a highly conductive material is preferably used.

[0450] Specifically, for example, it is preferable to use a titanium nitride film as the conductive layer 260a and a tungsten film as the conductive layer 260b. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260a and a copper film as the conductive layer 260b. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0451] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0452] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0453] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0454] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0455] Embodiment 2 In this embodiment, a memory device will be described. A semiconductor device according to one embodiment of the present invention can be applied to a memory device.

[0456] 39A and 39B , a structure of a memory device including a transistor and a capacitor will be described. Fig. 39A is a plan view of a memory device including a transistor 200 and a capacitor 100. Fig. 39B is a cross-sectional view corresponding to the dashed dotted line A1-A2 shown in Fig. 39A .

[0457] Fig. 39A is a plan view showing an example in which four memory cells 150 are arranged in two rows in the Y direction and two columns in the X direction. Fig. 39B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 39A.

[0458] Each memory cell 150 has a capacitor element 100 and a transistor 200 on the capacitor element.

[0459] The memory device shown in Figures 39A and 39B has an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a plurality of memory cells 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 281, and a conductive layer 265 on the memory cells 150.

[0460] The conductive layer 110 functions as a wiring and is shared by a plurality of memory cells 150 .

[0461] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0462] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0463] As shown in FIG. 39B , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIG. 39B , the conductive layer 120 is preferably disposed so as to fill the opening 190. The films disposed inside the opening 190 are preferably formed using a method with high coverage, such as an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed by an ALD method, a metal CVD method, or the like.

[0464] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote higher integration of memory devices.

[0465] 39B shows an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a configuration, a memory device can be highly integrated.

[0466] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench capacitor or a trench capacitor.

[0467] An insulating layer 280 and an insulating layer 281 are disposed on the capacitor element 100 .

[0468] The structure of the transistor 200 described in Embodiment 1 can be applied to the transistor 200. Note that in FIG. 39B , the conductive layer 120 is used instead of the conductive layer 220 of the transistor 200 described in Embodiment 1. Note that the conductive layer 220 can be formed over the conductive layer 120 without omitting the conductive layer 220.

[0469] The transistor 200 can be described in Embodiment 1; therefore, detailed description thereof will be omitted.

[0470] As shown in FIGS. 39A and 39B , the transistor 200 is provided so as to overlap with the capacitor 100. An opening 290 in which part of the structure of the transistor 200 is provided overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0471] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0472] [Insulating Layer 130] It is preferable to use a material with a high relative dielectric constant (high-k) as the insulating layer 130. By using a material with a high relative dielectric constant as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0473] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a stack structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0474] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material with a high relative dielectric constant and the material that can have ferroelectricity, see the description of the first embodiment.

[0475] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when the thickness is as thin as a few nanometers, and are therefore preferable as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0476] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0477] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0478] <Configuration Example 2 of Memory Device> The configuration of a memory device including a transistor and a capacitor will be described with reference to Figures 40A to 40C. Figure 40A is a plan view of a memory device including a transistor 200, a transistor 200(2), and a capacitor 100. Figure 40B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in Figure 40A. Figure 40C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in Figure 40A.

[0479] 40A to 40C includes an insulating layer 140 over a substrate (not shown) and a memory cell 151 over the insulating layer 140. The memory cell 151 includes a transistor 200 over a conductive layer 110, a capacitor 100b over the transistor 200, and a transistor 200 over the capacitor 100b. The two transistors 200 included in the memory cell 151 are stacked vertically with the capacitor 100b sandwiched between them. The transistor 200 located on the lower side is referred to as transistor 200(2). In addition, in FIGS. 40B and 40C, the conductive layer 220 and the conductive layer 240 included in the transistor 200(2) are referred to as conductive layer 220(2) and conductive layer 240(2), respectively.

[0480] The capacitor 100 b includes a conductive layer 120 , a conductive layer 115 , and an insulating layer 130 .

[0481] An insulating layer 180 is provided over the transistor 200(2). An insulating layer 130 is provided over the insulating layer 280.

[0482] The conductive layer 120 has a portion that is provided so as to be embedded in the insulating layer 180. The insulating layer 130 has a portion that is sandwiched between the conductive layer 115 and the conductive layer 120. In the capacitor 100b, the conductive layer 120 has a columnar shape, and the insulating layer 130 is provided so as to surround the conductive layer 120. The conductive layer 115 is provided so as to surround the conductive layer 120 with the insulating layer 130 sandwiched therebetween.

[0483] The conductive layer 260 of the transistor 200(2) and the conductive layer 220 of the transistor 200 are connected to each other through the conductive layer 120. The conductive layer 120 is preferably provided in contact with the top surface of the conductive layer 260 of the transistor 200(2). The conductive layer 220 of the transistor 200 is preferably provided in contact with the top surface of the conductive layer 120.

[0484] <Configuration Example 3 of Memory Device> FIG. 41 shows an example in which a plurality of memory cells are stacked in n layers (n is an integer of 3 or more) in the Z direction.

[0485] 41 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost level. The number of memory cells included in one memory layer 160 is not particularly limited, and one memory layer 160 may have two or more memory cells.

[0486] The memory layer 160 includes a plurality of memory cells 150. In FIG. 41, an insulating layer 286 is provided over the transistor 200, the insulating layer 281, and the conductive layer 265 included in the memory cell 150.

[0487] On the insulating layer 286, an upper memory layer 160 is further provided.

[0488] 41, two memory cells are connected to common wiring (conductive layer 245, conductive layer 246, conductive layer 247, conductive layer 248, etc.). The conductive layers 245, 246, 247, and 248 are connected to, for example, a sense amplifier (not shown) provided below the n-layer memory layer 160.

[0489] 41, by stacking a plurality of memory cells, it is possible to integrate and arrange the cells without increasing the area occupied by the memory cell array. In other words, it is possible to configure a 3D memory cell array.

[0490] 42 shows a cross-sectional structure example of a memory device. In the structure example shown in FIG. 42, a layer 168 including a transistor 200 and a memory layer 160 are stacked in this order over a layer 169 including a transistor 300.

[0491] Peripheral circuitry such as sense amplifiers may be provided in layer 169. Transistor 300 is, for example, a Si transistor.

[0492] 42 shows an example in which the transistor 300 included in the layer 169 is connected to the memory cell 150 included in the memory layer 160. The connection example shown in FIG. 42 can be applied to the case in which the transistor 300 is one of the transistors included in a sense amplifier.

[0493] 42, by providing a layer 169 so as to overlap the memory cell 150, it is possible to shorten the wiring connecting the memory cell 150 and the layer 169. For example, it is possible to shorten the bit line connected to the sense amplifier, which reduces the bit line capacitance and enables high-speed operation of the memory device.

[0494] The transistor included in the layer 168 can be used as, for example, a transistor that forms a peripheral circuit.

[0495] The transistor included in the layer 168 can be used in combination with, for example, the transistor included in the layer 169. A CMOS circuit can be configured by combining the transistor 300 in the layer 169 as a p-channel transistor and the transistor included in the layer 168 as an n-channel transistor.

[0496] 42 can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0497] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The semiconductor region 313, its neighboring regions, and the low-resistance regions 314a and 314b each preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the aforementioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. A configuration using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing may also be used. Alternatively, the transistor 200 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide and aluminum gallium arsenide.

[0498] Here, in the transistor 300 shown in FIG. 42 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0499] Note that the transistor 300 illustrated in FIG. 42 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0500] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0501] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0502] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0503] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in Fig. 42, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0504] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0505] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material, such as aluminum or copper, is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0506] The conductive layer 240 of the transistor 200 in the memory layer 160 is connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, the conductive layer 328, and a conductive layer provided to be embedded in the insulating layer of the layer 168.

[0507] The conductive layer 643 is embedded in the insulating layer 280. The conductive layer 240 of the transistor 200 included in the memory cell 150 is connected to the conductive layer 643. In the structure illustrated in FIG. 42 , the conductive layer 240 is located below the oxide semiconductor layer 230, and therefore the conductive layer 240 can be easily provided so as to be in contact with the top surface of the conductive layer 643.

[0508] The conductive layer 642 is provided over the insulating layer 130 and is embedded in the insulating layer 641. The conductive layer 642 can be manufactured using the same material and process as the conductive layer 120. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 can be manufactured using the same material and process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The insulating layer 648 insulates the transistor 300 from the layer 168. An insulating layer 647 is provided over the layer 168. The conductive layer 645 is embedded in the insulating layer 647. The insulating layer 647 insulates the transistor 200 of the layer 168 from the conductive layer 110.

[0509] As described above, the memory device of this embodiment has a transistor with reduced parasitic capacitance, and therefore the operating speed can be increased. In addition, the memory device of this embodiment has a capacitor and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a memory device with high integration can be realized.

[0510] <Application to Circuit Diagrams> The memory device described in this embodiment can be applied to the circuit diagrams described in later embodiments, for example, the circuit diagrams shown in FIGS.

[0511] The memory device described in this embodiment can be applied to, for example, the circuit diagram shown in FIG. 44A . The memory cell 951 includes a transistor M1 and a capacitor CA. Here, by using the transistor 200 as the transistor M1 and the capacitor 100 as the capacitor CA, the configuration of the memory cell 150 shown in FIGS. 39A and 39B can be applied to FIG. 44A .

[0512] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. The wiring BIL functions as a bit line, and the wiring WOL functions as a word line.

[0513] Here, in the transistor of one embodiment of the present invention, an insulating layer 281 is provided between the conductive layer 240 and the conductive layer 260 which function as a bit line, and an insulating layer 280 is provided between the conductive layer 220. Therefore, the wiring capacitance between the conductive layer 240 and the conductive layer 260 and the wiring capacitance between the conductive layer 240 and the conductive layer 220 can be reduced. That is, in the memory device of one embodiment of the present invention, the parasitic capacitance of the bit line can be made extremely small.

[0514] Furthermore, when a low potential signal is applied to the gate of the transistor, carriers are not induced in the semiconductor layer, and it can be said that parasitic capacitance generated between the conductive layer 260 functioning as a word line and the oxide semiconductor layer 230 is extremely small. When a high potential signal is applied to the gate, carriers are induced in the semiconductor layer, and significant parasitic capacitance may be generated between the conductive layer 260 and the oxide semiconductor layer 230. However, since the influence of parasitic capacitance on the word line is smaller than that on the bit line in the operation of the memory device, the memory device of one embodiment of the present invention can achieve sufficiently high operating speed by extremely reducing the parasitic capacitance of the bit line.

[0515] The memory device described in this embodiment can be applied to, for example, the circuit diagrams shown in Figures 44C and 44D. Each of the memory cell 953 and the memory cell 954 includes a transistor M2, a transistor M3, and a capacitor CB. Here, by applying the transistor 200 as the transistor M2, the transistor 200(2) as the transistor M3, and the capacitor CB as the capacitor CB, the configuration of the memory cell 151 shown in Figures 40A to 40C and the like can be applied to Figures 44C and 44D.

[0516] 44C , the wiring WBL corresponds to the conductive layer 240 of the transistor 200, the wiring WOL corresponds to the conductive layer 260 of the transistor 200, the wiring CAL corresponds to the conductive layer 115, and the wiring RBL and the wiring SL correspond to one of the conductive layers 240 and 220 of the transistor 200(2), respectively. The conductive layers 240 and 220 of the transistor 200(2) are referred to as the conductive layer 240(2) and the conductive layer 220(2), respectively, in FIGS. 40B and 40C . The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines.

[0517] In the memory device of one embodiment of the present invention, the conductive layer 240 of the transistor 200, which functions as a write bit line, has the insulating layer 281 between it and a wiring above it and the insulating layer 280 between it and a wiring below it, so that parasitic capacitance can be made extremely small. Similarly, the conductive layer 240(2) of the transistor 200(2), which functions as a read bit line, can also have extremely small parasitic capacitance.

[0518] Furthermore, the conductive layer 240 of the transistor 200 can be connected to one of the conductive layer 240 and the conductive layer 220 of the transistor 200(2) and at least one of them can be used as a wiring BIL, thereby applying the circuit diagram shown in FIG. 44D.

[0519] The circuit diagrams shown in Figures 44A to 44H and Figure 45 will be described in detail later.

[0520] This embodiment mode can be combined with other embodiment modes as appropriate.

[0521] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0522] Fig. 43A is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 43A has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 43A shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0523] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 43B, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 43C, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0524] The memory cell 950 can be any of the memory devices described in Embodiment 2 (such as the memory cell 150 ).

[0525] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0526] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0527] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0528] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0529] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0530] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0531] Each circuit included in the peripheral circuit 911 can have a function of generating or outputting a fixed potential, a variable potential (for example, a pulse voltage, a pulse signal, a clock signal, or the like).

[0532] The peripheral circuits may use Si transistors or the like.

[0533] An example of the structure of a Si transistor will be described below. An element isolation layer, a semiconductor region, a low-resistance region functioning as a source region or a drain region, and the like can be provided on a single-crystal silicon substrate or an SOI substrate having single-crystal silicon. Furthermore, a gate insulating layer, a gate electrode, and the like can be provided in a region overlapping with the semiconductor layer.

[0534] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0535] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0536] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 43A, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0537] Here, V ＤＤ For example, 0.8 V can be used as V. ＨＭ For example, 1.8 V, 2.5 V, 3.3 V, etc. can be used.

[0538] When the difference between the high power supply potential and the low power supply potential applied to the word line is 3.3 V, for example, the high power supply potential can be 3.3 V and the low power supply potential can be 0 V (e.g., ground potential). Alternatively, the high power supply potential can be 2.5 V and the low power supply potential can be −0.8 V. Alternatively, the high power supply potential can be 1.8 V and the low power supply potential can be −1.5 V.

[0539] Also, in the column driver 924, V ＤＤFor example, when data is written to the memory cell 950, a higher potential (for example, 1.8 V, 2.5 V, or 3.3 V) can be used. For example, when data is written to the memory cell 950, the write speed can be improved by using a higher potential. ＤＤ For example, V ＨＭ can be used for the column driver 924. Alternatively, V ＤＤ and V ＨＭ A different high power supply potential may be used.

[0540] 44A to 44H, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0541] 44A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0542] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0543] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0544] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0545] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0546] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 44B may be used. The memory cell 952 is an example in which the capacitor CA and the wiring CAL are not included. The first terminal of the transistor M1 is in a floating state.

[0547] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0548] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0549] 44C shows an example circuit configuration of a gain cell memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and elsewhere, a memory device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0550] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0551] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines. The wiring WOL may be called a write word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0552] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. At this time, a high-level potential is also applied to the wiring CAL. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential between the first and second terminals of the capacitor CB. Then, by applying a low-level potential to the wiring CAL, the gate potential of the transistor M3 decreases due to capacitive coupling of the capacitor CB, turning off the transistor M3.

[0553] Data is read by applying a high-level potential to the wiring CAL and a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0554] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 44D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0555] 44E is an example in which the capacitance element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 44F is an example in which the capacitance element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0556] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0557] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0558] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0559] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0560] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0561] 44G shows a gain cell type memory cell 957 having three transistors and one capacitor element. The memory cell 957 has transistors M4 to M6 and a capacitor element CC.

[0562] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0563] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0564] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0565] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0566] Note that at least the transistor M4 is preferably an OS transistor.

[0567] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0568] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0569] A memory cell 957b shown in FIG. 44H includes transistors M4 to M6, and does not include a capacitor CC.

[0570] A first terminal of the transistor M4 is connected to the gate of the transistor M5 and the node N, a second terminal of the transistor M4 is connected to the wiring WBL, and a gate of the transistor M4 is connected to the wiring WOL. A first terminal of the transistor M5 is connected to the wiring SL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6. A second terminal of the transistor M6 is connected to the wiring RBL, and a gate of the transistor M6 is connected to the wiring RWL.

[0571] To write data, a high-level potential is applied to the wiring WOL to turn on the transistor M4, thereby bringing the wiring WBL and the node N into electrical continuity, and charge is accumulated in the node N. After that, a low-level potential is applied to the wiring WOL to turn off the transistor M4, thereby maintaining the potential of the node N. Note that a constant potential (GND (ground potential) or low potential)) is always applied to the wiring SL.

[0572] To read data, the wiring RBL is precharged to a predetermined potential. The potential of the wiring SL is maintained constant. Furthermore, the potential of the wiring RWL is set to a high potential, and the transistor M6 is turned on, thereby bringing the wiring RWL and the second terminal of the transistor M5 into electrical continuity.

[0573] At this time, a high potential is applied to the second terminal of the transistor M5, and GND or a low potential is applied to the first terminal thereof. A potential having a magnitude corresponding to the data written to the node N is applied to the gate of the transistor M5. In other words, the type of data determines whether the transistor M5 is in an on state or an off state.

[0574] Here, when the data stored in the memory cell is "0", the difference between the gate potential and the source potential of transistor M5 is assumed to be lower than the threshold voltage of transistor M5. Also, when the data stored in the memory cell is "1", the difference between the gate potential and the source potential of transistor M5 is assumed to be higher than the threshold voltage of transistor M5. In this case, if the data stored in the memory cell is "0", transistor M5 is turned off (transistor M6 is turned on), and therefore no current flows from wiring RBL to wiring SL. On the other hand, if the data stored in the memory cell is "1", both transistors M5 and M6 are turned on, and therefore current flows from wiring RBL to wiring SL. The data stored in the memory cell can be read from the current flowing through wiring RBL or the potential of wiring RBL.

[0575] [OS-SRAM] FIG. 45 shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 45 is a memory cell of an SRAM capable of backing up data.

[0576] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0577] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0578] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0579] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0580] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0581] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0582] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0583] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0584] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0585] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0586] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0587] Note that Si transistors may be used as the transistors MS1 to MS4.

[0588] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0589] 46A shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 46A can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0590] The arithmetic device 960 shown in FIG. 46A has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0591] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0592] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0593] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0594] The arithmetic device 960 shown in FIG. 46A is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 46A as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0595] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0596] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and reads and writes data from and to the registers 996 depending on the state of the arithmetic unit 960.

[0597] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0598] In the arithmetic unit 960 shown in FIG. 46A, the register controller 997 selects the holding operation in the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 996 can be stopped.

[0599] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Figure 46B shows a perspective view of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separated in Figure 46B.

[0600] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance can reduce power consumption.

[0601] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0602] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0603] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0604] The arithmetic uni...

Claims

a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer and a second conductive layer on the first insulating layer, a third conductive layer on the second conductive layer, and a semiconductor layer; the first insulating layer, the second conductive layer, and the third conductive layer have openings that reach the first conductive layer; a periphery of the opening of the second conductive layer has a portion located outside a periphery of the opening of the third conductive layer in a plan view; the second insulating layer covers a side surface of the second conductive layer on the opening side; the second insulating layer is located outside a periphery of the opening of the third conductive layer and inside a periphery of the opening of the second conductive layer in a plan view; The semiconductor layer has a portion covering an area on the top surface of the first conductive layer that overlaps with the opening, a portion covering a side surface of the first insulating layer on the opening side, a portion covering a side surface of the second conductive layer on the opening side with the second insulating layer sandwiched therebetween, and a portion covering a side surface of the third conductive layer on the opening side. 　 In claim 1, a third insulating layer on the semiconductor layer; and a fourth conductive layer on the third insulating layer; The fourth conductive layer has a portion facing the side surface of the first insulating layer on the opening side, with the semiconductor layer and the third insulating layer sandwiched therebetween. 　 In claim 1, The semiconductor device includes a portion of the semiconductor layer that covers an upper surface of the third conductive layer. 　 a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer and a second conductive layer on the first insulating layer, a third conductive layer on the second conductive layer, a semiconductor layer, and a third insulating layer on the second insulating layer and the third conductive layer; the first insulating layer, the second conductive layer, the third conductive layer, and the third insulating layer have an opening that reaches the first conductive layer; a periphery of the opening of the second conductive layer has a portion located outside a periphery of the opening of the third conductive layer in a plan view; the second insulating layer covers a side surface of the second conductive layer on the opening side; the second insulating layer is located outside a periphery of the opening of the third conductive layer and inside a periphery of the opening of the second conductive layer in a plan view; The semiconductor layer has a first portion covering a region of the upper surface of the first conductive layer that overlaps with the opening, a second portion covering a side surface of the first insulating layer on the opening side, a third portion covering a side surface of the second conductive layer on the opening side with the second insulating layer in between, a fourth portion covering a side surface of the third conductive layer on the opening side, and a fifth portion covering a side surface of the third insulating layer on the opening side. 　 In claim 4, a fourth insulating layer on the semiconductor layer; and a fourth conductive layer on the fourth insulating layer; the fourth conductive layer has a portion facing the side surface of the first insulating layer on the opening side, with the semiconductor layer and the fourth insulating layer sandwiched therebetween, and a portion facing the side surface of the third insulating layer on the opening side, with the semiconductor layer and the fourth insulating layer sandwiched therebetween. 　 In claim 4, the semiconductor layer has a sixth portion covering an upper surface of the third conductive layer; The semiconductor device, wherein the third insulating layer covers an upper surface of the sixth portion of the semiconductor layer. 　 forming a first conductive layer; forming a first insulating layer, a second conductive layer, and a third conductive layer in this order on the first conductive layer; forming a first opening in the third conductive layer that reaches the second conductive layer; forming a second opening in the second conductive layer, the second opening reaching the first insulating layer; forming a third opening in the first insulating layer, the third opening reaching the first conductive layer; forming a first insulating film to include a first portion covering an upper surface of the first conductive layer that overlaps with the second opening, a second portion covering a side surface of the first insulating layer on the side of the third opening, a third portion covering a side surface of the second conductive layer on the side of the second opening and positioned below the third conductive layer, a fourth portion covering a side surface of the third conductive layer on the side of the first opening, and a fifth portion covering an upper surface of the third conductive layer; forming a second insulating layer by processing the first insulating film so as to leave the third portion and remove the first portion and the fifth portion; forming a semiconductor layer; forming a third insulating layer on the semiconductor layer; forming a fourth conductive layer on the third insulating layer; The method for manufacturing a semiconductor device, wherein the second opening is formed so that a periphery of the second opening has a portion located outside a periphery of the first opening in a plan view. 　 In claim 7, The method for manufacturing a semiconductor device, wherein the second opening in the second conductive layer is formed using an isotropic etching condition. 　 forming a first conductive layer; forming a first insulating layer, a second conductive layer, a third conductive layer, a first sacrificial layer, and a second insulating layer in this order on the first conductive layer; providing a first opening in the second insulating layer that reaches the first sacrificial layer; providing a second opening in the first sacrificial layer that reaches the third conductive layer; providing a third opening in the third conductive layer, the third opening reaching the second conductive layer; providing a fourth opening in the second conductive layer, the fourth opening reaching the first insulating layer; providing a fifth opening in the first insulating layer, the fifth opening reaching the first conductive layer; a first insulating film is formed to include: a first portion covering an upper surface of the first conductive layer that overlaps with the second opening; a second portion covering a side surface of the first insulating layer on the fifth opening side; a third portion covering a side surface of the second conductive layer on the fourth opening side and positioned below the third conductive layer; a fourth portion covering a side surface of the third conductive layer on the third opening side; a fifth portion covering a side surface of the first sacrificial layer on the second opening side; a sixth portion covering a side surface of the second insulating layer on the first opening side; and a seventh portion covering an upper surface of the second insulating layer; forming a third insulating layer by processing the first insulating film so as to leave the third portion and remove the first portion, the fifth portion, the sixth portion, and the seventh portion; removing the first sacrificial layer; forming a semiconductor layer; forming a second sacrificial layer; removing a portion of the semiconductor layer using the second sacrificial layer; forming a fourth insulating layer on the semiconductor layer; forming a fourth conductive layer on the fourth insulating layer; the fourth opening is formed such that a periphery of the fourth opening has a portion located outside a periphery of the third opening in a plan view, the semiconductor layer is formed to have a portion covering a side surface of the second insulating layer at least in the first opening, the second sacrificial layer is formed in the first opening so as to have a portion facing a side surface of the second insulating layer in the first opening with the semiconductor layer sandwiched therebetween; a second sacrificial layer formed in the first opening such that the height of the top surface of the second sacrificial layer is lower than the height of the top surface of the second insulating layer at the periphery of the first opening; 　 In claim 9, The method for manufacturing a semiconductor device, wherein the fourth opening in the second conductive layer is formed using an isotropic etching condition. 　 In claim 9, The method for manufacturing a semiconductor device, wherein the second sacrificial layer is Spin On Carbon.

Images