Semiconductor device

Abstract

A semiconductor device according to the present invention comprises a first inverter, a second inverter, a first PG transistor connected to a first bit line, a second PG transistor connected to a second bit line, a third PG transistor connected to a first complementary bit line, and a fourth PG transistor connected to a second complementary bit line. The first PG transistor and the second PG transistor share a first gate, and the third PG transistor and the fourth PG transistor share a second gate.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Static random access memories (SRAMs) are widely used as semiconductor devices. Because of their high read and write speeds, SRAMs are used in applications requiring high-speed processing. Dual-port static random access memories (SRAMs) with two ports for reading and writing data are also known (see, for example, Non-Patent Document 1). In a dual-port SRAM, one cell is composed of eight transistors: four pass gate (PG) transistors (Tr), two pull-up (PU) transistors, and two pull-down (PD) transistors. The dual-port SRAM described in Non-Patent Document 1 proposes a structure in which each transistor is formed using a fin field effect transistor (FinFET) to improve integration density (miniaturization and high integration) by miniaturizing elements and reducing cell area. Furthermore, in order to improve integration density by miniaturizing elements and reducing cell area, a configuration has been proposed for single-port SRAM in which pull-up and pull-down CMOS (Complementary Metal-Oxide-Semiconductor) inverters are formed using CFETs (Complementary Field-Effect Transistors) (see, for example, Patent Document 2).

[0003] K. Nii, et al., 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes, IEDM2015H. Liu, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO. 3, MARCH 2023

[0004] However, in the dual-port SRAM described in Non-Patent Document 1, although transistor miniaturization using FinFETs is possible, the number of transistors remains unchanged because eight transistors are arranged on a plane. Therefore, the configuration described in Non-Patent Document 1 limits the improvement of integration density. Furthermore, in the single-port SRAM described in Non-Patent Document 2, a pass gate transistor is formed adjacent to a CFET including a pull-up transistor and a pull-down transistor. However, the pass gate transistor is formed only on the lower layer of the pull-up transistor, and wiring for contacting the gate electrode and source / drain of the CMOS inverter is formed above the area where the pass gate transistor is formed. Thus, in the configuration described in Non-Patent Document 2, it is necessary to remove the upper layer of the area where the pass gate transistor is formed in order to form the wiring for the contact. Therefore, the configuration described in Non-Patent Document 2 does not allow the formation of four pass gate transistors required to form a dual-port SRAM. Therefore, the configuration described in Non-Patent Document 2 does not improve the integration density of a dual-port SRAM using a CFET structure.

[0005] In order to solve the above-mentioned problems, the present invention provides a semiconductor device that allows for an improvement in integration density.

[0006] The semiconductor device of the present invention includes a cross-coupled first inverter and a second inverter, a first pass gate transistor of a first conductivity type provided between a first bit line and the first and second inverters, a second pass gate transistor of a second conductivity type provided between a second bit line and the first and second inverters, a third pass gate transistor of the first conductivity type provided between a first complementary bit line and the first and second inverters, and a fourth pass gate transistor of the second conductivity type provided between the second complementary bit line and the first and second inverters, wherein the first and second pass gate transistors share a first gate connected to a word line, and the third and fourth pass gate transistors share a second gate connected to the word line.

[0007] According to the present invention, it is possible to provide a semiconductor device that allows for an improvement in integration density.

[0008] 1 is an equivalent circuit diagram of a bit cell of a dual-port SRAM. 2 is a plan layout diagram of an SRAM array including a dual-port SRAM. 3 is a plan layout diagram of transistors in an SRAM of a first embodiment. 4 is a cross-sectional view of the SRAM shown in FIG. 3 taken along line A-A. 5 is a cross-sectional view of the SRAM shown in FIG. 3 taken along line B-B. 6 is a cross-sectional view of the SRAM shown in FIG. 3 taken along line C-C. 7 is a diagram showing the relationship between the threshold voltage of an NMOS transistor, the threshold voltage of a PMOS transistor, and the standby voltage of a word line. 8 is a plan layout diagram of an SRAM array including word lines and sense amplifiers. 9 is a simplified timing chart of the SRAM when reading from port A. 10 is a simplified timing chart of the SRAM when reading from port B. 11 is a simplified timing chart of the SRAM when writing from port A. 12 is a simplified timing chart of the SRAM when writing from port B. 13 is a plan layout diagram of transistors in an SRAM of a second embodiment. 14 is a simplified timing chart of read and write operations in an SRAM of a third embodiment. 15 is a diagram showing a comparison between the standby voltage of a bit line in an SRAM of a third embodiment and the standby voltage of an SRAM bit line in an SRAM of a first embodiment.

[0009] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings, but the present invention is not limited to the following examples. In the following description, the drawings show only the configuration of the main parts of the semiconductor device, and other configurations such as insulating layers will be omitted. The description will be given in the following order: 1. First embodiment of the semiconductor device 2. Second embodiment of the semiconductor device 3. Third embodiment of the semiconductor device

[0010] 1. First Embodiment of Semiconductor Device A first embodiment of the semiconductor device of the present invention will now be described. [Circuit Diagram of Semiconductor Device] Fig. 1 shows an equivalent circuit diagram of a bit cell of a dual-port static random access memory (SRAM) as an example of a semiconductor device. Fig. 2 shows a plan layout diagram of an SRAM array including a dual-port SRAM.

[0011] As shown in FIG. 1, a dual-port SRAM cell 100 (hereinafter simply referred to as SRAM 100) has eight transistors (8Tr) in one bit cell. Of the eight Tr of SRAM 100, four transistors constitute a first CMOS (Complementary Metal-Oxide-Semiconductor) inverter INV1 (hereinafter referred to as the first inverter INV1) and a second CMOS inverter INV2 (hereinafter referred to as the second inverter INV2). Furthermore, SRAM 100 includes four transistors that control input and output to SRAM 100. In SRAM 100, the first conductivity type is n-type and the second conductivity type is p-type.

[0012] As shown in FIG. 2, an SRAM array using an 8-transistor SRAM 100 has SRAM 100 bit cells arranged in rows and columns in a plan view. The columns of the SRAM array are formed by a first bit line pair consisting of a first bit line BL_A and a first complementary bit line BLB_A, and a second bit line pair consisting of a second bit line BL_B and a second complementary bit line BLB_B. The rows of the SRAM array are formed by word lines WL. Therefore, the SRAM 100 is arranged along the word lines WL. FIG. 2 shows an example of an SRAM array, and three word lines WL are shown: word line WL<0>, word line WL<1>, and word line WL<2>. In addition, three pairs of first bit lines and second bit lines are shown: first bit line BL_A<0> and first complementary bit line BLB_A<0>, first bit line BL_A<1> and first complementary bit line BLB_A<1>, first bit line BL_A<2> and first complementary bit line BLB_A<2>, second bit line BL_B<0> and second complementary bit line BLB_B<0>, second bit line BL_B<1> and second complementary bit line BLB_B<1>, and second bit line BL_B<2> and second complementary bit line BLB_B<2>.

[0013] Each cell of the SRAM array is arranged between a pair of bit lines, each consisting of a first bit line pair and a second bit line pair. Therefore, as shown in FIG. 1, the SRAM 100 is arranged between a first bit line BL_A and a first complementary bit line BLB_A that make up the first bit line pair, and between a second bit line BL_B and a second complementary bit line BLB_B that make up the second bit line pair.

[0014] 1, the first inverter INV1 and the second inverter INV2 are cross-coupled, i.e., the output of the first inverter INV1 is connected to the input of the second inverter INV2, and similarly, the output of the second inverter INV2 is connected to the input of the first inverter INV1.

[0015] The first inverter INV1 constituting the SRAM 100 includes a pull-up PMOS (p-type metal oxide semiconductor) transistor PU1 (hereinafter referred to as transistor PU1) and a pull-down NMOS (n-type metal oxide semiconductor) transistor PD1 (hereinafter referred to as transistor PD1). The second inverter INV2 includes a pull-up PMOS transistor PU2 (hereinafter referred to as transistor PU2) and a pull-down NMOS transistor PD2 (hereinafter referred to as transistor PD2).

[0016] The SRAM 100 includes a pass-gate NMOS transistor PG1 (hereinafter referred to as transistor PG1) connected between a first bit line BL_A and the first and second inverters INV1 and INV2. The SRAM 100 also includes a pass-gate PMOS transistor PG2 (hereinafter referred to as transistor PG2) connected between a second bit line BL_B and the first and second inverters INV1 and INV2. One source / drain of the transistor PG1 is connected to the first bit line BL_A. One source / drain of the transistor PG2 is connected to the second bit line BL_B. The other source / drain of the transistors PG1 and PG2 is commonly connected to the output node Q of the first inverter INV1 and the input (gate) of the second inverter INV2.

[0017] The SRAM 100 further includes a pass-gate NMOS transistor PG3 (hereinafter referred to as transistor PG3) connected between the first complementary bit line BLB_A and the first and second inverters INV1 and INV2. The SRAM 100 also includes a pass-gate PMOS transistor PG4 (hereinafter referred to as transistor PG4) connected between the second complementary bit line BLB_B and the first and second inverters INV1 and INV2. One source / drain of the transistor PG3 is connected to the first complementary bit line BLB_A. One source / drain of the transistor PG4 is connected to the second complementary bit line BLB_B. The other source / drain of the transistors PG3 and PG4 is commonly connected to the output node QB of the second inverter INV2 and the input (gate) of the first inverter INV1. Hereinafter, the transistors PG1 and PG3 connected to the first bit line BL_A and the first complementary bit line BLB_A will be referred to as port A. The transistors PG2 and PG4 connected to the second bit line BL_B and the first complementary bit line BLB_A will be referred to as port B.

[0018] The gates of transistors PG1, PG2, PG3, and PG4 are connected to a word line WL that connects the SRAM 100 in a row of the SRAM array. Transistors PG1 and PG2 share a gate electrode. Therefore, the gates of transistors PG1 and PG2 are connected to the word line WL by a common electrode. Transistors PG3 and PG4 also share a gate electrode. Therefore, the gates of transistors PG3 and PG4 are connected to the word line WL by a common electrode.

[0019] In the SRAM 100, both the first inverter INV1 and the second inverter INV2 are coupled between a power supply voltage VDD and a reference potential VSS. That is, in the SRAM 100, one source / drain of the transistor PU1 is connected to the power supply voltage VDD, and the other source / drain is connected to the source / drain of the transistor PD1. One source / drain of the transistor PD1 is connected to the reference potential VSS, and the other source / drain is connected to the source / drain of the transistor PU1. One source / drain of the transistor PU2 is connected to the power supply voltage VDD, and the other source / drain is connected to the source / drain of the transistor PD2. One source / drain of the transistor PD2 is connected to the reference potential VSS, and the other source / drain is connected to the source / drain of the transistor PU2.

[0020] Transistors PU1 and PD1 share a gate. Transistors PU2 and PD2 share a gate. The common gate of transistors PU1 and PD1 is the input of the first inverter INV1. The common gate of transistors PU2 and PD2 is the input of the second inverter INV2. The connection (contact) between the source and drain of transistor PU1 and the source and drain of transistor PD1 is the output node Q of the first inverter INV1. The connection (contact) between the source and drain of transistor PU2 and the source and drain of transistor PD2 is the output node QB of the second inverter INV2.

[0021] [Configuration of Semiconductor Device] Next, the configuration of the SRAM 100 will be described. FIG. 3 shows a planar layout diagram of each transistor of the SRAM 100. FIGS. 4, 5, and 6 show cross-sectional views of the SRAM 100. The planar layout diagram shown in FIG. 3 shows the planar layout of each element in the top tier and bottom tier of the SRAM 100. FIG. 4 is a cross-sectional view of the SRAM 100 shown in FIG. 3 taken along line A-A. FIG. 5 is a cross-sectional view of the SRAM 100 shown in FIG. 3 taken along line B-B. FIG. 6 is a cross-sectional view of the SRAM 100 shown in FIG. 3 taken along line C-C. Note that in the drawings shown in FIGS. 3-6, insulating layers and the like other than those of the main components of the SRAM 100 are omitted unless necessary for explanation.

[0022] As shown in Figures 4-6, the SRAM 100 has a CFET (Complementary Field Effect Transistor) structure in which nanosheet transistors (semiconductor elements) having a GAA (Gate All Around)-FET structure are stacked vertically. In semiconductor devices, nanosheets also include nanowires. For this reason, Figure 3 shows the respective planar layouts of a GAA-FET with a nanosheet structure arranged on the upper layer side of the CFET and a GAA-FET with a nanosheet structure arranged on the lower layer side.

[0023] 3, in the SRAM 100, transistors PD1, PG1, PD2, and PG3, each formed by an NMOS, are arranged above the CFET. In the SRAM 100, transistors PU1, PG2, PG3, and PG4, each formed by a PMOS, are arranged below the CFET. In the SRAM 100 shown in FIG. 3, transistor PD1 is formed above transistor PU1. Transistor PG1 is formed above transistor PG2. Transistor PD2 is formed above transistor PU2. Transistor PG3 is formed above transistor PG4.

[0024] The SRAM 100 also includes two reference potential VSS lines and a word line WL as the wiring (Metal 1) in the top layer (first layer) on the front side of the CFET. The SRAM 100 also includes two word lines WL, a first bit line BL_A, and a first complementary bit line BLB_A as the wiring (Metal 2) in the second layer on the front side of the CFET. The SRAM 100 also includes two power supply voltage VDD lines, a second bit line BL_B, and a second complementary bit line BLB_B as the wiring (Back side metal) on the back side of the CFET. In the following description of the SRAM 100, the main surface of each transistor facing the substrate in the stacking direction is referred to as the back surface, and the main surface opposite the substrate is referred to as the front surface.

[0025] 3 and 5, gate electrodes 101, 102, 103, and 104 are formed continuously in the upper and lower layers of the CFET. That is, transistors PD1 and PU1 share a common gate electrode 101. Similarly, transistors PG1 and PG2 share a common gate electrode 103. Transistors PD2 and PU2 share a common gate electrode 104. Transistors PG3 and PG4 share a common gate electrode 102. The gate electrode 103 shared by transistors PG1 and PG2 is connected to a word line WL. The gate electrode 102 shared by transistors PG3 and PG4 is also connected to a word line WL.

[0026] 3, the transistor PD1 has a semiconductor layer 105 that serves as a channel and a source / drain, and a gate electrode 101. One end of the semiconductor layer 105 that serves as the source / drain of the transistor PD1 is provided with a contact metal 121 that connects the source / drain to the reference potential VSS. The other end of the semiconductor layer 105 is provided with a contact metal 123 that connects the source / drain of the transistor PD1 to the source / drain of the transistor PG1.

[0027] The transistor PG1 has a semiconductor layer 107 that serves as a channel, a source, and a drain, and a gate electrode 103. One end of the semiconductor layer 107 that serves as the source and drain of the transistor PG1 is provided with a contact metal 125 that connects the source and drain of the transistor PG1 to the first bit line BL_A. The other end of the semiconductor layer 107 is provided with a contact metal 123 that connects the source and drain of the transistor PG1 to the source and drain of the transistor PD1.

[0028] The transistor PG3 has a semiconductor layer 106 that serves as a channel, a source, and a drain, and a gate electrode 102. One end of the semiconductor layer 106 that serves as the source and drain of the transistor PG3 is provided with a contact metal 122 that connects the source and drain of the transistor PG3 to the first complementary bit line BLB_A. The other end of the semiconductor layer 106 is provided with a contact metal 124 that connects the source and drain of the transistor PG3 to the source and drain of the transistor PD2.

[0029] The transistor PD2 has a semiconductor layer 108 that serves as a channel, a source, and a drain, and a gate electrode 104. One end of the semiconductor layer 108 that serves as the source and drain of the transistor PD2 has a contact metal 126 that connects the source and drain to the reference potential VSS. The other end of the semiconductor layer 108 has a contact metal 124 that connects the source and drain of the transistor PD2 to the source and drain of the transistor PG3.

[0030] The transistor PU1 has a semiconductor layer 115 that serves as a channel, a source, and a drain, and a gate electrode 101. One end of the semiconductor layer 115 that serves as the source and drain of the transistor PU1 has a contact metal 131 that connects the source and drain to the power supply voltage VDD. The other end of the semiconductor layer 115 has a contact metal 133 that connects the source and drain of the transistor PU1 to the source and drain of the transistor PG2.

[0031] The transistor PG2 has a semiconductor layer 117 that serves as a channel, a source, and a drain, and a gate electrode 103. One end of the semiconductor layer 117 that serves as the source and drain of the transistor PG2 is provided with a contact metal 135 that connects the source and drain to the second bit line BL_B. The other end of the semiconductor layer 117 is provided with a contact metal 133 that connects the source and drain of the transistor PG2 to the source and drain of the transistor PU1.

[0032] The transistor PG4 has a semiconductor layer 116 that serves as a channel, a source, and a drain, and a gate electrode 102. One end of the semiconductor layer 116 that serves as the source and drain of the transistor PG4 is provided with a contact metal 132 that connects the source and drain to the second complementary bit line BLB_B. The other end of the semiconductor layer 116 is provided with a contact metal 134 that connects the source and drain of the transistor PG4 to the source and drain of the transistor PU2.

[0033] The transistor PU2 has a semiconductor layer 118 that serves as a channel, a source, and a drain, and a gate electrode 104. One end of the semiconductor layer 118 that serves as the source and drain of the transistor PU2 has a contact metal 136 that connects the source and drain to the power supply voltage VDD. The other end of the semiconductor layer 118 has a contact metal 134 that connects the source and drain of the transistor PU2 to the source and drain of the transistor PG4.

[0034] As shown in FIGS. 4-6 , the SRAM 100 is formed on a substrate 201. The substrate 201 has an insulating layer 202 on its surface, which serves as element isolation. The insulating layer 202 is formed between CFET elements to insulate the CFETs formed on the substrate 201. The top layer of wiring (Metal 1) of the SRAM 100 includes a word line WL and a reference potential VSS. The second layer of wiring (Metal 2) includes a first bit line BL_A and a first complementary bit line BLB_A. The word line WL and wiring 208 formed on the second layer are connected by contacts 203 and 211.

[0035] The wiring (back side metal) formed on the back side of the substrate 201 of the SRAM 100 includes two power supply voltage VDD lines, a second bit line BL_B, and a second complementary bit line BLB_B. In the wiring on the back side, the second bit line BL_B and the second complementary bit line BLB_B are arranged toward the center of the SRAM 100, and the two power supply voltage VDD lines are arranged outside the second bit line BL_B and the second complementary bit line BLB_B, respectively.

[0036] As shown in Fig. 4, in the cross-sectional view taken along line A-A in Fig. 3, contact metals 133 and 134 are formed on a substrate 201. Then, contact metals 123 are formed above contact metals 133, and contact metals 124 are formed above contact metals 134. Contact metals 133 and 123 are connected by wiring 137. This wiring 137 functions as an output node Q of the first inverter INV1. Contact metals 134 and 124 are connected by wiring 138. This wiring 138 functions as an output node QB of the second inverter INV2.

[0037] 3 , the gate electrode 101 is connected to the contact metal 124 by the gate contact metal 127. The gate electrode 104 is connected to the contact metal 123 by the gate contact metal 128. Therefore, the output node Q electrically connects the semiconductor layer 105 of the transistor PD1, the semiconductor layer 115 of the transistor PU1, the semiconductor layer 107 of the transistor PG1, the semiconductor layer 117 of the transistor PG2, and the gate electrode 104 shared by the transistors PD2 and PU2 via the contact metals 123, 133, and the gate contact metal 128. The output node QB electrically connects the semiconductor layer 108 of the transistor PD2, the semiconductor layer 118 of the transistor PU2, the semiconductor layer 106 of the transistor PG3, the semiconductor layer 116 of the transistor PG4, and the gate electrode 101 shared by the transistors PD1 and PU1 via the contact metals 124, 134, and the gate contact metal 127.

[0038] 5, in the cross-sectional view taken along line B-B in FIG. 3, gate electrodes 101 and 102 are formed on a substrate 201. Furthermore, on the lower layer side of the CFET, a semiconductor layer 115 is formed in the gate electrode 101, and a semiconductor layer 116 is formed in the gate electrode 102. On the upper layer side of the CFET, a semiconductor layer 105 is formed in the gate electrode 101, and a semiconductor layer 106 is formed in the gate electrode 102.

[0039] 5, in the SRAM 100, the periphery of semiconductor layers 105, 106, 115, and 116 constituting channel regions in a cross section in the gate width direction of transistor PD1, transistor PU1, transistor PG3, and transistor PG4 is covered with gate electrodes 101 and 102. Also, in the SRAM 100, the periphery of semiconductor layers 107, 108, 117, and 118 constituting channel regions in a cross section in the gate width direction of transistor PG1, transistor PG2, transistor PD2, and transistor PU2, which are not shown in the cross section of FIG. 5, is covered with gate electrodes 103 and 104. That is, the transistors PD1, PU1, PD2, PU2, PG1, PG2, PG3, and PG4 constituting the SRAM 100 are GAA (Gate All Around)-FETs with a nanosheet structure. 5 shows an example of an SRAM 100 in which three semiconductor layers 105, 106, 115, and 116 are formed. Also, as shown in FIG. 5, wiring 208 formed in the second layer is connected to the gate electrodes 102 of transistors PG3 and PG4 by contact 204. Therefore, in the SRAM 100, the word line WL and the gate electrodes 102 are connected via wiring 208 and contacts 203 and 204. Also, although not shown, in the SRAM 100, the gate electrodes 103 of transistors PG1 and PG2 are similarly connected to the word line WL via contact 211, a contact (not shown) at the same height as contact 204, and second-layer wiring 208.

[0040] 6, in the cross-sectional view taken along line CC in FIG. 3, contact metals 131 and 132 are formed on a substrate 201. Then, contact metals 121 are formed above contact metal 131, and contact metals 122 are formed above contact metal 132. The contact metals 131 and 121, and the contact metals 132 and 122 are each separated by an insulating layer or the like.

[0041] 6 , a reference potential VSS is provided in the wiring (Metal1) of the top layer of the SRAM 100. The reference potential VSS is connected to a second-layer wiring 208 by a contact 205. The second-layer wiring 208 is also connected to a contact metal 131 by a contact 207. Therefore, the contact metal 121 connected to the semiconductor layer 105 (source / drain) of the transistor PD1 is connected to the reference potential VSS via the second-layer wiring 208 and the contacts 205 and 207.

[0042] A first complementary bit line BLB_A formed in the second layer of the SRAM 100 is connected to a contact metal 122 connected to the semiconductor layer 106 (source / drain) of the transistor PG3 by a contact 206. A second complementary bit line BLB_B arranged on the back surface side of the SRAM 100 is connected to a contact metal 132 connected to the semiconductor layer 116 (source / drain) of the transistor PG4 by a contact 209 that passes through the substrate 201. A power supply voltage VDD arranged on the back surface side of the SRAM 100 is connected to a contact metal 131 connected to the semiconductor layer 115 (source / drain) of the transistor PU1 by a contact 210 that passes through the substrate 201.

[0043] Although not shown, in the SRAM 100, a contact metal 125 connected to the semiconductor layer 107 (source / drain) of transistor PG1 is connected to a first bit line BL_A arranged on the second layer via a contact. A contact metal 126 connected to the semiconductor layer 108 (source / drain) of transistor PD2 is connected to a reference potential VSS via a second layer wiring and a contact. A contact metal 135 connected to the semiconductor layer 117 (source / drain) of transistor PG2 is connected to a second bit line BL_B via a contact that penetrates the substrate 201. A contact metal 136 connected to the semiconductor layer 118 (source / drain) of transistor PU2 is connected to a power supply voltage VDD via a contact that penetrates the substrate 201.

[0044] With the above configuration, the dual-port SRAM shown in the equivalent circuit diagram in Figure 1 can be realized with a CFET structure in which nanosheet transistors having a GAA-FET structure are stacked vertically. This allows for a semiconductor device that can achieve improved integration density compared to SRAMs that use a FinFET structure. Furthermore, an 8-Tr dual-port SRAM in which a CFET structure is applied to the pass gate transistors as well can be formed in the same area as a 6-Tr single-port SRAM in which a CFET structure is applied to transistors other than the pass gate transistors. This allows for improved integration density of the semiconductor device. The SRAM 100 shown in Figures 3-6 above can be manufactured using conventional nanosheet transistor and CFET manufacturing methods and materials.

[0045] [Threshold Voltage Vth of Pass Gate Transistors] Next, the threshold voltage Vth of transistors PG1, PG2, PG3, and PG4 will be described. As described above, the SRAM 100 includes NMOS transistors PG1 and PG3 and PMOS transistors PG2 and PG4. In the SRAM 100, the threshold voltages Vth are set for the NMOS transistors PG1 and PG3 and the PMOS transistors PG2 and PG4, respectively. FIG. 7 shows the relationship between the threshold voltages Vth_PGn of the NMOS transistors PG1 and PG3, the threshold voltages Vth_PGp of the PMOS transistors PG2 and PG4, and the standby voltage VWL_stdby of the word line WL. In FIG. 7, the horizontal axis represents voltage, ranging from the reference potential VSS to the power supply voltage VDD.

[0046] 7, the voltage of the word line WL during standby is set to a standby voltage VWL_stdby. That is, the standby voltage of the word line WL is set between the voltage of the power supply voltage VDD and the voltage of the reference potential VSS. Also, as shown in FIG. 7, it is preferable to set the standby voltage VWL_stdby of the word line WL to about half the power supply voltage VDD.

[0047] Then, the threshold voltage Vth_PGn of the NMOS transistors PG1 and PG3 is set higher than the standby voltage VWL_stdby of the word line WL. That is, the threshold voltage Vth_PGn is set so that the relationship [VWL_stdby<Vth_PGn] holds. By setting the threshold voltage Vth_PGn higher than VWL_stdby, the transistors PG1 and PG3 do not operate in the standby state. When the transistors PG1 and PG3 are operated, the gate voltage applied from the word line WL to the NMOS transistors PG1 and PG3 is increased from the standby voltage VWL_stdby. Then, when the gate voltage from the word line WL reaches the threshold voltage Vth_PGn, the NMOS transistors PG1 and PG3 operate.

[0048] Furthermore, the threshold voltage Vth_PGp of the PMOS transistors PG2 and PG4 is set to be smaller than the standby voltage VWL_stdby of the word line WL, and the threshold voltage Vth_PGp is ​​set so that the relationship [VWL_stdby>Vth_PGp] holds. By setting the threshold voltage Vth_PGp to be smaller than VWL_stdby, the transistors PG2 and PG4 do not operate in the standby state. When the transistors PG2 and PG4 are to operate, the gate voltage applied from the word line WL to the PMOS transistors PG2 and PG3 is reduced from the standby voltage VWL_stdby. Then, when the gate voltage from the word line WL decreases to the threshold voltage Vth_PGp, the PMOS transistors PG2 and PG4 operate.

[0049] Therefore, the SRAM 100 includes transistors PG1, PG2, PG3, and PG4, each having a threshold voltage Vth such that [VWL_stdby<Vth_PGn] and [VWL_stdby>Vth_PGp] are satisfied. With this configuration, the NMOS transistors PG1 and PG3 and the PMOS transistors PG2 and PG4, which share a gate electrode, can be operated independently.

[0050] [Word Lines and Sense Amplifiers] Next, a description will be given of the word lines WL of the SRAM 100 and their connections to the sense amplifiers. Fig. 8 shows a plan view of an SRAM array including word lines and sense amplifiers.

[0051] As shown in FIG. 8, the SRAM 100 has a word line driver A (WL Driver A) and a word line driver B (WL Driver B). The word line driver A receives a row address RA_A. The word line driver B receives a row address RA_B. The SRAM 100 also has a sense amplifier SA_A and a sense amplifier SA_B. The sense amplifier SA_A receives a column address CA_A. The sense amplifier SA_B receives a column address CA_B.

[0052] The word line driver A (WL Driver A) and the word line driver B (WL Driver B) operate in different voltage ranges between the ports. That is, the word line driver A (WL Driver A) and the word line driver B (WL Driver B) have different circuits. In addition, the sense amplifier SA_A and the sense amplifier SA_BSA operate in different voltage ranges between the ports. That is, the sense amplifier SA_A and the sense amplifier SA_B have different circuits.

[0053] In the SRAM 100, bit cells are connected to a word line driver A (WL Driver A) and a word line driver B (WL Driver B) by word lines WL. Dual-port SRAMs cannot physically access the same word line WL. That is, NMOS transistors PG1 and PG3 (port A) and PMOS transistors PG2 and PG4 (port B) access different word line drivers A (WL Driver A) and B (WL Driver B). Furthermore, dual-port SRAMs prohibit the use of the same row address between ports. Therefore, different row addresses are assigned to the NMOS transistors PG1 and PG3 (port A) and the PMOS transistors PG2 and PG4 (port B).

[0054] In the SRAM 100, bit cells are connected to a sense amplifier SA_A and a sense amplifier SA_B via a first bit line BL_A, a first complementary bit line BLB_A, a second bit line BL_B, and a second complementary bit line BLB_B. In the dual-port SRAM, each port is connected to a different sense amplifier SA_A or SA_B. That is, a first bit line pair consisting of a first bit line BL_A and a first complementary bit line BLB_A is connected to the sense amplifier SA_A. A second bit line pair consisting of a second bit line BL_B and a second complementary bit line BLB_B is connected to the sense amplifier SA_B. Therefore, NMOS transistors PG1 and PG3 are connected to the sense amplifier SA_A via the first bit line pair. PMOS transistors PG2 and PG4 are connected to the sense amplifier SA_B via the second bit line pair.

[0055] [Simplified Timing Chart for Reading] Next, reading from the SRAM 100 will be described. Figures 9 and 10 show simplified timing charts for reading from the SRAM 100. Figure 9 is a timing chart for reading from port A. Figure 10 is a timing chart for reading from port B. In Figures 9 and 10, the vertical axis represents voltage (potential) and the horizontal axis represents time.

[0056] 9, in the SRAM 100 before the start of reading, the gate voltage from the word line WL to the transistors PG1 and PG3 is the standby voltage VWL_stdby. Also, in the SRAM 100 before the start of reading, the potential of the first bit line BL_A is the power supply voltage VDD. Also, as shown in FIG. 10, in the SRAM 100 before the start of reading, the gate voltage from the word line WL to the transistors PG2 and PG4 is the standby voltage VWL_stdby. Also, in the SRAM 100 before the start of reading, the potential of the second bit line BL_B is the reference potential VSS.

[0057] When reading from port A, i.e., NMOS transistors PG1 and PG3, as shown in FIG. 9 , the gate voltage supplied from the word line WL to the transistors PG1 and PG3 is set higher than the standby voltage VWL_stdby of the word line WL. By increasing the voltage from the word line WL, the first bit line BL_A is precharged to High. Thereafter, if the output node Q is Low, the potential of the first bit line BL_A drops. When the potential of the first bit line BL_A drops and a potential difference between the first bit line BL_A and the power supply voltage VDD is created that can be read by the sense amplifier SA_A, data from the first inverter INV1 and the second inverter INV2 can be read from port A.

[0058] When reading from port B, i.e., the PMOS transistors PG2 and PG4, as shown in FIG. 10, the gate voltage supplied from the word line WL to the transistors PG2 and PG4 is set lower than the standby voltage VWL_stdby of the word line WL. By reducing the voltage from the word line WL, the second bit line BL_B is precharged to low. Thereafter, if the output node Q is high, the potential of the second bit line BL_B rises. When the potential of the second bit line BL_B rises and a potential difference is created between the second bit line BL_B and the reference potential VSS that can be read by the sense amplifier SA_B, data from the first inverter INV1 and the second inverter INV2 can be read from port B.

[0059] [Simplified Timing Chart for Writing] Next, writing to the SRAM 100 will be described. Figures 11 and 12 show simplified timing charts for writing to the SRAM 100. Figure 11 is a timing chart for writing from port A. Figure 12 is a timing chart for writing from port B. In Figures 11 and 12, the vertical axis represents voltage (potential) and the horizontal axis represents time.

[0060] 11, before the start of writing in the SRAM 100, the gate voltage from the word line WL to the transistors PG1 and PG3 is the standby voltage VWL_stdby. Similarly, as shown in FIG. 12, before the start of writing in the SRAM 100, the gate voltage from the word line WL to the transistors PG2 and PG4 is the standby voltage VWL_stdby.

[0061] When writing data from port A, i.e., NMOS transistors PG1 and PG3, the gate voltage supplied to transistors PG1 and PG3 from word line WL is set higher than the standby voltage VWL_stdby of word line WL, as shown in FIG. 11 . By increasing the voltage from word line WL, output node Q is pulled to a low potential through first bit line BL_A. When the potential of output node Q drops below the trip potential of the data latch inside SRAM 100, the data in first inverter INV1 and second inverter INV2 is inverted. This makes it possible to write data from port A to the first inverter INV1 and second inverter INV2.

[0062] When writing data from port B, i.e., the PMOS transistors PG2 and PG4, as shown in FIG. 12, the gate voltage supplied to the transistors PG2 and PG4 from the word line WL is set lower than the standby voltage VWL_stdby of the word line WL. By reducing the voltage from the word line WL, the output node Q is raised to a high potential through the second bit line BL_B. When the potential of the output node Q rises above the trip potential of the data latch inside the SRAM 100, the data in the first inverter INV1 and the second inverter INV2 are inverted. This makes it possible to write data from port B to the first inverter INV1 and the second inverter INV2.

[0063] 2. Second Embodiment of Semiconductor Device Next, a second embodiment of the semiconductor device will be described. The semiconductor device of the second embodiment has a configuration in which the conductivity types of the transistors formed in the upper layer of the CFET and the transistors formed in the lower layer in the semiconductor device of the first embodiment described above are reversed. Furthermore, the semiconductor device of the second embodiment has the same configuration as the semiconductor device of the first embodiment described above, except for the change in conductivity type. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0064] As an example of the semiconductor device of the second embodiment, a planar layout diagram of each transistor of an SRAM 200 is shown in Fig. 13. The cross-sectional view of the SRAM 200 shown in Fig. 13 is similar to the structure shown in Figs. 4, 5, and 6 above, except for the conductivity type of the transistors and the positions of each wiring.

[0065] As shown in FIG. 13, the SRAM 200 shows the planar layout of a nanosheet structure GAA-FET arranged in the top tier of a CFET and a nanosheet structure GAA-FET arranged in the bottom tier. In the SRAM 200, transistors PU1, PG2, and PG4, which are formed by PMOS, are arranged above the CFET. In the SRAM 200, transistors PD1, PG1, PD2, and PG3, which are formed by NMOS, are arranged below the CFET. In the SRAM 200 shown in FIG. 13, transistor PU1 is formed above transistor PD1. Transistor PG2 is formed above transistor PG1. Transistor PU2 is formed above transistor PD2. Transistor PG4 is formed above transistor PG3.

[0066] The SRAM 200 also includes two power supply voltage VDD lines and a word line WL as wiring (Metal 1) in the top layer (first layer) of the CFET. The SRAM 200 also includes two word lines WL, a second bit line BL_B, and a second complementary bit line BLB_B as wiring (Metal 2) in the second layer of the CFET. The SRAM 200 also includes two reference potential VSS lines, a first bit line BL_A, and a first complementary bit line BLB_A as wiring (Back side metal) on the back side of the CFET.

[0067] Also, similar to the first embodiment described above, the gate electrodes 101, 102, 103, and 104 are formed continuously in the upper and lower layers of the CFET. That is, the transistors PD1 and PU1 share the gate electrode 101. Similarly, the transistors PG1 and PG2 share the gate electrode 103. The transistors PD2 and PU2 share the gate electrode 104. The transistors PG3 and PG4 share the gate electrode 102. The gate electrode 103 shared by the transistors PG1 and PG2 is connected to the word line WL. The gate electrode 102 shared by the transistors PG3 and PG4 is also connected to the word line WL.

[0068] The transistor PD1 has a semiconductor layer 105 that serves as a channel, a source, and a drain, and a gate electrode 101. One end of the semiconductor layer 105 that serves as the source and drain of the transistor PD1 is provided with a contact metal 121 that connects the source and drain to the reference potential VSS. The other end of the semiconductor layer 105 is provided with a contact metal 123 that connects the source and drain of the transistor PD1 to the source and drain of the transistor PG1.

[0069] The transistor PG1 has a semiconductor layer 107 that serves as a channel, a source, and a drain, and a gate electrode 103. One end of the semiconductor layer 107 that serves as the source and drain of the transistor PG1 is provided with a contact metal 125 that connects the source and drain of the transistor PG1 to the first bit line BL_A. The other end of the semiconductor layer 107 is provided with a contact metal 123 that connects the source and drain of the transistor PG1 to the source and drain of the transistor PD1.

[0070] The transistor PG3 has a semiconductor layer 106 that serves as a channel, a source, and a drain, and a gate electrode 102. One end of the semiconductor layer 106 that serves as the source and drain of the transistor PG3 has a contact metal 122 that connects the source and drain to the first complementary bit line BLB_A. The other end of the semiconductor layer 106 has a contact metal 124 that connects the source and drain of the transistor PG3 to the source and drain of the transistor PD2.

[0071] The transistor PD2 has a semiconductor layer 108 that serves as a channel, a source, and a drain, and a gate electrode 104. One end of the semiconductor layer 108 that serves as the source and drain of the transistor PD2 has a contact metal 126 that connects the source and drain to the reference potential VSS. The other end of the semiconductor layer 108 has a contact metal 124 that connects the source and drain of the transistor PD2 to the source and drain of the transistor PG3.

[0072] The transistor PU1 has a semiconductor layer 115 that serves as a channel, a source, and a drain, and a gate electrode 101. One end of the semiconductor layer 115 that serves as the source and drain of the transistor PU1 is provided with a contact metal 131 that connects the source and drain of the transistor PU1 to the power supply voltage VDD. The other end of the semiconductor layer 115 is provided with a contact metal 133 that connects the source and drain of the transistor PU1 to the source and drain of the transistor PG2.

[0073] The transistor PG2 has a semiconductor layer 117 that serves as a channel, a source, and a drain, and a gate electrode 103. One end of the semiconductor layer 117 that serves as the source and drain of the transistor PG2 is provided with a contact metal 135 that connects the source and drain to the second bit line BL_B. The other end of the semiconductor layer 117 is provided with a contact metal 133 that connects the source and drain of the transistor PG2 to the source and drain of the transistor PU1.

[0074] The transistor PG4 has a semiconductor layer 116 that serves as a channel, a source, and a drain, and a gate electrode 102. One end of the semiconductor layer 116 that serves as the source and drain of the transistor PG4 is provided with a contact metal 132 that connects the source and drain to the second complementary bit line BLB_B. The other end of the semiconductor layer 116 is provided with a contact metal 134 that connects the source and drain of the transistor PG4 to the source and drain of the transistor PU2.

[0075] The transistor PU2 has a semiconductor layer 118 that serves as a channel, a source, and a drain, and a gate electrode 104. One end of the semiconductor layer 118 that serves as the source and drain of the transistor PU2 has a contact metal 136 that connects the source and drain to the power supply voltage VDD. The other end of the semiconductor layer 118 has a contact metal 134 that connects the source and drain of the transistor PU2 to the source and drain of the transistor PG4.

[0076] 13, the contact metal 123 and the contact metal 133 are connected by a wiring 137. This wiring 137 functions as an output node Q of the first inverter INV1. The contact metal 124 and the contact metal 134 are connected by a wiring 138. This wiring 138 functions as an output node QB of the second inverter INV2.

[0077] 13 , the gate electrode 101 is connected to the contact metal 134 by the gate contact metal 127. The gate electrode 104 is connected to the contact metal 133 by the gate contact metal 128. Therefore, the output node Q electrically connects the semiconductor layer 105 of the transistor PD1, the semiconductor layer 115 of the transistor PU1, the semiconductor layer 107 of the transistor PG1, the semiconductor layer 117 of the transistor PG2, and the gate electrode 104 shared by the transistors PD2 and PU2 via the contact metals 123, 133, and the gate contact metal 128. The output node QB electrically connects the semiconductor layer 108 of the transistor PD2, the semiconductor layer 118 of the transistor PU2, the semiconductor layer 106 of the transistor PG3, the semiconductor layer 116 of the transistor PG4, and the gate electrode 101 shared by the transistors PD1 and PU1 via the contact metals 124, 134, and the gate contact metal 127.

[0078] With the above configuration, an SRAM 200 according to the second embodiment can be realized. The circuit diagram of this SRAM 200 is the same as the circuit diagram of the first embodiment shown in FIG. 1. In this way, the configuration of the semiconductor device according to the second embodiment also makes it possible to configure a dual-port SRAM having a CFET structure in which nanosheet transistors having a GAA-FET structure are stacked vertically. The semiconductor device according to the second embodiment also provides the same effects as the semiconductor device according to the first embodiment.

[0079] 3. Third Embodiment of Semiconductor Device Next, a third embodiment of the semiconductor device will be described. In the semiconductor device of the third embodiment, the voltage of the bit line before and after reading and before and after writing, i.e., the standby voltage of the bit line, is changed to a setting different from that of the first embodiment described above. Furthermore, the semiconductor device of the third embodiment can apply the configurations of the first and second embodiments described above, except for the changed standby voltage of the bit line. Therefore, detailed description of the configurations similar to those of the semiconductor device of the first and second embodiments described above will be omitted.

[0080] 14 shows a simplified timing chart of read and write operations of the SRAM of the third embodiment. In FIG. 14, the vertical axis represents voltage (potential) and the horizontal axis represents time. FIG. 14 shows changes in the potentials of the first bit line BL_A and the second bit line BL_B during read and write operations.

[0081] 14, the standby voltage of the first bit line BL_A and the second bit line BL_B of the SRAM before the start of a read or write operation (Standby) is set to the standby voltage VWL_stdby of the word line WL. Then, during a read or write operation (Read / Write), the potential of the first bit line BL_A is lowered to the reference potential VSS. Also, during a read or write operation (Read / Write), the potential of the second bit line BL_B is raised to the power supply voltage VDD. Also, after the read or write operation is completed (Standby), the standby voltage of the first bit line BL_A and the second bit line BL_B returns to the standby voltage VWL_stdby of the word line WL. In this way, in the SRAM of the third embodiment, the potentials of the first bit line BL_A and the second bit line BL_B are set to approximately the same as the standby voltage VWL_stdby of the word line WL before and after reading and before and after writing.

[0082] 15 shows a comparison between the standby voltage of the bit line in the SRAM of the third embodiment and the standby voltage of the bit line in the SRAM of the first embodiment described above. In FIG. 15, the table and diagram to the left of the arrow show the standby voltage of the bit line in the SRAM of the first embodiment, and the table and diagram to the right of the arrow show the standby voltage of the bit line in the SRAM of the third embodiment. Furthermore, FIG. 15 shows the combination of potentials when the leakage current is maximum in the transistor PG1 connected to the first bit line BL_A and the transistor PG2 connected to the second bit line BL_B.

[0083] 15, in the first embodiment described above, the standby voltage of the bit line is such that the leakage current is greatest when the potential of the first bit line BL_A is the power supply voltage VDD and the potential of the output node Q is the reference potential VSS. At this time, the NMOS transistor PG1 has a gate-source voltage VGS that is at most approximately half the power supply voltage VDD (VDD / 2), and a drain-source voltage VDS that is at most approximately the same as the power supply voltage VDD. Furthermore, the PMOS transistor PG2 has a gate-source voltage VGS that is at most approximately half the negative value of the power supply voltage VDD (-VDD / 2), and a drain-source voltage VDS that is at most approximately the same as the negative value of the power supply voltage VDD (-VDD).

[0084] In contrast, in the SRAM of the third embodiment, the standby voltage of the bit line is set to be approximately the same as the standby voltage VWL_stdby of the word line WL. Therefore, when the potential of the first bit line BL_A is the standby voltage VWL_stdby and the potential of the output node Q is the reference potential VSS, the leakage current of the bit line standby voltage is maximized. At this time, the gate-source voltage VGS of the NMOS transistor PG1 is approximately equal to half the power supply voltage VDD (VDD / 2) at maximum, and the drain-source voltage VDS is approximately equal to half the power supply voltage VDD (VDD / 2). Furthermore, the gate-source voltage VGS of the PMOS transistor PG2 is approximately equal to half the negative value of the power supply voltage VDD (-VDD / 2) at maximum, and the drain-source voltage VDS is approximately equal to half the negative value of the power supply voltage VDD (-VDD / 2).

[0085] As described above, in the SRAM of the third embodiment, the gate-source voltages VGS of the transistors PG1 and PG2 are approximately the same as those in the SRAM of the first embodiment. However, while the drain-source voltage VDS of the transistor PG1 in the SRAM of the first embodiment is VDD, in the SRAM of the third embodiment, the drain-source voltage VDS of the transistor PG1 is reduced to (VDD / 2). Furthermore, while the drain-source voltage VDS of the transistor PG2 in the SRAM of the first embodiment is −VDD, in the SRAM of the third embodiment, the drain-source voltage VDS of the transistor PG2 is reduced to (−VDD / 2). In this way, in the SRAM of the third embodiment, the standby voltage of the bit line is set to approximately the same as the standby voltage VWL_stdby of the word line WL, thereby reducing the leakage current of the transistors PG1 and PG2.

[0086] In the above-described third embodiment, the first bit line BL_A, the second bit line BL_B, the transistor PG1, and the transistor PG2 were described, but the first complementary bit line BL_A, the second complementary bit line BL_B, the transistor PG3, and the transistor PG4 can also be set in the same manner.

[0087] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0088] 100, 200... SRAM, 101, 102, 103, 104... gate electrode, 105, 106, 107, 108, 115, 116, 117, 118... semiconductor layer, 121, 122, 123, 124, 125, 126, 131, 132, 133, 134, 135, 136... contact metal, 127, 128... gate contact metal, 137, 138, 208... wiring, 201... substrate, 202... insulating layer, 203, 204, 205, 206, 207, 209, 210, 211... contact, INV1... first inverter, INV2... second inverter, PD1, PD2, PG1, PG2, PG3, PG4, PU1, PU2... transistor

Claims

1. A semiconductor device comprising: a cross-coupled first inverter and a second inverter; a first pass gate transistor of a first conductivity type provided between a first bit line and the first inverter and the second inverter; a second pass gate transistor of a second conductivity type provided between a second bit line and the first inverter and the second inverter; a third pass gate transistor of a first conductivity type provided between a first complementary bit line and the first inverter and the second inverter; and a fourth pass gate transistor of a second conductivity type provided between a second complementary bit line and the first inverter and the second inverter, wherein the first pass gate transistor and the second pass gate transistor share a first gate connected to a word line, and the third pass gate transistor and the fourth pass gate transistor share a second gate connected to the word line.

2. The semiconductor device according to claim 1, wherein the first pass gate transistor, the second pass gate transistor, the third pass gate transistor, and the fourth pass gate transistor are nanosheet-type semiconductor elements.

3. The semiconductor device according to claim 2, wherein the first pass gate transistor and the second pass gate transistor are stacked, and the third pass gate transistor and the fourth pass gate transistor are stacked.

4. The semiconductor device according to claim 3, wherein the first inverter has a stacked first pull-down transistor of a first conductivity type and a first pull-up transistor of a second conductivity type; the second inverter has a stacked second pull-down transistor of a first conductivity type and a second pull-up transistor of a second conductivity type; and the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor are nanosheet-type semiconductor elements.

5. The semiconductor device according to claim 4, further comprising a substrate on which the first pass gate transistor, the second pass gate transistor, the third pass gate transistor, the fourth pass gate transistor, the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor are formed, the first pull-up transistor, the second pull-up transistor, the second pass gate transistor, and the fourth pass gate transistor being arranged on the substrate side, and the first pull-down transistor, the second pull-down transistor, the first pass gate transistor, and the third pass gate transistor being arranged on the first pull-up transistor, the second pull-up transistor, the second pass gate transistor, and the fourth pass gate transistor.

6. The semiconductor device according to claim 4, further comprising a substrate on which the first pass gate transistor, the second pass gate transistor, the third pass gate transistor, the fourth pass gate transistor, the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor are formed, the first pull-down transistor, the second pull-down transistor, the first pass gate transistor, and the third pass gate transistor being arranged on the substrate side, and the first pull-up transistor, the second pull-up transistor, the second pass gate transistor, and the fourth pass gate transistor being arranged on the first pull-down transistor, the second pull-down transistor, the first pass gate transistor, and the third pass gate transistor.

7. The semiconductor device according to claim 1, wherein the first bit line and the first complementary bit line are arranged on one surface side in the stacking direction of the first pass gate transistor and the second pass gate transistor, and the third pass gate transistor and the fourth pass gate transistor, and the second bit line and the second complementary bit line are arranged on the other surface.

8. The semiconductor device according to claim 1, wherein a voltage higher than a standby voltage is supplied from the word line to the first gate or the second gate, and the potentials of the first bit line and the first complementary bit line are lowered to read out data of the first inverter and the second inverter from the first pass gate transistor and the second pass gate transistor; and a voltage lower than the standby voltage is supplied from the word line to the first gate or the second gate, and the potentials of the second bit line and the second complementary bit line are raised to read out data of the first inverter and the second inverter from the third pass gate transistor and the fourth pass gate transistor.

9. The semiconductor device according to claim 1, wherein a voltage higher than a standby voltage is supplied from the word line to the first gate or the second gate, and potentials of the first bit line and the first complementary bit line are lowered to write data from the first pass gate transistor and the second pass gate transistor to the first inverter and the second inverter; and a voltage lower than the standby voltage is supplied from the word line to the first gate or the second gate, and potentials of the second bit line and the second complementary bit line are raised to write data from the third pass gate transistor and the fourth pass gate transistor to the first inverter and the second inverter.

10. The semiconductor device according to claim 1, wherein the potentials of the first bit line, the first complementary bit line, the second bit line, and the second complementary bit line are set to the standby voltage of the word line before and after reading data from the first inverter and the second inverter and before and after writing data to the first inverter and the second inverter.

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