Semiconductor device

Abstract

This semiconductor device comprises a semiconductor substrate having an upper surface. The semiconductor substrate includes: a main transistor part having a main gate trench part including a main gate conductive part; a sense transistor part having a sense gate trench part including a sense gate conductive part; a gate pad provided above the upper surface of the semiconductor substrate; main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive part; sense gate wiring disposed along the sense transistor part; and a gate wiring connection part connecting the main gate wiring and the sense gate wiring, wherein a resistance part is provided in the gate wiring connection part.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, a transistor overcurrent protection device in which a gate resistor is connected to a current detection transistor is known (see, for example, Patent Document 1). Also, a semiconductor device in which a diode and a resistor wiring are arranged in a gate wiring is known (see, for example, Patent Document 2). [Prior Art Literature] [Patent Document] [Patent Document 1] JP-A-7-146722 [Patent Document 2] JP-A-6510310 General disclosure

[0003] (Problem to be Solved) It is preferable to suppress the oscillation of the gate voltage of the sense transistor section. (Means for Solving the Problem)

[0004] A first aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface. In the semiconductor device, the semiconductor substrate may have a main transistor portion having a main gate trench portion including a main gate conductive portion. In the semiconductor device, the semiconductor substrate may have a sense transistor portion having a sense gate trench portion including a sense gate conductive portion. In any of the semiconductor devices, the semiconductor substrate may have a gate pad provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices, the semiconductor substrate may have a main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion. In any of the semiconductor devices, the semiconductor substrate may have a sense gate wiring arranged along the sense transistor portion. In any of the semiconductor devices, the semiconductor substrate may have a gate wiring connection portion connecting the main gate wiring and the sense gate wiring. In any of the semiconductor devices, a resistor portion may be provided in the gate wiring connection portion.

[0005] In any of the above semiconductor devices, the semiconductor substrate may further include a sense pad disposed adjacent to the sense transistor portion, and the gate wiring connection portion may be provided on an opposite side of the sense transistor portion from the sense pad.

[0006] In any one of the semiconductor devices described above, the sense gate trench portion may extend in an extension direction, and the gate wiring connection portion may be provided at a position overlapping with the sense transistor portion in a direction perpendicular to the extension direction in a top view.

[0007] In any of the above semiconductor devices, the resistor portion may include a first polysilicon layer disposed above the upper surface of the semiconductor substrate.

[0008] In any of the semiconductor devices described above, the main gate wiring may include a second polysilicon layer disposed above the top surface of the semiconductor substrate, and the first polysilicon layer may be connected to the second polysilicon layer.

[0009] In any of the above semiconductor devices, a metal layer may be provided above the first polysilicon layer via an insulating film.

[0010] In the top view of any of the above semiconductor devices, at least a portion of the first polysilicon layer may not be covered with a metal layer.

[0011] In any of the semiconductor devices described above, the main gate wiring may include a second polysilicon layer disposed above the top surface of the semiconductor substrate, and the first polysilicon layer may have a thickness different from that of the second polysilicon layer.

[0012] In any of the above semiconductor devices, the first polysilicon layer may have a stacked structure of an upper polysilicon layer and a lower polysilicon layer, and the thickness of the first polysilicon layer may be greater than the thickness of the second polysilicon layer.

[0013] In any of the above semiconductor devices, the upper polysilicon layer may not be provided on a portion of the upper surface of the lower polysilicon layer.

[0014] In a top view of any of the above semiconductor devices, the density of the sense gate trench portions may be greater than the density of the main gate trench portions.

[0015] In any of the above semiconductor devices, a plurality of the main gate trench portions and a plurality of the sense gate trench portions may be provided, and a spacing between the plurality of the sense gate trench portions may be smaller than a spacing between the plurality of the main gate trench portions.

[0016] In any of the above semiconductor devices, a plurality of the main gate trench portions may be provided. In any of the above semiconductor devices, the main transistor portion may have a plurality of main dummy trench portions. In any of the above semiconductor devices, a plurality of the sense gate trench portions may be provided. In any of the above semiconductor devices, the sense transistor portion may have a plurality of sense dummy trench portions. In any of the above semiconductor devices, the ratio of the number of the sense gate trench portions to the number of the sense dummy trench portions in the sense transistor portion may be greater than the ratio of the number of the main gate trench portions to the number of the main dummy trench portions in the main transistor portion.

[0017] In any one of the above semiconductor devices, the short-circuit current density when the rated voltage is applied is 5000 A / cm ２ It may be more than that.

[0018] In any of the above semiconductor devices, the sense gate wiring may be arranged in a closed loop shape surrounding the sense transistor portion.

[0019] In any of the above semiconductor devices, a drift region of a first conductivity type may be provided in the semiconductor substrate, and a trench bottom region of a second conductivity type may be provided at a bottom of the sense gate trench portion.

[0020] In any of the above semiconductor devices, the trench bottom region of the second conductivity type may be provided at the bottom of the main gate trench portion.

[0021] A second aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface. In the semiconductor device, the semiconductor substrate may have a drift region of a first conductivity type. In any of the semiconductor devices, the semiconductor substrate may have a main transistor portion having a main gate trench portion including a main gate conductive portion. In any of the semiconductor devices, the semiconductor substrate may have a sense transistor portion having a sense gate trench portion including a sense gate conductive portion. In any of the semiconductor devices, the semiconductor substrate may have a gate pad provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices, the semiconductor substrate may have a main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion. In any of the semiconductor devices, the semiconductor substrate may have a gate wiring connection portion connecting the main gate wiring and the sense gate conductive portion. In any of the semiconductor devices, a resistor portion may be provided in the gate wiring connection portion. In any of the semiconductor devices, a trench bottom region of a second conductivity type may be provided at the bottom of the sense gate trench portion.

[0022] In any of the above semiconductor devices, the trench bottom region of the second conductivity type may be provided at the bottom of the main gate trench portion.

[0023] Any of the above semiconductor devices may further include a sense gate wiring arranged along the sense transistor portion and connected to the sense gate conductive portion. In any of the above semiconductor devices, the gate wiring connection portion may connect the main gate wiring and the sense gate wiring.

[0024] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also be inventions.

[0025] 9 is a diagram showing an equivalent circuit of a semiconductor device 100 according to an embodiment of the present invention. FIG. 10 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. FIG. 11 is an enlarged view of region A in FIG. 2. FIG. 12 is an enlarged view of region A in FIG. 2. FIG. 13 is an enlarged view of region A in FIG. 2. FIG. 14 is a diagram showing an example of a B-B' cross section in FIG. 3A. FIG. 15 is a diagram showing simulation results of gate voltages. FIG. 16 is a diagram showing simulation results of gate voltages. FIG. 17 is a diagram showing another example of a B-B' cross section in FIG. 3A. FIG. 18 is a diagram showing another example of a B-B' cross section in FIG. 3A. FIG. 19 is a diagram showing another example of a B-B' cross section in FIG. 3A. FIG. 19 is a diagram showing another example of a B-B' cross section in FIG. 3A. FIG. 19 is a diagram showing an example of a configuration of a gate wiring connection portion 50 in a top view. FIG. 19 is a diagram showing an example of a D-D' cross section in FIG. 9. FIG. 19 is a diagram showing an example of a C-C' cross section in FIG. 3A. FIG. 20 is a diagram showing an A-A' cross section in FIG. 2. FIG. 21 is a diagram showing another example of region A in FIG. 2. FIG. 22 is a diagram showing another example of region A in FIG. 2. FIG. 23 is a diagram showing another example of an A-A' cross section in FIG. 2. FIG. 24 is a diagram showing another example of a B-B' cross section in FIG. 3A.

[0026] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification, the same parts in each drawing are given the same reference numerals, and their description may be omitted. Furthermore, for the sake of convenience, some components may not be illustrated.

[0027] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0028] In this specification, technical matters may be explained using an orthogonal coordinate system of X, Y, and Z axes. The orthogonal coordinate system merely specifies the relative positions of components and does not limit a specific direction. For example, the Z-axis direction does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0029] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0030] In this specification, when terms such as "same" or "equal" are used, it may include cases where there is an error due to manufacturing variations or the like. The error is, for example, within 10%. Furthermore, in this specification, when terms such as "parallel" or "perpendicular" are used, it may include an error of within 5°.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the term "impurity" may particularly refer to either an N-type donor or a P-type acceptor, and may be referred to as a "dopant." In this specification, "doping" means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type. In this specification, the doping concentration of an N-type region may be referred to as a "donor concentration," and the doping concentration of a P-type region may be referred to as an "acceptor concentration."

[0032] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. The unit system in this specification is the SI unit system unless otherwise specified.

[0033] 1 is a diagram showing an equivalent circuit of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 has a main transistor section 70 and a sense transistor section 170. The sense transistor section 170 has a similar structure to the main transistor section 70 and measures the current flowing through the main transistor section 70. The main transistor section 70 and the sense transistor section 170 may be formed within the same chip. In this example, the main transistor section 70 and the sense transistor section 170 are IGBTs, but the main transistor section 70 and the sense transistor section 170 may also be MOSFETs.

[0034] The collector electrode of the main transistor section 70 and the collector electrode of the sense transistor section 170 are connected to each other and to a common collector terminal (C). The gate of the main transistor section 70 and the gate of the sense transistor section 170 are connected to a common gate driver circuit via a gate terminal (G). The gate wiring of the main transistor section 70 and the sense transistor section 170 respectively have parasitic resistance components Rg, Rgg and parasitic inductance components Lg, Lgg.

[0035] The emitter electrode of the main transistor section 70 (sometimes referred to as the main emitter electrode) and the emitter electrode of the sense transistor section 170 (sometimes referred to as the sense emitter electrode) are electrically separated inside the semiconductor device 100. The main emitter electrode of the main transistor section 70 is connected to an emitter terminal (E) and is supplied with an emitter potential. The sense emitter electrode of the sense transistor section 170 is connected to the emitter terminal via a sense resistor Rs. A voltage Vcc is applied between the collector terminal and the emitter terminal from an external power supply.

[0036] When the semiconductor device 100 is operating, a predetermined current flows through the main transistor section 70, and a current corresponding to the current value of the main transistor section 70 flows through the sense transistor section 170. The value of the current flowing through the sense transistor section 170 is measured from the voltage drop across the sense resistor Rs at that time. The current value of the main transistor section 70 is estimated based on the measurement results from the sense transistor section 170. This makes it possible to detect an overcurrent in the main transistor section 70 and shut down the device. Note that the inductance component of wires, wiring, etc. is represented by Ls.

[0037] The main transistor section 70 has a gate-emitter capacitance Cge, a gate-collector capacitance Cgc, and a collector-emitter capacitance Cce. Similarly, the sense transistor section 170 also has a gate-emitter capacitance Cge, a gate-collector capacitance Cgc, and a collector-emitter capacitance Cce. Because the main transistor section 70 and the sense transistor section 170 are connected in parallel, a feedback loop is formed through the path of the gate terminal, the sense transistor section 170, the emitter terminal, the main transistor section 70, and the gate terminal. As a result, voltage oscillation may occur in this feedback loop. In this specification, this oscillation may be referred to as parallel oscillation.

[0038] The gate-emitter capacitance Cge of the sense transistor section 170 is significantly smaller than the gate-emitter capacitance Cge of the main transistor section 70. Therefore, if parallel oscillation occurs, the gate signal of the sense transistor section 170 is easily affected, and the gate voltage of the sense transistor section 170 may oscillate. This tendency becomes particularly pronounced as the performance of the semiconductor device 100 improves. Oscillation of the gate voltage of the sense transistor section 170 may cause malfunction in the main transistor section 70 or the sense transistor section 170, resulting in a decrease in short-circuit resistance. Therefore, it is preferable to suppress parallel oscillation. In an embodiment of the present invention, a resistor is provided in the gate wiring of the sense transistor section 170, thereby providing a resistor in the feedback loop and suppressing parallel oscillation.

[0039] Fig. 2 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 2 shows the positions of each component projected onto the top surface of the semiconductor substrate 10. Fig. 2 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0040] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In this specification, the outer peripheral edge of the semiconductor substrate 10 in a top view is referred to as an outer peripheral edge 138. The top view refers to a view parallel to the Z-axis from the top surface side of the semiconductor substrate 10. Furthermore, one of the edges of the outer peripheral edge 138 of the semiconductor substrate 10 in a top view is referred to as a first edge 139. In a top view, the direction parallel to the first edge 139 is referred to as the X-axis direction, and the direction perpendicular to the first edge 139 is referred to as the Y-axis direction.

[0041] An active portion 120 is provided in the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. The active portion 120 may be a region in which the main transistor portion 70 is formed. A main emitter electrode is provided above the active portion 120, but is omitted in FIG. 2 .

[0042] The active section 120 is provided with at least one of a main transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 2, the main transistor sections 70 and the diode sections 80 are alternately arranged along the X-axis direction. Note that the diode section 80 does not necessarily have to be provided.

[0043] In this example, the main transistor section 70 and the diode section 80 each have a longitudinal direction in the Y-axis direction. That is, the length of the main transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The longitudinal direction of the main transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0044] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, the region in which the diode section 80 is extended in the Y-axis direction to an active well region, which will be described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extended region.

[0045] A plurality of pad portions are provided above the upper surface of the semiconductor substrate 10. In the example of Fig. 2, a sense pad 114, an auxiliary emitter pad 115, a gate pad 116, a cathode pad 117, and an anode pad 118 are provided above the upper surface of the semiconductor substrate 10.

[0046] The sense pad 114 is connected to the sense transistor section 170. The sense transistor section 170 has the same structure as the main transistor section 70, but has a smaller area (corresponding to the area of ​​the channel) in a top view than the main transistor section 70. By detecting the current flowing in the sense transistor section 170, it is possible to estimate the current flowing throughout the semiconductor device 100. When wiring the output from the sense transistor section 170 to the main emitter electrode, a wire may be extended from the sense pad 114.

[0047] The auxiliary emitter pad 115 is connected to a main emitter electrode disposed above the upper surface of the semiconductor substrate 10. The wiring extending from the sense pad 114 may be connected to the main emitter electrode at the auxiliary emitter pad 115 by wire bonding so as to have the same potential as the main emitter electrode.

[0048] A gate signal is sent from a gate driver circuit to the gate pad 116. The gate pad 116 is connected to the gates of the main transistor section 70 and the sense transistor section 170 via gate wiring.

[0049] The cathode pad 117 and the anode pad 118 are connected to the temperature sensing unit 111 via the temperature sensing wiring 112. The temperature sensing unit 111 measures the temperature of the semiconductor device 100. The temperature sensing unit 111 is, for example, a diode for temperature measurement. The temperature sensing wiring 112 extends from the temperature sensing unit 111 to a region between the active unit 120 and the outer peripheral edge 138 on the upper surface of the semiconductor substrate 10, and is connected to the cathode pad 117 and the anode pad 118. The temperature sensing wiring 112 may be polysilicon. Note that the number and types of pads provided on the semiconductor substrate 10 are not limited to the example shown in FIG. 2 .

[0050] Each pad portion is formed of a metal material such as aluminum. The multiple pad portions may be arranged in a predetermined direction between the active portion 120 and a first edge 139 on the upper surface of the semiconductor substrate 10. The multiple pad portions in this example are arranged in the X-axis direction and are sandwiched between the active portion 120 and the first edge 139 in the Y-axis direction. The multiple pad portions in this example are provided above an active main well region 29, which will be described later.

[0051] In the arrangement direction of the pad sections, the sense transistor section 170 may be provided between any two pad sections. In this example, the sense transistor section 170 is disposed between the sense pad 114 and the auxiliary emitter pad 115 in the X-axis direction.

[0052] The sense transistor portion 170 has a sense gate trench portion having a trench structure, as will be described later. The sense gate trench portion has a sense gate conductive portion to which a gate voltage is applied. The main transistor portion 70 also has a main gate trench portion having a trench structure, as will be described later. The main gate trench portion has a main gate conductive portion to which a gate voltage is applied.

[0053] The semiconductor substrate 10 has a main gate wiring 48 and a sense gate wiring 148. The main gate wiring 48 is provided on the upper surface of the semiconductor substrate 10, and surrounds the active section 120 and at least one of the plurality of pad sections. The main gate wiring 48 is also provided so as to cross the active section 120. The main gate wiring 48 is connected to the main gate conductive section of the main transistor section 70. That is, the main gate wiring 48 extends from the gate pad 116 to the main gate conductive section.

[0054] The main gate wiring 48 is a wiring that transmits a gate signal to the main gate conductive portion. The main gate wiring 48 may be a wiring through which a charging current flows to charge the main gate conductive portion. The main gate wiring 48 may be a gate wiring other than the sense gate wiring 148 described later. In FIG. 2, the main gate wiring 48 is indicated by a dotted line.

[0055] The sense gate wiring 148 is provided above the upper surface of the semiconductor substrate 10 and is arranged along the sense transistor section 170. In this example, the sense gate wiring 148 surrounds the sense transistor section 170. The sense gate wiring 148 is connected to the sense gate conductive portion of the sense transistor section 170. "Arranged along the sense transistor section 170" may refer to being arranged parallel to one of the sides of the sense transistor section 170. The distance between the sense gate wiring 148 and the sense transistor section 170 may be smaller than the distance between the sense transistor section 170 and the sense pad 114. For example, if the sense transistor section 170 is rectangular, the sense gate wiring 148 may be arranged parallel to two or more sides of the sense transistor section 170, or may be arranged parallel to three or more sides. If there are multiple gate wirings arranged parallel to one of the sides of the sense transistor section 170, the sense gate wiring 148 may refer to the gate wiring closest to the sense transistor section 170.

[0056] The sense gate wiring 148 is a wiring that transmits a gate signal to the sense gate conductive portion. The sense gate wiring 148 may be a wiring that is arranged along the outer shape of the sense transistor portion 170 and that carries a charging current that charges the sense gate conductive portion. The sense gate wiring 148 does not need to include a wiring that carries a charging current that charges the main gate conductive portion.

[0057] In FIG. 2 , the sense gate wiring 148 is indicated by a thick solid line. In this example, the sense gate wiring 148 is arranged in a closed loop surrounding the sense transistor section 170. At least a portion of the main gate wiring 48 and the sense gate wiring 148 may have a laminated structure of metal and polysilicon. An insulating film may be provided between the metal wiring and the polysilicon wiring. The metal wiring and the polysilicon wiring may be electrically connected via a contact hole provided in the insulating film. The main gate wiring 48 and the sense gate wiring 148 are insulated from the upper surface of the semiconductor substrate 10 by an interlayer insulating film.

[0058] The semiconductor substrate 10 has a gate wiring connection portion 50 that connects the main gate wiring 48 and the sense gate wiring 148. In this example, the gate wiring connection portion 50 is disposed between the sense transistor portion 170 and the auxiliary emitter pad 115. The gate wiring connection portion 50 is a wiring that transmits a gate signal to the sense gate conductive portion, and is a wiring through which a charging current flows to charge the sense gate conductive portion. In other words, the sense gate wiring 148 is provided between the gate terminal (G) in FIG. 1 and the gate of the sense transistor portion 170. The gate wiring connection portion 50 may be a wiring through which no charging current flows to charge the main gate conductive portion.

[0059] The semiconductor substrate 10 has an active main well region 29 formed to surround the active section 120 in a top view. The active main well region 29 surrounds the main transistor section 70 and the diode section 80 in a top view. The active main well region 29 is a second conductivity type region provided from the top surface of the semiconductor substrate 10 to the interior. The active main well region 29 may surround the active section 120 along the main gate wiring 48. The active main well region 29 is also provided around the pad section, but the periphery of the pad section is not shown in FIG. 2 .

[0060] The edge termination structure 90 is provided on the top surface of the semiconductor substrate 10 between the active well region and the outer periphery edge 138 of the semiconductor substrate 10. The edge termination structure 90 may be arranged in an annular shape to surround the active well region on the top surface of the semiconductor substrate 10. In this example, the edge termination structure 90 is arranged along the outer periphery edge 138 of the semiconductor substrate 10. The edge termination structure 90 reduces electric field concentration on the top surface side of the semiconductor substrate 10. The edge termination structure 90 may have, for example, a guard ring, a field plate, a resurf structure, or a structure combining these.

[0061] 3A is an enlarged view of region A in FIG. 2. Region A includes the sense transistor section 170, the gate wiring connection section 50, and the surrounding area. In this example, the sense transistor section 170 faces the main transistor section 70 in the Y-axis direction. As an example, the length of the sense transistor section 170 in the Y-axis direction is 300 μm or more and 400 μm or less.

[0062] The sense transistor section 170 has a sense gate trench section 140 and a sense dummy trench section 130. In this example, the sense gate trench section 140 and the sense dummy trench section 130 extend in the Y-axis direction.

[0063] In this example, the main gate wiring 48 and the sense gate wiring 148 have a laminated structure of metal and polysilicon. An insulating film may be provided between the metal wiring and the polysilicon wiring. The metal wiring and the polysilicon wiring may be electrically connected via contact holes provided in the insulating film. In this specification, the polysilicon of the main gate wiring 48 is referred to as a second polysilicon layer 48-1. Furthermore, the polysilicon of the sense gate wiring 148 is referred to as a third polysilicon layer 148-1. In FIG. 3A, the second polysilicon layer 48-1 and the third polysilicon layer 148-1 are hatched. However, at least a portion of the main gate wiring 48 and the sense gate wiring 148 may have a laminated structure, and the entire wiring does not have to have a laminated structure.

[0064] The second polysilicon layer 48-1 is provided along the main transistor section 70, the sense pad 114, and the auxiliary emitter pad 115 in top view. The main gate wiring 48 is provided so as to surround the sense transistor section 170 and the sense gate wiring 148. An interlayer insulating film (not shown) is formed between the second polysilicon layer 48-1 and the metal of the main gate wiring 48. A contact hole 64 is formed in the interlayer insulating film, and the metal of the main gate wiring 48 and the second polysilicon layer 48-1 are connected via the contact hole 64. However, the contact hole 64 shown in FIG. 3A may actually include a plurality of through holes.

[0065] In top view, the third polysilicon layer 148-1 is provided in the shape of a closed loop surrounding the sense transistor portion 170. An interlayer insulating film (not shown) is also formed between the third polysilicon layer 148-1 and the metal of the sense gate wiring 148. A contact hole 64 is formed in the interlayer insulating film, and the metal of the sense gate wiring 148 and the third polysilicon layer 148-1 are connected via the contact hole 64.

[0066] The third polysilicon layer 148-1 and the sense gate trench portion 140 have an overlapping portion in top view, and the third polysilicon layer 148-1 and the sense gate conductive portion of the sense gate trench portion 140 are connected in this portion. The third polysilicon layer 148-1 does not need to be connected to the sense dummy conductive portion of the sense dummy trench portion 130. The sense dummy conductive portion of the sense dummy trench portion 130 may be connected to the sense emitter electrode.

[0067] The gate wiring connection portion 50 connects the third polysilicon layer 148-1 and the second polysilicon layer 48-1. A gate signal is transmitted from the main gate wiring 48 to the sense gate wiring 148 via the gate wiring connection portion 50. The gate wiring connection portion 50 is provided with a resistor portion 59. The resistor portion 59 is a portion having a higher resistance per unit length in the direction in which current flows through the resistor portion 59 than the main gate wiring 48 or the sense gate wiring 148 connected to the resistor portion 59. Current flows in the resistor portion 59 in the connection direction (e.g., the X-axis direction) connecting the main gate wiring 48 and the sense gate wiring 148. The resistance per unit length of the resistor portion 59 in the connection direction is higher than the resistance per unit length of the portion of the main gate wiring 48 connected to the resistor portion 59 in that connection direction, and is also higher than the resistance per unit length of the portion of the sense gate wiring 148 connected to the resistor portion 59 in that connection direction. The resistance value per unit length of the resistor portion 59 may be at least two times, at least five times, or at least ten times the resistance value per unit length of the main gate wiring 48 or the sense gate wiring 148. If the resistance value is higher in the area where the gate wiring connection portion 50 is provided than if a wiring similar to the main gate wiring 48 or the sense gate wiring 148 were extended as the gate wiring connection portion 50, the resistor portion 59 may be considered to be provided in the gate wiring connection portion 50. The resistor portion 59 is formed of polysilicon, for example. The portions of the main gate wiring 48 and the sense gate wiring 148 connected to the resistor portion 59 are, for example, stacked wiring of polysilicon and metal. In FIG. 3A , the polysilicon of the resistor portion 59 is also hatched.

[0068] The gate wiring connection portion 50 has the resistor portion 59, which makes it possible to suppress the above-mentioned parallel oscillation. Therefore, it is possible to suppress oscillation of the gate voltage of the sense transistor portion 170. The structure of the gate wiring connection portion 50 will be described later. The third polysilicon layer 148-1 and the second polysilicon layer 48-1 are not connected at any point other than the gate wiring connection portion 50. As an example, the length of the gate wiring connection portion 50 in the Y-axis direction is 100 μm or more and 300 μm or less, and the length in the X-axis direction is 100 μm or more and 150 μm or less.

[0069] In this example, a contact hole 64 is provided on the positive side of the gate wiring connection portion 50 along the X axis, connecting the main gate wiring 48 and the gate wiring connection portion 50. In addition, a contact hole 64 is provided on the negative side of the gate wiring connection portion 50 along the X axis, connecting the sense gate wiring 148 and the gate wiring connection portion 50. In this example, the contact hole 64 on the negative side of the gate wiring connection portion 50 along the X axis, and the contact hole 64 provided on the positive side of the sense transistor portion 170 along the Y axis and the contact hole 64 provided on the negative side of the Y axis are each separate, but these may also be provided continuously to surround the sense transistor portion 170 in a U-shape.

[0070] The sense gate trench portion 140 in this example extends in the extension direction (Y-axis direction). The sense gate wiring 148 in this example is connected to both ends of the sense gate trench portion 140 in the extension direction. The gate wiring connection portion 50 in this example is provided at a position overlapping the sense transistor portion 170 in a direction perpendicular to the extension direction (X-axis direction) in a top view. Therefore, the difference in wiring length of the sense gate wiring 148 from the gate wiring connection portion 50 to the connection portion with each sense gate trench portion 140 is small. This makes it possible to suppress gate delay (variation in switching speed) of the sense gate trench portion 140. The gate wiring connection portion 50 may be provided at a position overlapping the center of the sense transistor portion 170 in the extension direction in a direction perpendicular to the extension direction.

[0071] The sense transistor section 170 in this example is disposed adjacent to the sense pad 114 in the X-axis direction. The gate wiring connection section 50 in this example is provided on the opposite side of the sense transistor section 170 from the sense pad 114. This arrangement also makes it possible to suppress gate delay (variation in switching speed) of the sense gate trench section 140. The sense pad 114 and the gate wiring connection section 50 may be disposed so as to sandwich the sense transistor section 170 in a direction perpendicular to the extension direction in a top view.

[0072] Fig. 3B is an enlarged view of region A in Fig. 2. Fig. 3B shows the metal of the main gate wiring 48 (sometimes referred to as the second metal layer 48-2), the metal of the sense gate wiring 148 (sometimes referred to as the third metal layer 148-2), the main emitter electrode 52, the sense emitter electrode 152, and the auxiliary emitter pad 115.

[0073] As described above, the second polysilicon layer 48-1 and the second metal layer 48-2 are stacked and connected via the contact hole 64 extending in the direction of current flow. The same is true for the third polysilicon layer 148-1 and the third metal layer 148-2.

[0074] The third metal layer 148-2 is provided along three sides of the sense transistor section 170. A sense emitter electrode 152 is provided on the other side of the sense transistor section 170. Therefore, the third metal layer 148-2 does not surround the sense transistor section 170.

[0075] The sense emitter electrode 152 extends in the negative direction of the X-axis from above the sense transistor portion 170 to the sense pad 114. Therefore, the current flowing through the sense transistor portion 170 is output to the sense pad 114. The direction in which the sense emitter electrode 152 extends from the sense transistor portion 170 to the sense pad 114 may be perpendicular to the extension direction (Y-axis direction) of the sense gate trench portion 140 (see FIG. 3A ). Furthermore, in this example, the sense emitter electrode 152 also extends in the Y-axis direction between the main emitter electrode 52 and the third metal layer 148-2 and between the third metal layer 148-2 and the second metal layer 48-2.

[0076] Fig. 3C is an enlarged view of region A in Fig. 2. In Fig. 3C, the main well region 29 and the sense well region 129 are shown in addition to the sense transistor section 170 and the gate wiring connection section 50.

[0077] The main well region 29 surrounds the active portion 120. 3C shows a band portion of the main well region 29 surrounding the active portion 120. The main gate wiring 48, the sense pad 114, and the auxiliary emitter pad 115 are arranged to overlap the main well region 29 in a top view. In the main transistor portion 70, the end of the main gate trench portion extending in the Y-axis direction may overlap the main well region 29.

[0078] The sense well region 129 surrounds the sense transistor portion 170 in a top view. The sense well region 129 is a second conductivity type region formed inward from the upper surface of the semiconductor substrate 10. The doping concentrations of the main well region 29 and the sense well region 129 may be the same or different. By providing the sense well region 129, holes that have trickled from the main transistor portion 70 to the sense transistor portion 170 can be extracted, thereby suppressing the accumulation of holes in the sense transistor portion 170. At least a portion of the sense well region 129 may face the main transistor portion 70.

[0079] The sense gate wiring 148 is arranged to overlap the sense well region 129 in top view. An end of the sense gate trench portion 140 may overlap the sense well region 129. The sense well region 129 and the main well region 29 are separated. In this example, the sense well region 129 is surrounded by the main well region 29. Furthermore, the gate wiring connection portion 50 may be provided from a position overlapping with the main well region 29 to a position overlapping with the sense well region 129 in top view.

[0080] 4 is a diagram showing an example of the B-B' cross section in FIG. 3A. The B-B' cross section is an XZ cross section passing through the emitter region 12, sense well region 129, and active main well region 29 of the sense transistor section 170. In the B-B' cross section, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, a sense emitter electrode 152, a sense gate wiring 148, a main gate wiring 48, and a gate wiring connection section 50. FIG. 4 shows only the configuration of the upper surface side of the semiconductor substrate 10.

[0081] The semiconductor substrate 10 has an upper surface 21. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and another insulating film. A contact hole 54 is provided in the interlayer insulating film 38.

[0082] The sense emitter electrode 152 is provided above the interlayer insulating film 38 in the sense transistor portion 170. The sense emitter electrode 152 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The sense emitter electrode 152 is made of a metal material such as aluminum.

[0083] The sense transistor portion 170 has a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is N-type, and the base region 14 is P-type.

[0084] The sense transistor portion 170 has a sense gate trench portion 140 and a sense dummy trench portion 130 provided inward from the upper surface 21 of the semiconductor substrate 10. The sense gate trench portions 140 and the sense dummy trench portions 130 in this example are arranged along the X-axis direction and have their longitudinal directions in the Y-axis direction. As shown in FIG. 3A , a plurality of sense gate trench portions 140 and a plurality of sense dummy trench portions 130 are provided.

[0085] The sense gate trench portion 140 has a trench, a sense gate insulating film 142, and a sense gate conductive portion 144. The sense gate insulating film 142 is provided to cover the inner wall of the trench. The sense gate insulating film 142 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench. The sense gate conductive portion 144 is provided inside the trench, more inward than the sense gate insulating film 142. In other words, the sense gate insulating film 142 insulates the sense gate conductive portion 144 from the semiconductor substrate 10. The sense gate conductive portion 144 is formed of a conductive material such as polysilicon.

[0086] The sense dummy trench portion 130 has a trench, a sense dummy insulating film 132, and a sense dummy conductive portion 134. The structure of the sense dummy trench portion 130 may be similar to that of the sense gate trench portion 140. However, while the sense gate conductive portion 144 is connected to the sense gate wiring 148, the sense dummy trench portion 130 does not have to be connected to the sense gate wiring 148. The sense dummy conductive portion 134 may be connected to the sense emitter electrode 152 in a cross section different from the B-B' cross section. In the B-B' cross section, the sense gate trench portion 140 and the sense dummy trench portion 130 are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.

[0087] The sense transistor section 170 has a mesa section 160, which is a region between the sense gate trench sections 140 or the sense dummy trench sections 130. In this example, the mesa section 160 is provided between each trench section in the X-axis direction and extends in the Y-axis direction. The mesa section 160 has an emitter region 12, a base region 14, and an accumulation region 16 provided from an upper surface 21 thereof.

[0088] The sense transistor portion 170 has an emitter region 12 of a first conductivity type provided on the upper surface 21. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the sense gate trench portion 140 and the sense dummy trench portion 130. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 160. The emitter region 12 has a higher doping concentration than the drift region 18. In this example, the emitter region 12 is of N+ type.

[0089] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 160. The sense gate conductive portion 144 may be provided to be longer than the base region 14 in the depth direction. When a predetermined gate voltage is applied to the sense gate conductive portion 144, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the sense gate trench portion 140. As a result, a current flows between the main emitter electrode 52 and the collector electrode in the main transistor portion 70.

[0090] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In this example, the semiconductor substrate 10 is provided with accumulation regions 16-1 and 16-2, but the number of accumulation regions 16 is not limited to two. The number, doping concentration, etc. of the accumulation regions 16 may be the same as those of the main transistor section 70. The same applies to the other regions.

[0091] The mesa portion 160 located at the end of the sense transistor portion 170 in the X-axis direction may not be provided with an emitter region 12 or an accumulation region 16. In the mesa portion 160, a P+ contact region 17 may be provided on the surface side of the base region 14. The emitter region 12 and accumulation region 16 may also not be provided in the region between the trench portion located at the end of the sense transistor portion 170 in the X-axis direction (the sense gate trench portion 140 in this example) and the sense well region 129. In this region, a P+ contact region 17 may be provided on the surface side of the base region 14 adjacent to the sense well region 129. For example, the P+ contact region 17 is provided in contact with the inner periphery of the sense well region 129 and surrounds the sense transistor portion 170. The P+ contact region 17 is connected to the sense emitter electrode 152 via a contact hole 54. This makes it easier to extract holes that have flowed into the sense well region 129.

[0092] A contact region of the second conductivity type may be provided in the sense transistor section 170 in a cross section different from the B-B' cross section. The contact region may be provided between the base region 14 and the upper surface 21. The contact region may be a P+ type region with a higher doping concentration than the base region 14. By providing the contact region in the sense transistor section 170, holes that have leaked in from the main transistor section 70 can be extracted via the contact region.

[0093] The main well region 29 and the sense well region 129 are formed from the upper surface 21 of the semiconductor substrate 10 in the depth direction. In this example, the main well region 29 and the sense well region 129 are P+ type. The main well region 29 and the sense well region 129 may be formed deeper than the sense gate trench portion 140 and the sense dummy trench portion 130. The sense well region 129 may be connected to the sense emitter electrode 152 via a contact hole 54. A base region 14 and a P+ contact region 17 may be formed between the main well region 29 and the sense well region 129.

[0094] An interlayer insulating film 39 is provided on the upper surface 21 above the main well region 29 and the sense well region 129. The interlayer insulating film 39 may be a native oxide film, or may be a sense gate insulating film 142 formed up to the upper surface 21 of the semiconductor substrate 10.

[0095] A second polysilicon layer 48-1 and a third polysilicon layer 148-1 are provided above the interlayer insulating film 39. A second metal layer 48-2 is provided above the second polysilicon layer 48-1 with the interlayer insulating film 38 interposed therebetween. The second polysilicon layer 48-1 and the second metal layer 48-2 are connected via a contact hole 64 formed in the interlayer insulating film 38. Similarly, a third metal layer 148-2 is provided above the third polysilicon layer 148-1 with the interlayer insulating film 38 interposed therebetween. The third polysilicon layer 148-1 and the third metal layer 148-2 are connected via the contact hole 64 formed in the interlayer insulating film 38.

[0096] A gate wiring connection portion 50 is provided between the main gate wiring 48 and the sense gate wiring 148. The gate wiring connection portion 50 connects the main gate wiring 48 and the sense gate wiring 148. The gate wiring connection portion 50 has a resistor portion 59. In this example, the resistor portion 59 includes polysilicon arranged above the upper surface 21 of the semiconductor substrate 10. In this specification, the polysilicon of the resistor portion 59 is referred to as a first polysilicon layer 61.

[0097] The first polysilicon layer 61 is formed above the interlayer insulating film 39. The first polysilicon layer 61 is connected to the second polysilicon layer 48-1. The first polysilicon layer 61 is also connected to the third polysilicon layer 148-1. That is, the first polysilicon layer 61 connects the second polysilicon layer 48-1 and the third polysilicon layer 148-1. In this example, the first polysilicon layer 61 is polysilicon provided from the end of the contact hole 64 connecting the second polysilicon layer 48-1 and the second metal layer 48-2 that is closest to the gate wiring connection portion 50 to the end of the contact hole 64 connecting the third polysilicon layer 148-1 and the third metal layer 148-2 that is closest to the gate wiring connection portion 50.

[0098] The main gate wiring 48 and the sense gate wiring 148 have a stacked structure, but in the gate wiring connection portion 50 of this example, the gate signal is transmitted by the first polysilicon layer 61. Therefore, the resistance value is higher than that of the main gate wiring 48 and the sense gate wiring 148. Therefore, the above-mentioned parallel oscillation can be suppressed, and oscillation of the gate voltage of the sense transistor portion 170 can be suppressed.

[0099] The first polysilicon layer 61 may be formed in the same process as the second polysilicon layer 48-1 and the third polysilicon layer 148-1. This allows the first polysilicon layer 61 to be formed without adding any additional manufacturing steps. The doping concentration of the first polysilicon layer 61 may be the same as the doping concentration of the second polysilicon layer 48-1 and the third polysilicon layer 148-1. The thickness of the first polysilicon layer 61 may be the same as the thickness of the second polysilicon layer 48-1 and the third polysilicon layer 148-1. The thickness of the first polysilicon layer 61 is, for example, not less than 0.5 μm and not more than 1.0 μm.

[0100] A first insulating film 37 is provided above the first polysilicon layer 61, and a metal layer 51 is provided via the first insulating film 37. Although not shown in FIG. 4 , polyimide is provided as a protective film above the sense emitter electrode 152, the metal layer 51, the main gate wiring 48, and the sense gate wiring 148.

[0101] If the metal layer 51 is not formed, the polyimide will come into contact with the first insulating film 37 above the first polysilicon layer 61. If the polyimide becomes charged in this state, charges will also be induced on the upper surface of the first polysilicon layer 61 across the first insulating film 37, causing a change in the resistance value of the first polysilicon layer 61. As will be described later, the resistance value of the resistor portion 59 affects the characteristics of the semiconductor device 100, so it is preferable to set it to a predetermined value. By providing the metal layer 51, the resistance value of the resistor portion 59 can be stabilized. Furthermore, atomic diffusion from the polyimide can be prevented.

[0102] The metal layer 51 may cover 50% or more, 80% or more, or 100% of the area of ​​the first polysilicon layer 61. However, when viewed from above, at least a portion of the first polysilicon layer 61 may not be covered by the metal layer 51. 30% or more, 50% or more, or 80% or more of the area of ​​the first polysilicon layer 61 may not be covered by the metal layer 51.

[0103] In this example, the metal layer 51 is insulated from the first polysilicon layer 61 by the first insulating film 37 at the gate wiring connection portion 50. In this specification, when an insulating film-interposed region in which the first insulating film 37 is provided between the metal layer 51 and the first polysilicon layer 61 exists, the metal layer 51 and the first polysilicon layer 61 are considered to be insulated from each other in the insulating film-interposed region, even if the metal layer 51 and the first polysilicon layer 61 are connected in other regions. A region in which the first insulating film 37 is provided between the metal layer 51 and the first polysilicon layer 61 and in which no contact hole is provided in the first insulating film 37 is an insulating film-interposed region. A region in which the contact hole provided in the first insulating film 37 extends in the Y-axis direction does not need to be treated as an insulating film-interposed region. The insulating film-interposed region may refer to a portion of the metal layer 51 through which no gate current flows and which does not function as wiring.

[0104] In another example, a contact hole may be formed in the first insulating film 37, connecting the metal layer 51 and the first polysilicon layer 61. Even in this case, an insulating film-mediated region in which the metal layer 51 and the first polysilicon layer 61 are insulated from each other may be provided over a range of 50% or more of the length of the gate wiring connection portion 50 in the X-axis direction. In this case, the insulating film-mediated region may be a region from the end of the contact hole provided in the first insulating film 37 that is closest to the second metal layer 48-2 to the end of the metal layer 51 that is closest to the second metal layer 48-2.

[0105] The metal layer 51 may be connected to either the main gate wiring 48 or the sense gate wiring 148. In this example, the metal layer 51 is connected to the third metal layer 148-2 of the sense gate wiring 148. The metal layer 51 may be a portion of the second metal layer 48-2 or the third metal layer 148-2 that extends above the gate wiring connection portion 50. However, the metal layer 51 does not have to be connected to either the main gate wiring 48 or the sense gate wiring 148. In the example of FIG. 4, the metal layer 51 is provided by extending from the third metal layer 148-2 in the direction of the second metal layer 48-2. The metal layer 51 is not connected to either the second metal layer 48-2 or the third metal layer 148-2, and may be floating in terms of potential.

[0106] 5A, 5B, and 5C are diagrams showing the results of a gate voltage simulation. In Figures 5A, 5B, and 5C, the changes in the gate voltage of the main transistor section 70 and the sense transistor section 170 from when the semiconductor device 100 is turned on to when it is turned off are simulated. In each diagram, the horizontal axis represents time, and the vertical axis represents voltage.

[0107] 5A shows the simulation results when the resistance value of the gate wiring connection portion 50 is 0.3 Ω. In this example, it is assumed that the gate wiring connection portion 50 does not have the resistance portion 59, and the main gate wiring 48 or the sense gate wiring 148 is used as the gate wiring connection portion 50. In this case, oscillation of the gate voltage of the sense transistor portion 170 was confirmed after a certain period of time had elapsed since the semiconductor device 100 was turned on.

[0108] 5B shows the simulation results when the resistance value of the gate wiring connection portion 50 is 5.0Ω. This example assumes that the gate wiring connection portion 50 has a resistor portion 59. In this case, oscillation of the gate voltage of the sense transistor portion 170 was also confirmed. However, the amplitude of the gate voltage is smaller than in the case of FIG. 5A. Furthermore, the time during which the gate voltage oscillates is shorter than in the case of FIG. 5A. This is thought to be due to the presence of the resistor portion 59 in the gate wiring connection portion 50.

[0109] 5C shows the simulation results when the resistance value of the gate wiring connection portion 50 is 10.0 Ω. This example assumes that the resistance value of the gate wiring connection portion 50 is further increased. In this case, oscillation of the gate voltage was not confirmed. In other words, it was confirmed that oscillation of the gate voltage is suppressed by increasing the resistance value of the gate wiring connection portion 50.

[0110] However, if the resistance value of the gate wiring connection part 50 is made too large, the gate signal of the sense transistor part 170 will lag behind the gate signal of the main transistor part 70. In particular, if the gate signal of the sense transistor part 170 is delayed at turn-off, current will concentrate in the sense transistor part 170, which may destroy the sense transistor part 170. Therefore, it is desirable to adjust the resistance value of the gate wiring connection part 50 to an appropriate value.

[0111] Fig. 6 is a diagram showing another example of the cross section taken along line BB' in Fig. 3A. The first polysilicon layer 61 in this example has a different thickness from the first polysilicon layer 61 shown in Fig. 4. The other configurations are the same as those shown in Fig. 4, so a description thereof will be omitted.

[0112] The first polysilicon layer 61 in this example has a thickness different from that of the second polysilicon layer 48-1. The first polysilicon layer 61 in this example has a stacked structure of an upper polysilicon layer 63 and a lower polysilicon layer 62. The thickness t1 of the first polysilicon layer 61 in this example is greater than the thickness t2 of the second polysilicon layer 48-1. The resistance value of the gate wiring connection portion 50 can be adjusted by adjusting the thickness t1 of the first polysilicon layer 61. The thickness t1 may be two or more times the thickness t2. The thickness of the polysilicon layer may be an average value or a maximum value.

[0113] However, thickness t1 may be smaller than thickness t2. In that case, the first polysilicon layer 61 does not need to have a stacked structure of the upper polysilicon layer 63 and the lower polysilicon layer 62. For example, thickness t1 can be reduced by etching the first polysilicon layer 61. Thickness t1 may be equal to or smaller than twice thickness t2.

[0114] In this example, the upper polysilicon layer 63 covers the entire lower polysilicon layer 62. The upper polysilicon layer 63 may be formed in the same process as the polysilicon of the temperature sense wiring 112 (see FIG. 2) described above. The lower polysilicon layer 62 may be formed in the same process as the second polysilicon layer 48-1. This allows the upper polysilicon layer 63 and the lower polysilicon layer 62 to be formed without adding any additional manufacturing steps.

[0115] The upper polysilicon layer 63 may have the same thickness and doping concentration as the temperature sense wiring 112. The lower polysilicon layer 62 may have the same thickness and doping concentration as the second polysilicon layer 48-1. The upper polysilicon layer 63 and the lower polysilicon layer 62 may have different thicknesses and doping concentrations. The example shown in FIG. 6 may be combined with any other modified example other than the modified example shown in FIG.

[0116] FIG. 7 is a diagram showing another example of the cross section B-B' in FIG. 3A. Similar to FIG. 6, the first polysilicon layer 61 in this example also has a stacked structure of an upper polysilicon layer 63 and a lower polysilicon layer 62. However, the upper polysilicon layer 63 in this example is not provided on a portion of the upper surface of the lower polysilicon layer 62. The upper polysilicon layer 63 in this example can be formed by partially etching the upper polysilicon layer 63. This etching may be performed in the same process as etching the temperature sense wiring 112. This configuration also allows the resistance value of the gate wiring connection portion 50 to be adjusted. The upper polysilicon layer 63 may be provided in a range of 20% to 40% of the upper surface of the lower polysilicon layer 62, in a range of 40% to 60%, or in a range of 60% to 80%. The example shown in FIG. 7 may be combined with any other modification other than the modification shown in FIG. 6.

[0117] 8 is a diagram showing another example of the cross section taken along the line BB' in FIG. 3A. In this example, regions with different doping concentrations are formed in the first polysilicon layer 61. The other configuration is the same as that shown in FIG. 4, so a description thereof will be omitted.

[0118] The first polysilicon layer 61 of this example has a high-concentration region 66 having a predetermined concentration of dopant and a low-concentration region 65 having a lower dopant concentration than the high-concentration region 66. A dopant of the first conductivity type may be implanted into the high-concentration region 66. The low-concentration region 65 may be a region that remains without being implanted with dopant. This configuration also makes it possible to adjust the resistance value of the gate wiring connection portion 50. The example shown in FIG. 8 may be combined with any of the other modified examples.

[0119] 9 is a diagram showing an example of the configuration of the gate wiring connection portion 50 in a top view. Fig. 9 shows the positions of the gate wiring connection portion 50, the second polysilicon layer 48-1, the third polysilicon layer 148-1, and the sense transistor portion 170 in a top view.

[0120] The gate wiring connection portion 50 of this example also has a first polysilicon layer 61 and a metal layer 51. However, the gate wiring connection portion 50 of this example has a bellows-like structure that is folded back multiple times from the connection point with the second polysilicon layer 48-1 to the connection point with the third polysilicon layer 148-1. This configuration also makes it possible to adjust the resistance value of the gate wiring connection portion 50.

[0121] 10 is a diagram showing an example of the DD' cross section of FIG. 9. In the DD' cross section, the gate wiring connection portion 50 has a first polysilicon layer 61 and a metal layer 51. In this example, the metal layer 51 is connected to the first polysilicon layer 61 via a contact hole provided in the first insulating film 37. The metal layer 51 corresponds to the peaks or valleys of the bellows, and the first polysilicon layer 61 is connected to the first polysilicon layer 61 in another cross section via the metal layer 51.

[0122] In the gate wiring connection portion 50, the region above the first insulating film 37 is defined as an adjustment portion 53. One of the two metal layers 51 in the DD' cross section may extend to the adjustment portion 53 and connect to the other metal layer 51. In this case, the resistance value of the gate wiring connection portion 50 in the DD' cross section is lowered, and the overall resistance value of the gate wiring connection portion 50 is also lowered. Furthermore, the metal layer 51 may be formed from polysilicon. With such a configuration, the resistance value of the gate wiring connection portion 50 can be adjusted.

[0123] 11 is a diagram showing an example of a CC' cross section of Fig. 3A. The CC' cross section is a cross section that crosses the Y-axis direction from the sense gate wiring 148 to the main gate wiring 48. In the CC' cross section, a sense well region 129 and a main well region 29 are provided in the semiconductor substrate 10.

[0124] A second polysilicon layer 48-1 and a third polysilicon layer 148-1 are provided above the upper surface 21 of the semiconductor substrate 10 via an interlayer insulating film 39. A second metal layer 48-2 is provided above the second polysilicon layer 48-1 via an interlayer insulating film 38, and the second polysilicon layer 48-1 and the second metal layer 48-2 are connected by a contact hole 64 in the interlayer insulating film 38. The same is true for the third polysilicon layer 148-1 and the third metal layer 148-2.

[0125] A sense emitter electrode 152 extends between the second metal layer 48-2 and the third metal layer 148-2. In the CC' cross section, the sense emitter electrode 152 is insulated from the second polysilicon layer 48-1 and the third polysilicon layer 148-1 by the interlayer insulating film .

[0126] 12 is a diagram showing an example of the AA' cross section in FIG. 2. The AA' cross section is an XZ cross section passing through the emitter region 12 of the main transistor section 70 and the diode section 80. In the AA' cross section, the semiconductor device 100 includes a semiconductor substrate 10, a collector electrode 24, an interlayer insulating film 38, and a main emitter electrode 52. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor substrate 10. Hereinafter, descriptions of the same configuration as the sense transistor section 170 described in FIG. 4 and the like will be omitted as appropriate.

[0127] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The main emitter electrode 52 is provided above the interlayer insulating film 38. The main emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The main emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0128] The main transistor section 70 and the diode section 80 have a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is N-type, and the base region 14 is P-type.

[0129] The main transistor section 70 includes multiple main gate trench sections 40 and multiple main dummy trench sections 30 extending inward from the upper surface 21 of the semiconductor substrate 10. In this example, the main gate trench sections 40 and the main dummy trench sections 30 are arranged along the X-axis direction and extend longitudinally in the Y-axis direction. The main gate trench section 40 includes a trench, a main gate insulating film 42, and a main gate conductive section 44. The main gate insulating film 42 covers the inner wall of the trench. The main gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench. The main gate conductive section 44 is located inside the trench, closer to the main gate insulating film 42. In other words, the main gate insulating film 42 insulates the main gate conductive section 44 from the semiconductor substrate 10. The main gate conductive section 44 is formed of a conductive material such as polysilicon.

[0130] The main dummy trench portion 30 has a trench, a main dummy insulating film 32, and a main dummy conductive portion 34. The structure of the main dummy trench portion 30 may be similar to that of the main gate trench portion 40. However, although the main gate conductive portion 44 is connected to the main gate wiring 48, the main dummy trench portion 30 does not have to be connected to the main gate wiring 48. The main dummy conductive portion 34 may be connected to the main emitter electrode 52 in a cross section different from the A-A' cross section. The diode portion 80 also has multiple main dummy trench portions 30.

[0131] The main transistor section 70 has a mesa section 60 which is a region between the main gate trench sections 40 or the main dummy trench sections 30. Similarly, the diode section 80 has a mesa section 72 which is a region between the main dummy trench sections 30. A base region 14 is provided in each mesa section.

[0132] The main transistor section 70 has a first conductivity type emitter region 12 provided on the upper surface 21. The emitter region 12 is exposed at the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the main gate trench section 40 or the main dummy trench section 30. The emitter region 12 may be in contact with the main gate trench section 40 or the main dummy trench section 30 on both sides of the mesa section 60.

[0133] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the main gate trench portion 40 or the main dummy trench portion 30 on both sides of the mesa portion 60.

[0134] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0135] A P-type base region 14 is provided in the mesa portion 72 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. No emitter region 12 is provided in the mesa portion 72 of the diode portion 80.

[0136] The main transistor section 70 has a collector region 22 of the second conductivity type provided on the lower surface 23 of the semiconductor substrate 10. In this example, the collector region 22 is of P+ type. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0137] The diode section 80 has a cathode region 82 of a first conductivity type provided on the lower surface 23 of the semiconductor substrate 10. In this example, the cathode region 82 is N+ type. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples.

[0138] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.

[0139] The main transistor section 70 may be a region in which a collector region 22 is provided on the lower surface 23. The diode section 80 may be a region in which a cathode region 82 is provided on the lower surface 23. The boundary between the main transistor section 70 and the diode section 80 may be the boundary between the cathode region 82 and the collector region 22.

[0140] An N+ type buffer region 20 may be provided between the drift region 18 and the collector region 22 and the cathode region 82. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22.

[0141] In a cross section different from the A-A' cross section, a second conductivity type contact region may be provided in the main transistor section 70 and the diode section 80. The contact region may be provided between the base region 14 and the upper surface 21. The contact region may be a P+ type region having a higher doping concentration than the base region 14.

[0142] The main gate trench portion 40 and the main dummy trench portion 30 extend from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14 and reaching the drift region 18. In regions where at least one of the emitter region 12, the contact region, and the accumulation region 16 is provided, the main gate trench portion 40 and the main dummy trench portion 30 also penetrate these doped regions and reach the drift region 18. The trench portion penetrating the doped region does not necessarily mean that the trench portion is formed after the doped region is formed. Forming the doped region between the trench portions after the trench portions is also included in the trench portion penetrating the doped region. The bottom of the trench portion may have a downwardly convex curved shape (curved in cross section).

[0143] The main gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The main gate trench portion 40 is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The main gate conductive portion 44 is electrically connected to a main gate wiring 48. When a predetermined gate voltage is applied to the main gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the main gate trench portion 40. As a result, a main current flows between the main emitter electrode 52 and the collector electrode 24 in the main transistor portion 70.

[0144] Fig. 13 is a diagram showing another example of region A in Fig. 2. Fig. 13 shows the arrangement of the main gate trench portion 40 and the main dummy trench portion 30 of the main transistor portion 70, and the arrangement of the sense gate trench portion 140 and the sense dummy trench portion 130 of the sense transistor portion 170.

[0145] A plurality of main gate trench portions 40, main dummy trench portions 30, sense gate trench portions 140, and sense dummy trench portions 130 are provided. Each trench portion may extend in the same direction. In this example, each trench portion extends in the Y-axis direction and is aligned in the X-axis direction. Also, in FIG. 13, the second polysilicon layer 48-1 and the third polysilicon layer 148-1 are not hatched. Furthermore, the contact holes 64 on the positive and negative sides of the Y-axis direction of the sense transistor portion 170 are omitted.

[0146] In a top view, the density of the sense gate trench portions 140 may be greater than the density of the main gate trench portions 40. This density is the number of trench portions per unit area. In this case, the number of straight line portions of each trench portion may be counted even if the ends of the straight line portions are connected. This increases the gate-emitter capacitance of the sense transistor portion 170, making it possible to suppress oscillation of the gate voltage of the sense transistor portion 170.

[0147] The spacing D1 between the multiple sense gate trench portions 140 may be smaller than the spacing D2 between the multiple main gate trench portions 40. This increases the density of the sense gate trench portions 140 and increases the gate-emitter capacitance of the sense transistor portion 170, making it possible to suppress oscillation of the gate voltage. A sense dummy trench portion 130 may be provided between the multiple sense gate trench portions 140, and a main dummy trench portion 30 may be provided between the multiple main gate trench portions 40. The spacing D1 may be equal to or less than half the spacing D2. The example shown in FIG. 13 may be combined with any of the other modified examples.

[0148] Fig. 14 is a diagram showing another example of region A in Fig. 2. In Fig. 14, the arrangement of the sense gate trench portion 140 and the sense dummy trench portion 130 of the sense transistor portion 170 is different from the example shown in Fig. 13 .

[0149] The ratio R1 of the number of sense gate trenches 140 to the number of sense dummy trenches 130 in the sense transistor section 170 may be greater than the ratio R2 of the number of main gate trenches 40 to the number of main dummy trenches 30 in the main transistor section 70. In this example, the ratio R1 is 1, while the ratio R2 is 0.5. This also increases the density of the sense gate trenches 140 and the gate-emitter capacitance of the sense transistor section 170, thereby suppressing gate voltage oscillation. The ratio R1 may be two or more times, three or more times, or four or more times the ratio R2. The example shown in FIG. 14 may be combined with any of the other modified examples.

[0150] In any example, the semiconductor device 100 has a short-circuit current density of 5000 A / cm when the rated voltage is applied. ２ or more. Furthermore, the width W1 of the mesa portion 160 of the sense transistor portion 170 (see FIG. 4) and the width W3 of the mesa portion 60 of the main transistor portion 70 (see FIG. 12) may be 1 μm or less. Furthermore, the cell pitch W2 of the sense transistor portion 170 (see FIG. 4) and the cell pitch W4 of the main transistor portion 70 (see FIG. 12) may be 1 μm or more and 3 μm or less. As the performance of the semiconductor device 100 improves, gate voltage oscillation becomes more likely to occur, so it is desirable to suppress this oscillation.

[0151] 15 is a diagram showing another example of the cross section taken along line AA' in FIG. 2. In this example, a trench bottom region 26 of the second conductivity type is provided at the bottom of the main gate trench portion 40. In this example, the trench bottom region 26 is of P+ type. By providing the trench bottom region 26, on-loss can be reduced. A drift region 18 may be present between the trench bottom region 26 and the base region 14 or the accumulation region 16. The trench bottom region 26 may be provided at the bottom of the main dummy trench portion 30, or may be provided across the bottoms of multiple trench portions.

[0152] FIG. 16 is a diagram showing another example of the cross section B-B' in FIG. 3A. In this example, a trench bottom region 26 of the second conductivity type is provided at the bottom of the sense gate trench portion 140. From the perspective of current detection, it is desirable that the main transistor portion 70 and the sense transistor portion 170 have the same configuration. Therefore, if the main transistor portion 70 has a trench bottom region 26, it is desirable that the sense transistor portion 170 also has a trench bottom region 26. However, in this case, the voltage dependency of the gate-emitter capacitance of the sense transistor portion 170 changes, making oscillation more likely to occur. Therefore, it is desirable to suppress oscillation using the above-mentioned configuration.

[0153] A drift region 18 may be present between the trench bottom region 26 and the base region 14 or the accumulation region 16. The trench bottom region 26 may be provided at the bottom of the sense dummy trench portion 130, or may be provided across the bottoms of multiple trench portions. The trench bottom region 26 of the sense transistor portion 170 and the trench bottom region 26 of the main transistor portion 70 may have the same doping concentration and may be formed in the same process. However, the trench bottom region 26 may be provided in either the main transistor portion 70 or the sense transistor portion 170.

[0154] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0155] 10: Semiconductor substrate, 12: Emitter region, 14: Base region, 16: Accumulation region, 17: P+ contact region, 18: Drift region, 20: Buffer region, 21: Upper surface, 22: Collector region, 23: Lower surface, 24: Collector electrode, 29: Main well region, 30: Main dummy trench portion, 32: Main dummy insulating film, 34: Main dummy conductive portion, 37: First insulating film, 38: Interlayer insulating film, 39: Interlayer insulating film, 40 . . . Main gate trench portion, 42: Main gate insulating film, 44: Main gate conductive portion, 48: Main gate wiring, 48-1: Second polysilicon layer, 48-2: Second metal layer, 50: Gate wiring connection portion, 51: Metal layer, 52: Main emitter electrode, 53: Adjustment portion, 54: Contact hole, 59: Resistor portion, 60: Mesa portion, 61: First polysilicon layer, 62: Lower polysilicon layer, 63: Upper polysilicon layer, 64: Contact hole Contact hole, 65...low concentration region, 66...high concentration region, 70...main transistor portion, 72...mesa portion, 80...diode portion, 82...cathode region, 90...edge termination structure portion, 100...semiconductor device, 111...temperature sensing portion, 112...temperature sensing wiring, 114...sense pad, 115...auxiliary emitter pad, 116...gate pad, 117...cathode pad, 118...anode pad, 120...active portion, 129...sensor Response region, 130: sense dummy trench portion, 132: sense dummy insulating film, 134: sense dummy conductive portion, 138: outer peripheral edge, 139: first edge, 140: sense gate trench portion, 142: sense gate insulating film, 144: sense gate conductive portion, 148: sense gate wiring, 148-1: third polysilicon layer, 148-2: third metal layer, 152: sense emitter electrode, 160: mesa portion, 170: sense transistor portion

Claims

1. A semiconductor device comprising a semiconductor substrate having an upper surface, the semiconductor substrate comprising: a main transistor portion having a main gate trench portion including a main gate conductive portion; a sense transistor portion having a sense gate trench portion including a sense gate conductive portion; a gate pad provided above the upper surface of the semiconductor substrate; a main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion; a sense gate wiring arranged along the sense transistor portion; and a gate wiring connection portion connecting the main gate wiring and the sense gate wiring, wherein a resistor portion is provided in the gate wiring connection portion.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate further has a sense pad arranged adjacent to the sense transistor section, and the gate wiring connection section is provided on the opposite side of the sense pad with respect to the sense transistor section.

3. The semiconductor device according to claim 1, wherein the sense gate trench portion extends in an extension direction, and the gate wiring connection portion is provided at a position overlapping the sense transistor portion in a direction perpendicular to the extension direction in a top view.

4. The semiconductor device according to claim 1, wherein the resistor portion includes a first polysilicon layer disposed above the upper surface of the semiconductor substrate.

5. The semiconductor device according to claim 4, wherein the main gate wiring includes a second polysilicon layer disposed above the upper surface of the semiconductor substrate, and the first polysilicon layer is connected to the second polysilicon layer.

6. The semiconductor device according to claim 4, wherein a metal layer is provided above the first polysilicon layer via an insulating film.

7. The semiconductor device according to claim 6, wherein at least a portion of said first polysilicon layer is not covered with said metal layer when viewed from above.

8. The semiconductor device according to claim 4, wherein the main gate wiring includes a second polysilicon layer disposed above the upper surface of the semiconductor substrate, and the first polysilicon layer has a thickness different from that of the second polysilicon layer.

9. The semiconductor device according to claim 8, wherein the first polysilicon layer has a stacked structure of an upper polysilicon layer and a lower polysilicon layer, and the thickness of the first polysilicon layer is greater than the thickness of the second polysilicon layer.

10. The semiconductor device according to claim 9, wherein the upper polysilicon layer is not provided on a portion of the upper surface of the lower polysilicon layer.

11. The semiconductor device according to claim 1, wherein, in a top view, the density occupied by the sense gate trench portion is greater than the density occupied by the main gate trench portion.

12. The semiconductor device according to claim 11, wherein a plurality of the main gate trench portions and a plurality of the sense gate trench portions are provided, and the spacing between the plurality of the sense gate trench portions is smaller than the spacing between the plurality of the main gate trench portions.

13. The semiconductor device according to claim 11, wherein a plurality of the main gate trench portions are provided, the main transistor portion has a plurality of main dummy trench portions, a plurality of the sense gate trench portions are provided, the sense transistor portion has a plurality of sense dummy trench portions, and the ratio of the number of the sense gate trench portions to the number of the sense dummy trench portions in the sense transistor portion is greater than the ratio of the number of the main gate trench portions to the number of the main dummy trench portions in the main transistor portion.

14. The short circuit current density when the rated voltage is applied is 5000 A / cm ２ The semiconductor device according to claim 1 .

15. The semiconductor device according to claim 1, wherein the sense gate wiring is arranged in a closed loop surrounding the sense transistor section.

16. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor substrate is provided with a drift region of a first conductivity type, and a trench bottom region of a second conductivity type is provided at the bottom of the sense gate trench portion.

17. The semiconductor device according to claim 16, wherein the trench bottom region of the second conductivity type is provided at the bottom of the main gate trench portion.

18. A semiconductor device comprising a semiconductor substrate having an upper surface, the semiconductor substrate having: a drift region of a first conductivity type; a main transistor portion having a main gate trench portion including a main gate conductive portion; a sense transistor portion having a sense gate trench portion including a sense gate conductive portion; a gate pad provided above the upper surface of the semiconductor substrate; main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion; and a gate wiring connection portion connecting the main gate wiring and the sense gate conductive portion, wherein a resistor portion is provided in the gate wiring connection portion; and a trench bottom region of a second conductivity type is provided at the bottom of the sense gate trench portion.

19. The semiconductor device according to claim 18, wherein the trench bottom region of the second conductivity type is provided at the bottom of the main gate trench portion.

20. The semiconductor device according to claim 18, further comprising a sense gate wiring arranged along the sense transistor section and connected to the sense gate conductive section, wherein the gate wiring connection section connects the main gate wiring and the sense gate wiring.

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