Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention reduces switching loss. This semiconductor device comprises a semiconductor substrate, a lower electrode, and an upper electrode. The semiconductor substrate is provided with an IGBT region, an FWD region, and a boundary region disposed between the IGBT region and the FWD region. The semiconductor substrate is provided with a first conductivity-type Schottky region disposed in a portion of a surface layer part of a base layer in the FWD region. A concentration distribution curve of a first conductivity-type impurity in the depth direction of the Schottky region has a first peak height, and the integral value of the concentration distribution curve has a first surface density. A concentration distribution curve of a second conductivity-type impurity in the depth direction of the base layer disposed below the Schottky region has a second peak height, and the integral value of the concentration distribution curve has a second surface density. The second peak height is lower than the first peak height. The second surface density is 0.6 times or more the first surface density.

Description

Semiconductor device and method for manufacturing the same

[0001] (Cross-reference to related applications) This application is a related application of Japanese Patent Application No. 2024-072884 filed on April 26, 2024, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a semiconductor device having an insulated gate field effect transistor (hereinafter referred to as an IGBT (abbreviation for Insulated Gate Bipolar Transistor)) region in which an IGBT element is formed, and a free wheeling diode (hereinafter referred to as an FWD (abbreviation for Free Wheeling Diode)) region in which an FWD element is formed, and a method for manufacturing the semiconductor device.

[0003] Conventionally, semiconductor devices have been proposed that have an RC-IGBT (abbreviation for Reverse-Conducting IGBT) structure in which an IGBT element and an FWD element are mounted on a single chip, for example, as switching elements for inverters and the like. Japanese Patent Application Laid-Open Publication No. 2021-34726 also discloses a technique in which an N-type Schottky region is disposed on a portion of the surface of a P-type anode layer in an FWD element. Because the Schottky region is in Schottky contact with the anode electrode, it is possible to reduce the accumulation of minority carriers. Because hole injection can be reduced, it is possible to reduce reverse recovery current and switching loss.

[0004] In an FWD device with a Schottky region, it is necessary to appropriately adjust the relationship between the doping concentration of P-type impurities in the anode layer and the doping concentration of N-type impurities in the Schottky region. This is to prevent a parasitic bipolar transistor formed by the Schottky region from turning on and causing recovery breakdown. Therefore, in the past, the peak concentration of P-type impurities in the anode layer had to be higher than the peak concentration of N-type impurities in the Schottky region. To increase the peak concentration of P-type impurities, the injection amount of P-type impurities was increased, which raised the P-type impurity concentration of the entire anode layer. As a result, it became difficult to sufficiently suppress the injection amount of holes from the anode layer, resulting in a problem of difficulty in sufficiently reducing switching loss.

[0005] The semiconductor device (3) disclosed in this specification includes a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate. The semiconductor substrate includes a plurality of IGBT regions (1a) having IGBT elements, a plurality of FWD regions (1b) having FWD elements, and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions. The plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extend in a first direction (x) and are alternately arranged in a second direction (y) perpendicular to the first direction. A plurality of boundary regions (1c) are located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b). The semiconductor substrate includes a drift layer (11) of a first conductivity type (N), a base layer (12) of a second conductivity type (P) formed in a surface layer portion of the drift layer, a collector layer (22) of the second conductivity type formed on the side of the drift layer opposite to the base layer side in the IGBT region, a cathode layer (23) of the first conductivity type formed on the side of the drift layer opposite to the base layer side in the FWD region, and a gate insulating film (17) and a gate electrode (18) arranged in a plurality of trenches (14) formed in the IGBT region, with one direction as the longitudinal direction and formed deeper than the base layer to reach the drift layer. the first conductivity type impurity concentration distribution curve in the depth direction of the Schottky region has a first peak height (PKn), and an integral value of the concentration distribution curve has a first areal density (ADn).The concentration distribution curve of the second conductivity type impurity in the depth direction of the base layer disposed below the Schottky region has a second peak height (PKp), and the integral value of the concentration distribution curve has a second areal density (ADp). The second peak height is lower than the first peak height. The second areal density is 0.6 times or more the first areal density.

[0006] The present inventors focused on the mechanism of recovery breakdown in FWD devices with Schottky regions. Recovery breakdown occurs when the total number of carriers decreases, causing a decrease in the base current from the Schottky region to the base layer, which functions as an anode layer, preventing electrons from being discharged to the collector layer. Therefore, the present inventors discovered that the total number of carriers is important. The total number of carriers can be expressed as an areal density. The areal density is a value obtained by integrating the impurity concentration distribution curve in the depth direction. In other words, the areal density is a value indicating the total number of impurity ions per unit area when impurities are implanted from the top surface of a semiconductor substrate. The inventors then discovered that recovery breakdown occurs when the areal density (second areal density) of P-type impurities in the base layer, which functions as an anode layer, is less than 0.6 times the areal density (first areal density) of N-type impurities in the Schottky region. Therefore, if the condition that the second areal density is 0.6 times or more the first areal density is satisfied, the peak concentration of the P-type impurity in the base layer can be made lower than the peak concentration of the N-type impurity in the Schottky region. It is no longer necessary to unnecessarily increase the peak concentration of the P-type impurity in the base layer. Therefore, it is possible to appropriately reduce the integrated concentration of the P-type impurity in the base layer. Therefore, it is possible to further reduce the P-type impurity concentration in the base layer while preventing recovery breakdown, thereby reducing switching loss.

[0007] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0008] 1. A top view of the semiconductor device 3. An enlarged perspective view of the semiconductor substrate 10 in the region RII of FIG. 1. A cross-sectional view taken along line III-III of FIG. 2. A cross-sectional view taken along line IV-IV of FIG. 2. A graph of the concentration distribution curve of impurities in the conventional FWD region 1b. A graph of the concentration distribution curve of impurities in the FWD region 1b of the present embodiment. A graph of the first simulation result. A graph of the second simulation result. A flow chart showing the manufacturing process of the FWD region 1b and the boundary region 1c. An enlarged perspective view of the semiconductor substrate 10 according to Example 2. An enlarged perspective view of the semiconductor substrate 10 according to Example 3.

[0009] (Configuration of Semiconductor Device 3) Hereinafter, embodiments according to the technology of the present specification will be described with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be described by using the same reference numerals.

[0010] FIG. 1 shows a top view of the semiconductor device 3. FIG. 2 shows an enlarged perspective view of the semiconductor substrate 10 in region RII in FIG. 1. Note that the interlayer insulating film 19 and the upper electrode 20 are omitted from FIGS. 1 and 2. FIG. 3 shows a cross-sectional view taken along line III-III in FIG. 2. FIG. 3 is a cross-sectional view that does not pass through the emitter region 15 and the Schottky region 30b. FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 4 is a cross-sectional view that passes through the emitter region 15 and the Schottky region 30b.

[0011] As shown in FIG. 1 , the semiconductor device 3 has a semiconductor substrate 10 made of silicon. The semiconductor substrate 10 includes a cell region 1 and a peripheral region 2 surrounding the cell region 1. The cell region 1 includes multiple IGBT regions 1a, multiple FWD regions 1b, and multiple boundary regions 1c. Note that in FIG. 1 , the multiple FWD regions 1b are indicated by gray fill. The multiple IGBT regions 1a are regions having IGBT elements and extend in the x direction. In the IGBT region 1a, a channel is formed in response to a gate voltage applied to a trench electrode 18, and a current flows through the IGBT region 1a. The multiple FWD regions 1b are regions having FWD elements and extend in the x direction. In the FWD region 1b, a current flows in response to a forward bias voltage applied between an upper electrode 20 and a lower electrode 24. The multiple IGBT regions 1a and the multiple FWD regions 1b are alternately arranged in the y direction. A plurality of boundary regions 1c are located between the plurality of IGBT regions 1a and the plurality of FWD regions 1b. The plurality of boundary regions 1c are ineffective regions that do not function as semiconductor elements.

[0012] Although not shown, a voltage-resistant structure such as a guard ring is provided in the peripheral region 2. In addition, signal electrode pads 5 are provided on the peripheral region 2. The signal electrode pads 5 include gate pads that control the gate voltage of the IGBT.

[0013] A P-type base layer 12 is formed on the drift layer 11. Furthermore, a plurality of trenches 14 are formed in the IGBT region 1a, the boundary region 1c, and the FWD region 1b so as to penetrate the base layer 12 and reach the drift layer 11. Each of the plurality of trenches 14 extends in the x direction and is arranged at equal intervals in the y direction. The trenches 14 separate the base layer 12 into a plurality of pieces.

[0014] In this embodiment, the base layer 12 has different impurity concentrations in the IGBT region 1a and in the FWD region 1b and boundary region 1c. Specifically, the base layer 12 in the IGBT region 1a has a higher impurity concentration than the base layer 12 in the FWD region 1b and boundary region 1c. Hereinafter, the base layer 12 formed in the IGBT region 1a will also be referred to as a first base layer 12a, and the base layer 12 formed in the FWD region 1b and boundary region 1c will also be referred to as a second base layer 12b.

[0015] The first base layer 12a functions as a channel region and also as a body region. The surface layer of the first base layer 12a is partially provided with an N-type junction layer having a depth shallower than that of the first base layer 12a, as shown in FIGS. ＋ A mold emitter region 15 is formed.

[0016] The emitter regions 15 have a higher impurity concentration than the drift layer 11, terminate in the first base layer 12a, and are formed so as to contact the side surfaces of the trenches 14. In this embodiment, a plurality of emitter regions 15 are scattered between the trenches 14 at equal intervals along the longitudinal direction (x direction) of the trenches 14. In other words, when viewed from the normal direction (+z direction) to the top surface 10a of the semiconductor substrate 10, the emitter regions 15 extend in a direction (y direction) perpendicular to the longitudinal direction of the plurality of trenches 14.

[0017] The first base layer 12a is formed up to the upper surface 10a of the semiconductor substrate 10 in a portion where the emitter region 15 is not formed. This portion serves as a first contact region 16a that is in ohmic contact with an upper electrode 20 (described later). In this embodiment, the first contact region 16a has the same upper surface layout as the emitter region 15 when viewed from the normal direction (+z direction), and the portion of the first base layer 12a that is not formed as the emitter region 15 serves as the first contact region 16a.

[0018] In the FWD region 1b, the second base layer 12b constitutes an anode layer. The second base layer 12b does not have an emitter region 15. A second contact region 16b and a Schottky region 30b are formed on the upper surface of the second base layer 12b.

[0019] The second contact region 16b has a higher impurity concentration than the second base layer 12b and is a region that is in ohmic contact with the upper electrode 20, which will be described later. The depth of each second contact region 16b is shallower than the second base layer 12b. The width of each second contact region 16b is optional, but in this embodiment it is set equal to that of the first contact region 16a.

[0020] The Schottky regions 30b are N-type regions that are in ohmic contact with the upper electrode 20. In FIGS. 2 and 4, the Schottky regions 30b are indicated by gray doping. The N-type impurity concentration of the Schottky regions 30b may be set within a range that allows ohmic contact with the upper electrode 20. The depth of each Schottky region 30b is shallower than the second base layer 12b. The width of each Schottky region 30b is arbitrary, but in this embodiment, it is set equal to the emitter region 15.

[0021] Similarly, in the boundary region 1c, a third contact region 16c and a Schottky region 30c are formed on the upper surface of the second base layer 12b. The third contact region 16c is similar to the second contact region 16b described above. The Schottky region 30c is similar to the Schottky region 30b described above. Therefore, detailed description thereof will be omitted.

[0022] Each trench 14 is filled with a gate insulating film 17 formed to cover the inner wall surface of the trench 14, and a trench electrode 18 formed on the gate insulating film 17. The trench electrode 18 is made of, for example, polysilicon. This forms a trench gate structure.

[0023] In this embodiment, the trench electrode 18 formed in the IGBT region 1a is connected to a gate drive circuit (not shown) so that a desired gate voltage can be applied thereto. Meanwhile, the trench electrode 18 formed in the FWD region 1b and the boundary region 1c is connected to an upper electrode 20 (described later). That is, the trench electrodes 18 formed in the FWD region 1b and the boundary region 1c are emitter-connected. As a result, when a high-level voltage is applied as a gate voltage for IGBT operation in the IGBT region 1a, a channel is formed on the side surface of the trench 14. Furthermore, in the FWD region 1b, since the trench electrode 18 is set to the emitter potential, no channel is formed even during IGBT operation, and a predetermined FWD operation is performed.

[0024] 3 and 4 , an interlayer insulating film 19 is formed on the upper surface 10a of the semiconductor substrate 10. A contact hole 19a is formed in the interlayer insulating film 19 in the IGBT region 1a, exposing a part of the emitter region 15 and the first contact region 16a. A contact hole 19b is formed in the interlayer insulating film 19 in the FWD region 1b, exposing the Schottky region 30b and the second contact region 16b. A contact hole 19c is formed in the interlayer insulating film 19 in the boundary region 1c, exposing the Schottky region 30c and the third contact region 16c. Furthermore, a contact hole 19d is formed in the interlayer insulating film 19 in the FWD region 1b and the boundary region 1c, exposing the trench electrode 18.

[0025] An upper electrode 20 is formed on the interlayer insulating film 19. In the IGBT region 1a, the upper electrode 20 is electrically connected to the emitter region 15 and the first contact region 16a through a contact hole 19a. In the FWD region 1b, the upper electrode 20 is electrically connected to the Schottky region 30b and the second contact region 16b through a contact hole 19b. In the boundary region 1c, the upper electrode 20 is electrically connected to the Schottky region 30c and the third contact region 16c through a contact hole 19c. Furthermore, the upper electrode 20 is connected to the trench electrode 18 through a contact hole 19d. That is, the upper electrode 20 functions as an emitter electrode in the IGBT region 1a and as an anode electrode in the FWD region 1b.

[0026] An N-type field stop (hereinafter referred to as FS) layer 21 having an impurity concentration higher than that of the drift layer 11 is formed on the lower surface 10b side of the semiconductor substrate 10. This FS layer 21 is not essential, but is provided to improve the breakdown voltage and steady-state loss performance by preventing the expansion of the depletion layer, and to control the amount of holes injected from the lower surface 10b side of the semiconductor substrate 10.

[0027] In the IGBT region 1a and the boundary region 1c, a P-type collector layer 22 is formed on the opposite side of the drift layer 11 with the FS layer 21 in between. In the FWD region 1b, an N-type cathode layer 23 is formed on the opposite side of the drift layer 11 with the FS layer 21 in between. That is, in this embodiment, the IGBT region 1a and the boundary region 1c and the FWD region 1b are distinguished from each other by whether the layer formed on the lower surface 10b side of the semiconductor substrate 10 is the collector layer 22 or the cathode layer 23.

[0028] On the lower surface 10b, a lower electrode 24 is formed on the surfaces of the collector layer 22 and the cathode layer 23. This lower electrode 24 functions as a collector electrode in the IGBT region 1a and the boundary region 1c, and functions as a cathode electrode in the FWD region 1b.

[0029] With this configuration, an IGBT element is configured in the IGBT region 1a, with the first base layer 12a as the base, the emitter region 15 as the emitter, and the collector layer 22 as the collector. Also, in the FWD region 1b, a PN-junction FWD element is configured, with the second base layer 12b and the second contact region 16b as the anode, and the drift layer 11 and the cathode layer 23 as the cathode.

[0030] In this embodiment, N-type ＋ Type, N － The type corresponds to the first conductivity type, and P type, P ＋ Type, P － The type corresponds to the second conductivity type.

[0031] (Problem) The problem will be explained. In the FWD region 1b including the Schottky region 30b, it is necessary to appropriately adjust the relationship between the doping concentration of the P-type impurity in the second base layer 12b and the doping concentration of the N-type impurity in the Schottky region 30b. This is to prevent the parasitic bipolar transistor formed by the Schottky region 30b from turning on and causing recovery breakdown.

[0032] FIG. 5 shows the impurity concentration distribution curve in the conventional FWD region 1b. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4. That is, FIG. 5 shows the concentration distribution curve in a cross section of the FWD region 1b, in which the Schottky region 30b is disposed in the surface layer portion and the second base layer 12b is disposed below the Schottky region 30b. The horizontal axis of FIG. 5 represents the depth from the upper surface 10a, and the vertical axis represents the doping concentration. The concentration distribution curve NC represents the implantation concentration of the N-type impurity. The concentration distribution curve PC represents the implantation concentration of the P-type impurity. The concentration distribution curves NC and PC intersect at an intersection point IS. The region shallower than the intersection point IS is a region where the N-type impurity concentration is higher than the P-type impurity concentration, and functions as the N-type Schottky region 30b. On the other hand, the region deeper than the intersection point IS is a region where the P-type impurity concentration is higher than the N-type impurity concentration, and functions as the P-type second base layer 12b.

[0033] In the conventional FWD region 1b shown in FIG. 5 , to prevent recovery breakdown, the second peak height PKp of the concentration distribution curve PC had to be higher than the first peak height PKn of the concentration distribution curve NC. Therefore, in order to increase the second peak height PKp, the amount of P-type impurities implanted was unnecessarily large. That is, the second areal density ADp, which is represented by the area of ​​the region surrounded by the concentration distribution curve PC (the region shaded in gray), was large. The second areal density ADp will be described later. This is because the concentration distribution curve obtained by ion implantation follows a Gaussian distribution, and the higher the second peak height PKp, the higher the overall concentration. As a result, it became difficult to sufficiently suppress the amount of holes injected from the second base layer 12b, which made it difficult to sufficiently reduce switching loss.

[0034] (Solution) The present inventors focused on the mechanism of recovery breakdown in the FWD region 1b including the Schottky region 30b. Recovery breakdown is a phenomenon that occurs when the total number of carriers decreases, causing a decrease in the base current from the Schottky region of the parasitic bipolar transistor to the anode layer, preventing electrons from being discharged to the collector layer. Therefore, the present inventors found that the total number of carriers is important for preventing recovery breakdown.

[0035] The total number of carriers can be expressed by areal density. The areal density is a value obtained by integrating the concentration distribution curve of the impurity in the depth direction. In other words, the areal density is a value indicating the total number of impurity ions per unit area when the impurity is implanted from the upper surface 10a of the semiconductor substrate 10. The unit of areal density is "ions / cm ２ "

[0036] FIG. 6 shows the impurity concentration distribution curve in the FWD region 1b of this embodiment. The content of FIG. 6 is similar to that of FIG. 5 described above. The integral value of the concentration distribution curve NC over the entire depth direction has a first areal density ADn. That is, the area of ​​the region surrounded by the concentration distribution curve NC (the region indicated by hatching) corresponds to the first areal density ADn. Furthermore, the integral value of the concentration distribution curve PC over the entire depth direction has a second areal density ADp. That is, the area of ​​the region surrounded by the concentration distribution curve PC (the region indicated by gray fill) corresponds to the second areal density ADp.

[0037] The present inventors have succeeded in deriving the relationship between the first areal density ADn and the second areal density ADp that can prevent recovery breakdown and reduce switching loss at the same time, as will be explained below.

[0038] (Relationship between First Areal Density ADn and Second Areal Density ADp) Using CAE (Computer Aided Engineering), a simulation was performed on the relationship between the first areal density ADn and the second areal density ADp. As a result, a first relationship and a second relationship were derived, as described below.

[0039] The first relationship will be explained. FIG. 7 shows a graph of the first simulation results. The horizontal axis is the second areal density ADp. The vertical axis is the FWD normalized withstand voltage (static withstand voltage of FWD). In this simulation, the first areal density ADn is set to 5×10 １１ [ions / cm ２ As shown in FIG. 7, when the second areal density ADp is 3×10 １１ [ions / cm ２ ], the FWD normalized withstand voltage decreases exponentially. That is, the threshold voltage TV for allowing the FWD region 1b to function sufficiently as a diode is 3×10 １１ [ions / cm ２ ]. This threshold value TV is calculated based on the first surface density ADn (5×10 １１ [ions / cm ２]) From the above, the first relationship can be derived, that is, "the second areal density ADp is equal to or greater than 0.6 times the first areal density ADn."

[0040] The second relationship will now be described. FIG. 8 shows a graph of the results of the second simulation. The horizontal axis represents the second areal density ADp. The vertical axis represents various losses when the semiconductor device 3 of this embodiment is incorporated into and operated in an inverter. The FWD loss Vf is the loss when a forward current flows through the FWD. The turn-on loss Eon is the loss that occurs when the IGBT is turned on. The reverse recovery loss Err is the loss that occurs during reverse recovery of the FWD. The total loss Et is the total loss of the FWD loss Vf, the turn-on loss Eon, and the reverse recovery loss Err.

[0041] 8, the FWD loss Vf decreases simply as the second areal density ADp increases. On the other hand, the turn-on loss Eon and the reverse recovery loss Err increase simply as the second areal density ADp increases. Therefore, the total loss Et is plotted as a downward convex graph, with a minimum value LM.

[0042] Then, a range of the second areal density ADp was defined in which the total loss Et could be close to the minimum value LM. Specifically, a loss tolerance value PV was set in consideration of variations when incorporated into an inverter. Then, a range of the second areal density ADp in which the total loss Et is equal to or less than the loss tolerance value PV was determined. As a result, the lower limit value LL of the second areal density ADp was determined to be approximately 1.5×10 １２ [ions / cm ２ The upper limit UL of the second areal density ADp is about 5×10 １２ [ions / cm ２ The lower limit LL is the first areal density ADn (5×10 １１ [ions / cm ２ ]). The upper limit value UL is a value that is about 10 times the first areal density ADn. From the above, the second relationship can be derived, which states that "it is more preferable that the second areal density ADp be in the range of 3 times or more the first areal density ADn to 10 times or less the first areal density ADn."

[0043] (Effects) As described above with reference to FIG. 5 , in the conventional FWD region 1b, the second peak height PKp of the concentration distribution curve PC had to be higher than the first peak height PKn of the concentration distribution curve NC. This resulted in a large second areal density ADp (the area indicated by the gray fill). As a result, it was difficult to sufficiently suppress the amount of holes injected from the second base layer 12b. Therefore, the technology of this specification derives a first relationship in which "the second areal density ADp is 0.6 times or more the first areal density ADn" (see FIG. 7 ). As long as this first relationship is satisfied, there is no restriction on the magnitude relationship between the first peak height PKn and the second peak height PKp. Therefore, as shown in the concentration distribution curve of this embodiment in FIG. 6 , the second peak height PKp can be made lower than the first peak height PKn. This eliminates the need to unnecessarily increase the second peak height PKp, making it possible to appropriately reduce the second areal density ADp. That is, the area of ​​the region surrounded by the concentration distribution curve PC (the region shaded in gray) can be reduced from the conventional concentration distribution curve PC ( FIG. 5 ) to the concentration distribution curve PC ( FIG. 6 ) of this embodiment. Therefore, the P-type impurity concentration of the second base layer 12 b can be further reduced, making it possible to sufficiently suppress the amount of holes injected from the second base layer 12 b. This makes it possible to reduce switching loss while preventing recovery breakdown.

[0044] Furthermore, the technology of this specification derives a second relationship that states that "the second areal density ADp is more preferably in the range of 3 times or more the first areal density ADn to 10 times or less the first areal density ADn" (see FIG. 8). By satisfying this second relationship, it becomes possible to further reduce the total loss.

[0045] (Manufacturing Method) Among the manufacturing processes for the FWD region 1b and the boundary region 1c, the processes related to this specification will be described using the flow chart in Fig. 9. Note that the description of the manufacturing process for the IGBT region 1a and the processes not related to this specification may be omitted.

[0046] In step S10, a semiconductor substrate 10 including a drift layer 11 and a trench gate structure is prepared. In step S20, a first mask layer having openings corresponding to the FWD region 1b and the boundary region 1c is formed on the upper surface 10a. The first mask layer may be a resist mask or a hard mask formed of a silicon oxide film or the like. Then, P-type impurities are ion-implanted into the entire FWD region 1b and the boundary region 1c through the first mask layer (first implantation step). This ion implantation is performed at a second areal density ADp. This results in the formation of a second base layer 12b.

[0047] In step S30, a striped second mask layer having openings corresponding to the second contact region 16b and the third contact region 16c is formed on the upper surface 10a. P-type impurity ions are then implanted through the second mask layer. As a result, the second contact region 16b and the third contact region 16c are formed in the regions into which the P-type impurity has been implanted. The concentration of the P-type impurity is set to a concentration that allows the second contact region 16b and the third contact region 16c to make ohmic contact with the upper electrode 20.

[0048] In step S40, a third mask layer having openings corresponding to the FWD region 1b and the boundary region 1c is formed on the upper surface 10a. Then, N-type impurities are ion-implanted into the entire FWD region 1b and the boundary region 1c through the third mask layer (second implantation step). This ion implantation is performed at a first areal density ADn. The first areal density ADn is set to a value at which the Schottky regions 30b and 30c (described later) make Schottky contact with the upper electrode 20. － In the region where the second base layer 12b of the mold is exposed on the upper surface 10a, P of the surface layer portion of the second base layer 12b － The impurity concentration in the P-type layer is converted to an N-type layer. As a result, N-type Schottky regions 30b and 30c are formed in the surface portion of the second base layer 12b. On the other hand, in the region where the P-type second contact region 16b and third contact region 16c are exposed on the upper surface 10a, the P-type impurity concentration is sufficiently high and the region is not converted to an N-type layer. This completes the structure shown in FIG. 2. The subsequent steps will not be described here.

[0049] The second contact region 16b and the third contact region 16c are implanted with the same concentration of N-type impurities as the Schottky regions 30b and 30c. The amount of P-type charge in the second contact region 16b and the third contact region 16c is greater than the amount of N-type charge, and the second contact region 16b and the third contact region 16c function as P-type regions. Meanwhile, the amount of N-type charge in the Schottky regions 30b and 30c is greater than the amount of P-type charge, and the Schottky regions function as N-type regions. This characteristic distribution of impurity concentration can be easily identified by cross-sectional analysis.

[0050] By setting the second areal density ADp of P-type impurities in step S20 to be 0.6 times or more the first areal density ADn of N-type impurities in step S40, it becomes possible to reduce switching loss while preventing recovery breakdown, as described above. Furthermore, by setting the second areal density ADp in the range from 3 times or more the first areal density ADn to 10 times or less the first areal density ADn, it becomes possible to further reduce total loss, as described above.

[0051] Fig. 10 shows a semiconductor substrate 10 according to Example 2. Fig. 10 is a diagram similar to Fig. 2 of Example 1. Example 2 differs from Example 1 in that it includes a lifetime control region 201. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0052] In the technology of Example 2, a lifetime control region 201 is formed in at least one of the IGBT region 1a, the FWD region 1b, and the boundary region 1c. In the example of Fig. 10, a plurality of lifetime control regions 201 are formed in at least a portion of the IGBT region 1a. In Fig. 10, the lifetime control regions 201 are indicated by crosses. The plurality of lifetime control regions 201 are arranged in a planar shape at a predetermined depth from the upper surface 10a in the drift layer 11.

[0053] The lifetime control region 201 is a region where a large number of crystal defects are formed, and serves as a carrier recombination center. The lifetime control region 201 can be formed by irradiating helium ions from the upper surface 10a of the semiconductor substrate 10. The crystal defect density peaks at a predetermined depth, and the lifetime control region 201 is formed.

[0054] The technology described in this specification can also be applied to a structure including such a lifetime control region 201. That is, when the first areal density ADn and the second areal density ADp have the above-described relationship, it becomes possible to reduce switching loss while preventing recovery breakdown.

[0055] The range in which the lifetime control region 201 is formed may vary. For example, it may be formed only in the FWD region 1b, or may be formed over the entire region including the IGBT region 1a, the FWD region 1b, and the boundary region 1c.

[0056] Fig. 11 shows a semiconductor substrate 10 according to Example 3. Fig. 11 is a diagram similar to Fig. 2 of Example 1. Example 3 differs from Example 1 in that it includes a hole injection suppression structure 310. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0057] In the technology of Example 3, a hole injection suppression structure 310 is formed in at least one of the IGBT region 1a, the FWD region 1b, and the boundary region 1c. In the example of FIG. 11 , a plurality of hole injection suppression structures 310 are provided in at least a portion of the IGBT region 1a. The hole injection suppression structure 310 is disposed in a semiconductor region sandwiched between a plurality of trenches 14. The hole injection suppression structure 310 includes an N-type barrier region 311 and an N-type pillar region 312. The barrier region 311 is a region that contacts the base layer 12 from below. A P-type lower base layer 313 is disposed below the barrier region 311. The pillar region 312 is a region that extends from the barrier region 311 to the upper surface 10a. The upper surface of the barrier region 311 is exposed in a portion of the first contact region 16a and is electrically connected to the upper electrode 20.

[0058] The hole injection suppression structure 310 can suppress the injection of holes from the body region to the drift region when the diode is turned on, thereby suppressing the recovery current when the diode performs a recovery operation.

[0059] The techniques described in this specification can also be applied to a structure including such a hole injection suppression structure 310. That is, when the first areal density ADn and the second areal density ADp have the above-described relationship, it becomes possible to reduce switching loss while preventing recovery breakdown.

[0060] The hole injection suppression structure 310 may be formed in various regions. For example, it may be formed only in the FWD region 1b, or may be formed over the entire region including the IGBT region 1a, the FWD region 1b, and the boundary region 1c.

[0061] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

[0062] The Schottky region 30b may be disposed in various ways as long as it is disposed in at least a part of the FWD region 1b. For example, the Schottky region 30b may not be disposed in the boundary region 1c.

[0063] The steps may be performed in various orders in the manufacturing method of the semiconductor device 3. For example, the trench gate structure may be formed after the FWD region 1b and the boundary region 1c are formed.

[0064] In the above-described embodiment, the case where the emitter potential is applied to the trench electrode 18 in the FWD region 1 b has been described. However, a gate voltage may be applied to the trench electrode 18 in the FWD region 1 b. Also, the trench electrode 18 may not be provided in at least one of the FWD region 1 b and the boundary region 1 c.

[0065] In the above-described embodiment, a trench type IGBT is formed in the IGBT region 1a, but a planar type IGBT may also be formed in the IGBT region 1a.

[0066] The numerical values ​​of the concentration distribution curves PC and NC, the first peak height PKn, the second peak height PKp, the first surface density ADn, the second surface density ADp, etc. shown in this embodiment are merely examples, and various values ​​can be used.

[0067] The material of the semiconductor substrate 10 is not limited to silicon, but may be a wide-gap semiconductor (e.g., SiC, GaN, Ga ２ O ３ etc.) can be used.

[0068] In each of the above embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0069] The configurations of the techniques disclosed in this specification are listed below. [Configuration 1] A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements, a plurality of FWD regions (1b) having FWD elements, and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extending in a first direction (x) and alternately arranged in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b), and the semiconductor substrate a drift layer (11) of a first conductivity type (N); a base layer (12) of a second conductivity type (P) formed in a surface layer portion of the drift layer; a collector layer (22) of a second conductivity type formed in the IGBT region on a side of the drift layer opposite to the base layer side; a cathode layer (23) of a first conductivity type formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and deeper than the base layer to reach the drift layer; and an emitter region (15) of a first conductivity type formed in a surface layer portion of the base layer in the IGBT region, the emitter region (15) being in contact with the trench. a second conductivity type contact region (16b) disposed in a part of a surface layer portion of the base layer in the FWD region, the contact region having a higher impurity concentration than the base layer and making ohmic contact with the upper electrode; and a first conductivity type Schottky region (30b) disposed in a part of a surface layer portion of the base layer in the FWD region, the Schottky region making Schottky contact with the upper electrode,A semiconductor device, wherein a concentration distribution curve of a first conductivity type impurity in a depth direction of the Schottky region has a first peak height (PKn), and an integral value of the concentration distribution curve has a first areal density (ADn), and a concentration distribution curve of a second conductivity type impurity in a depth direction of the base layer disposed below the Schottky region has a second peak height (PKp), and an integral value of the concentration distribution curve has a second areal density (ADp), the second peak height is lower than the first peak height, and the second areal density is 0.6 times or more the first areal density. [Structure 2] The semiconductor device according to Structure 1, wherein the second areal density is 10 times or less the first areal density. [Structure 3] The semiconductor device according to Structure 1 or 2, wherein the second areal density is 3 times or more the first areal density. [Structure 4] The semiconductor device according to any one of Structures 1 to 3, wherein the contact region and the Schottky region are disposed in at least a portion of a surface layer portion of the base layer in the boundary region. [Configuration 5] The semiconductor device according to any one of configurations 1 to 4, wherein the concentrations of the first conductivity type impurities implanted in the contact region and the Schottky region are the same; the amount of charge of the second conductivity type is greater than the amount of charge of the first conductivity type in the contact region; and the amount of charge of the first conductivity type is greater than the amount of charge of the second conductivity type in the Schottky region. [Configuration 6] A method for manufacturing a semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with a top surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements; a plurality of FWD regions (1b) having FWD elements; and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extending in a first direction (x) and arranged alternately in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b),a first conductivity type (N) drift layer (11); a second conductivity type (P) base layer (12) formed in a surface layer portion of the drift layer; a second conductivity type collector layer (22) formed in the IGBT region on a side of the drift layer opposite to the base layer side; a first conductivity type cathode layer (23) formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and deeper than the base layer to reach the drift layer; and a first conductivity type emitter region (15) formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trenches, A manufacturing method comprising: a first implantation step (S20) of implanting second-conductivity-type impurities into the upper surface of the FWD region to form the base layer; and a second implantation step (S40) of implanting first-conductivity-type impurities into a first region (30b) that is a portion of the upper surface of the FWD region, the second implantation step comprising implanting the first-conductivity-type impurities at a concentration that causes the first region to make Schottky contact with the upper electrode, wherein a second areal density (ADp) of the second-conductivity-type impurities in the first implantation step is 0.6 times or more the first areal density (ADn) of the first-conductivity-type impurities in the second implantation step. [Structure 7] The manufacturing method according to Structure 6, wherein the second areal density is 10 times or less the first areal density. [Structure 8] The manufacturing method according to Structure 6 or 7, wherein the second areal density is 3 times or more the first areal density. [Structure 9] The manufacturing method according to any one of Structures 6 to 8, wherein in the first implantation step, the second conductivity type impurity is implanted into the upper surface of the boundary region, and in the second implantation step, the first conductivity type impurity is implanted into a second region (30c) that is a part of the upper surface of the boundary region. [Structure 10] The manufacturing method according to any one of Structures 6 to 9, wherein in the second implantation step, the first conductivity type impurity is implanted into the entire upper surface of the FWD region.

[0070] According to the sixth aspect, if the second areal density is equal to or greater than 0.6 times the first areal density, the peak concentration of the P-type impurity in the base layer can be made lower than the peak concentration of the N-type impurity in the first region. Therefore, the integrated concentration of the P-type impurity in the base layer can be appropriately reduced. The P-type impurity concentration in the base layer can be further reduced while preventing recovery breakdown.

[0071] According to the configurations 2 and 7, it is possible to further reduce various losses in the semiconductor device.

[0072] According to the configurations 3 and 8, it is possible to further reduce various losses in the semiconductor device.

[0073] According to the fourth and ninth configurations, the P-type impurity concentration of the base layer can be further reduced even in the boundary region, so that the switching loss can be further reduced.

[0074] According to the fifth and tenth configurations, a Schottky region can be formed by converting the second conductivity type region back to the first conductivity type.

Claims

1. A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements; a plurality of FWD regions (1b) having FWD elements; and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, wherein the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extend in a first direction (x) and are arranged alternately in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) are located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b), and the semiconductor substrate comprises: a drift layer (11) of a first conductivity type (N), a second conductivity type (P) base layer (12) formed in a surface portion of the drift layer; a second conductivity type collector layer (22) formed in the IGBT region on a side of the drift layer opposite to the base layer side; a first conductivity type cathode layer (23) formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and deeper than the base layer to reach the drift layer; a first conductivity type emitter region (15) formed in a surface portion of the base layer in the IGBT region so as to be in contact with the trench; and a second conductivity type contact region (16b) arranged in a part of the surface portion of the base layer in the FWD region, the contact region having a higher impurity concentration than the base layer and making ohmic contact with the upper electrode. a first conductivity type Schottky region (30b) disposed in a part of a surface layer portion of the base layer in the FWD region, the Schottky region being in Schottky contact with the upper electrode,a concentration distribution curve of a first conductivity type impurity in a depth direction of the Schottky region has a first peak height (PKn), and an integral value of the concentration distribution curve has a first areal density (ADn); a concentration distribution curve of a second conductivity type impurity in a depth direction of the base layer disposed below the Schottky region has a second peak height (PKp), and an integral value of the concentration distribution curve has a second areal density (ADp), the second peak height is lower than the first peak height, and the second areal density is 0.6 times or more of the first areal density.

2. The semiconductor device according to claim 1, wherein said second areal density is 10 times or less than said first areal density.

3. The semiconductor device according to claim 2, wherein said second areal density is at least three times as large as said first areal density.

4. The semiconductor device according to any one of claims 1 to 3, wherein the contact region and the Schottky region are disposed in at least a portion of the surface layer portion of the base layer in the boundary region.

5. The semiconductor device according to claim 1, wherein the concentrations of the first conductivity type impurities implanted in the contact region and the Schottky region are the same, the amount of charge of the second conductivity type is greater than the amount of charge of the first conductivity type in the contact region, and the amount of charge of the first conductivity type is greater than the amount of charge of the second conductivity type in the Schottky region.

6. A method for manufacturing a semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements; a plurality of FWD regions (1b) having FWD elements; and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extending in a first direction (x) and arranged alternately in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b), and the semiconductor substrate a first conductivity type (N) drift layer (11); a second conductivity type (P) base layer (12) formed in a surface layer portion of the drift layer; a second conductivity type collector layer (22) formed in the IGBT region on a side of the drift layer opposite to the base layer side; a first conductivity type cathode layer (23) formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and deeper than the base layer to reach the drift layer; and a first conductivity type emitter region (15) formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trenches, a first implantation step (S20) of implanting a second conductivity type impurity into the upper surface of the FWD region to form the base layer; and a second implantation step (S40) of implanting a first conductivity type impurity into a first region (30b) that is a part of the upper surface of the FWD region, the implantation concentration of the first conductivity type impurity being a concentration at which the first region makes Schottky contact with the upper electrode,a second areal density (ADp) of the second conductivity type impurity in the first implantation step is 0.6 times or more a first areal density (ADn) of the first conductivity type impurity in the second implantation step.

7. The manufacturing method according to claim 6, wherein the second areal density is 10 times or less than the first areal density.

8. The manufacturing method according to claim 7, wherein the second areal density is at least three times the first areal density.

9. A manufacturing method according to any one of claims 6 to 8, wherein in the first implantation step, the second conductivity type impurity is implanted into the upper surface of the boundary region, and in the second implantation step, the first conductivity type impurity is implanted into a second region (30c) that is a portion of the upper surface of the boundary region.

10. The manufacturing method according to claim 6, wherein in the second implantation step, the first conductivity type impurity is implanted into the entire upper surface of the FWD region.

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