Semiconductor device

Abstract

A semiconductor device disclosed herein comprises: an MIS transistor structure including a first impurity region of a first conductivity type formed in a surface layer portion of a first main surface of a chip, a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region, a third impurity region of a first conductivity type formed in a surface layer portion of the second impurity region, and control electrodes facing each other in a first channel region of the second impurity region via a control insulating film; a rectifying element structure including shield regions of the second conductivity type formed in a surface layer portion of the first impurity region and facing each other, in a direction crossing the thickness direction of the chip, in the first impurity region, and a second channel region provided by a portion of the first impurity region sandwiched between the shield regions; a first main surface electrode ohmic-connected to the third impurity region, the shield regions, and the second channel region; and a second main surface electrode ohmic-connected to the first impurity region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-069388 filed with the Japan Patent Office on April 22, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] a first impurity region of a first conductivity type formed in a surface layer portion of the first impurity region; a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region; and a control electrode facing a first channel region of the second impurity region via a control insulating film; a rectifying element structure including: shield regions of the second conductivity type formed in a surface layer portion of the first impurity region and facing each other in the first impurity region in a direction intersecting a thickness direction of the chip; and a second channel region provided by a portion of the first impurity region sandwiched between the shield regions; a first main surface electrode ohmically connected to the third impurity region, the shield region, and the second channel region; and a second main surface electrode ohmically connected to the first impurity region.

[0005] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a perspective view showing an active region and a gate structure. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is the same cross-sectional view as FIG. 6 but mainly shows dimensions of various components. FIG. 9 is the same cross-sectional view as FIG. 7 but mainly shows dimensions of various components. FIG. 10 is an enlarged plan view showing a main portion of an active region. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 . FIG. 12 is a cross-sectional view showing a peripheral region. FIG. 13 is a plan view showing an example layout of a transistor region and a blank region. FIG. 14 is a plan view showing an example layout of a transistor region and a blank region. FIG. 15 is a plan view showing an example layout of a transistor region and a blank region. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a diagram showing a circuit configuration of the semiconductor device. FIG. 18 is a cross-sectional view showing a second embodiment of a rectifying element. FIG. 19 is a plan view showing an example layout of a transistor region and a blank region. FIG. 20 is a plan view showing an example layout of a transistor region and a blank region. FIG. 21 is a plan view showing an example layout of a transistor region and a blank region. FIG. 22 is a perspective view showing a third embodiment of a rectifying element. FIG. 23 is a perspective view showing the third embodiment of a rectifying element. FIG. 24A is a cross-sectional view of section A shown in FIGS. 19 to 21. FIG. 24B is a cross-sectional view of section B shown in FIGS. 19 to 21. FIG. 24C is a cross-sectional view of section C shown in FIGS. 20 and 21. FIG. 24D is a cross-sectional view of section D shown in FIG. 21. FIG. 25 is a cross-sectional view showing a fourth embodiment of a rectifying element. FIG. 26 is a perspective view showing a fifth embodiment of a rectifying element. FIG. 27 is a plan view showing an example layout of a transistor region and a blank region. FIG. 28 is a plan view showing an example layout of a transistor region and a blank region. Fig. 29 is a plan view showing an example of the layout of a transistor region and a blank region, Fig. 30 is a perspective view showing a sixth embodiment of a rectifying element, and Fig. 31 is a cross-sectional view showing a modified example of an interlayer film.

[0006] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0008] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] [Overall Configuration of Semiconductor Device 1] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0011] 1 to 4, a semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0012] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0013] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0014] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0019] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0020] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0021] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0022] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential is applied to the first semiconductor layer 6 as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0024] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate (i.e., a SiC substrate) made of SiC single crystal. The first semiconductor layer 6 has the off direction Do and off angle θo described above.

[0025] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0026] The first semiconductor layer 6 may have a first thickness T1 of 10 μm to 500 μm. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0027] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0028] In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the off-direction Do and off-angle θo described above. The second semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first semiconductor layer 6.

[0029] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the ending point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0030] The second semiconductor layer 7 includes an n-type drift region 8 as an example of a first impurity region. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor layer 7.

[0031] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 7 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the first semiconductor layer 6.

[0032] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0033] The semiconductor device 1 includes an active region 9 defined in a chip 2. The active region 9 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0034] The active region 9 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0035] The ratio (area ratio) of the planar area of ​​the active region 9 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0036] The semiconductor device 1 includes a peripheral region 10 set outside the active region 9 in the chip 2. The peripheral region 10 is a region that does not include a device structure (transistor structure Tr). The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a planar view. The peripheral region 10 extends in a strip shape along the active region 9 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0037] The semiconductor device 1 includes a plurality of trench electrode type gate structures 11 formed on the first main surface 3 in the active region 9. The gate structures 11 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 11 as a control potential.

[0038] The multiple gate structures 11 are arranged at intervals inward from the periphery of the active region 9. In this embodiment, the multiple gate structures 11 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the multiple gate structures 11 are arranged at intervals in the m-axis direction and each extend in the a-axis direction.

[0039] In this embodiment, the multiple gate structures 11 are arranged in stripes extending in the a-axis direction (second direction Y). The extending direction of the multiple gate structures 11 coincides with the off-direction Do of the second semiconductor layer 7. The multiple gate structures 11 are formed at intervals from the lower end (first semiconductor layer 6) of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.

[0040] The semiconductor device 1 includes a plurality of p-type well regions 12 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. Specifically, the plurality of well regions 12 are formed at the bottom of the gate structure 11, respectively.

[0041] The semiconductor device 1 includes a p-type outer well region 13 and a p-type field region 14 formed in a surface layer portion of the first main surface 3 in a peripheral region 10 (the peripheral portion of the first main surface 3).

[0042] The semiconductor device 1 includes a surface insulating film 15 that selectively covers the first main surface 3. The surface insulating film 15 may also be referred to as an "outer surface insulating film," etc. The surface insulating film 15 covers the first main surface 3 in the peripheral region 10 in a film-like manner.

[0043] Specifically, the surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14 in the peripheral region 10. The surface insulating film 15 is continuous with the first to fourth side surfaces 5A to 5D. The surface insulating film 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge portion of the first main surface 3.

[0044] The semiconductor device 1 includes one or more (one in this embodiment) gate wirings 66 arranged on the first main surface 3 in the peripheral region 10. The gate wiring 66 is arranged on the surface insulating film 15.

[0045] 3 , the gate wiring 66 extends in a strip shape along the periphery of the plurality of gate structures 11. The gate wiring 66 has a portion extending in a first direction X and a portion extending in a second direction Y. The gate wiring 66 extends in a strip shape so as to intersect (specifically, perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 11.

[0046] In this embodiment, the gate wiring 66 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the plurality of gate structures 11 (active regions 9). Of course, the gate wiring 66 may be formed in a strip shape with ends. The gate wiring 66 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape).

[0047] The semiconductor device 1 includes a gate pad wiring 67 arranged on the first main surface 3 in the peripheral region 10. The gate pad wiring 67 is electrically connected to the gate wiring 66 and applies a gate potential to the gate wiring 66.

[0048] The semiconductor device 1 includes an insulating interlayer film 65 that covers the surface insulating film 15. The interlayer film 65 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 65 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0049] The semiconductor device 1 includes the aforementioned source pad electrode 70 disposed on the first main surface 3. The source pad electrode 70 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source electrode," or the like. The source pad electrode 70 is disposed on the interlayer film 65.

[0050] In this embodiment, the source pad electrode 70 has a first pad portion 70a, a second pad portion 70b, and a third pad portion 70c. The first pad portion 70a has a relatively large planar area and forms the main body of the source pad electrode 70. In this embodiment, the first pad portion 70a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0051] The second pad portion 70b has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 70a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 70c has a planar area smaller than that of the first pad portion 70a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 70a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 70b in the second direction Y.

[0052] The planar area of ​​the third pad portion 70c may be approximately equal to the planar area of ​​the second pad portion 70b. The planar area of ​​the third pad portion 70c may be larger or smaller than the planar area of ​​the second pad portion 70b. Either or both of the second pad portion 70b and the third pad portion 70c may be used as a terminal portion for monitoring a current.

[0053] The source pad electrode 70 does not necessarily have to have both the second pad portion 70b and the third pad portion 70c at the same time. The source pad electrode 70 may have only one of the second pad portion 70b and the third pad portion 70c. The source pad electrode 70 may be composed of only the first pad portion 70a, and may not have both the second pad portion 70b and the third pad portion 70c.

[0054] The source pad electrode 70 covers the entire region of the interlayer film 65 where the source opening 68 is formed, and extends into the source opening 68 from above the interlayer film 65. The source pad electrode 70 has a portion that covers the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the source opening 68 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 68 in a film-like manner.

[0055] The semiconductor device 1 includes a gate pad electrode 80 disposed on the first main surface 3 at a distance from the source pad electrode 70. The gate pad electrode 80 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate electrode," or the like. The gate pad electrode 80 is disposed on the interlayer film 65 at a distance from the source pad electrode 70.

[0056] In this embodiment, the gate pad electrode 80 is disposed on a portion of the interlayer film 65 that covers the gate pad wiring 67, and faces the gate pad wiring 67 across the interlayer film 65. In this embodiment, the gate pad electrode 80 does not have a direct electrical connection to the gate pad wiring 67. Of course, the gate pad electrode 80 may be mechanically and electrically connected to the gate pad wiring 67 via one or more gate openings.

[0057] The gate pad electrode 80 is disposed in a region on the third side surface 5C side of the first pad portion 70a, and faces the center of the third side surface 5C and the first pad portion 70a in the first direction X. The gate pad electrode 80 is interposed in a region between the second pad portion 70b and the third pad portion 70c, and faces both the second pad portion 70b and the third pad portion 70c in the second direction Y.

[0058] The gate pad electrode 80 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the source pad electrode 70. The gate pad electrode 80 has a planar area smaller than the planar area of ​​the first pad portion 70a. The gate pad electrode 80 may have a planar area smaller than the planar area of ​​the second pad portion 70b (third pad portion 70c).

[0059] The gate pad electrode 80 faces the outer well region 13 across the interlayer film 65 and the gate pad wiring 67. In this embodiment, the gate pad electrode 80 is formed at a distance from the ends (both ends) of the plurality of gate structures 11. In other words, the gate pad electrode 80 does not face the plurality of gate structures 11 in the stacking direction. Of course, the gate structure 11 may have a portion that faces a part (for example, an end) of the gate structure 11 across the interlayer film 65.

[0060] The semiconductor device 1 includes a gate finger electrode 81 extending from the gate pad electrode 80 onto the first main surface 3. The gate finger electrode 81 may also be referred to as a "gate wiring" or a "gate finger." The gate finger electrode 81 transmits the gate potential applied to the gate pad electrode 80 to other regions.

[0061] The gate finger electrode 81 is drawn out from the gate pad electrode 80 onto a portion of the interlayer film 65 that covers the gate wiring 66. The gate finger electrode 81 is routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrode 70. The gate finger electrode 81 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in plan view.

[0062] In this embodiment, the gate finger electrode 81 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70. The gate finger electrode 81 is arranged closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 11. The gate finger electrode 81 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0063] The semiconductor device 1 includes a first slit portion 82 defined in a region between the source pad electrode 70 and the gate finger electrode 81. The first slit portion 82 exposes the interlayer film 65.

[0064] The semiconductor device 1 includes source finger electrodes 85 extending from the source pad electrode 70 onto the first main surface 3. The source finger electrodes 85 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 85 transmit the gate potential applied to the source pad electrode 70 to other regions.

[0065] The source finger electrodes 85 are arranged at intervals from the gate pad electrode 80 and the gate finger electrodes 81. The source finger electrodes 85 are arranged in regions on the peripheral edge side of the first main surface 3 with respect to both end portions of the plurality of gate structures 11.

[0066] The source finger electrodes 85 are drawn out from the source pad electrode 70 onto the interlayer film 65. The source finger electrodes 85 are routed in a strip shape around the periphery of the first main surface 3 and in the region between the source pad electrodes 70. The source finger electrodes 85 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0067] In this embodiment, the source finger electrode 85 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 70 and the gate finger electrode 81. The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0068] The semiconductor device 1 includes a second slit portion 86 defined in a region between the gate finger electrode 81 and the source finger electrode 85. The second slit portion 86 is defined in a region between the outer edge of the gate wiring 66 and the outer edge of the outer well region 13, and overlaps the first main surface 3 in the stacking direction.

[0069] The semiconductor device 1 includes a drain pad electrode 87 covering the second main surface 4. The drain pad electrode 87 may also be referred to as a "third main surface electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain electrode," or the like. The drain pad electrode 87 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 87 forms ohmic contact with the first semiconductor layer 6.

[0070] The drain pad electrode 87 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 87 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0071] A breakdown voltage that can be applied between source pad electrode 70 and drain pad electrode 87 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0072] [Detailed Structure of Active Region 9 of Semiconductor Device 1] Fig. 5 is a perspective view showing the active region 9 and gate structure 11. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. Fig. 8 is the same cross-sectional view as Fig. 6, mainly showing the dimensions of each part. Fig. 9 is the same cross-sectional view as Fig. 7, mainly showing the dimensions of each part.

[0073] In the following, for clarity of the drawings, the dimensions (thickness, width, depth, etc.) of each part of the semiconductor device 1 are shown in Figures 8 and 9, and are omitted from Figures 5 to 7. In Figures 8 and 9, in addition to the dimensions of each part, reference numerals are used to denote the main components.

[0074] 5 to 9, semiconductor device 1 includes p-type body region 18 formed in a surface layer portion of drift region 8. In this embodiment, body region 18, which is an example of a second impurity region, is formed in a layer shape extending along first main surface 3. Referring to Fig. 5, body region 18 is formed at an interval from the lower end of second semiconductor layer 7 toward first main surface 3.

[0075] The body region 18 is 1×10 １５ cm －３ 1x10 or more１８ cm －３ The p-type impurity concentration may have the following peak value:

[0076] As described above, the semiconductor device 1 includes gate structures 11. With reference to Figures 8 and 9, each gate structure 11 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 (see Figure 4) of the second semiconductor layer 7. The trench width WT may be not less than 0.1 µm and not more than 5 µm.

[0077] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0078] The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. In other words, the multiple gate structures 11 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0079] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0080] The multiple gate structures 11 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0081] The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 3 μm, and more preferably 0.5 μm to 1.5 μm.

[0082] 5 to 7 , each gate structure 11 includes a trench 19, a trench insulating film 20 as an example of a control insulating film, and a buried conductive layer 21 as an example of a control electrode. The trench 19 may be referred to as an "element trench," a "gate trench," or the like. The trench insulating film 20 may be referred to as a "control insulating film," an "element insulating film," a "gate insulating film," or the like. The buried conductive layer 21 may be referred to as a "control electrode," a "buried electrode," a "gate electrode," or the like.

[0083] The trenches 19 are formed in the first main surface 3 and define the inner surfaces (side surfaces 22 and bottom surfaces 23 shown in FIGS. 6 and 7 ) of the gate structure 11. The bottom surfaces 23 of the trenches 19 preferably have flat portions. Between adjacent trenches 19, mesa portions 24 are formed by part of the second semiconductor layer 7. The mesa portions 24 may also be referred to as "element mesa portions."

[0084] 5 , the gate structures 11 (trenches 19) and mesas 24 are strip-shaped and extend along the second direction Y, and are alternately arranged in the first direction X. The trenches 19 and mesas 24 are arranged in a stripe pattern as a whole. Each mesa 24 provides a unit cell UC of the trench-gate transistor. Each unit cell UC includes at least a body region 18 and a source region 32 (described later), and may be the minimum unit that functions as a MIS transistor.

[0085] 6 and 7 , it is particularly preferable that the flat portion of bottom surface 23 of trench 19 extends substantially parallel to first main surface 3. That is, it is preferable that the bottom wall of trench 19 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do (see FIG. 4 ) with respect to the c-plane. That is, it is preferable that bottom surface 23 of trench 19 has a flat portion extending in off direction Do. Of course, bottom surface 23 of trench 19 may be curved in an arc shape toward the lower end side of second semiconductor layer 7.

[0086] The trench insulating film 20 covers the inner surface of the trench 19. The trench insulating film 20 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 20 has a single-layer structure made of a silicon oxide film. The trench insulating film 20 may also include a silicon oxide film made of an oxide of the chip 2.

[0087] The buried conductive layer 21 is buried in the trench 19 and faces the body region 18 (first channel region 16) across the trench insulating film 20. The buried conductive layer 21 may include p-type or n-type conductive polysilicon.

[0088] 6 and 7 , the buried conductive layer 21 is buried up to the middle of the trench 19 in the depth direction. The buried conductive layer 21 has an upper surface 25 located closer to the second main surface 4 than the first main surface 3. A low step 26 is formed on the second main surface 4 side between the upper surface 25 of the buried conductive layer 21 and the first main surface 3. This step 26 forms a recess 27 in the upper part of the trench 19, which is defined by the upper surface 25 of the buried conductive layer 21 and the side surface 22 of the trench 19.

[0089] The recess 27 is a space sandwiched between both side surfaces 22 of the trench 19 and the top surface 25 of the buried conductive layer 21. As shown in Fig. 5 , the recess 27 is formed in a continuous strip shape in the depth direction (second direction Y) of the trench 19. The depth direction of the trench 19 may also be referred to as the "length direction of the trench 19," the "depth direction of the mesa portion 24," or the "length direction of the mesa portion 24."

[0090] The trench insulating film 20 is selectively formed in the region sandwiched between the inner surface of the trench 19 and the buried conductive layer 21, and the side surface 22 of the recess 27 (part of the side surface 22 of the trench 19) is exposed from the trench insulating film 20.

[0091] Due to the formation of the recess 27, a part of the mesa portion 24 in the depth direction of the trench 19 protrudes as a protrusion 28 toward the first main surface 3 (upward) beyond the buried conductive layer 21. As shown in Fig. 5 , the protrusion 28 of the mesa portion 24 is a part of the mesa portion 24 sandwiched between adjacent recesses 27, and is formed in a continuous band shape in the depth direction of the trench 19.

[0092] As described above, the semiconductor device 1 includes the well region 12. The well region 12 is formed in the bottom of the gate structure 11. More specifically, the well region 12 is formed in the bottom of the trench 19. The well region 12 is exposed from the bottom surface 23 of the trench 19 and is in contact with the trench insulating film 20. Therefore, the upper end of the well region 12 is exposed at the bottom surface 23 of the gate structure 11 (trench 19). The well region 12 may also be referred to as an "electric field relaxation layer."

[0093] The well region 12 faces the buried conductive layer 21 via the trench insulating film 20 in the depth direction of the trench 19. At the bottom of the trench 19, the trench insulating film 20 is sandwiched between the buried conductive layer 21 and the well region 12.

[0094] 5, well region 12 is formed in the bottom of trench 19 over the entire depth of trench 19, and is formed in a strip shape extending in the depth direction of trench 19. With reference to FIGS. 6 and 7, well region 12 is formed across one end and the other end of trench 19 in the width direction of trench 19. In this embodiment, well region 12 has, in the depth direction of trench 19, one side surface 29 formed on approximately the same plane as one side surface 22 of trench 19 in the width direction, and the other side surface 29 formed on approximately the same plane as the other side surface 22 of trench 19 in the width direction.

[0095] In other words, each well region 12 has a side surface 29 that is flush with both side surfaces 22 of the trench 19 in the depth direction of the gate structure 11. The side surface 29 of the well region 12 extends in the depth direction of the gate structure 11 and forms a boundary surface with the second semiconductor layer 7 (drift region 8). Therefore, the well region 12 is physically separated from the body region 18 in the depth direction of the gate structure 11 and forms the entire bottom surface 23 of the gate structure 11.

[0096] In this embodiment, the well region 12 has a stacked structure of a first layer 30 and a second layer 31. The first layer 30 is a layer formed away from the bottom of the trench 19 (bottom surface 23 in this embodiment) toward the second main surface 4. The second layer 31 is a layer formed between the first layer 30 and the bottom of the trench 19 (bottom surface 23 in this embodiment). The second layer 31 is exposed from the bottom surface 23 of the trench 19 and contacts the trench insulating film 20. The second layer 31 is sandwiched between the first layer 30 and the trench 19 portion.

[0097] Regarding the impurity concentration of the well region 12, the first layer 30 has a first impurity concentration, and the second layer 31 has a second impurity concentration. In this embodiment, the second impurity concentration of the second layer 31 is higher than the first impurity concentration of the first layer 30. Furthermore, the first impurity concentration of the first layer 30 may be equal to the impurity concentration of the body region 18. The second impurity concentration of the second layer 31 may be higher than the impurity concentration of the body region 18.

[0098] For example, the first impurity concentration of the first layer 30 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The second layer 31 may have a p-type impurity concentration of 1×10 or less as a peak value. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0099] The stacked structure of the first layer 30 and the second layer 31 is continuous in the depth direction of the trench 19. In this embodiment, as shown in FIG. 5 , the well region 12 is formed in a strip shape extending in the depth direction of the trench 19 so that the stacked structure of the first layer 30 and the second layer 31 is continuous throughout the entire depth direction of the trench 19. For example, the multiple well regions 12 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple well regions 12 are formed in a stripe shape extending in the a-axis direction (second direction Y), and the extending direction of the multiple well regions 12 coincides with the off-direction Do (see FIG. 4 ) of the second semiconductor layer 7.

[0100] The multiple well regions 12 overlap the multiple gate structures 11 in the depth direction of the trench 19. Specifically, the multiple well regions 12 overlap the multiple gate structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this configuration, the multiple well regions 12 are connected to the bottom surfaces 23 of the corresponding gate structures 11.

[0101] 8 and 9, well region 12 has a relaxation depth DR in the vertical direction Z.

[0102] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 1.5 μm to 2.5 μm.

[0103] Each of the multiple well regions 12 has a relaxed width WR in the arrangement direction. The relaxed width WR may be 0.25 μm or more and 5 μm or less. The relaxed width WR may have a value belonging to any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0104] 5 and 6 , semiconductor device 1 includes a source region 32 as an example of a third impurity region in a surface layer portion of first main surface 3. Source region 32 is formed in a region between a plurality of gate structures 11. Source region 32 is formed in a surface layer portion of body region 18 in mesa portion 24.

[0105] In this embodiment, a plurality of source regions 32 are formed across the mesa portion 24 in the width direction, extending from one side surface 22 of the mesa portion 24 to the other side surface 22 (one side surface 22 and the other side surface 22 of the trench 19). The plurality of source regions 32 are arranged at intervals in each mesa portion 24 along the depth direction of the trench 19. As a result, in each mesa portion 24, a plurality of channel sections 33 are arranged at intervals in the second direction Y (depth direction of the trench 19). In the channel sections 33, channels are formed on both side surfaces 22 of the trench 19 on both sides of the mesa portion 24 in the first direction X.

[0106] The source region 32 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more２１ cm －３ The n-type impurity concentration may have the following peak value:

[0107] 8 , source region 32 has a source thickness ST1. Source thickness ST1 may be the thickness of source region 32 in vertical direction Z from first main surface 3. Source thickness ST1 may be, for example, not less than 0.2 μm and not more than 1.0 μm, preferably not less than 0.4 μm and not more than 0.8 μm.

[0108] 5 and 7 , semiconductor device 1 includes first contact region 34 in a surface layer portion of first main surface 3. First contact region 34 is formed in a region between multiple gate structures 11. First contact region 34 is formed adjacent to source region 32 in a surface layer portion of body region 18 in the depth direction of mesa portion 24.

[0109] In this embodiment, a plurality of first contact regions 34 are formed across the mesa portion 24 in the width direction, from one side surface 22 to the other side surface 22 of the mesa portion 24. In each mesa portion 24, the plurality of source regions 32 and the plurality of first contact regions 34 are alternately arranged along the depth direction of the trench 19. Each source region 32 and each first contact region 34 is exposed from both side surfaces 22 of the trench 19 (both side surfaces 22 of the mesa portion 24).

[0110] 6 and 7 , the body region 18 includes a first body portion 35 ( FIG. 6 ) formed directly below the source region 32 and a second body portion 36 ( FIG. 7 ) formed directly below the first contact region 34. The first body portion 35 is a portion of the body region 18 that is sandwiched between the source region 32 and the drift region 8 in the depth direction of the trench 19. The second body portion 36 is a portion of the body region 18 that is sandwiched between the first contact region 34 and the drift region 8 in the depth direction of the trench 19.

[0111] 8 and 9, the first body portion 35 has a first body thickness BT1, and the second body portion 36 has a second body thickness BT2. The second body thickness BT2 is greater than the first body thickness BT1. Referring to FIGS. 5 to 7, the body region 18 forms a base interface 37 with the drift region 8. The base interface 37 is located at a certain depth from the bottom surface 23 of the trench 19 along the depth direction of the trench 19. As shown in FIG. 5, the body region 18 has a body protrusion 38 that selectively protrudes toward the first main surface 3 directly below the first contact region 34. The body protrusion 38 causes the body region 18 to have a second body portion 36 that is selectively thicker than the base interface 37.

[0112] 6, a first boundary surface 39 between the first body portion 35 and the source region 32 is located closer to the second main surface 4 than the upper surface 25 of the buried conductive layer 21. The first boundary surface 39 is formed at a position lower than the upper surface 25 of the buried conductive layer 21, and a first step 40 is formed between the upper surface 25 of the buried conductive layer 21 and the first boundary surface 39. A part of the source region 32 (for example, the lower end) faces the buried conductive layer 21 via the trench insulating film 20. This ensures the formation of a channel between the source and the drain.

[0113] 7 , a second boundary surface 41 between the second body portion 36 and the first contact region 34 is located closer to the first major surface 3 than the upper surface 25 of the buried conductive layer 21. The second boundary surface 41 is formed at a position higher than the upper surface 25 of the buried conductive layer 21, and a second step 42 is formed between the upper surface 25 of the buried conductive layer 21 and the second boundary surface 41. A portion (e.g., an upper end) of the second body portion 36 protrudes toward the first major surface 3 (upper side) than the buried conductive layer 21. The first contact region 34 does not directly contribute to the formation of a channel between the source and drain, and therefore, unlike the source region 32, does not need to face the buried conductive layer 21 via the trench insulating film 20. In FIG. 7 , the first boundary surface 39 is indicated by a dashed line for reference of the difference in elevation between the first boundary surface 39 and the second boundary surface 41.

[0114] The first contact region 34 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 18. The p-type impurity concentration (peak value) of the first contact region 34 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0115] 5 and 7 , the semiconductor device 1 includes a second contact region 43 in a surface layer portion of the first main surface 3. The second contact region 43 is connected to the first contact region 34 and the well region 12. The second contact region 43 is formed along the side surface 22 of the trench 19 from the first contact region 34 toward the second main surface 4 and is connected to the well region 12. In this embodiment, the second contact region 43 is formed from the first contact region 34 exposed from both side surfaces 22 of the mesa portion 24 along both the one side surface 22 and the other side surface 22 of the mesa portion 24.

[0116] The second contact region 43 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 18. The p-type impurity concentration (peak value) of the second contact region 43 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0117] The second contact region 43 is formed over the entire depth direction of the trench 19 from the top to the bottom of the trench 19. The second contact region 43 has a lower end near the bottom of the trench 19 and an upper end near the top of the trench 19.

[0118] The second contact region 43 penetrates the body region 18 and straddles the gap between the body region 18 and the well region 12. The second contact region 43 forms a boundary with the body region 18 and is connected to the body region 18. The second contact region 43 is further connected to the second semiconductor layer 7 (drift region 8) below the body region 18. That is, a pn junction is formed by the second contact region 43 and the drift region 8 in the section between the body region 18 and the well region 12.

[0119] 7 , the second contact region 43 is exposed from the side surface 22 of the trench 19 and is in contact with the trench insulating film 20 at the side surface 22 of the trench 19. The lower end of the second contact region 43 is in contact with the second layer 31 of the well region 12. As a result, a p-type integral impurity region 44 is formed in the second semiconductor layer 7 by the first contact region 34, the second contact region 43, and the second layer 31.

[0120] 7 , on the side surface 22 and the bottom surface 23 of the trench 19, the integral impurity region 44 partially covers the buried conductive layer 21 via the trench insulating film 20. More specifically, both end corners 45 of the trench 19 in the width direction are covered by the integral impurity region 44 having a generally Z-shaped cross section in the second relaxation portion 47. This makes it possible to suppress electric field concentration at the corners 45 of the trench 19.

[0121] 6 , in the first relaxation portion 46, a part of the well region 12 (second layer 31) may be spaced apart from the corner of the trench 19. That is, in the depth direction of the trench 19, the corner 45 of the trench 19 may have a part that is covered by the well region 12 and a part that is not covered by the well region 12.

[0122] In this embodiment, a plurality of integral impurity regions 44 are formed at intervals along the depth direction of the trench 19. The first contact region 34 and the second contact region 43 have the same width along the depth direction of the trench 19, and form strip-shaped integral impurity regions 44 of a constant width on the top surface (first main surface 3) of the mesa portion 24 and on the side surface 22 of the mesa portion 24 (side surface 22 of the trench 19).

[0123] 6 and 7, the integrated impurity region 44 has a width greater than that of the first layer 30 of the well region 12 in the width direction of the trench 19. This is because the second contact region 43 is connected to the side of the second layer 31, and the portion of the second layer 31 that is integrated with the second contact region 43 is selectively wider.

[0124] 9 , the second contact region 43 has a second contact thickness CT2. The second contact thickness CT2 may be the thickness of the second contact region 43 in the horizontal direction from the side surface 22 of the trench 19. The second contact thickness CT2 may be, for example, not less than 10 nm and not more than 200 nm, preferably not less than 20 nm and not more than 100 nm.

[0125] 9 , the first contact region 34 has a first contact thickness CT1. The first contact thickness CT1 may be the thickness of the first contact region 34 in the vertical direction Z from the first main surface 3. In this embodiment, the first contact thickness CT1 is greater than the second contact thickness CT2. The first contact thickness CT1 may be, for example, not less than 0.1 μm and not more than 1.0 μm, preferably not less than 0.2 μm and not more than 0.5 μm.

[0126] 8 and 9, in this embodiment, the ratio of the thickness of the first layer 30 to the second layer 31 of the well region 12 is different between the first relaxation portion 46 (FIG. 6) formed directly below the source region 32 and the second relaxation portion 47 (FIG. 7) formed directly below the first contact region 34.

[0127] More specifically, it is assumed that the first layer 30 has a first relaxation thickness RT1A (RT1B) and the second layer 31 has a second relaxation thickness RT2A (RT2B). In this case, the thickness ratio (RT2A / RT1A) of the second relaxation thickness RT2A to the first relaxation thickness RT1A in the first relaxation portion 46 shown in Figure 8 is smaller than the thickness ratio (RT2B / RT1B) in the second relaxation portion 47 shown in Figure 9. Of course, the thickness ratio (RT2A / RT1A) may be the same as the thickness ratio (RT2B / RT1B).

[0128] For example, if the total thickness RT0 (RT1A+RT2A or RT1B+RT2B) defined by the relaxation depth DR of well region 12 is the same in first relaxation portion 46 and second relaxation portion 47, the first relaxation thickness RT1A in first relaxation portion 46 is greater than the first relaxation thickness RT1B in second relaxation portion 47. Conversely, the second relaxation thickness RT2A in first relaxation portion 46 is less than the second relaxation thickness RT2B in second relaxation portion 47. However, if the thickness ratio (RT2A / RT1A) is the same as the thickness ratio (RT2B / RT1B), the first relaxation thickness RT1A may be equal to the first relaxation thickness RT1B, and the second relaxation thickness RT2A may be equal to the second relaxation thickness RT2B.

[0129] In this embodiment, the first relaxation thickness RT1A may be 0.2 μm or more and 1.0 μm or less, and the second relaxation thickness RT2A may be 0.2 μm or more and 1.0 μm or less. The first relaxation thickness RT1A is preferably 0.4 μm or more and 0.8 μm or less, and the second relaxation thickness RT2A is preferably 0.4 μm or more and 0.8 μm or less.

[0130] The first relaxation thickness RT1B may be 0.1 μm or more and 0.6 μm or less, and the second relaxation thickness RT2B may be 0.1 μm or more and 0.6 μm or less. The first relaxation thickness RT1B is preferably 0.2 μm or more and 0.5 μm or less, and the second relaxation thickness RT2B is preferably 0.2 μm or more and 0.5 μm or less.

[0131] 6 and 7 , a first boundary surface 48 between the first layer 30 and the second layer 31 in the first relaxation section 46 is located closer to the first main surface 3 than a second boundary surface 49 between the first layer 30 and the second layer 31 in the second relaxation section 47. Conversely, the second boundary surface 49 is located closer to the second main surface 4 than the first boundary surface 48.

[0132] 5 to 7, drift region 8 includes a stacked structure of base region 50 and high concentration region 51.

[0133] The base region 50 is formed closer to the second main surface 4 than the well region 12 and away from the body region 18. The base region 50 is formed in a layer shape extending along the first main surface 3 at a position away from the body region 18 and the trench 19 toward the second main surface 4. The base region 50 is formed over the entire surface portion of the second semiconductor layer 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 50 forms the boundary surface of the second semiconductor layer 7 with the first semiconductor layer 6.

[0134] 8 and 9, base region 50 has a base thickness BT. Base thickness BT may be equal to or greater than 0.5 μm and equal to or less than 20 μm. Base thickness BT is preferably equal to or greater than 1 μm and equal to or less than 10 μm.

[0135] The n-type impurity concentration of the base region 50 is preferably lower than the n-type impurity concentration of the first semiconductor layer 6. The base region 50 has a dopant concentration of 1×10 １５ cm －３ 5x10 or more １６ cm －３ The n-type impurity concentration may have the following peak value:

[0136] 5 to 7, regarding the relationship between the well region 12 and the base region 50, the first layer 30 of the well region 12 is formed to a depth that reaches the base region 50 in the thickness direction of the chip 2. More specifically, the bottom of the first layer 30 of the well region 12 is in contact with the base region 50, forming a boundary between the well region 12 and the base region 50.

[0137] The high-concentration region 51 is formed between the base region 50 and the body region 18, on the side of the trench 19 and the well region 12. The high-concentration region 51 is in contact with the body region 18 and is formed in a layer shape extending along the first main surface 3. The high-concentration region 51 is formed in the entire surface portion of the drift region 8 on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the high-concentration region 51 forms the boundary surface between the drift region 8 and the body region 18.

[0138] In this embodiment, the high-concentration region 51 contacts the sides of the first layer 30 and the second layer 31 of the well region 12 over the entire thickness direction of the chip 2, from the first main surface 3 side to the second main surface 4 side. The high-concentration region 51 also covers the boundary between the bottom of the trench 19 and the well region 12 (see FIG. 6 ).

[0139] The n-type impurity concentration of the high concentration region 51 is preferably higher than the n-type impurity concentration of the base region 50. The high concentration region 51 has a concentration of 1×10 １８ cm －３ 1x10 or more １９ cm －３ The n-type impurity concentration may have the following peak value:

[0140] 8 and 9, regarding the thickness of high concentration region 51, first thickness HT1 of high concentration region 51 may be not less than 0.6 μm and not more than 2.5 μm.

[0141] The semiconductor device 1 includes a buried insulating layer 55 buried in the recess 27 of the second semiconductor layer 7. The buried insulating layer 55 may also be referred to as an "interlayer insulating layer," an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this form, the buried insulating layer 55 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0142] 6 and 7 , the buried insulating layer 55 is buried in the recess 27 so that an upper edge 56 of the trench 19 is exposed from the first main surface 3. The upper edge 56 of the trench 19 may be a portion at the top of the trench 19 where the side surface 22 of the trench 19 intersects with the first main surface 3. In other words, the buried insulating layer 55 does not cover the periphery of the trench 19 on the first main surface 3, but is contained within the inner region of the trench 19 in the width direction of the trench 19. In this form, the upper surface 57 of the buried insulating layer 55 is located closer to the bottom of the trench 19 than the first main surface 3 in the depth direction of the trench 19.

[0143] 5, buried insulating layer 55 is embedded in recess 27 over the entire depth direction of trench 19, and is formed in a strip shape extending in the depth direction of trench 19. Referring to Figures 6 and 7, buried insulating layer 55 contacts source region 32 and first contact region 34 on side surface 22 of recess 27 (side surface 22 of trench 19).

[0144] 8 and 9 , buried insulating layer 55 may have a thickness IT of, for example, 0.05 μm to 0.8 μm inclusive. Thickness IT may have a value belonging to at least one of the ranges of 0.05 μm to 0.3 μm inclusive, 0.3 μm to 0.55 μm inclusive, and 0.55 μm to 0.8 μm inclusive.

[0145] 6 and 7 , semiconductor device 1 includes silicide layers 58 formed on the surfaces of source region 32 and first contact region 34. Formation of silicide layer 58 can reduce contact resistance with source region 32 and first contact region 34.

[0146] In this embodiment, the silicide layer 58 is selectively formed on the protruding portion 28 of each mesa portion 24. More specifically, the silicide layer 58 is formed along the upper surface (first main surface 3) and the side surface 22 (side surface 22 of the recess 27) of the protruding portion 28 of the mesa portion 24. A non-silicide portion 59 defined by the silicide layer 58 (surrounded on three sides) may be formed in the inner portion of the protruding portion 28 of the mesa portion 24 away from the upper surface (first main surface 3) and the side surface 22 of the mesa portion 24 inward.

[0147] The silicide layer 58 may be, for example, nickel silicide, titanium silicide, aluminum silicide, copper silicide, etc. The thickness ST2 of the silicide layer 58 may be, for example, 50 nm or more and 500 nm or less in the vertical direction Z from the upper surface (first main surface 3) and side surface 22 of the protruding portion 28 of the mesa portion 24. The thickness ST2 of the silicide layer 58 is preferably 80 nm or more and 300 nm or less.

[0148] 6 and 7 , semiconductor device 1 includes a first principal surface electrode 60. First principal surface electrode 60 is formed on first principal surface 3 so as to cover buried insulating layer 55. First principal surface electrode 60 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first principal surface 3 side.

[0149] The barrier layer 61 is formed in a film shape along the first main surface 3 and the inner surfaces of the recess 27 (the side surfaces 22 of the recess 27 and the upper surface 57 of the buried insulating layer 55). The barrier layer 61 is in ohmic contact with the silicide layer 58. The barrier layer 61 further defines a second recess 63 within the recess 27.

[0150] The barrier layer 61 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier layer 61 may be 0.05 μm or more and 0.3 μm or less. The thickness of the barrier layer 61 is preferably 0.1 μm or more and 0.2 μm or less.

[0151] The main body layer 62 is formed on the barrier layer 61. The main body layer 62 covers the entire main surface of the barrier layer 61. The main body layer 62 is partially embedded in the second recess 63. The main body layer 62 is ohmically connected to the source region 32 and the first contact region 34 via the barrier layer 61 and the silicide layer 58. In this embodiment, the first main surface electrode 60 is connected to the source region 32 and the first contact region 34 at the side surface 22 of the recess 27 and the first main surface 3. Therefore, in the semiconductor device 1, the first main surface electrode 60 may include the source pad electrode 70 described above. The well region 12 is fixed to the source potential via the first contact region 34 and the second contact region 43.

[0152] The main body layer 62 includes at least one of a pure Al layer (meaning an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0153] The thickness of the main layer 62 exceeds the thickness of the barrier layer 61. The thickness of the main layer 62 may be 1 μm or more and 10 μm or less. The thickness of the main layer 62 is preferably 3 μm or more and 6 μm or less.

[0154] The semiconductor device 1 includes a resin layer 64 that covers the first principal surface electrode 60. The resin layer 64 is formed in the form of a film along the principal surface of the first principal surface electrode 60. The resin layer 64 may include a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 64 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 64 includes polybenzoxazole.

[0155] [Detailed Structure of the Vicinity of the Peripheral Region 10 of the Semiconductor Device 1] Fig. 10 is an enlarged plan view showing a main portion of the active region 9. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 10. Fig. 12 is a cross-sectional view showing the peripheral region 10. With reference to Figs. 10 to 12, the detailed structure of the peripheral region 10 and the vicinities of the peripheral region 10 of the active region 9 will be described.

[0156] 11 and 12 , the aforementioned outer well region 13 is formed in the surface layer portion of the first main surface 3 in the peripheral region 10 (the peripheral portion of the first main surface 3). A source potential is applied to the outer well region 13. The outer well region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the body region 18.

[0157] The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the first contact region 34. The p-type impurity concentration of the outer well region 13 is lower than the p-type impurity concentration of the second layer 31 of the well region 12. The p-type impurity concentration of the outer well region 13 may be higher or lower than the p-type impurity concentration of the first layer 30 of the well region 12.

[0158] The outer well region 13 is formed in a surface layer portion of the second semiconductor layer 7. The outer well region 13 extends in a layered manner along the first main surface 3. The outer well region 13 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the multiple gate structures 11. The outer well region 13 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 9) in a plan view.

[0159] In this embodiment, the outer well region 13 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 9) of the first main surface 3. In other words, the outer well region 13 collectively surrounds the multiple gate structures 11.

[0160] The outer well region 13 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 13 has an inner edge portion on the side of the multiple gate structures 11 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 13 defines the boundary between the active region 9 and the outer periphery region 10.

[0161] The inner edge of the outer well region 13 is connected to the ends of the multiple gate structures 11 in a portion extending in the first direction X. The inner edge of the outer well region 13 faces the buried conductive layer 21 with the trench insulating film 20 interposed therebetween.

[0162] The inner edge of the outer well region 13 may be located closer to the inner side of the plurality of gate structures 11 than the ends of the plurality of gate structures 11. The inner edge of the outer well region 13 may have a portion located in a region between the plurality of gate structures 11 and connected to the body region 18. The outer edge of the outer well region 13 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 13.

[0163] The outer well region 13 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 13 may have a value belonging to at least one of the ranges greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0164] The outer well region 13 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 across a part of the second semiconductor layer 7. The outer well region 13 may be formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor layer 7 (toward the second main surface 4) with respect to the depth position of the intermediate portion of the second semiconductor layer 7.

[0165] In this embodiment, the outer well region 13 is formed at an interval toward the first main surface 3 from the depth position of the bottom walls of the plurality of gate structures 11. The depth of the outer well region 13 may be greater or smaller than the depth of the body region 18.

[0166] The outer well region 13 may have a portion located on the bottom side of the second semiconductor layer 7 relative to the depth positions of the bottom walls of the plurality of gate structures 11. In this case, the outer well region 13 may be connected to either or both of the second layer 31 of the well region 12 and the first layer 30 of the well region 12.

[0167] The outer well region 13 forms a pn junction with the second semiconductor layer 7. The outer well region 13 spreads a depletion layer into the second semiconductor layer 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 13 spreads in the horizontal and thickness directions and integrates with the depletion layers spreading from the body region 18 and the well region 12. The outer well region 13 expands the depletion layers spreading from the body region 18 and the well region 12 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 10) of the first main surface 3.

[0168] The semiconductor device 1 includes a p-type outer contact region 71 formed in a surface layer portion of the outer well region 13. The outer contact region 71 has a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 13. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the body region 18.

[0169] The p-type impurity concentration of the outer contact region 71 may be approximately equal to the p-type impurity concentration of the first contact region 34. The p-type impurity concentration of the outer contact region 71 may be higher or lower than the p-type impurity concentration of the first contact region 34.

[0170] The outer contact region 71 is formed at a distance from the bottom of the outer well region 13 toward the first main surface 3, and faces the second semiconductor layer 7 across a part of the outer well region 13. The outer contact region 71 extends in a strip shape along the outer well region 13 (active region 9) in a plan view.

[0171] In this embodiment, the outer contact region 71 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0172] The semiconductor device 1 may include a plurality of outer contact regions 71 arranged at intervals along the extension direction of the outer well region 13 so as to surround the plurality of gate structures 11. In this case, the plurality of outer contact regions 71 may each extend in a strip shape along the extension direction of the outer well region 13.

[0173] The outer contact region 71 has a width less than the width of the outer well region 13, and is formed in the outer well region 13. The outer contact region 71 is formed in the inner part of the outer well region 13 with a gap between both edges of the outer well region 13. The outer contact region 71 is biased toward the outer edge of the outer well region 13 relative to the central part of the outer well region 13. The outer contact region 71 may be formed in the central part of the outer well region 13.

[0174] 11 and 12 , the above-mentioned surface insulating film 15 extends from the peripheral region 10 to the active region 9 and covers the peripheries of the ends of the plurality of gate structures 11 in the active region 9. The surface insulating film 15 is connected to the trench insulating film 20 of the plurality of gate structures 11 and exposes the buried conductive layer 21 and the buried insulating layer 55. The surface insulating film 15 has a portion located in a region between the plurality of gate structures 11. The surface insulating film 15 is connected to the trench insulating film 20 at both the portion extending in the first direction X and the portion extending in the second direction Y of the ends of the plurality of gate structures 11.

[0175] The surface insulating film 15 directly covers the first main surface 3 around the plurality of gate structures 11. The surface insulating film 15 selectively covers the peripheral region of the first main surface 3 relative to the plurality of gate structures 11 in a film-like manner.

[0176] The surface insulating film 15 covers the outer well region 13 and the plurality of field regions 14. The surface insulating film 15 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. The surface insulating film 15 may be formed in a polygonal ring shape (quadratic ring shape) surrounding the plurality of gate structures 11 (active regions 9) in plan view.

[0177] The surface insulating film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0178] The semiconductor device 1 includes a main surface insulating film 69 formed on the first main surface 3. The main surface insulating film 69 extends from the peripheral region 10 toward the active region 9 to the gate structure 11, and is formed integrally with the trench insulating film 20. The main surface insulating film 69 may be an extension portion that is extended from the gate structure 11 toward the peripheral region 10.

[0179] The main surface insulating film 69 covers the first main surface 3 and the surface insulating film 15 exposed between the gate structure 11 and the surface insulating film 15. The main surface insulating film 69 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 69 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D.

[0180] The main surface insulating film 69 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0181] The aforementioned gate wiring 66 is disposed on the main surface insulating film 69 and the surface insulating film 15. The gate wiring 66 is selectively routed on the main surface insulating film 69 and the surface insulating film 15 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 11, and faces the outer well region 13 with the main surface insulating film 69 and the surface insulating film 15 interposed therebetween.

[0182] The gate wiring 66 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 66 is disposed on the main surface insulating film 69 and faces the outer well region 13 with the main surface insulating film 69 in between. The inner edge portion of the gate wiring 66 covers the ends (both ends in this embodiment) of the multiple gate structures 11 and is mechanically and electrically connected to the multiple gate structures 11.

[0183] Specifically, the inner edge of the gate wiring 66 is mechanically and electrically connected to the plurality of buried conductive layers 21. In this embodiment, the inner edge of the gate wiring 66 is integrally formed with the plurality of buried conductive layers 21. In other words, the gate wiring 66 is formed as an extension of the plurality of buried conductive layers 21, and is drawn out from the trench 19 onto the main surface insulating film 69.

[0184] The outer edge of the gate wiring 66 is formed as an extension portion that is extended from above the main surface insulating film 69 onto the laminated structure of the main surface insulating film 69 and the surface insulating film 15, and is disposed on this laminated structure. The outer edge of the gate wiring 66 faces the outer well region 13 with the main surface insulating film 69 and the surface insulating film 15 sandwiched therebetween.

[0185] The outer edge of the gate wiring 66 is formed at a distance from the plurality of field regions 14 toward the plurality of gate structures 11. Specifically, the outer edge of the gate wiring 66 is formed at a distance from the outer edge of the outer well region 13 toward the plurality of gate structures 11. The outer edge of the gate wiring 66 is formed at a distance from the inner edge of the outer contact region 71 toward the plurality of gate structures 11.

[0186] The semiconductor device 1 may include a plurality of gate wirings 66. In this case, the plurality of gate wirings 66 may be arranged at least at both ends of the plurality of gate structures 11. One of the gate wirings 66 may have a portion extending in a strip shape in the first direction X and intersect (specifically, orthogonal to) one end of the plurality of gate structures 11. The other of the gate wirings 66 may have a portion extending in a strip shape in the first direction X and intersect (specifically, orthogonal to) the other end of the plurality of gate structures 11. Of course, the plurality of gate wirings 66 may have a portion extending in the second direction Y.

[0187] The interlayer film 65 described above covers the main surface insulating film 69 in a film form in the peripheral region 10. Specifically, the interlayer film 65 directly covers the main surface insulating film 69 in a film form, and faces the outer well region 13, the outer contact region 71, and the plurality of field regions 14 with the main surface insulating film 69 in between.

[0188] The interlayer film 65 covers the gate wiring 66 and the gate pad wiring 67. The interlayer film 65 covers the entire gate wiring 66 and the entire gate pad wiring 67. The interlayer film 65 has a portion facing the main surface insulating film 69 with the gate wiring 66 interposed therebetween, and a portion facing the main surface insulating film 69 with the gate wiring 66 interposed therebetween. The interlayer film 65 has a portion facing the outer well region 13 with the gate wiring 66 interposed therebetween, and a portion facing the outer well region 13 with the gate pad wiring 67 interposed therebetween.

[0189] The interlayer film 65 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the interlayer film 65 is disposed in the active region 9. The inner edge portion of the interlayer film 65 is positioned on the inner side of the first main surface 3 with respect to the inner edge portion of the gate wiring 66 and the peripheral edge portion of the gate pad wiring 67, and covers the ends of the multiple gate structures 11.

[0190] The inner edge of the interlayer film 65 covers the buried conductive layer 21 at the ends of the multiple gate structures 11 and is connected to the buried insulating layer 55. In this embodiment, the interlayer film 65 is formed integrally with the buried insulating layer 55. The portion of the interlayer film 65 located within the trench 19 is formed as the buried insulating layer 55. The connection portion of the interlayer film 65 to the buried insulating layer 55 may be considered as part of the buried insulating layer 55 or may be considered as part of the interlayer film 65.

[0191] The inner edge of the interlayer film 65 has a portion located in a region between the plurality of gate structures 11. The inner edge of the interlayer film 65 covers either or both of the body region 18 and the outer well region 13 in the region between the plurality of gate structures 11, with the surface insulating film 15 sandwiched therebetween.

[0192] The outer edge of the interlayer film 65 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the interlayer film 65 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the surface insulating film 15.

[0193] The semiconductor device 1 includes one or more (one in this embodiment) source openings 68 formed in the interlayer film 65. The source opening 68 penetrates the interlayer film 65 in the inner portion of the active region 9, collectively exposing the plurality of gate structures 11 and the plurality of mesa portions 24. In this embodiment, the source opening 68 is formed in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view (in this embodiment, a quadrilateral shape having a recessed portion recessed along the gate pad wiring 67).

[0194] The source openings 68 are formed at intervals from the ends (both ends in this embodiment) of the plurality of gate structures 11 toward the inner portion of the first main surface 3, and expose the inner portions of the plurality of gate structures 11 and the inner portions of the plurality of mesa portions 24. Specifically, the source openings 68 expose the trench insulating film 20 and the buried insulating layer 55 in the inner portions of the plurality of gate structures 11.

[0195] The above-described gate finger electrode 81 may be a part of the first main surface electrode 60. Like the source pad electrode 70, the gate finger electrode 81 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first main surface 3 side.

[0196] The gate finger electrodes 81 extend into the plurality of gate openings 79 from above the interlayer film 65, and are mechanically and electrically connected to the gate wiring 66 within the plurality of gate openings 79. As a result, the gate potential applied to the gate pad electrode 80 is applied to the plurality of gate structures 11 via the gate finger electrodes 81. More specifically, the gate finger electrodes 81 are mechanically and electrically connected to the gate wiring 66 through the gate openings 79.

[0197] The plurality of gate openings 79 penetrate the interlayer film 65 and selectively expose the gate wiring 66. In this embodiment, the plurality of gate openings 79 extend in a strip shape following the direction in which the gate wiring 66 extends.

[0198] The plurality of gate openings 79 may be formed at intervals along the extension direction of the gate wiring 66. The plurality of gate openings 79 may be formed in a polygonal or circular shape in a plan view. For example, the plurality of gate structures 11 may be formed in a quadrangular or hexagonal shape in a plan view.

[0199] The plurality of gate openings 79 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 79 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0200] The gate finger electrode 81 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 81 is formed at a distance from the ends of the multiple gate structures 11 toward the peripheral side of the first main surface 3. In other words, the gate finger electrode 81 does not face the multiple gate structures 11 in the stacking direction.

[0201] The inner edge of the gate finger electrode 81 is disposed on the gate wiring 66. The inner edge of the gate finger electrode 81 faces the peripheral edge of the source pad electrode 70 in the horizontal direction above the gate wiring 66. The inner edge of the gate finger electrode 81 is formed at a distance from the middle of the gate wiring 66 towards the peripheral edge of the first main surface 3.

[0202] The outer edge of the gate finger electrode 81 is drawn out from above the gate wiring 66 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the gate wiring 66. In other words, the outer edge of the gate finger electrode 81 does not face the gate wiring 66 in the stacking direction. The outer edge of the gate finger electrode 81 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0203] The outer edge of the gate finger electrode 81 is disposed at a distance from the outer edge of the outer well region 13 toward the inside of the first main surface 3, and faces the outer well region 13 across the surface insulating film 15 and the interlayer film 65. The outer edge of the gate finger electrode 81 is disposed on the peripheral side of the first main surface 3 relative to the outer edge of the outer well region 13, and may face the second semiconductor layer 7 in the stacking direction.

[0204] The above-described source finger electrode 85 may be a part of the first principal surface electrode 60. Like the source pad electrode 70, the source finger electrode 85 has a laminated structure including a barrier layer 61 and a main body layer 62 laminated in this order from the first principal surface 3 side.

[0205] The source finger electrodes 85 extend into the plurality of outer openings 83 from above the interlayer film 65, and are mechanically and electrically connected to the outer contact regions 71 within the plurality of outer openings 83. As a result, the gate potential applied to the source pad electrode 70 is applied to the plurality of gate structures 11 via the source finger electrodes 85.

[0206] The outer opening 83 is formed at a distance from the gate wiring 66 toward the peripheral edge of the first main surface 3. The outer opening 83 penetrates the surface insulating film 15 and the interlayer film 65 to expose the outer contact region 71.

[0207] The outer opening 83 has a width less than the width of the outer contact region 71, and exposes an inner portion of the outer contact region 71 at a distance from the inner and outer edges of the outer contact region 71. The outer opening 83 may expose the outer well region 13.

[0208] In this embodiment, the outer opening 83 extends in a strip shape following the extension direction of the outer contact region 71. In this embodiment, the outer opening 83 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the multiple gate structures 11 (active regions 9). The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0209] The semiconductor device 1 may have a plurality of outer openings 83. In this case, the plurality of outer openings 83 may be formed at intervals following the extension direction of the outer contact region 71. Furthermore, the plurality of outer openings 83 may each extend in a strip shape following the extension direction of the outer contact region 71.

[0210] The source finger electrodes 85 have inner edges on the inward side of the first main surface 3 and outer edges on the peripheral side of the first main surface 3. The inner edges of the source finger electrodes 85 are spaced apart from the gate finger electrodes 81 on the peripheral side of the first main surface 3, and face the gate finger electrodes 81 in the horizontal direction.

[0211] The inner edge of the source finger electrode 85 is formed at a distance from the middle of the outer contact region 71 toward the inside of the first main surface 3. The inner edge of the source finger electrode 85 may be disposed on the outer well region 13 or on the outer contact region 71.

[0212] The outer edge of the source finger electrode 85 is drawn out from above the outer contact region 71 toward the peripheral edge of the first main surface 3, and is disposed on the interlayer film 65 in a region outside the outer contact region 71. The outer edge of the source finger electrode 85 is disposed at a distance from the innermost field region 14 toward the inside of the first main surface 3.

[0213] The outer edge of the source finger electrode 85 is disposed at a distance from the outer edge of the outer well region 13 toward the inside of the first main surface 3, and faces the outer well region 13 across the interlayer film 65. The outer edge of the source finger electrode 85 may be drawn out from the outer edge of the outer well region 13 toward the periphery of the first main surface 3, and faces the second semiconductor layer 7 across the interlayer film 65.

[0214] [Rectifying Element PBR Built into Active Region 9] In the semiconductor device 1 according to this embodiment, a rectifying element PBR is built into the active region 9. The rectifying element PBR is a PBR (Pinched Barrier Rectifier) ​​arranged using a part of the active region 9. Several forms of the PBR will be described below with reference to FIGS. 13 to 30 .

[0215] (1) First Form Figures 13 to 15 are plan views showing layout examples of the transistor region Tr and the blank region Bs. Figures 13 to 15 selectively show a part of the active region 9 (the region where the rectifying element PBR is arranged). The layout examples shown in Figures 13 to 15 may be applied to a part of the active region 9 in Figure 5.

[0216] 13 to 15, the plurality of mesas 24 (unit cells UC) include a plurality of blank spaces Bs formed by selectively removing the body region 18.

[0217] 13 and 14 , blank regions Bs and transistor regions Tr excluding the blank regions Bs are formed in each of the plurality of stripe-shaped mesas 24. In each stripe-shaped mesa 24, the blank regions Bs and the transistor regions Tr are disposed adjacent to each other in the depth direction of the mesa 24. In this embodiment, the blank regions Bs and the transistor regions Tr are alternately arranged in the depth direction of the mesa 24. The layout of the blank regions Bs for the plurality of stripe-shaped mesas 24 may be in a matrix pattern as shown in FIG. 13 or a staggered pattern as shown in FIG. 14 .

[0218] 15 , the plurality of transistor regions Tr and the plurality of blank regions Bs may be formed in separate mesa portions 24. For example, the plurality of mesa portions 24 may include mesa portions 24 for the transistor regions Tr and mesa portions 24 for the blank regions Bs, which are independent of each other. In FIG. 15 , the mesa portions 24 for the plurality of transistor regions Tr and the mesa portions 24 for the plurality of blank regions Bs are alternately arranged in the first direction X. In each mesa portion 24, a strip-shaped transistor region Tr or blank region Bs is arranged extending over the entire depth direction of the mesa portion 24.

[0219] Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 5, showing a first embodiment of the rectifying element PBR. Next, a specific structure of the rectifying element PBR arranged in the blank region Bs will be described with reference to Figs. 5 and 16.

[0220] The rectifying element PBR has an element structure arranged in a surface layer portion on the first main surface 3 side of the second semiconductor layer 7. The rectifying element PBR includes a second channel region 102, a second channel contact region 103, and a shield region 101 in the drift region 8 in which the gate structure 11 is formed.

[0221] The second channel region 102 is an impurity region that provides a current path for the rectifying element PBR. The second channel region 102 is formed by a part of the drift region 8 disposed between adjacent trenches 19. In comparison with the MIS transistor structure of the transistor region Tr (see FIG. 6 ), the body region 18 is removed from the MIS transistor structure, and the region where the body region 18 is formed is replaced with the drift region 8.

[0222] The second channel region 102 faces the buried conductive layer 21 via the shield region 101 and the trench insulating film 20 in a direction (first direction X) perpendicular to the depth direction of the trench 19. In this embodiment, the second channel region 102 is formed from the bottom of the buried conductive layer 21 to a position closer to the first main surface 3 than the center of the buried conductive layer 21 in the depth direction of the trench 19. For example, the second channel region 102 may face a range of more than 50% to 80% of the entire thickness of the buried conductive layer 21 in the depth direction of the trench 19.

[0223] The n-type impurity concentration of the second channel region 102 is preferably higher than the n-type impurity concentration of the base region 50 and lower than the n-type impurity concentration of the high concentration region 51. The second channel region 102 has a concentration of 5×10 １５ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration may have the following peak value: By keeping the n-type impurity concentration of the second channel region 102 low, it is possible to make it easier for a depletion layer to spread in the second channel region 102 .

[0224] The second channel contact region 103 is formed in the blank region Bs in the surface layer portion of the first main surface 3 of the mesa portion 24. With reference to Fig. 5 , the second channel contact region 103 is provided by an extension of the source region 32 in the depth direction of the trench 19. The second channel contact region 103 may be in the shape of a strip that is continuous with the source region 32 and extends in the depth direction of the trench 19.

[0225] 16 , the second channel contact region 103 is disposed in a region directly above the second channel region 102 in the depth direction of the mesa portion 24. In the blank region Bs of the mesa portion 24, a stacked structure of the second channel region 102 and the second channel contact region 103 is formed in this order from the bottom side of the trench 19 toward the first main surface 3.

[0226] The second channel contact region 103 is formed across the mesa portion 24 in the width direction, from one side surface 22 to the other side surface 22 of the mesa portion 24 (one side surface 22 and the other side surface 22 of the trench 19). In a direction (first direction X) perpendicular to the depth direction of the trench 19, the second channel contact region 103 is in direct contact with the trench insulating film 20 and the buried insulating layer 55. A portion of the second channel contact region 103 faces the buried conductive layer 21 via the trench insulating film 20. In this embodiment, a lower portion 100 of the second channel contact region 103 faces the buried conductive layer 21 via the trench insulating film 20.

[0227] The second channel contact region 103 is connected to the second channel region 102 in the depth direction of the trench 19. In this embodiment, the second channel contact region 103 has a bottom 104 connected to the second channel region 102.

[0228] The n-type impurity concentration of the second channel contact region 103 is preferably higher than the n-type impurity concentration of the second channel region 102. The n-type impurity concentration of the second channel contact region 103 may be the same as the n-type impurity concentration of the source region 32. The second channel contact region 103 has an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0229] The contact thickness CT4 of the second channel contact region 103 in the vertical direction Z from the first major surface 3 may be the same as the source thickness ST1 (for example, 0.2 μm or more and 1.0 μm or less, preferably 0.4 μm or more and 0.8 μm or less).

[0230] A silicide layer 58 is formed on the surface of the second channel contact region 103, similar to the source region 32 and the first contact region 34. By forming the silicide layer 58, the contact resistance to the second channel contact region 103 can be reduced.

[0231] 16 , the shield region 101 is disposed on the side surface 22 of the trench 19. The shield region 101 is connected to the second channel contact region 103 and the well region 12. The shield region 101 is formed along the side surface 22 of the trench 19 from the bottom 104 of the second channel contact region 103 toward the second main surface 4, and is connected to the well region 12.

[0232] The shield region 101 sandwiches the second channel region 102 between adjacent trenches 19 in the blank region Bs. The shield region 101 is an impurity region formed in the same process as the second contact region 43, and has the same impurity concentration and thickness as the second contact region 43.

[0233] The p-type impurity concentration of the shield region 101 is higher than the p-type impurity concentration of the body region 18. The shield region 101 has a p-type impurity concentration of, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0234] The shield thickness ST3 of the shield region 101 in the horizontal direction from the side surface 22 of the trench 19 may be the same as the second contact thickness CT2 (for example, 10 nm to 200 nm, preferably 20 nm to 100 nm). The channel thickness CT3 in the same direction of the second channel region 102 sandwiched by the shield regions 101 may be greater than the shield thickness ST3. The channel thickness CT3 may be, for example, 100 nm to 1000 nm, preferably 150 nm to 500 nm.

[0235] 5 , the shield region 101 is electrically connected to the integral impurity region 44 via the well region 12 extending in the depth direction of the trench 19. The shield region 101 may be extended from the first contact region 34 toward the blank region Bs by the second contact region 43 and the well region 12 along the depth direction of the trench 19, and may be provided by an impurity region integral with the first contact region 34. Therefore, the shield region 101 is ohmically connected to the source pad electrode 70 by a current path that runs from the well region 12 through the second contact region 43 and the first contact region 34. The shield region 101 is fixed to the source potential.

[0236] The shield region 101 is formed over the entire depth direction from the bottom 104 of the second channel contact region 103 to the bottom surface 23 of the trench 19. The shield region 101 has a lower end near the bottom surface 23 of the trench 19 and an upper end near the bottom 104 of the second channel contact region 103. In this embodiment, the upper end of the shield region 101 is located in the middle of the trench 19 in the depth direction. The second channel contact region 103 crosses the boundary between the shield region 101 and the second channel region 102 in a direction (first direction X) perpendicular to the depth direction of the trench 19.

[0237] The source pad electrode 70 is directly ohmically connected to the second channel contact region 103 within the recess 27. The source pad electrode 70 is ohmically connected to the second channel region 102 via the silicide layer 58 and the second channel contact region 103. The second channel region 102 is ohmically connected to the drain pad electrode 87 via the first semiconductor layer 6 on the second main surface 4 side. As a result, a current path is provided between the source pad electrode 70 and the drain pad electrode 87 (between the source and the drain) via the second channel region 102 and the second channel contact region 103.

[0238] 17 is a diagram showing the circuit configuration of the semiconductor device 1. As shown in FIG. 16, the semiconductor device 1 has a rectifier element PBR formed by utilizing a part of the active region 9. As a result, the body diode BDi and the rectifier element PBR are connected in parallel between the source and drain of the MIS transistor Tr, which includes the source region 32 (S), the first semiconductor layer 6 (D), and the buried conductive layer 21 (G). Referring to FIG. 6, the body diode BDi is a diode formed by a pn junction between the body region 18 and the drift region 8.

[0239] When a forward voltage is applied between the source and drain of the MIS transistor Tr to turn on the MIS transistor Tr, a reverse voltage is applied to the pn junction between the p-type shield region 101 and the n-type second channel region 102 in the rectifier element PBR. As a result, a depletion layer extending horizontally from the pn junction toward the inside of the mesa portion 24 closes the current path in the second channel region 102, turning off the rectifier element PBR. On the other hand, when a reverse voltage is applied between the source and drain of the MIS transistor Tr, the depletion layer opens, establishing conduction between the source pad electrode 70 and the drain pad electrode 87 via the second channel region 102. As a result, a current IA flows from the source pad electrode 70 to the drain pad electrode 87, as shown in FIG. 16 .

[0240] Since the rectifier element PBR connected in parallel to the body diode BDi is incorporated in the active region 9, current can be preferentially passed through the rectifier element PBR when the MIS transistor Tr is in reverse conduction (when a reverse voltage is applied). In a SiC semiconductor device, when a current flows through the body diode BDi, stacking faults in the SiC semiconductor layer (for example, the second semiconductor layer 7) may expand, resulting in degradation of device characteristics (increased on-resistance, increased leakage current, etc.). However, in the semiconductor device 1, the rectifier element PBR is provided in the active region 9, so this type of degradation of device characteristics can be suppressed.

[0241] Since the second channel contact region 103 is disposed in a region directly above the second channel region 102, the current path of the rectifier element PBR can be ensured to be a short path from the first main surface 3 toward the second main surface 4. This reduces the resistance of the current path of the rectifier element PBR, allowing current to flow preferentially through the rectifier element PBR compared to the body diode BDi.

[0242] One possible means for suppressing the degradation of the device characteristics described above is to incorporate a Schottky barrier diode instead of the rectifying element PBR. In a Schottky barrier diode, a Schottky metal must be junctioned with the drift region 8. The Schottky barrier disappears when the first main surface 3 is silicided. Therefore, when forming the silicide layer 58, the first main surface 3 must be selectively masked, which increases the number of manufacturing steps and complicates the structure.

[0243] In this form of semiconductor device 1, a rectifying element PBR that is ohmically connected to the source pad electrode 70 is used without using a Schottky barrier diode, which solves the problems of an increase in the number of manufacturing steps and a complicated structure.

[0244] (2) Second Form Fig. 18 is a cross-sectional view showing a second form of the rectifying element PBR, and corresponds to Fig. 16. The rectifying element PBR in Fig. 18 differs from the rectifying element PBR in Fig. 16 in that the second channel contact region 103 is omitted.

[0245] 18 , the second channel region 102 extends from the bottom of the trench 19 to the first main surface 3 of the mesa portion 24 (the opening end of the trench 19), and is exposed from the first main surface 3. The silicide layer 58 is formed on the portion (exposed surface) of the second channel region 102 exposed from the first main surface 3. As a result, the source pad electrode 70 is in direct ohmic contact with the second channel region 102 via the silicide layer 58.

[0246] The shield region 101 extends along the side surface 22 of the trench 19 in the depth direction of the trench 19, crossing the boundary between the trench insulating film 20 and the buried insulating layer 55. In this embodiment, the upper end of the shield region 101 is located at or near the upper surface 57 of the buried insulating layer 55 in the depth direction of the trench 19.

[0247] Like the rectifier element PBR of the first embodiment, the rectifier element PBR of the second embodiment also allows current to flow preferentially through the rectifier element PBR when the MIS transistor Tr is in reverse conduction (when a reverse voltage is applied).

[0248] Furthermore, according to the rectifier PBR of the second embodiment, the length of the shield region 101 in the depth direction of the trench 19 can be made longer than in the first embodiment. This is because, in the second embodiment, the shield region 101 extends from the bottom of the trench 19 beyond the upper surface 25 of the buried conductive layer 21 toward the first main surface 3. As a result, even if there is variation in the extension width of the depletion layer in the horizontal direction, the shield region 101 is long in the vertical direction, so that the second channel region 102 can be reliably opened and closed by the depletion layer at some position in the depth direction of the trench 19. As a result, the reliability of the rectifier PBR can be improved.

[0249] (3) Third Form Figures 19 to 21 are plan views showing layout examples of the transistor region Tr and the blank region Bs. Figures 22 and 23 are perspective views showing a third form of the rectifying element PBR. Figure 24A is a cross-sectional view of section A shown in Figures 19 to 21. Figure 24B is a cross-sectional view of section B shown in Figures 19 to 21. Figure 24C is a cross-sectional view of section C shown in Figures 20 and 21. Figure 24D is a cross-sectional view of section D shown in Figure 21.

[0250] The rectifying element PBR of the third embodiment differs from the rectifying element PBR of the first embodiment and the rectifying element PBR of the second embodiment in that the position of the ohmic contact between the second channel region 102 and the source pad electrode 70 is away from the region directly above the second channel region 102 in the depth direction of the trench 19.

[0251] In the first configuration, a second channel contact region 103 is disposed in a region directly above the second channel region 102, and the second channel region 102 and the source pad electrode 70 are in ohmic contact via this second channel contact region 103 (see FIG. 16 ). In the second configuration, a silicide layer 58 is disposed in a region directly above the second channel region 102, and the second channel region 102 and the source pad electrode 70 are in ohmic contact via this silicide layer 58 (see FIG. 18 ).

[0252] In contrast, in the third embodiment, an ohmic contact between the second channel region 102 and the source pad electrode 70 is provided by utilizing a source region 32 disposed in the transistor region Tr that is spaced apart in the depth direction of the trench 19 from the region directly above the second channel region 102 in the depth direction of the trench 19 (i.e., the blank region Bs). The source region 32 also serves as the second channel contact region 103. The second channel region 102 is ohmically connected to the source pad electrode 70 by a three-dimensional connection structure defined by the depth direction and the transverse direction of the trench 19.

[0253] 19 to 21 , the region hatched with dashed lines in the mesa portion 24 is the transistor region Tr in which the body region 18 is formed in plan view. In contrast, the open region without hatching in the mesa portion 24 is a blank region Bs where the body region 18 has been removed. The configuration of the three-dimensional connection structure of the second channel region 102 includes a first pattern shown in FIGS. 19 and 22 and a second pattern shown in FIGS. 20 , 21 , and 23 . The difference between the first pattern and the second pattern is the presence or absence of a second source protrusion 108 in the source region 32.

[0254] 22 , in the first pattern, the source end face 111 of the source region 32 coincides with the body end face 110 of the body region 18 in the depth direction of the mesa portion 24. As shown in FIG. 23 , in the second pattern, the source end face 111 of the source region 32 is located closer to the blank region Bs than the body end face 110 of the body region 18 in the depth direction of the mesa portion 24. As a result, a second source protrusion 108 that is integrally drawn out from the source region 32 is formed in the blank region Bs.

[0255] The transistor region Tr and the blank region Bs can be further divided into a plurality of sections based on the layer structure of the impurity region in the mesa portion 24. In this embodiment, the transistor region Tr can be divided into sections A and D. The blank region Bs can be divided into sections B and C.

[0256] 24A, the cross-sectional structure in section A is the same as the cross section of the transistor region Tr shown in Fig. 6. In the mesa portion 24, a drift region 8, a body region 18, and a source region 32 are formed in this order in the depth direction of the trench 19 from the second main surface 4 side toward the first main surface 3. A first channel region 16 is formed in a portion of the body region 18 that contacts the trench insulating film 20.

[0257] 24B , the cross-sectional structure in section B is the cross-sectional structure of rectifying element PBR. In mesa portion 24, second channel region 102, shield region 101, and shield contact region 105 are formed in this order in the depth direction of trench 19 from second main surface 4 toward first main surface 3.

[0258] The shield contact region 105 is formed in the blank region Bs in a surface layer portion of the first main surface 3 of the mesa portion 24. The shield contact region 105 is disposed in a region directly above the second channel region 102 in the depth direction of the mesa portion 24. In the blank region Bs of the mesa portion 24, a layered structure of the second channel region 102 and the shield contact region 105 is formed in this order from the bottom side of the trench 19 toward the first main surface 3.

[0259] The shield contact region 105 is formed across the mesa portion 24 in the width direction, from one side surface 22 to the other side surface 22 of the mesa portion 24 (one side surface 22 and the other side surface 22 of the trench 19). In a direction perpendicular to the depth direction of the trench 19 (first direction X), the shield contact region 105 is in direct contact with the buried insulating layer 55. The shield contact region 105 does not face the buried conductive layer 21 via the trench insulating film 20.

[0260] The shield contact region 105 is connected to the second channel region 102 in the depth direction of the trench 19. In this embodiment, the shield contact region 105 has a bottom 106 connected to the second channel region 102.

[0261] The p-type impurity concentration of the shield contact region 105 is preferably higher than the p-type impurity concentration of the body region 18. The p-type impurity concentration of the shield contact region 105 may be the same as the p-type impurity concentration of the first contact region 34. The shield contact region 105 has a p-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0262] The shield contact thickness CT5 of the shield contact region 105 in the vertical direction Z from the first main surface 3 may be the same as the first contact thickness CT1 (for example, 0.1 μm or more and 1.0 μm or less, preferably 0.2 μm or more and 0.5 μm or less). The shield contact thickness CT5 is smaller than the source thickness ST1. Due to the difference between the shield contact thickness CT5 and the source thickness ST1, there is a difference in elevation between the first boundary surface 39 and the bottom 106 of the shield contact region 105. As a result, the source region 32 has a first source protrusion 107 that protrudes toward the second main surface 4 beyond the bottom 106 of the shield contact region 105.

[0263] A silicide layer 58 is formed on the surface of the shield contact region 105, similar to the source region 32 and the first contact region 34. By forming the silicide layer 58, the contact resistance to the shield contact region 105 can be reduced.

[0264] The shield region 101 is disposed on a side surface 22 of the trench 19. The shield region 101 is connected to the shield contact region 105 and the well region 12. The shield region 101 is formed along the side surface 22 of the trench 19 from a bottom 106 of the shield contact region 105 toward the second main surface 4, and is connected to the well region 12.

[0265] 24C, the cross-sectional structure in section C is the same as the cross section of blank region Bs shown in Fig. 16. In the mesa portion 24, a second channel region 102, a shield region 101, and a second channel contact region 103 are formed in this order in the depth direction of the trench 19 from the second main surface 4 side toward the first main surface 3. In this embodiment, the second channel contact region 103 is formed by a second source protrusion 108.

[0266] 24D , the cross-sectional structure in section D is the same as that in section C, except that body region 18 is further formed. Body region 18 separates second channel contact region 103 (second source protrusion 108) from second channel region 102. Therefore, in section D, no current path is formed for rectifying element PBR.

[0267] 22 , in pattern 1, the source end surface 111 of the first source protrusion 107 of the source region 32 is connected to the second channel region 102. As a result, the second channel region 102 is ohmically connected to the source pad electrode 70 via the first source protrusion 107 of the source region 32. On the other hand, with reference to FIG. 23 , in pattern 2, the source end surface 111 of the first source protrusion 107 of the source region 32 and the bottom 109 of the second source protrusion 108 are connected to the second channel region 102. As a result, the second channel region 102 is ohmically connected to the source pad electrode 70 via the first source protrusion 107 and the second source protrusion 108 of the source region 32. Since the ohmic connection is provided at two locations, the source end surface 111 and the bottom 109, the contact area with the second channel region 102 can be increased, and the contact resistance can be reduced.

[0268] 22 and the second pattern of Fig. 23, a current path is provided between the source pad electrode 70 and the drain pad electrode 87 (between the source and drain) via the second channel region 102 and the source region 32. As shown in Fig. 22 and Fig. 23, a current IB flows from the source pad electrode 70 to the drain pad electrode 87.

[0269] Like the rectifier element PBR of the first embodiment, the rectifier element PBR of the third embodiment also allows current to flow preferentially through the rectifier element PBR when the MIS transistor Tr is reverse conductive (when a reverse voltage is applied).

[0270] Furthermore, in the rectifying element PBR of the third embodiment, the shield contact region 105 is disposed in a region directly above the shield region 101 and is in direct ohmic contact with the shield region 101. Although the second channel contact region 103 is spaced apart from a region directly above the second channel region 102, the source region 32 is used as the second channel contact region 103. Therefore, the ohmic contact position of the second channel region 102 can be set at the boundary with the blank region Bs in the depth direction of the mesa portion 24.

[0271] Since the p-type ohmic contact position is the blank region Bs and the n-type ohmic contact position is the boundary between the transistor region Tr and the blank region Bs, the two ohmic contact positions can be arranged close to each other. As a result, the rectifying element PBR can operate stably. This structure is superior in terms of operational stability of the rectifying element PBR to the first embodiment, in which the ohmic contact position with the shield region 101 is the first contact region 34, which is far from the boundary between the transistor region Tr and the blank region Bs in the depth direction of the mesa portion 24, as shown in FIG. 5 .

[0272] (4) Fourth Configuration Fig. 25 is a cross-sectional view showing a fourth configuration of rectifier element PBR, and corresponds to Fig. 6. Referring to Fig. 25, in this configuration, a part of body region 18 extends from transistor region Tr to blank region Bs along the side surface of trench 19, and also serves as shield region 101 between adjacent trenches 19.

[0273] Like the rectifier element PBR of the first embodiment, the rectifier element PBR of the fourth embodiment also allows current to flow preferentially through the rectifier element PBR when the MIS transistor Tr is reverse conductive (when a reverse voltage is applied).

[0274] (5) Fifth Form Fig. 26 is a perspective view showing a fifth form of the rectifying element PBR. Figs. 27 to 29 are plan views showing layout examples of the transistor region Tr and the blank region Bs.

[0275] Referring to FIG. 26, a transistor structure Tr of a semiconductor device 1 of this embodiment has a planar gate vertical structure.

[0276] The semiconductor device 1 includes a plurality of p-type body regions 88 formed in the active region 9. In this embodiment, the plurality of body regions 88 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. The plurality of body regions 88 are arranged in a stripe shape as a whole. Each body region 88 provides a unit cell UC of a planar gate transistor. Each unit cell UC includes at least a body region 88 and a source region 89 (described later), and may be the minimum unit that functions as a MIS transistor.

[0277] The plurality of body regions 88 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0278] The semiconductor device 1 includes one or more n-type source regions 89 formed in the surface layer portions of the plurality of body regions 88 in the active region 9. In this embodiment, a plurality of (two in this embodiment) source regions 89 are formed at intervals in the surface layer portion of each body region 88. The plurality of source regions 89 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The plurality of source regions 89 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0279] The multiple source regions 89 may each extend in a strip shape along the extension direction of the corresponding body region 88. Of course, the multiple source regions 89 may be formed at intervals along the extension direction of the corresponding body region 88. The multiple source regions 89 are formed at intervals from the bottom of the corresponding body region 88 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 88. The multiple source regions 89 define a first channel region 90 along the first main surface 3 at the periphery of the body region 88.

[0280] The semiconductor device 1 includes one or more p-type first contact regions 91 formed in the surface layer portions of the plurality of body regions 88 in the active region 9. The first contact region 91 may also be referred to as a "back gate region." In this embodiment, one first contact region 91 is formed in a region between the plurality of adjacent source regions 89 in the surface layer portion of each body region 88.

[0281] The plurality of first contact regions 91 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 88. The plurality of first contact regions 91 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 88. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0282] The multiple first contact regions 91 may each extend in a strip shape along the extension direction of the corresponding body region 88. Of course, the multiple first contact regions 91 may also be formed at intervals along the extension direction of the corresponding body region 88. The multiple first contact regions 91 are formed at intervals from the bottom of the corresponding body region 88 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 88.

[0283] The semiconductor device 1 includes a plurality of planar electrode type gate structures 92 arranged on the first main surface 3 in the active region 9. The gate structures 92 may also be referred to as "planar structures" or "planar gate structures." The plurality of gate structures 92 are arranged at intervals on the first main surface 3 so as to overlap at least one first channel region 90 in the stacking direction. A gate potential is applied to the plurality of gate structures 92 as a control potential. The plurality of gate structures 92 control the inversion and non-inversion of a channel (current path) in the body region 88 in response to the gate potential.

[0284] In this embodiment, the multiple gate structures 92 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate structures 92 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The multiple gate structures 92 are formed in stripes extending in the a-axis direction (second direction Y), and the extending direction of the multiple gate structures 92 coincides with the off-direction Do of the second semiconductor layer 7 (see FIG. 4 ).

[0285] In this embodiment, the multiple gate structures 92 are each arranged to straddle two adjacent body regions 88 and cover multiple source regions 89 located in one and the other body regions 88, respectively.

[0286] Each of the multiple gate structures 92 has a stacked structure including a gate insulating film 93 disposed on the first main surface 3 and a gate electrode 94 disposed on the gate insulating film 93. The gate insulating film 93 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 93 has a single-layer structure made of a silicon oxide film. The gate insulating film 93 may include a silicon oxide film made of an oxide of the chip 2. The gate electrode 94 may include p-type or n-type conductive polysilicon.

[0287] The semiconductor device 1 includes an interlayer film 95 covering the first main surface 3. The interlayer film 95 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 95 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0288] The semiconductor device 1 includes a plurality of contact openings 96 formed in an interlayer film 95. The plurality of contact openings 96 include a plurality of contact openings 96 (not shown) that expose a plurality of gate structures 92 (gate electrodes 94), and a plurality of contact openings 96 (source openings 97) that expose a plurality of source regions 89 and a plurality of first contact regions 91. The source openings 97 are formed in regions between adjacent plurality of gate structures 92, and expose a plurality of source regions 89 and a plurality of first contact regions 91.

[0289] The source pad electrode 70 covers the entire region of the interlayer film 65 where the source opening 97 is formed, and extends from above the interlayer film 65 into the source opening 97. The source pad electrode 70 has a portion that covers the interlayer film 65 in a film-like manner, a portion that covers the wall surface of the source opening 97 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 97 in a film-like manner. The source pad electrode 70 is partially buried in the source opening 97. The source pad electrode 70 is in ohmic contact with the source region 89 and the first contact region 91.

[0290] 27 to 29 , the body regions 88 (unit cells UC) include blank spaces (Bs) formed by selectively removing portions of the body regions 88. A body opening 98 is formed in each blank space Bs, penetrating the body region 88 in the thickness direction. In each blank space Bs, a portion of the body region 88 surrounding the body opening 98 also serves as a shield region 101. In FIGS. 27 and 28 , the shield region 101 may be a ring-shaped portion of the body region 88 surrounding the entire periphery of the body opening 98. In FIG. 29 , the shield region 101 may be striped portions of the body region 88 sandwiching the body opening 98 in the first direction X.

[0291] 27 and 28 , blank regions Bs and transistor regions Tr excluding the blank regions Bs are formed in each of the plurality of stripe-shaped body regions 88. In each stripe-shaped body region 88, the blank regions Bs and the transistor regions Tr are disposed adjacent to each other in the depth direction of the body region 88. In this embodiment, the blank regions Bs and the transistor regions Tr are alternately arranged in the depth direction of the body region 88. The layout of the blank regions Bs (body openings 98) for the plurality of stripe-shaped body regions 88 may be in a matrix pattern as shown in FIG. 27 or a staggered pattern as shown in FIG. 28 .

[0292] 29 , the plurality of transistor regions Tr and the plurality of blank regions Bs may be formed in separate body regions 88. For example, the plurality of body regions 88 may include a body region 88 for the transistor region Tr and a body region 88 for the blank region Bs, which are independent of each other. In FIG. 29 , the body regions 88 for the plurality of transistor regions Tr and the body regions 88 for the plurality of blank regions Bs are alternately arranged in the first direction X. In each body region 88, a strip-shaped transistor region Tr or blank region Bs is arranged extending across the entire depth direction of the body region 88.

[0293] Within the body opening 98, a second channel region 102 is formed by a part of the drift region 8. The second channel region 102 may be a part of the drift region 8 that is surrounded by a shield region 101 around the body opening 98.

[0294] 27 and 28 , the second channel contact region 103 connects the source regions 89 adjacent to each other in the first direction X with the first contact region 91 interposed therebetween. The second channel contact region 103 crosses the first contact region 91 and is formed integrally with the adjacent source regions 89. In the layout of FIG. 29 , the second channel contact region 103 is formed in a strip shape extending in the depth direction of the body region 88.

[0295] The source pad electrode 70 is directly ohmically connected to the second channel contact region 103 within the source opening 97. The source pad electrode 70 is ohmically connected to the second channel region 102 via the second channel contact region 103. As a result, a current path is provided between the source pad electrode 70 and the drain pad electrode 87 (see FIG. 5) (between the source and drain) via the second channel region 102 and the second channel contact region 103. As shown in FIG. 26, a current IC flows from the source pad electrode 70 to the drain pad electrode 87.

[0296] Like the rectifier element PBR of the first embodiment, the rectifier element PBR of the fifth embodiment also allows current to flow preferentially through the rectifier element PBR when the MIS transistor Tr is reverse conductive (when a reverse voltage is applied).

[0297] (6) Sixth Form Fig. 30 is a perspective view showing a sixth form of the rectifying element PBR, and corresponds to Fig. 26. The rectifying element PBR in Fig. 30 differs from the rectifying element PBR in Fig. 26 in that the second channel contact region 103 is omitted.

[0298] 30 , the second channel region 102 extends from the bottom of the body opening 98 to the first main surface 3 and is exposed from the first main surface 3. The silicide layer 58 is formed in the portion (exposed surface) of the second channel region 102 exposed from the first main surface 3. As a result, the source pad electrode 70 is in direct ohmic contact with the second channel region 102 via the silicide layer 58.

[0299] Like the rectifier element PBR of the first embodiment, the rectifier element PBR of the sixth embodiment also allows current to flow preferentially through the rectifier element PBR when the MIS transistor Tr is reverse conductive (when a reverse voltage is applied).

[0300] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0301] 31 , the buried insulating layer 55 may be omitted, and the buried conductive layer 21 may be buried up to the opening edge of the trench 19. In this case, the interlayer film 65 may cover the active region 9, and may have a source opening 68 in the active region 9 that selectively exposes the mesa portion 24.

[0302] For example, in each of the above-described embodiments, the first semiconductor layer 6 and the second semiconductor layer 7 each contain a SiC single crystal. However, at least one or all of the first semiconductor layer 6 and the second semiconductor layer 7 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0303] The first semiconductor layer 6 and the second semiconductor layer 7 may be made of the same type of single crystal or different types of single crystal, and at least one of the first semiconductor layer 6 and the second semiconductor layer 7 or all of them may be made of silicon (Si).

[0304] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0305] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (8) of a first conductivity type formed in a surface layer portion of the first main surface (3); a MIS transistor structure (Tr) including: a second impurity region (18, 88) of a second conductivity type formed in a surface layer portion of the first impurity region (8); a third impurity region (32, 89) of the first conductivity type formed in a surface layer portion of the second impurity region (18, 88); and a control electrode (21, 94) facing a first channel region (16, 90) of the second impurity region (18, 88) via a control insulating film (20, 93); a rectifying element structure (PBR) including: second conductivity type shield regions (101) formed in a surface layer portion of the first impurity region (8) and opposing each other in a direction intersecting the thickness direction of the chip (2) within the first impurity region (8); a second channel region (102) provided by a portion of the first impurity region (8) sandwiched between the shield regions (101); a first principal surface electrode (70) ohmically connected to the third impurity region (32, 89), the shield region (101), and the second channel region (102); and a second principal surface electrode (87) ohmically connected to the first impurity region (8).

[0306] [Appendix 1-2] The semiconductor device (1) according to Appendix 1-1, further comprising a silicide layer (58) formed on the first main surface (3) of the chip (2), wherein the first main surface electrode (70) is ohmically connected to the third impurity region (32, 89), the shield region (101), and the second channel region (102) via the silicide layer (58).

[0307] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-1 or Supplementary Note 1-2, comprising: an active region (9) in which a plurality of unit cells (UC) of the MIS transistor structure (Tr) are regularly arranged; and a blank region (Bs) selectively provided in the plurality of unit cells (UC) in the active region (9) and in which a part of the second impurity region (18, 88) is removed, wherein the rectifying element structure (PBR) is arranged in the blank region (Bs).

[0308] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-3 further includes a second channel contact region (103) of a first conductivity type that is arranged on a surface layer portion of the first main surface (3) in the blank region (Bs), is connected to the second channel region (102), and has a higher concentration than the second channel region (102), and the first main surface electrode (70) is ohmically connected to the second channel region (102) via the second channel contact region (103).

[0309] [Appendix 1-5] The semiconductor device (1) according to appendix 1-3, wherein the second channel region (102) is exposed from the first main surface (3) and has a silicide layer (58) in the exposed portion of the first main surface (3), and the first main surface electrode (70) is in direct ohmic contact with the second channel region (102) via the silicide layer (58).

[0310] [Supplementary Note 1-6] The semiconductor device (1) according to Supplementary Note 1-3, wherein the plurality of unit cells (UC) are arranged in a stripe pattern, and further includes a second channel contact region (103) provided by a protruding portion (108) integral with the third impurity region (32, 89) that protrudes toward the blank region (Bs) beyond an end (110) of the second impurity region (18, 88) in the length direction of the unit cell (UC), and having a bottom (109) connected to the second channel region (102), and the first main surface electrode (70) is in ohmic contact with the second channel region (102) via the second channel contact region (103).

[0311] [Supplementary Note 1-7] The MIS transistor structure (Tr) includes a trench structure (11) including a trench (19) that defines a mesa portion (24) that provides the plurality of unit cells (UC), the control insulating film (20) formed on the inner surface of the trench (19), and the control electrode (21) embedded in the trench (19) via the control insulating film (20), and the mesa portion (24) has a transistor region (Tr) including the third impurity region (32) and the second impurity region (18) in this order from the first main surface (3) side, and the blank region (Bs) adjacent to the transistor region (Tr) in the length direction of the trench (19), The semiconductor device (1) described in Appendix 1-3, wherein the shield region (101) is arranged on the side surface (22) of the adjacent trenches (19) in the blank region (Bs), and sandwiches the second channel region (102) between the adjacent trenches (19).

[0312] [Appendix 1-8] The semiconductor device (1) according to Appendix 1-7, further comprising a second channel contact region (103) of the first conductivity type that is arranged in a surface layer portion of the first main surface (3) of the mesa portion (24) in the blank region (Bs), is connected to the second channel region (102), and has a higher concentration than the second channel region (102), and the first main surface electrode (70) is ohmically connected to the second channel region (102) via the second channel contact region (103).

[0313] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-7, wherein the second channel region (102) extends from a bottom of the trench (19) to the first main surface (3) of the mesa portion (24) and has a silicide layer (58) on a surface layer of the first main surface (3), and the first main surface electrode (70) is in direct ohmic contact with the second channel region (102) via the silicide layer (58).

[0314] [Supplementary Note 1-10] The semiconductor device (1) according to Supplementary Note 1-8, further comprising a first channel contact region (34) of a second conductivity type that is disposed in a surface layer portion of the first main surface (3) of the mesa portion (24) in the transistor region (Tr), is connected to the second impurity region (18), and has a higher concentration than the second impurity region (18), and the shield region (101) is drawn from the first channel contact region (34) along the trench (19) toward the blank region (Bs) and is provided by an impurity region that is integral with the first channel contact region (34).

[0315] [Appendix 1-11] The semiconductor device (1) according to Appendix 1-7 further includes a second channel contact region (103) including a protruding portion (108) integral with the third impurity region (32, 89) that protrudes toward the blank region (Bs) beyond an end (110) of the second impurity region (18) in the length direction of the trench (19), and having a bottom (109) connected to the second channel region (102), wherein the first main surface electrode (70) is in ohmic contact with the second channel region (102) via the second channel contact region (103).

[0316] [Appendix 1-12] The semiconductor device (1) according to Appendix 1-11, further comprising: a shield contact region (105) of a second conductivity type that is disposed in a surface layer portion of the first main surface (3) of the mesa portion (24) in the blank region (Bs) and has a higher concentration than the second impurity region (18), wherein the shield region (101) is integral with the shield contact region (105) and extends in a depth direction of the trench (19) along a side surface (22) of the trench (19).

[0317] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-7 to 1-12, further comprising a well region (12) of a second conductivity type formed at a bottom of the trench (19), the well region (12) extending across the transistor region (Tr) and the blank region (Bs) in a length direction of the trench (19), and the shield region (101) being connected to the well region (12).

[0318] [Appendix 1-14] The semiconductor device (1) according to Appendix 1-7, wherein a part of the second impurity region (18) extends from the transistor region (Tr) to the blank region (Bs) along a side surface (22) of the trench (19) and also serves as the shield region (101) sandwiching the second channel region (102) between adjacent trenches (19).

[0319] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-7 to 1-14, further comprising: a recess (27) defined by an upper surface (25) of the control electrode (21) and a side surface (22) of the trench (19) at an upper portion of the trench (19); a buried insulating layer (55) buried in the recess (27); and the first principal surface electrode (70) partially buried in the recess (27) so as to cover the buried insulating layer (55).

[0320] [Supplementary Note 1-16] The semiconductor device (1) according to Supplementary Note 1-3, wherein the plurality of unit cells (UC) are provided by a plurality of the second impurity regions (88) regularly arranged and the third impurity region (89) arranged in an inner region of each of the second impurity regions (88) and sandwiching the first channel region (90) between the second impurity region (88) and an outer edge of the second impurity region (88), the MIS transistor structure (Tr) includes a planar structure (92) formed on the first main surface (3) and including a control insulating film (93) covering the first channel region (90) and the control electrode (94) facing the first channel region (90) via the control insulating film (93), and an opening (98) penetrating the second impurity region (88) in a thickness direction is formed in the blank region (Bs), and a part of the second impurity region (88) surrounding the opening (98) also serves as the shield region (101).

[0321] [Appendix 1-17] The semiconductor device (1) according to Appendix 1-16, further including a second channel contact region (103) of the first conductivity type that is arranged on a surface layer portion of the first main surface (3) so as to cover the opening (98) in the blank region (Bs), is connected to the second channel region (102), and has a higher concentration than the second channel region (102), and the first main surface electrode (70) is ohmically connected to the second channel region (102) via the second channel contact region (103).

[0322] [Appendix 1-18] The semiconductor device (1) according to Appendix 1-16, wherein the second channel region (102) extends through the opening (98) in the thickness direction of the chip (2) to the first main surface (3), and has a silicide layer (58) on a surface layer of the first main surface (3), and the first main surface electrode (70) is in direct ohmic contact with the second channel region (102) via the silicide layer (58).

[0323] [Appendix 1-19] The semiconductor device (1) according to Appendix 1-16, further including a first channel contact region (91) of a second conductivity type that is arranged adjacent to the third impurity region (89) in a surface layer portion of the second impurity region (88), is connected to the second impurity region (88), and has a higher concentration than the second impurity region (88).

[0324] [Appendix 1-20] The semiconductor device (1) according to any one of Appendices 1-1 to 1-19, wherein the first impurity region (8) includes a base region (50) arranged on the second main surface (4) side away from the second impurity region (18, 88), and a low-concentration region (102) that provides the second channel region (102) on the first main surface (3) side of the base region (50) and has a lower concentration than the base region (50).

[0325] [Appendix 1-21] The semiconductor device (1) according to any one of Appendices 1-1 to 1-20, wherein the chip (2) includes a SiC chip (2).

[0326] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor layer 7: Second semiconductor layer 8: Drift region 9: Active region 10: Peripheral region 11: Gate structure 12: Well region 13: Outer well region 14: Field region 15: Surface insulating film 16: First channel region 18: Body region 19: Trench 20: Trench insulating film 21: Buried conductive layer 22: Side surface 23: Bottom surface 24: Mesa portion 25: Top surface 26: Step 27: Recess 28: Protrusion 29: Side surface 30: First layer 31: Second layer 32 : Source region 33 : Channel section 34 : First contact region 35 : First body portion 36 : Second body portion 37 : Base boundary surface 38 : Body protrusion 39 : First boundary surface 40 : First step 41 : Second boundary surface 42 : Second step 43 : Second contact region 44 : Integrated impurity region 45 : Corner portion 46 : First relaxation portion 47 : Second relaxation portion 48 : First boundary surface 49 : Second boundary surface 50 : Base region 51 : High concentration region 55 : Buried insulating layer 56 : Upper edge 57 : Upper surface 58 : Silicide layer 59 : Non-silicide portion 60 : First main surface electrode 61 : Barrier layer 62 : Main body layer 63 : Second recess 64 : Resin layer 65 : Interlayer film 66 : Gate wiring 67 : Gate pad wiring 68 : Source opening 69 : Main surface insulating film 70 : Source pad electrode 70 a : First pad portion 70 b : Second pad portion 70 c : Third pad portion 71 : Outer contact region 79 : Gate opening 80 : Gate pad electrode 81 : Gate finger electrode 82 : First slit portion 83 : Outer opening 85 : Source finger electrode 86 : Second slit portion 87 : Drain pad electrode88: Body region 89: Source region 90: First channel region 91: First contact region 92: Gate structure 93: Gate insulating film 94: Gate electrode 95: Interlayer film 96: Contact opening 97: Source opening 98: Body opening 100: Lower portion 101: Shield region 102: Second channel region 103: Second channel contact region 104: Bottom portion 105: Shield contact region 106: Bottom portion 107: First source protrusion 108: Second source protrusion 109: Bottom portion 110: Body end surface 111: Source end surface A: Section B: Section BDi: Body diode Bs: Blank region C: Section D: Section PBR: Rectifier element Tr: Transistor region (transistor structure) UC: unit cell

Claims

1. A semiconductor device comprising: a chip having a first main surface and a second main surface; a MIS transistor structure including: a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface; a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region; and a control electrode facing a first channel region of the second impurity region via a control insulating film; a rectifying element structure including shield regions of the second conductivity type formed in the surface layer portion of the first impurity region and facing each other in the first impurity region in a direction intersecting the thickness direction of the chip, and a second channel region provided by portions of the first impurity region sandwiched between the shield regions; a first main surface electrode ohmically connected to the third impurity region, the shield region, and the second channel region; and a second main surface electrode ohmically connected to the first impurity region.

2. The semiconductor device according to claim 1, further comprising a silicide layer formed on the first main surface of the chip, wherein the first main surface electrode is ohmically connected to the third impurity region, the shield region, and the second channel region via the silicide layer.

3. The semiconductor device according to claim 1 or 2, comprising: an active region in which a plurality of unit cells of the MIS transistor structure are regularly arranged; and a blank region selectively provided in the active region for the plurality of unit cells, the blank region being formed by removing a portion of the second impurity region; and the rectifying element structure being disposed in the blank region.

4. The semiconductor device according to claim 3, further comprising a second channel contact region of the first conductivity type that is disposed in a surface layer portion of the first main surface in the blank region, is connected to the second channel region, and has a higher concentration than the second channel region, and the first main surface electrode is ohmically connected to the second channel region via the second channel contact region.

5. The semiconductor device according to claim 3, wherein the second channel region is exposed from the first main surface and has a silicide layer in the exposed portion of the first main surface, and the first main surface electrode is in direct ohmic contact with the second channel region via the silicide layer.

6. The semiconductor device according to claim 3, wherein the plurality of unit cells are arranged in a stripe pattern, and further includes a second channel contact region provided by a protruding portion integral with the third impurity region that protrudes toward the blank region beyond the end of the second impurity region in the longitudinal direction of the unit cell, and having a bottom connected to the second channel region, and wherein the first main surface electrode is ohmically connected to the second channel region via the second channel contact region.

7. The semiconductor device according to claim 3, wherein the MIS transistor structure includes a trench structure including a trench that defines a mesa portion providing the plurality of unit cells, the control insulating film formed on the inner surface of the trench, and the control electrode embedded in the trench via the control insulating film, the mesa portion having a transistor region including the third impurity region and the second impurity region in that order from the first main surface side, and the blank region adjacent to the transistor region in the longitudinal direction of the trench, and the shield region is arranged on the side surface of adjacent trenches in the blank region, sandwiching the second channel region between the adjacent trenches.

8. The semiconductor device according to claim 7, further comprising a second channel contact region of the first conductivity type that is disposed in a surface layer portion of the first main surface of the mesa portion in the blank region, is connected to the second channel region, and has a higher concentration than the second channel region, and the first main surface electrode is ohmically connected to the second channel region via the second channel contact region.

9. The semiconductor device according to claim 7, wherein the second channel region extends from the bottom of the trench to the first main surface of the mesa portion and has a silicide layer on a surface layer of the first main surface, and the first main surface electrode is in direct ohmic contact with the second channel region via the silicide layer.

10. The semiconductor device according to claim 8, further comprising a first channel contact region of a second conductivity type that is disposed in a surface layer portion of the first main surface of the mesa portion in the transistor region, connected to the second impurity region, and has a higher concentration than the second impurity region, and the shield region is extended from the first channel contact region along the trench toward the blank region and is provided by an impurity region that is integral with the first channel contact region.

11. The semiconductor device described in claim 7, further comprising a second channel contact region having a bottom connected to the second channel region and including a protruding portion integral with the third impurity region that protrudes toward the blank region beyond the end of the second impurity region in the longitudinal direction of the trench, and wherein the first main surface electrode is ohmically connected to the second channel region via the second channel contact region.

12. The semiconductor device described in claim 11, further comprising a shield contact region of a second conductivity type that is disposed in a surface layer portion of the first main surface of the mesa portion in the blank region and has a higher concentration than the second impurity region, the shield region being integral with the shield contact region and extending in the depth direction of the trench along the side surface of the trench.

13. The semiconductor device according to any one of claims 7 to 12, further comprising a well region of a second conductivity type formed at the bottom of the trench, extending across the transistor region and the blank region in the longitudinal direction of the trench, and the shield region being connected to the well region.

14. The semiconductor device according to claim 7, wherein a portion of the second impurity region extends from the transistor region to the blank region along the side of the trench and also serves as the shield region sandwiching the second channel region between adjacent trenches.

15. A semiconductor device as described in any one of claims 7 to 14, wherein a recess defined by the upper surface of the control electrode and the side surface of the trench is formed in the upper part of the trench, and further comprising a buried insulating layer buried in the recess, and wherein the first main surface electrode is partially buried in the recess so as to cover the buried insulating layer.

16. The semiconductor device according to claim 3, wherein the plurality of unit cells are provided by a plurality of the second impurity regions arranged regularly and the third impurity region disposed in an inner region of each of the second impurity regions and sandwiching the first channel region between the second impurity regions and the outer edge of the second impurity region, the MIS transistor structure includes a planar structure formed on the first main surface and including a control insulating film covering the first channel region and the control electrode facing the first channel region via the control insulating film, an opening penetrating the second impurity region in the thickness direction is formed in the blank region, and a part of the second impurity region surrounding the opening also serves as the shield region.

17. The semiconductor device described in claim 16, further including a second channel contact region of the first conductivity type that is connected to the second channel region and has a higher concentration than the second channel region, the second channel contact region being disposed on a surface layer portion of the first main surface so as to cover the opening in the blank region, the first main surface electrode being ohmically connected to the second channel region via the second channel contact region.

18. The semiconductor device described in claim 16, wherein the second channel region extends through the opening in the thickness direction of the chip to the first main surface, and has a silicide layer on a surface layer of the first main surface, and the first main surface electrode is directly ohmically connected to the second channel region through the silicide layer.

19. The semiconductor device according to claim 16, further comprising a first channel contact region of a second conductivity type that is arranged adjacent to the third impurity region in a surface layer portion of the second impurity region in the transistor region, is connected to the second impurity region, and has a higher concentration than the second impurity region.

20. A semiconductor device according to any one of claims 1 to 19, wherein the first impurity region includes a base region located on the second main surface side away from the second impurity region, and a low concentration region that provides the second channel region on the first main surface side of the base region and has a lower concentration than the base region.

21. The semiconductor device according to any one of claims 1 to 20, wherein the chip includes a SiC chip.

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