Semiconductor device

Abstract

The present invention suppresses an increase in chip size. This semiconductor device comprises a semiconductor substrate, a lower electrode, and an upper electrode. The semiconductor substrate comprises: insulated gate bipolar transistor (IGBT) regions; free wheeling diode (FWD) regions; and a boundary region disposed between the IGBT regions and the FWD regions. The plurality of the IGBT regions and the plurality of FWD regions extend in a first direction and are alternatingly disposed in a second direction orthogonal to the first direction. When the width of the boundary region in the second direction is defined as a boundary region width W1μm and the value of half the width of the FWD region in the second direction is defined as FWD region width W2μm, the boundary region width W1 is at least a prescribed value found by using a specific formula represented by {W1=-0.25×W2+94μm}.

Description

Semiconductor Devices

[0001] (Cross-reference to related applications) This application is a related application of Japanese Patent Application No. 2024-069830 filed on April 23, 2024, and Japanese Patent Application No. 2025-012403 filed on January 28, 2025, and claims priority based on this Japanese patent application. All contents of this Japanese patent application are incorporated by reference as constituting this specification.

[0002] The technology disclosed in this specification relates to a semiconductor device having an insulated gate field effect transistor (hereinafter referred to as an IGBT (abbreviation of Insulated Gate Bipolar Transistor)) region in which an IGBT element is formed, and a free wheeling diode (hereinafter referred to as an FWD (abbreviation of Free Wheeling Diode)) region in which an FWD element is formed.

[0003] Conventionally, semiconductor devices have been proposed that have an RC-IGBT (reverse-conducting IGBT) structure in which an IGBT element and an FWD element are mounted on a single chip as switching elements for inverters, etc. Japanese Patent Application Laid-Open Publication No. 2015-109341 discloses related technology.

[0004] In the configuration of Patent Document 1, the IGBT region and the FWD region are arranged adjacent to each other. During diode operation, holes are injected from a high-concentration P-type region, such as a channel formed on the front surface of the IGBT region, toward the N-type cathode layer formed on the back surface of the FWD region. This hole injection increases the maximum reverse current during recovery, resulting in increased switching loss. On the other hand, it is conceivable to suppress hole injection from the IGBT region to the FWD region by placing a boundary region that does not function as a diode between the adjacent IGBT and FWD regions. However, increasing the width of the boundary region reduces the active area, resulting in an increase in chip size.

[0005] The semiconductor device disclosed in this specification includes a semiconductor substrate, a lower electrode in contact with a lower surface of the semiconductor substrate, and an upper electrode in contact with an upper surface of the semiconductor substrate. The semiconductor substrate includes a plurality of IGBT regions having IGBT elements, a plurality of FWD regions having FWD elements, and a plurality of boundary regions disposed between the plurality of IGBT regions and the FWD regions. The plurality of IGBT regions and the plurality of FWD regions extend in a first direction and are alternately disposed in a second direction perpendicular to the first direction. A plurality of boundary regions are located in each of the regions between the plurality of IGBT regions and the plurality of FWD regions. the semiconductor substrate includes: a drift layer of a first conductivity type; a base layer of a second conductivity type formed in a surface layer portion of the drift layer; a collector layer of the second conductivity type formed in the IGBT region on a side of the drift layer opposite to the base layer side; a cathode layer of the first conductivity type formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film and a gate electrode are arranged in a plurality of trenches formed in the IGBT region, the FWD region, and the boundary region, the trenches extending longitudinally in one direction and being deeper than the base layer to reach the drift layer; and an emitter region of the first conductivity type formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trenches. When the width of the boundary region in the second direction is defined as boundary region width W1 μm and half the width of the FWD region in the second direction is defined as FWD region width W2 μm, the boundary region width W1 is equal to or greater than a predetermined value calculated by a specific formula expressed as {W1 = -0.25 × W2 + 94 μm}.

[0006] The FWD region width W2 μm is set to half the width of the FWD region in the second direction. The reason for this is explained below. The FWD regions and IGBT regions have a periodic structure in which they are alternately arranged in the second direction. Therefore, the IGBT regions are located on both sides of the FWD region in the second direction. Carriers (e.g., holes) are injected into the FWD region from the IGBT regions on both sides. Therefore, by halving the width of the FWD region, a periodic boundary condition can be formed.

[0007] The inventors have found a specific relationship between the boundary region width W1 and the FWD region width W2. That is, in order to suppress carrier injection from the base layer of the IGBT region to the FWD region, the boundary region width W1 must be equal to or greater than a certain predetermined value. The inventors have discovered that this predetermined value can be made smaller as the FWD region width W2 increases. Based on this discovery, they have successfully formulated a specific equation for determining the predetermined value. By following this specific equation, it is possible to determine an appropriate boundary region width W1 based on the FWD region width W2. Therefore, it is possible to minimize the reduction in active area caused by the placement of the boundary region, thereby suppressing an increase in chip size.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0009] 1. A top view of the semiconductor device 3. An enlarged perspective view of the semiconductor substrate 10 in the region RII of FIG. 1. A cross-sectional view taken along line III-III of FIG. 2. A cross-sectional view taken along line IV-IV of FIG. 2. A graph of a first simulation result. A cross-sectional view for deriving the relationship between the boundary region width W1 and the substrate thickness ST. A graph of a second simulation result. A graph of a second simulation result. A graph of a second simulation result. A graph showing the relationship between the FWD region width W2 and the boundary region width W1. An enlarged perspective view of the semiconductor substrate 10 according to Example 2. An enlarged perspective view of the semiconductor substrate 10 according to Example 3. An enlarged perspective view of the semiconductor substrate 10 according to Example 4. A graph showing the on-voltage of the IGBT region 1a and the amount of voltage change at turn-on. A modified example of the semiconductor substrate 10 according to Example 4. A modified example of the semiconductor substrate 10 according to Example 4. An enlarged perspective view of a first example of the semiconductor substrate 10 according to Example 5. An enlarged perspective view of a second example of the semiconductor substrate 10 according to Example 5. An enlarged perspective view of a third example of the semiconductor substrate 10 according to Example 5. 10 is an enlarged perspective view of a fourth example of the semiconductor substrate 10 according to the fifth embodiment; FIG. 11 is an enlarged perspective view of a fifth example of the semiconductor substrate 10 according to the fifth embodiment; FIG. 12 is an enlarged perspective view of a sixth example of the semiconductor substrate 10 according to the fifth embodiment; FIG. 13 is an enlarged perspective view of a semiconductor substrate 10 according to the sixth embodiment;

[0010] (Configuration of Semiconductor Device 3) Hereinafter, embodiments according to the technology of the present specification will be described with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be described by using the same reference numerals.

[0011] FIG. 1 shows a top view of the semiconductor device 3. FIG. 2 shows an enlarged perspective view of the semiconductor substrate 10 in the region RII in FIG. 1. The contour line of the region RII passes through the midpoint 1bm of the FWD region 1b in the y direction. Note that the interlayer insulating film 19 and the upper electrode 20 are omitted from FIGS. 1 and 2. FIG. 3 shows a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 3 is a cross-sectional view that does not pass through the emitter region 15, while FIG. 4 is a cross-sectional view that passes through the emitter region 15.

[0012] As shown in FIG. 1 , the semiconductor device 3 has a semiconductor substrate 10 made of silicon. The semiconductor substrate 10 includes a cell region 1 and a peripheral region 2 surrounding the cell region 1. The cell region 1 includes multiple IGBT regions 1a, multiple FWD regions 1b, and multiple boundary regions 1c. Note that in FIG. 1 , the multiple FWD regions 1b are indicated by gray fill. The multiple IGBT regions 1a are regions having IGBT elements and extend in the x direction. In the IGBT region 1a, a channel is formed in response to a gate voltage applied to a trench electrode 18, and a current flows through the IGBT region 1a. The multiple FWD regions 1b are regions having FWD elements and extend in the x direction. In the FWD region 1b, a current flows in response to a forward bias voltage applied between an upper electrode 20 and a lower electrode 24. The multiple IGBT regions 1a and the multiple FWD regions 1b are alternately arranged in the y direction. A plurality of boundary regions 1c are located between the plurality of IGBT regions 1a and the plurality of FWD regions 1b. The plurality of boundary regions 1c are ineffective regions that do not function as semiconductor elements.

[0013] Although not shown, a voltage-resistant structure such as a guard ring is provided in the peripheral region 2. In addition, signal electrode pads 5 are provided on the peripheral region 2. The signal electrode pads 5 include gate pads that control the gate voltage of the IGBT.

[0014] As shown in FIGS. 2 to 4, the midpoint 1bm of the FWD region 1b in the y direction is located at the end of the FWD region 1b in the -y direction. That is, FIGS. 2 to 4 show only the half of the FWD region 1b on the +y direction side, obtained by dividing the FWD region 1b into two equal halves in the y direction. Here, the width from the boundary BD between the FWD region 1b and the boundary region 1c to the midpoint 1bm is defined as the FWD region width W2 [μm]. That is, the FWD region width W2 is half the y direction width of the FWD region 1b. The reason for this is explained below. The FWD regions 1b and the IGBT regions 1a have a periodic structure in which they are alternately arranged in the y direction (see FIG. 1). Therefore, the IGBT regions 1a are located on both sides of the FWD region 1b in the ±y directions. Carriers (e.g., holes) are injected into the FWD region from the IGBT regions on both sides in the ±y directions. Therefore, by halving the width of the FWD region 1b, a periodic boundary condition can be formed. That is, carrier injection from the IGBT region 1a located on the left side (+y direction side) of the FWD region 1b can be considered to be injected into the left half of the FWD region 1b, which is divided into two equal parts. Also, carrier injection from the IGBT region on the right side (-y direction side) of the FWD region 1b can be considered to be injected into the right half of the FWD region 1b, which is divided into two equal parts. This makes it possible to properly perform the simulation described below.

[0015] 2 to 4, the width of the boundary region 1c in the y direction is defined as boundary region width W1 [μm]. The thickness of the semiconductor substrate 10 is defined as substrate thickness ST. Substrate thickness ST is the thickness of the semiconductor substrate 10 itself in the z direction, and does not include the thickness of the upper electrode 20, the lower electrode 24, and the interlayer insulating film 19.

[0016] A P-type base layer 12 is formed on the drift layer 11. That is, the base layer 12 is formed on the top surface 10a side of the semiconductor substrate 10. Furthermore, a plurality of trenches 14 are formed in the IGBT region 1a, the boundary region 1c, and the FWD region 1b so as to penetrate the base layer 12 and reach the drift layer 11. Each of the plurality of trenches 14 extends in the x direction and is arranged at equal intervals in the y direction. The trenches 14 separate the base layer 12 into a plurality of pieces.

[0017] In this embodiment, the base layer 12 has different impurity concentrations in the IGBT region 1a and in the FWD region 1b and boundary region 1c. Specifically, the base layer 12 in the IGBT region 1a has a higher impurity concentration than the base layer 12 in the FWD region 1b and boundary region 1c. Hereinafter, the base layer 12 formed in the IGBT region 1a will also be referred to as a first base layer 12a, and the base layer 12 formed in the FWD region 1b and boundary region 1c will also be referred to as a second base layer 12b.

[0018] The first base layer 12a functions as a channel region and also as a body region. The surface layer of the first base layer 12a is partially provided with an N-type junction layer having a depth shallower than that of the first base layer 12a, as shown in FIGS. ＋ A mold emitter region 15 is formed.

[0019] The emitter regions 15 have a higher impurity concentration than the drift layer 11, terminate in the first base layer 12a, and are formed so as to contact the side surfaces of the trenches 14. In this embodiment, a plurality of emitter regions 15 are scattered between the trenches 14 at equal intervals along the longitudinal direction (x direction) of the trenches 14. In other words, when viewed from the normal direction (+z direction) to the top surface 10a of the semiconductor substrate 10, the emitter regions 15 extend in a direction (y direction) perpendicular to the longitudinal direction of the plurality of trenches 14.

[0020] The first base layer 12a is formed up to the upper surface 10a of the semiconductor substrate 10 in a portion where the emitter region 15 is not formed. This portion serves as a first contact region 16a that is in ohmic contact with an upper electrode 20 (described later). In this embodiment, the first contact region 16a has the same upper surface layout as the emitter region 15 when viewed from the normal direction (+z direction), and the portion of the first base layer 12a that is not formed as the emitter region 15 serves as the first contact region 16a.

[0021] In the FWD region 1b, the second base layer 12b constitutes an anode layer. Note that the second base layer 12b does not have an emitter region 15 formed therein. A second contact region 16b is formed on the upper surface of the second base layer 12b. The second contact region 16b has a higher impurity concentration than the second base layer 12b and is a region that is in ohmic contact with an upper electrode 20 (described later).

[0022] The depth of each second contact region 16b is shallower than the second base layer 12b. The width of each second contact region 16b is arbitrary, but in this embodiment, it is set equal to the width of the first contact region 16a.

[0023] Similarly, in the boundary region 1c, third contact regions 16c are formed on the upper surface of the second base layer 12b. The third contact regions 16c have a higher impurity concentration than the second base layer 12b and are regions that are in ohmic contact with the upper electrode 20 (described later). The depth of each third contact region 16c is the same as that of the second contact region 16b. The width of each third contact region 16c is optional, but is set to be equal to that of the second contact region 16b.

[0024] Each trench 14 is filled with a gate insulating film 17 formed to cover the inner wall surface of the trench 14, and a trench electrode 18 formed on the gate insulating film 17. The trench electrode 18 is made of, for example, polysilicon. This forms a trench gate structure.

[0025] In this embodiment, the trench electrode 18 formed in the IGBT region 1a is connected to a gate drive circuit (not shown) so that a desired gate voltage can be applied thereto. Meanwhile, the trench electrode 18 formed in the FWD region 1b and the boundary region 1c is connected to an upper electrode 20 (described later). That is, the trench electrodes 18 formed in the FWD region 1b and the boundary region 1c are emitter-connected. As a result, when a high-level voltage is applied as a gate voltage for IGBT operation in the IGBT region 1a, a channel is formed on the side surface of the trench 14. Furthermore, in the FWD region 1b, since the trench electrode 18 is set to the emitter potential, no channel is formed even during IGBT operation, and a predetermined FWD operation is performed.

[0026] 3 and 4 , an interlayer insulating film 19 is formed on the upper surface 10a of the semiconductor substrate 10. A contact hole 19a is formed in the interlayer insulating film 19 in the IGBT region 1a, exposing a part of the emitter region 15 and the first contact region 16a. A contact hole 19b is formed in the interlayer insulating film 19 in the FWD region 1b, exposing the second base layer 12b and the second contact region 16b. A contact hole 19c is formed in the interlayer insulating film 19 in the boundary region 1c, exposing the second base layer 12b and the third contact region 16c. Furthermore, a contact hole 19d is formed in the interlayer insulating film 19 in the FWD region 1b and the boundary region 1c, exposing the trench electrode 18.

[0027] An upper electrode 20 is formed on the interlayer insulating film 19. In the IGBT region 1a, the upper electrode 20 is electrically connected to the emitter region 15 and the first contact region 16a through contact holes 19a. In the FWD region 1b and boundary region 1c, the upper electrode 20 is electrically connected to the second base layer 12b, the second contact region 16b, and the third contact region 16c through contact holes 19b and 19c. The upper electrode 20 is further connected to the trench electrode 18 through contact hole 19d. That is, the upper electrode 20 functions as an emitter electrode in the IGBT region 1a and as an anode electrode in the FWD region 1b.

[0028] An N-type field stop (hereinafter referred to as FS) layer 21 having an impurity concentration higher than that of the drift layer 11 is formed on the lower surface 10b side of the semiconductor substrate 10. This FS layer 21 is not essential, but is provided to improve the breakdown voltage and steady-state loss performance by preventing the expansion of the depletion layer, and to control the amount of holes injected from the lower surface 10b side of the semiconductor substrate 10.

[0029] In the IGBT region 1a and the boundary region 1c, a P-type collector layer 22 is formed on the opposite side of the drift layer 11 with the FS layer 21 in between. In the FWD region 1b, an N-type cathode layer 23 is formed on the opposite side of the drift layer 11 with the FS layer 21 in between. That is, in this embodiment, the IGBT region 1a and the boundary region 1c and the FWD region 1b are distinguished from each other by whether the layer formed on the lower surface 10b side of the semiconductor substrate 10 is the collector layer 22 or the cathode layer 23.

[0030] On the lower surface 10b, a lower electrode 24 is formed on the surfaces of the collector layer 22 and the cathode layer 23. This lower electrode 24 functions as a collector electrode in the IGBT region 1a and the boundary region 1c, and functions as a cathode electrode in the FWD region 1b.

[0031] With this configuration, an IGBT element is configured in the IGBT region 1a, with the first base layer 12a as the base, the emitter region 15 as the emitter, and the collector layer 22 as the collector. Also, in the FWD region 1b, an FWD element is configured by PN junction, with the second base layer 12b and the second contact region 16b as the anode, and the drift layer 11 and the cathode layer 23 as the cathode.

[0032] In this embodiment, N-type ＋ Type, N － The type corresponds to the first conductivity type, and P type, P ＋ Type, P － The type corresponds to the second conductivity type.

[0033] (First Simulation Results) A first simulation was performed on the semiconductor device 3 using CAE (Computer Aided Engineering). In the first simulation, the boundary region width W1 was kept constant, and the FWD region width W2 was varied. The degree of carrier injection from the IGBT region 1a to the FWD region 1b was then simulated. The substrate thickness ST was kept constant at 80 μm.

[0034] FIG. 5 shows a graph of the simulation results. The horizontal axis represents the FWD region width W2. The vertical axis represents the voltage ratio VR. The voltage ratio VR is the ratio of the second voltage VFp to the first voltage VF. That is, the equation "VR = VFp / VF" holds. The first voltage VF is the reverse voltage when the gate voltage of the IGBT is smaller than the threshold voltage (e.g., 0 V). The second voltage VFp is the reverse voltage when the gate voltage of the IGBT is larger than the threshold voltage (e.g., 15 V). As the carrier injection from the IGBT region 1a to the FWD region 1b decreases, the second voltage VFp decreases and approaches the first voltage VF. Therefore, a voltage ratio VR closer to 1 indicates that carrier injection from the IGBT region 1a is more effectively suppressed (good characteristics), while a voltage ratio VR greater than 1 indicates that the amount of carrier injection is greater (poor characteristics).

[0035] As shown in FIG. 5 , the voltage ratio VR was simulated while varying the FWD region width W2 from approximately 38 μm to approximately 150 μm. The nine plots obtained indicated that the voltage ratio VR decreased as the FWD region width W2 increased (i.e., carrier injection from the IGBT region 1 a decreased). The nine plots obtained were then approximated by two approximate straight lines L1 and L2. The approximate straight lines L1 and L2 intersect at an intersection IP1. Here, the value of the FWD region width W2 at the intersection IP1 is defined as the specific FWD width W2_S. In the example of FIG. 5 , the specific FWD width W2_S is approximately 67 μm.

[0036] The meaning of the specific FWD width W2_S will be explained. In a region where the FWD region width W2 is smaller than the specific FWD width W2_S, the slope of decrease in the voltage ratio VR is large (approximate line L1). On the other hand, in a region where the FWD region width W2 is larger than the specific FWD width W2_S, the slope of decrease in the voltage ratio VR is small (approximate line L2). Therefore, by setting the FWD region width W2 to be equal to or larger than the specific FWD width W2_S, the carrier injection suppression effect can be sufficiently exhibited.

[0037] Furthermore, the relationship between the boundary region width W1 and the substrate thickness ST can also be derived from the results of the first simulation. This will be explained using FIG. 6 . FIG. 6 is a cross-sectional view similar to FIG. 4 . During diode operation of the semiconductor device 3, carriers (holes) are injected from a high-concentration P-type region, such as the first base layer 12a formed on the upper surface 10a of the IGBT region 1a, toward the N-type cathode layer 23 formed on the lower surface 10b of the FWD region 1b. This carrier injection is performed obliquely, as shown by the imaginary line VL, at an injection angle IA relative to the thickness direction (z direction) of the substrate. This injection angle IA can be approximated to 45°. Furthermore, with the lower end VLe of the imaginary line VL as the boundary, the carrier injection amount can be modeled as being greater on the IGBT region 1a side (+y direction side) than the lower end VLe, and less on the FWD region 1b side (−y direction side) than the lower end VLe. That is, the farther the position of the bottom end VLe is from the boundary BD between the FWD region 1b and the boundary region 1c toward the IGBT region 1a (+y direction), the greater the effect of suppressing carrier injection.

[0038] Consider a hypothetical isosceles triangle IT with a base defined by the virtual line VL and a 90° apex angle. The lengths of the equilateral sides S1 and S2 are equal to the substrate thickness ST. If the boundary region width W1 is set equal to the substrate thickness ST, the lower end VLe of the virtual line VL will be positioned at the boundary BD, making it possible to sufficiently suppress carrier injection (see FIG. 6). From the above, we can derive the relationship that "if the boundary region width W1 is set to a value equal to or greater than the substrate thickness ST, the carrier injection suppression effect can be sufficiently obtained."

[0039] (Second Simulation Results) A second simulation was performed on the semiconductor device 3 using CAE. In the second simulation, both the boundary region width W1 and the FWD region width W2 were changed. The degree of carrier injection from the IGBT region 1 a to the FWD region 1 b was simulated. The substrate thickness ST was kept constant at 80 μm.

[0040] 7 to 10 show graphs of the simulation results. The horizontal axis represents the boundary region width W1. The vertical axis represents the voltage ratio VR. In each of FIGS. 7 to 10, the values ​​of the FWD region width W2 are 63.6 μm, 75.2 μm, 88.8 μm, and 136.8 μm.

[0041] As shown in Figure 7, the obtained plot was approximated by two approximate straight lines L11 and L12. The value of the boundary region width W1 at the intersection IP11 of the approximate straight lines L11 and L12 is defined as the specific boundary width W1_S1. The specific boundary width W1_S1 is approximately 78 µm.

[0042] The meaning of the specific boundary width W1_S1 will be explained. In the region where the boundary region width W1 is smaller than the specific boundary width W1_S1, the slope of decrease in the voltage ratio VR is large (approximate line L11). On the other hand, in the region where the boundary region width W1 is larger than the specific boundary width W1_S1, the slope of decrease in the voltage ratio VR is very small (approximate line L12). In other words, in the region where the boundary region width W1 is larger than the specific boundary width W1_S1, the effect of suppressing carrier injection is saturated. Therefore, it can be seen that the specific boundary width W1_S1 is a value that can minimize the boundary region width W1 while maximizing the effect of suppressing carrier injection. In other words, the specific boundary width W1_S1 is an optimal value that can maximize both the effect of suppressing carrier injection and the effect of shrinking the chip area.

[0043] As shown in FIG. 8 , the plot obtained was approximated by two approximate straight lines L21 and L22. The value of the boundary region width W1 at the intersection IP21 of the approximate straight lines L21 and L22 is defined as the specific boundary width W1_S2. The specific boundary width W1_S2 is approximately 76 μm. Like the specific boundary width W1_S1 described above, the specific boundary width W1_S2 is an optimal value.

[0044] As shown in FIG. 9 , the plot obtained was approximated by two approximate straight lines L31 and L32. The value of the boundary region width W1 at the intersection IP31 of the approximate straight lines L31 and L32 is defined as the specific boundary width W1_S3. The specific boundary width W1_S3 is approximately 72 μm. Like the specific boundary width W1_S1 described above, the specific boundary width W1_S3 is an optimal value.

[0045] As shown in Figure 10, the obtained plot was approximated by two approximate straight lines L41 and L42. The value of the boundary region width W1 at the intersection IP41 of the approximate straight lines L41 and L42 is defined as the specific boundary width W1_S4. The specific boundary width W1_S4 is approximately 59 µm. Like the specific boundary width W1_S1 described above, the specific boundary width W1_S4 is an optimal value.

[0046] The graph of FIG. 11 was then created based on FIGS. 7 to 10. The horizontal axis represents the FWD region width W2, and the vertical axis represents the boundary region width W1. Each of the plots PL1-PL4 corresponds to the specific boundary widths W1_S1-W1_S4 described above. That is, the graph of FIG. 11 shows how the optimal value of the boundary region width W1 changes with respect to the FWD region width W2. An approximate line L51 was then created using the plots PL1-PL4. The approximate line L51 was created within a range equal to or greater than the lower limit value LL of the FWD region width W2 and equal to or less than the upper limit value UL. The lower limit value LL is half the value of the substrate thickness ST. The upper limit value UL is 1.75 times the value of the substrate thickness ST. In this example, the substrate thickness ST is set to 80 μm. Therefore, the lower limit value LL is 40 μm, and the upper limit value UL is 140 μm.

[0047] The lower limit LL and upper limit UL of the FWD region width W2 will now be described. The lower limit LL and upper limit UL can be derived based on the approximate straight lines L1 and L2 described above in FIG. 5 . Plot PP1 in FIG. 5 indicates the lower limit that can be approximated by the approximate straight line L1. The FWD region width W2 of plot PP1 is approximately 38 μm, which is approximately half the substrate thickness ST (80 μm). Therefore, it can be seen that the lower limit LL can be considered to be half the value of the substrate thickness ST. Furthermore, the voltage ratio VR value of plot PP2 (1.0067) is very close to the limit value of 1, and therefore indicates the upper limit that can be approximated by the approximate straight line L2. The FWD region width W2 of plot PP2 is approximately 150 μm, which is approximately 1.8 times the substrate thickness ST (80 μm). Therefore, it can be seen that the upper limit UL can be considered to be 1.75 times the substrate thickness ST.

[0048] 11, the specific formula "W1=-0.25×W2+94 μm" can be derived. This specific formula is valid in the range equal to or greater than the lower limit value LL of the FWD region width W2, and is valid in the range equal to or less than the upper limit value UL.

[0049] Furthermore, as shown by the straight line L52 in FIG. 11 , in the range where the FWD region width W2 is greater than the upper limit value UL, the optimal value of the boundary region width W1 is a constant value. This constant value is obtained by substituting the upper limit value UL into the aforementioned specific formula. The reason for this will be explained. As described above, the upper limit value UL is the limit value at which the effect of suppressing carrier injection from the IGBT region 1a can be enhanced. In other words, in the range where the FWD region width W2 is greater than the upper limit value UL, the boundary region width W1 cannot be narrowed to ensure a predetermined suppression effect of carrier injection. Therefore, the boundary region width W1 indicated by the value obtained by substituting the upper limit value UL into the specific formula is the lower limit that the boundary region width W1 can take.

[0050] In this embodiment, the upper limit value UL is set to 140 μm. Therefore, the value obtained by substituting the upper limit value UL into the specific formula (the lower limit value of the boundary region width W1) is 59 μm.

[0051] As shown by the gray fill in FIG. 11 , a preferred range SR of the boundary region width W1 and the FWD region width W2 can be defined. The preferred range SR is a range within which the effect of suppressing carrier injection from the IGBT region 1a can be appropriately obtained. The range of the boundary region width W1 within the preferred range SR is defined by the approximate lines L51 and L52. That is, the boundary region width W1 is equal to or greater than the values ​​represented by the approximate lines L51 and L52. Furthermore, the range of the FWD region width W2 within the preferred range SR is equal to or greater than a lower limit value LL and equal to or less than an upper limit value UL.

[0052] Note that within the preferred range SR, the smaller the boundary region width W1 is, the more the chip size can be reduced. That is, within the preferred range SR, the closer values ​​to the approximate lines L51 and L52 are used, the more the chip size can be reduced. Using values ​​on the approximate lines L51 and L52 allows the chip size to be minimized.

[0053] (Effect) In an RC-IGBT having an IGBT and an FWD on a single chip, a boundary region 1c that does not function as a diode is disposed between the adjacent IGBT region 1a and FWD region 1b. In this configuration, to suppress carrier injection from the IGBT region 1a to the FWD region 1b, the boundary region width W1 of the boundary region 1c must be equal to or greater than a predetermined value. The inventors discovered that this predetermined value can be reduced as the FWD region width W2 increases. The inventors then proposed a specific formula (W1 = -0.25 × W2 + 94 μm) for determining the predetermined value. Using this specific formula, it is possible to determine an appropriate boundary region width W1 that can fully suppress carrier injection based on the FWD region width W2. Therefore, it is possible to minimize the reduction in active area caused by the placement of the boundary region 1c while maximizing the carrier injection suppression effect.

[0054] Fig. 12 shows a semiconductor substrate 10 according to Example 2. Fig. 12 is a diagram similar to Fig. 2 of Example 1. Example 2 differs from Example 1 in that it includes a lifetime control region 201. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0055] In the technology of Example 2, a lifetime control region 201 is formed in at least one of the IGBT region 1a, the FWD region 1b, and the boundary region 1c. In the example of Fig. 12, a plurality of lifetime control regions 201 are formed in at least a portion of the IGBT region 1a. In Fig. 12, the lifetime control regions 201 are indicated by crosses. The plurality of lifetime control regions 201 are arranged in a plane at a predetermined depth from the upper surface 10a in the drift layer 11.

[0056] The lifetime control region 201 is a region where a large number of crystal defects are formed, and serves as a carrier recombination center. The lifetime control region 201 can be formed by irradiating helium ions from the upper surface 10a of the semiconductor substrate 10. The crystal defect density peaks at a predetermined depth, and the lifetime control region 201 is formed.

[0057] The technology described in this specification can also be applied to a structure including such a lifetime control region 201. That is, it is possible to determine an appropriate boundary region width W1 from the FWD region width W2 using a specific formula.

[0058] The range in which the lifetime control region 201 is formed may vary. For example, it may be formed only in the FWD region 1b, or may be formed over the entire region including the IGBT region 1a, the FWD region 1b, and the boundary region 1c.

[0059] Fig. 13 shows a semiconductor substrate 10 according to Example 3. Fig. 13 is a diagram similar to Fig. 2 of Example 1. Example 3 differs from Example 1 in that it includes a hole injection suppression structure 310. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0060] In the technology of Example 3, a hole injection suppression structure 310 is formed in at least one of the IGBT region 1a, the FWD region 1b, and the boundary region 1c. In the example of FIG. 13 , a plurality of hole injection suppression structures 310 are provided in at least a portion of the IGBT region 1a. The hole injection suppression structure 310 is disposed in a semiconductor region sandwiched between a plurality of trenches 14. The hole injection suppression structure 310 includes an n-type barrier region 311 and an n-type pillar region 312. The barrier region 311 is a region that contacts the base layer 12 from below. A p-type lower base layer 313 is disposed below the barrier region 311. The pillar region 312 is a region that extends from the barrier region 311 to the upper surface 10a. The upper surface of the barrier region 311 is exposed in a portion of the first contact region 16a and is electrically connected to the upper electrode 20.

[0061] The hole injection suppression structure 310 can suppress the injection of holes from the body region to the drift region when the diode is turned on, thereby suppressing the recovery current when the diode performs a recovery operation.

[0062] The techniques described in this specification can also be applied to a structure including such a hole injection suppression structure 310. That is, it is possible to determine an appropriate boundary region width W1 from the FWD region width W2 using a specific formula.

[0063] The hole injection suppression structure 310 may be formed in various regions. For example, it may be formed only in the FWD region 1b, or may be formed over the entire region including the IGBT region 1a, the FWD region 1b, and the boundary region 1c.

[0064] Fig. 14 shows a semiconductor substrate 10 according to Example 4. Fig. 14 is a diagram similar to Fig. 2 of Example 1. Example 4 differs from Example 1 in that it includes a floating region 410. Contents common to Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0065] In the technology of the fourth embodiment, the floating region 410 is formed in at least one of the IGBT region 1 a, the FWD region 1 b, and the boundary region 1 c. In the example of Fig. 14, the floating region 410 is provided over the entire IGBT region 1 a.

[0066] The floating region 410 is provided in the base layer 12. The potential of the floating region 410 is not fixed, but fluctuates depending on the surrounding potential. In this specification, this state in which the potential is not fixed is referred to as a floating state. The floating region 410 extends between adjacent trenches 14. The floating region 410 divides the base layer 12 in the direction connecting the lower electrode 24 and the upper electrode 20 (the z direction). In this embodiment, the base layer located closer to the upper electrode 20 than the floating region 410 is referred to as a first base layer 12a. The base layer located closer to the lower electrode 24 than the floating region 410 is referred to as a lower base layer 12c. The lower base layer 12c is separated from the first base layer 12a by the floating region 410 and is in a floating state.

[0067] The floating region 410 forms a potential barrier against holes. Therefore, when the IGBT element in the IGBT region 1a is turned on, holes injected from the collector layer 22 on the back surface are accumulated at a high concentration in the lower base layer 12c. This allows the IGBT region 1a to be driven with a low on-voltage.

[0068] (Dopant Concentration Range of Floating Region 410) In order to improve the hole accumulation effect of the floating region 410, it is desirable to increase the dopant concentration of the floating region 410. However, if the dopant concentration of the floating region 410 is increased, a pnpn parasitic thyristor consisting of the p-type collector layer 22, the n-type drift layer 11, the p-type lower base layer 12c, and the n-type floating region 410 may operate immediately after turn-on. As a result, a sudden increase in current may occur, inducing a surge voltage. The parasitic thyristor operates because electrons are injected from the floating region 410 into the lower base layer 12c immediately after turn-on of the IGBT region 1a, causing a rise in the potential of the lower base layer 12c.

[0069] Here, the total amount of carriers (total amount of free electrons) in the floating region 410 is defined as the first total amount of carriers. The total amount of carriers (total amount of holes) in the lower base layer 12c is defined as the second total amount of carriers. The ratio of the first total amount of carriers to the second total amount of carriers (total amount of first carriers / total amount of second carriers) is defined as the total carrier amount ratio. In order to suppress the surge voltage described above, it is important to make this total carrier amount ratio smaller than a predetermined value.

[0070] FIG. 15 shows the on-voltage and voltage change during turn-on of the IGBT region 1a when the total carrier ratio is changed. In FIG. 15, the example of a total carrier ratio of "0" represents the result when the floating region 410 is not formed. The example of an increased total carrier ratio represents the result when the carrier concentration (free electron concentration) of the floating region 410 is high. As shown in FIG. 15, when the floating region 410 is formed, the on-voltage drops sharply. When the total carrier ratio is 0.4 or higher, the on-voltage reduction effect saturates. It can be seen that a total carrier ratio of 0.4 or higher significantly reduces the on-voltage. Furthermore, the voltage change during turn-on remains constant up to a total carrier ratio of 1.83 and increases sharply when the total carrier ratio exceeds 1.83. This total carrier ratio of 1.83 is the point at which the parasitic thyristor operates.

[0071] 15, if the total carrier amount ratio is greater than 0 and equal to or less than 1.83, it is possible to obtain a reduction effect in on-state voltage and to prevent the parasitic thyristor from substantially operating. In other words, if the total carrier amount ratio is equal to or greater than 0.4 and equal to or less than 1.83, it is possible to simultaneously achieve both a significant reduction effect in on-state voltage and an effect of suppressing surge voltage.

[0072] (Manufacturing Method) The floating region 410 can be formed by introducing a dopant into the upper surface 10a of the semiconductor substrate 10 using an ion implantation technique.

[0073] A first mask covering the FWD region 1b and the boundary region 1c is formed on the upper surface 10a using a well-known photolithography technique. A base layer 12 is formed in the IGBT region 1a by ion implanting p-type impurities through the first mask. A floating region 410 is formed in the IGBT region 1a by ion implanting n-type impurities through the first mask. By appropriately controlling the implantation depth of the n-type impurities, the floating region 410 is formed at a midpoint in the depth direction of the base layer 12. This allows the base layer 12 to be divided into a first base layer 12a and a lower base layer 12c.

[0074] A second mask covering the IGBT region 1a is formed on the upper surface 10a using a well-known photolithography technique. A second base layer 12b is formed in the FWD region 1b and the boundary region 1c by ion implantation of p-type impurities through the second mask. The p-type impurity concentration of the second base layer 12b is set lower than the p-type impurity concentration of the first base layer 12a.

[0075] The first mask and the second mask are masks used to differentiate the p-type impurity concentrations of the first base layer 12 a and the second base layer 12 b. These masks can be used to selectively form the floating region 410 in the IGBT region 1 a. Because an additional photolithography process is not required, the manufacturing cost of the floating region 410 can be reduced.

[0076] (Modification of Fourth Embodiment) The region where the floating region 410 is formed may be various. For example, as shown in Fig. 16, the floating region 410 and the lower base layer 12c may be arranged in the IGBT region 1a and the boundary region 1c. Furthermore, as shown in Fig. 17, the floating region 410 and the lower base layer 12c may be arranged across the entire IGBT region 1a, the boundary region 1c, and the FWD region 1b.

[0077] 18 to 23 show a semiconductor substrate 10 according to a fifth embodiment. 18 to 23 are similar to FIG. 2 of the first embodiment. In the fifth embodiment, six examples will be described in which the area of ​​the contact region exposed to the upper surface 10 a in the FWD region 1 b and the boundary region 1 c is smaller than the area of ​​the contact region exposed to the upper surface 10 a in the IGBT region 1 a. The same reference numerals will be used to designate parts common to the first to fourth embodiments, and descriptions thereof will be omitted.

[0078] A semiconductor substrate 10 according to the first embodiment shown in FIG. 2 will be described. In the IGBT region 1a, a first contact region 16a is exposed on the top surface 10a. In the FWD region 1b, a second contact region 16b is exposed on the top surface 10a. In the boundary region 1c, a third contact region 16c is exposed on the top surface 10a. The first contact region 16a, the second contact region 16b, and the third contact region 16c have the same width in the x direction. The first contact region 16a, the second contact region 16b, and the third contact region 16c are aligned linearly along the y direction and are periodically and repeatedly arranged in the x direction. As a result, in the first embodiment, the first contact region 16a, the second contact region 16b, and the third contact region 16c all have the same layout area per unit area.

[0079] A first example ( FIG. 18 ) of the semiconductor substrate 10 of Example 5 will be described. The first contact region 16a has a width Wa in the x-direction. The second contact region 16b and the third contact region 16c have a width Wb in the x-direction. The width Wb is smaller than the width Wa. The period of repetition in the x-direction of the second contact region 16b and the third contact region 16c is longer than that of the first contact region 16a. Specifically, the second contact region 16b and the third contact region 16c are arranged every other first contact region 16a that are repeatedly arranged in the x-direction. That is, the number of second contact regions 16b and the third contact regions 16c is approximately half the number of first contact regions 16a. As a result, in Example 5, the layout area per unit area of ​​the second contact region 16b and the third contact region 16c is smaller than the layout area per unit area of ​​the first contact region 16a.

[0080] The effects of the fifth embodiment will be described below. In the configuration of the fifth embodiment shown in FIG. 18, the layout area of ​​the second contact region 16b in the FWD region 1b and the layout area of ​​the third contact region 16c in the boundary region 1c can be made smaller than the layout area of ​​the first contact region 16a in the IGBT region 1a. Therefore, hole injection from the FWD region 1b and the boundary region 1c can be suppressed during recovery. This makes it possible to reduce switching loss and increase resistance to recovery breakdown.

[0081] A second example ( FIG. 19 ) of the semiconductor substrate 10 of Example 5 will be described. The second example ( FIG. 19 ) differs from the first example ( FIG. 18 ) only in that a lifetime control region 201 is formed in at least one of the IGBT region 1 a, the FWD region 1 b, and the boundary region 1 c. The multiple lifetime control regions 201 are arranged in a planar shape at a predetermined depth from the upper surface 10 a in the drift layer 11. The effect of the lifetime control region 201 has already been described in Example 2.

[0082] A third example ( FIG. 20 ) { FIG. 13} of the semiconductor substrate 10 of the fifth embodiment will be described. The third example ( FIG. 20 ) differs from the first example ( FIG. 18 ) only in that a hole injection suppression structure 310 is formed in at least one of the IGBT region 1 a, the FWD region 1 b, and the boundary region 1 c. In the example of FIG. 20 , a plurality of hole injection suppression structures 310 are provided in the IGBT region 1 a. The effect of the hole injection suppression structure 310 has already been described in the third embodiment.

[0083] A fourth example ( FIG. 21 ) { FIG. 14} of the semiconductor substrate 10 of the fifth embodiment will be described. The fourth example ( FIG. 21 ) differs from the first example ( FIG. 18 ) only in that a floating region 410 is formed in at least one of the IGBT region 1 a, the FWD region 1 b, and the boundary region 1 c. In the example of FIG. 21 , the floating region 410 is provided over the entire IGBT region 1 a. The effect of the floating region 410 has already been described in the fourth embodiment.

[0084] A fifth example (FIG. 22) {FIG. 16} of the semiconductor substrate 10 of the fifth embodiment will be described. The fifth example (FIG. 22) differs from the fourth example (FIG. 21) in that the floating region 410 and the lower base layer 12c are disposed in the IGBT region 1a and the boundary region 1c.

[0085] A sixth example (FIG. 23) {FIG. 17} of the semiconductor substrate 10 of Example 5 will be described. The sixth example (FIG. 23) differs from the fourth example (FIG. 21) in that the floating region 410 and the lower base layer 12c are disposed over the entire IGBT region 1a, boundary region 1c, and FWD region 1b.

[0086] FIG. 24 shows a semiconductor substrate 10 according to a sixth embodiment. FIG. 24 is a diagram similar to FIG. 2 of the first embodiment. In the fifth embodiment, a case will be described in which the area of ​​the contact region exposed to the upper surface 10 a in the boundary region 1 c is smaller than the area of ​​the contact region exposed to the upper surface 10 a in the IGBT region 1 a and the FWD region 1 b. Contents common to the first to fifth embodiments will be denoted by the same reference numerals, and description thereof will be omitted.

[0087] The x-direction width of the first contact region 16a is equal to the x-direction width of the adjacent emitter region 15. The x-direction width of the second contact region 16b is equal to or smaller than the x-direction width of the first contact region 16a. In Example 6, the x-direction width of the second contact region 16b is equal to the x-direction width of the first contact region 16a. The x-direction width of the third contact region 16c is smaller than the x-direction width of the second contact region 16b. Here, the x-direction width of the third contact region 16c is defined as width W3. Furthermore, the x-direction width of a region disposed between the third contact regions 16c and from which the second base layer 12b is exposed is defined as width W4. In Example 6, the ratio of widths W3 to W4 is 1:2. As a result, the layout area per unit area of ​​the third contact region 16c is smaller than the layout area per unit area of ​​the second contact region 16b.

[0088] In Example 6, a boundary region 1c is provided between the IGBT region 1a and the FWD region 1b, in which the formation ratio of the contact region is smaller than that of the IGBT region 1a. This makes it possible to suppress hole injection from the IGBT region 1a to the diode region 1b during recovery. Furthermore, because the formation ratio of the third contact region 16c in the boundary region 1c is small, the amount of holes injected from the third contact region 16c can also be reduced. This makes it possible to reduce switching loss and increase resistance to recovery breakdown.

[0089] The configuration of the sixth embodiment can be applied to each of the second example (FIG. 19) to the sixth example (FIG. 23) of the fifth embodiment described above.

[0090] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

[0091] (Modification) In the above-described embodiment, the case where the emitter potential is applied to the trench electrode 18 in the FWD region 1 b has been described. However, a gate voltage may be applied to the trench electrode 18 in the FWD region 1 b. Furthermore, the trench electrode 18 may not be provided in at least one of the FWD region 1 b and the boundary region 1 c.

[0092] In the above-described embodiment, a trench type IGBT is formed in the IGBT region 1a, but a planar type IGBT may also be formed in the IGBT region 1a.

[0093] The values ​​of the substrate thickness ST, the boundary region width W1, the FWD region width W2, etc. shown in this embodiment are merely examples, and various values ​​can be used.

[0094] The material of the semiconductor substrate 10 is not limited to silicon, but may be a wide-gap semiconductor (e.g., SiC, GaN, Ga ２ O ３ etc.) can be used.

[0095] In each of the above embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0096] The configurations of the techniques disclosed in this specification are listed below. [Configuration 1] A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements; a plurality of FWD regions (1b) having FWD elements; and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, wherein the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extend in a first direction (x) and are arranged alternately in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) are located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b), and the semiconductor substrate comprises: a drift layer (11) of a first conductivity type; a second conductivity type base layer (12) formed in a surface layer portion of the drift layer; a second conductivity type collector layer (22) formed in the IGBT region on a side of the drift layer opposite to the base layer side; a first conductivity type cathode layer (23) formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and formed deeper than the base layer to reach the drift layer; and a first conductivity type emitter region (15) formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trenches, a semiconductor device according to the first embodiment, wherein the width of the boundary region (1c) in the second direction is a boundary region width W1 μm, and half the width of the FWD region (1b) in the second direction is an FWD region width W2 μm, and the boundary region width W1 is equal to or greater than a predetermined value calculated by a specific formula expressed as {W1 = -0.25 × W2 + 94 μm}. [Configuration 2] The semiconductor device according to the first embodiment, wherein the specific formula is valid in a range equal to or greater than a lower limit value of the FWD region width W2, and the lower limit value is half the thickness of the semiconductor substrate.[Configuration 3] The semiconductor device according to configuration 1 or 2, wherein the specifying formula is valid in a range equal to or less than an upper limit value of the FWD region width W2, and the upper limit value is 1.75 times the substrate thickness of the semiconductor substrate. [Configuration 4] The semiconductor device according to any one of configurations 1-3, wherein, when the FWD region width W2 is in a range greater than the upper limit value, the value of the boundary region width W1 is equal to or greater than a certain value obtained by substituting the upper limit value into the specifying formula. [Configuration 5] The semiconductor device according to any one of configurations 1-4, further comprising a first conductivity type floating region (410) provided within the base layer (12a, 12c) and dividing the base layer in a direction connecting the lower electrode and the upper electrode, the floating region being disposed at least within the IGBT region. [Configuration 6] The semiconductor device according to configuration 5, wherein the floating region is further disposed within the boundary region. [Configuration 7] The semiconductor device according to configuration 6, wherein the floating region is further disposed within the FWD region. [Configuration 8] The semiconductor device according to any one of configurations 5 to 7, wherein when a total amount of carriers in the floating region is defined as a first total amount of carriers, and a total amount of carriers in a base region located closer to the drift layer than the floating region is defined as a second total amount of carriers, a total amount of carriers ratio, which is a ratio of the first total amount of carriers to the second total amount of carriers, is set within a range in which a parasitic thyristor does not operate when the IGBT element is turned on.[Configuration 9] The base layer comprises a first base layer (12a) formed in the IGBT region and a second base layer (12b) formed in the FWD region and the boundary region, wherein a second conductivity type impurity concentration of the second base layer is lower than a second conductivity type impurity concentration of the first base layer, and the semiconductor substrate further comprises: a first contact region (16a) formed by the first base layer exposed at the upper surface (10a) of the semiconductor substrate in a region where the emitter region is not arranged in the IGBT region; a second contact region (16b) formed above the second base layer in the FWD region, exposed at the upper surface (10a), and having a second conductivity type impurity concentration higher than that of the second base layer; and a third contact region (16c) formed above the second base layer in the boundary region, exposed at the upper surface, and having a second conductivity type impurity concentration higher than that of the second base layer, The semiconductor device according to any one of the preceding claims, wherein the layout areas per unit area of ​​the second contact region and the third contact region are smaller than the layout area per unit area of ​​the first contact region. [Structure 10] The semiconductor device according to the preceding claim, wherein the layout area per unit area of ​​the third contact region is smaller than the layout area per unit area of ​​the second contact region.

[0097] According to the second configuration, by using the specific formula within a range equal to or greater than the lower limit, it is possible to determine an appropriate boundary region width W1 based on the FWD region width W2.

[0098] According to the third aspect, by using the specific expression within a range equal to or less than the upper limit value, it is possible to determine an appropriate boundary region width W1 based on the FWD region width W2.

[0099] According to the fourth configuration, even when the FWD region width W2 is in a range greater than the upper limit value, it is possible to determine an appropriate boundary region width W1.

[0100] According to the configuration 5-7, the IGBT elements in the IGBT region can be driven with a low on-voltage.

[0101] According to the eighth configuration, it is possible to obtain the effect of reducing the on-state voltage and the effect of suppressing the surge voltage.

[0102] According to the ninth configuration, hole injection from the FWD region and the boundary region can be suppressed during recovery.

[0103] According to the tenth aspect, the amount of holes injected from the third contact region can be further reduced.

Claims

1. A semiconductor device (3) comprising a semiconductor substrate (10), a lower electrode (24) in contact with a lower surface (10b) of the semiconductor substrate, and an upper electrode (20) in contact with an upper surface (10a) of the semiconductor substrate, wherein the semiconductor substrate comprises: a plurality of IGBT regions (1a) having IGBT elements; a plurality of FWD regions (1b) having FWD elements; and a plurality of boundary regions (1c) arranged between the plurality of IGBT regions and the FWD regions, wherein the plurality of IGBT regions (1a) and the plurality of FWD regions (1b) extend in a first direction (x) and are arranged alternately in a second direction (y) perpendicular to the first direction, and a plurality of the boundary regions (1c) are located in each of the regions between the plurality of IGBT regions (1a) and the plurality of FWD regions (1b), and the semiconductor substrate comprises: a drift layer (11) of a first conductivity type; a second conductivity type base layer (12) formed in a surface layer portion of the drift layer; a second conductivity type collector layer (22) formed in the IGBT region on a side of the drift layer opposite to the base layer side; a first conductivity type cathode layer (23) formed in the FWD region on a side of the drift layer opposite to the base layer side; a trench gate structure in which a gate insulating film (17) and a gate electrode (18) are arranged in a plurality of trenches (14) formed in the IGBT region, the trenches extending longitudinally in one direction and formed deeper than the base layer to reach the drift layer; and a first conductivity type emitter region (15) formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trenches, a semiconductor device, wherein when the width of the boundary region (1c) in the second direction is a boundary region width W1 μm and half the width of the FWD region (1b) in the second direction is an FWD region width W2 μm, the boundary region width W1 is equal to or greater than a predetermined value calculated by a specific formula expressed as {W1 = -0.25 × W2 + 94 μm}.

2. The semiconductor device according to claim 1, wherein the specified formula is valid in a range equal to or greater than a lower limit value of the FWD region width W2, and the lower limit value is half the thickness of the semiconductor substrate.

3. The semiconductor device according to claim 1 or 2, wherein the specified formula is valid in a range equal to or less than an upper limit value of the FWD region width W2, and the upper limit value is 1.75 times the substrate thickness of the semiconductor substrate.

4. The semiconductor device according to claim 3, wherein, in a range in which the FWD region width W2 is greater than the upper limit value, the value of the boundary region width W1 is equal to or greater than a certain value obtained by substituting the upper limit value into the specified formula.

5. The semiconductor device according to claim 1, further comprising a floating region (410) of a first conductivity type provided inside the base layer (12a, 12c) and dividing the base layer in a direction connecting the lower electrode and the upper electrode, the floating region being arranged at least within the IGBT region.

6. The semiconductor device according to claim 5, wherein the floating region is further disposed within the boundary region.

7. The semiconductor device according to claim 6, wherein the floating region is further disposed within the FWD region.

8. The semiconductor device according to claim 5, wherein, when a total amount of carriers in the floating region is defined as a first total amount of carriers, and a total amount of carriers in a base region located closer to the drift layer than the floating region is defined as a second total amount of carriers, a total amount of carriers ratio, which is the ratio of the first total amount of carriers to the second total amount of carriers, is set within a range in which a parasitic thyristor does not operate when the IGBT element is turned on.

9. The base layer comprises a first base layer (12a) formed in the IGBT region and a second base layer (12b) formed in the FWD region and the boundary region, wherein a second conductivity type impurity concentration of the second base layer is lower than a second conductivity type impurity concentration of the first base layer, and the semiconductor substrate further comprises: a first contact region (16a) formed by the first base layer exposed at the upper surface (10a) of the semiconductor substrate in a region where the emitter region is not arranged in the IGBT region; a second contact region (16b) formed above the second base layer in the FWD region, exposed at the upper surface (10a), and having a second conductivity type impurity concentration higher than that of the second base layer; and a third contact region (16c) formed above the second base layer in the boundary region, exposed at the upper surface, and having a second conductivity type impurity concentration higher than that of the second base layer, 2. The semiconductor device according to claim 1, wherein the layout area per unit area of ​​said second contact region and said third contact region is smaller than the layout area per unit area of ​​said first contact region.

10. The semiconductor device according to claim 9, wherein the layout area per unit area of ​​said third contact region is smaller than the layout area per unit area of ​​said second contact region.

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