Semiconductor package and high-frequency module

Abstract

A semiconductor package (1) comprises: an IC chip (10) including an analog circuit block (11); and a substrate on which the IC chip (10) is mounted. The IC chip (10) includes a metal pad (12) electrically connected to a power supply. A metal terminal (40) is connected to the metal pad (12). The substrate includes a via (24) and a wiring pattern (23) that connects the via (24) and the metal terminal (40). The metal pad (12), the metal terminal (40), the via (24), and the wiring pattern (23) are disposed at positions that do not overlap the analog circuit block (11) in plan view.

Description

Semiconductor packages and high-frequency modules

[0001] This application claims priority to Japanese Patent Application No. 2024-071684, filed on April 25, 2024, the contents of which are incorporated herein by reference.

[0002] Japanese Patent Application Laid-Open No. 2003-144222 discloses a semiconductor package in which an RFIC (Radio Frequency Integrated Circuit) chip is flip-chip mounted on a resin substrate and then resin-molded.

[0003] Japanese Patent No. 3933601

[0004] In semiconductor packages that handle high-frequency signals, the high-frequency signals processed by the analog circuits can affect the power supply path that supplies power to the semiconductor package, generating unwanted waves in this power supply path. This effect may become even more pronounced as semiconductor packages become smaller. For this reason, there is a demand for improved isolation between the analog circuits and power supply paths in semiconductor packages.

[0005] The present disclosure has been made in consideration of the above circumstances, and aims to provide a semiconductor package and a high-frequency module that can improve isolation between an analog circuit and a power supply path.

[0006] A semiconductor package according to a first aspect of the present disclosure comprises an IC chip having an analog circuit block and a substrate on which the IC chip is mounted, wherein the IC chip has metal pads electrically connected to a power supply, and metal terminals are connected to the metal pads, and the substrate has vias and a wiring pattern connecting the vias and the metal terminals, and the metal pads, the metal terminals, the vias, and the wiring pattern are positioned so as not to overlap with the analog circuit block in a planar view.

[0007] A semiconductor package according to a second aspect of the present disclosure is the semiconductor package according to the first aspect, wherein the IC chip has a plurality of the analog circuit blocks, and the metal pads, the metal terminals, the vias, and the wiring pattern are arranged in positions that overlap in a planar view with an area between at least two of the plurality of analog circuit blocks that are adjacent to each other.

[0008] A semiconductor package according to a third aspect of the present disclosure is the same as the second aspect, in that the metal terminals and the vias are arranged on a straight line extending in a direction perpendicular to the opposing direction of the two analog circuit blocks in a planar view.

[0009] A semiconductor package according to a fourth aspect of the present disclosure is the semiconductor package of the second or third aspect, wherein a plurality of the metal terminals and a plurality of the vias are formed.

[0010] A semiconductor package according to a fifth aspect of the present disclosure is the fourth aspect, wherein the plurality of metal terminals and the plurality of vias are arranged alternately at equal intervals in a direction perpendicular to the opposing direction of the two analog circuit blocks in a planar view.

[0011] A semiconductor package according to a sixth aspect of the present disclosure is any one of the second to fifth aspects, in which the metal pad, the metal terminal, the via, and the wiring pattern are arranged at a central position in a planar view between the two analog circuit blocks.

[0012] A semiconductor package according to a seventh aspect of the present disclosure is any one of the second to sixth aspects, wherein the substrate has peripheral vias connected to the wiring pattern and arranged closer to the outer edge of the package in a planar view than the plurality of analog circuit blocks, and the peripheral vias are not arranged on a straight line passing through the metal terminals and the vias arranged in the area between the two analog circuit blocks.

[0013] A semiconductor package according to an eighth aspect of the present disclosure is any one of the first to seventh aspects, wherein the substrate has a plurality of wiring layers, and a GND solid pattern is formed on at least one of the plurality of wiring layers, and the GND solid pattern overlaps with at least a portion of the metal pads, the metal terminals, the vias, and the wiring pattern in a planar view.

[0014] The semiconductor package according to a ninth aspect of the present disclosure is the eighth aspect, further comprising an external connection terminal for inputting and outputting high-frequency signals, arranged in a position overlapping the GND solid pattern in a plan view.

[0015] A semiconductor package according to a tenth aspect of the present disclosure is any one of the first to ninth aspects, wherein the metal terminal and the via are arranged at different positions from each other in a plan view.

[0016] A high-frequency module according to an eleventh aspect of the present disclosure includes a semiconductor package according to any one of the first to tenth aspects, and a module substrate having an antenna and on which the semiconductor package is mounted.

[0017] According to aspects of the present disclosure, it is possible to provide a semiconductor package and a high-frequency module that can improve isolation between an analog circuit and a power supply path.

[0018] Fig. 3 is a block diagram of a phased array antenna device according to an embodiment. Fig. 4 is a schematic diagram of a phased array antenna device according to an embodiment. Fig. 5 is a plan view of a semiconductor package according to an embodiment. Fig. 6 is a cross-sectional view taken along arrows IV-IV in Fig. 3. Fig. 7 is a plan view of a semiconductor package according to a modified example of the embodiment. Fig. 8 is a plan view of a semiconductor package according to a modified example of the embodiment. Fig. 9 is a schematic diagram of a semiconductor package according to a modified example of the embodiment.

[0019] Hereinafter, a semiconductor package and a high-frequency module according to an embodiment of the present disclosure will be described with reference to the drawings.

[0020] 1 is a block diagram of a phased array antenna apparatus 100 according to an embodiment. As shown in Fig. 1, the phased array antenna apparatus 100 includes a frequency conversion IC (FCIC) 101, a bandpass filter (BPF) 102, an antenna combiner 103, a beamforming IC (BFIC) 104, and a phased array antenna 105.

[0021] The frequency conversion IC 101 converts the frequency of an intermediate frequency (IF) signal using a local oscillator (LO) signal to generate a high-frequency signal (radio frequency (RF) signal), and outputs the generated high-frequency signal to a band-pass filter 102. The band-pass filter 102 attenuates signals outside a predetermined frequency band (e.g., LO signal components) and outputs the high-frequency signal that has passed through the filter to an antenna combiner 103. The antenna combiner 103 distributes the high-frequency signal and outputs it to each of a plurality of beamforming ICs 104 provided.

[0022] The beamforming IC 104 imparts a phase difference to the high-frequency signal and outputs it to the phased array antenna 105. The phased array antenna 105 changes the beam direction according to the phase difference of the high-frequency signal. Note that, although the flow of the signal when transmitting the high-frequency signal is indicated by an arrow in FIG. 1, when receiving the high-frequency signal, the signal flows in the opposite direction to the arrow shown in FIG. 1.

[0023] Fig. 2 is a schematic diagram of the phased array antenna apparatus 100 according to the embodiment. Fig. 2 corresponds to a partial cross-sectional view of the phased array antenna apparatus 100 taken in the thickness direction of a substrate 2 (described later).

[0024] As shown in FIG. 2 , a semiconductor package 1 is mounted on a substrate 2 (i.e., a module substrate). The direction in which the semiconductor package 1 faces the substrate 2 may be referred to as the thickness direction of the substrate 2. The semiconductor package 1 and the substrate 2 constitute a phased array antenna module 3. The phased array antenna module 3 is an example of a high-frequency module. The substrate 2 may be formed using epoxy resin, modified polyphenylene ether, or the like. A build-up substrate including a core material may be used for the substrate 2.

[0025] The semiconductor package 1 has a plurality of analog circuits formed therein, for example, circuits corresponding to the frequency conversion IC 101, bandpass filter 102, antenna combiner 103, and beamforming IC 104 described above. Note that it is not necessary to form all of these components in one semiconductor package 1, and these components may be formed separately in multiple semiconductor packages. The semiconductor package 1 may also have a digital circuit formed therein that processes digital signals.

[0026] A plurality of pads 4 are formed on the surface of the substrate 2 facing the semiconductor package 1. A plurality of solder bumps 50 connected to the plurality of pads 4 are formed on the surface of the semiconductor package 1 facing the substrate 2. The solder bumps 50 are external connection terminals for mounting the semiconductor package 1. The solder bumps 50 include RF bumps 51 through which high frequency signals pass, power supply bumps 52 for supplying power to each circuit of the semiconductor package 1, and electrically grounded GND bumps 53.

[0027] A phased array antenna 105 is provided on the surface of the substrate 2 opposite to the surface facing the semiconductor package 1. The phased array antenna 105 is electrically connected to the RF bumps 51 of the semiconductor package 1 via the conductors 6 and pads 4 formed on the substrate 2.

[0028] The power supply bumps 52 of the semiconductor package 1 are electrically connected to a power supply 8 via pads 4 and conductors 7 formed on the substrate 2. The power supply 8 supplies power to each circuit in the semiconductor package 1. The power supply 8 may be disposed in the phased array antenna module 3 or may be provided outside the phased array antenna module 3.

[0029] Fig. 3 is a plan view of the semiconductor package 1 according to the embodiment. Fig. 4 is a cross-sectional view taken along the line IV-IV in Fig. 3. As shown in Figs. 3 and 4, the semiconductor package 1 includes an IC chip 10 that processes high-frequency signals, a substrate 20 on which the IC chip 10 is mounted, a mold resin 35 filled between the IC chip 10 and the substrate 20, and a plurality of solder bumps 50.

[0030] The IC chip 10 has a plurality of analog circuits that process high-frequency signals. The locations in the IC chip 10 where these analog circuits are formed are referred to as analog circuit blocks 11. That is, the IC chip 10 has a plurality of analog circuit blocks 11. Note that Fig. 3 shows only two of the multiple (e.g., eight) analog circuit blocks 11. Note that the IC chip 10 may also have a digital circuit block that processes digital signals.

[0031] The analog circuit block 11 may be, for example, a circuit corresponding to any one of the frequency conversion IC 101, the bandpass filter 102, the antenna combiner 103, and the beamforming IC 104 described above.

[0032] Hereinafter, the direction in which the IC chip 10 and the substrate 20 face each other may be referred to as the up-down direction (or thickness direction), and in this case, the side on which the IC chip 10 is provided will be referred to as the upper side, and the side on which the substrate 20 is provided will be referred to as the lower side. "Planar view" refers to viewing the semiconductor package 1 in the up-down direction. The up-down direction may be the same as or different from the direction of gravity. The direction in which the two analog circuit blocks 11 shown in FIG. 3 face each other may be referred to as the left-right direction, and the direction perpendicular to the left-right direction in planar view may be referred to as the front-rear direction.

[0033] The semiconductor package 1 and the IC chip 10 are both rectangular in plan view, and are both formed in the shape of a plate with its plate surface facing up and down, but there are no particular limitations on their outer shapes.

[0034] As shown in FIGS. 3 and 4 , a plurality of metal pads 12 are formed on the underside of the IC chip 10. Note that FIGS. 3 and 4 show two of the plurality of metal pads 12. The metal pads 12 are formed using, for example, aluminum. While the metal pads 12 are rectangular in plan view, their shape is not particularly limited and they may be circular in plan view, for example. Some of the metal pads 12 are electrically connected to the power source 8 described above. That is, power is supplied to the IC chip 10 via the some of the metal pads 12. The two metal pads 12 shown in FIGS. 3 and 4 are electrically connected to the power source 8 and are used to supply power to the IC chip 10. The other metal pads 12 may be used for inputting and outputting, for example, high-frequency signals or digital signals to and from the IC chip 10.

[0035] A passivation film (not shown) is formed on the underside of the IC chip 10. The passivation film is, for example, a nitride film or an oxide film, and is provided to protect the IC chip 10. The passivation film covers the periphery of the metal pad 12, and the portion of the metal pad 12 other than the periphery (i.e., the central portion) is exposed downward.

[0036] Metal terminals 40 are connected to the metal pads 12. That is, the number of metal pads 12 and the number of metal terminals 40 are the same. FIGS. 3 and 4 show two of the multiple metal terminals 40. The metal terminals 40 are fabricated, for example, by plating the metal pads 12 with copper (Cu) to form copper terminals, and then plating the formed copper terminals with nickel (Ni). Note that the manufacturing method and composition of the metal terminals 40 are not limited to this. Solder (e.g., tin-silver alloy (SnAg), tin (Sn), SAC305, or SAC405) is used to connect the metal terminals 40 to the wiring pattern 23 of the substrate 20, which will be described later. To improve isolation, the height of the metal terminals 40 is preferably, for example, 30 μm or more.

[0037] The substrate 20 has multiple wiring layers stacked in the vertical direction, namely, a first wiring layer 21 arranged on the IC chip 10 side and a second wiring layer 22 stacked on the lower surface of the first wiring layer 21. The first wiring layer 21 and the second wiring layer 22 are formed from a resin material such as epoxy or polyimide. The first wiring layer 21 and the second wiring layer 22 may contain a filler such as silica.

[0038] The first wiring layer 21 and the second wiring layer 22 may be formed from a dielectric layer. In this case, each dielectric layer may be made of the same material from the viewpoint of reducing changes in material properties and reducing characteristic variations. It is preferable that the wiring (not shown) of the substrate 20 through which high-frequency signals pass be impedance-matched from the viewpoint of reducing reflections.

[0039] A strip-shaped wiring pattern 23 extending in the front-rear direction is provided on the upper surface of the first wiring layer 21. The wiring pattern 23 is formed using, for example, copper. The wiring pattern 23 is disposed at a central position between the two analog circuit blocks 11 described above in a plan view. The wiring pattern 23 shown in FIGS. 3 and 4 is provided with two pads 23a and two lands 23b. The two pads 23a and the two lands 23b are, for example, arranged alternately at equal intervals in the front-rear direction. The wiring pattern 23 may be provided with one or three or more pads, or one or three or more lands. The semiconductor package 1 may be provided with wiring patterns other than the wiring pattern 23.

[0040] The pad 23a is formed in a circular shape in a plan view, and the upper surface of the pad 23a is connected to the metal terminal 40. As described above, the pad 23a and the metal terminal 40 are connected to each other using solder (e.g., tin-silver alloy, tin, SAC305, or SAC405).

[0041] The land 23b is formed in a circular shape in a plan view. Figures 3 and 4 show two vias 24 that penetrate the first wiring layer 21 in the vertical direction. The vias 24 are formed using, for example, copper. The upper ends of the vias 24 are connected to the lands 23b. Therefore, the wiring pattern 23 electrically connects the vias 24 and the metal terminals 40. The number of vias 24 may be one or three or more.

[0042] A wiring pattern 25 is formed on the upper surface of the second wiring layer 22. The wiring pattern 25 is connected to the lower ends of the two vias 24. The wiring pattern 25 is formed using, for example, copper. Two vias 26 that penetrate the second wiring layer 22 in the vertical direction are shown in Figures 3 and 4. The upper ends of the vias 26 are connected to the lower side of the wiring pattern 25. The number of vias 26 may be one or three or more.

[0043] The lower ends of the two vias 26 are connected to the power bump 52 via a metal layer 54. The metal layer 54 is provided on the lower surface of the second wiring layer 22. The metal layer 54 constitutes an under bump metal (UMB) and is formed using, for example, copper. The metal layer 54 covers the upper ends of the power bump 52. For example, conformal vias or filled vias may be used as the vias 24 and 26.

[0044] As described above, the power supply bump 52 is configured to be electrically connected to the power supply 8, and therefore, power can be supplied to the metal pad 12 of the IC chip 10 via the above-mentioned power supply path, thereby driving the analog circuit block 11, digital circuit block, etc. in the IC chip 10.

[0045] The molding resin 35 is filled on the sides of the IC chip 10 and between the IC chip 10 and the substrate 20. For example, an epoxy resin or the like is used as the molding resin 35. The molding resin 35 may contain a filler such as silica.

[0046] The semiconductor package 1 can be manufactured using so-called FOWLP (Fan Out Wafer Level Package). For example, a manufacturing method may be used in which components for the IC chip 10 and components for the substrate 20 are manufactured separately, and the two are joined by reflow or the like, and then filled with mold resin 35. Note that, similar to FOWLP, the semiconductor package 1 may also be manufactured using a similar package having solder bumps 50 and mold resin 35, such as FC-BGA (Flip Chip-Ball Grid Array) technology or PLP (Panel Level Package) technology.

[0047] The semiconductor package 1 of this embodiment comprises an IC chip 10 having an analog circuit block 11 and a substrate 20 on which the IC chip 10 is mounted, the IC chip 10 having a metal pad 12 electrically connected to a power supply 8, a metal terminal 40 connected to the metal pad 12, the substrate 20 having a via 24 and a wiring pattern 23 connecting the via 24 and the metal terminal 40, and the metal pad 12, the metal terminal 40, the via 24 and the wiring pattern 23 are arranged in positions that do not overlap with the analog circuit block 11 in a planar view.

[0048] For example, if the power supply path supplying power to the IC chip 10 is located at a position overlapping the analog circuit block 11 in a planar view, the high-frequency signals processed by the analog circuit block 11 may affect the power supply path, generating spurious signals in the power supply path. Such spurious signals may interfere with the proper operation of the circuits formed on the IC chip 10. On the other hand, in this embodiment, the metal pads 12, metal terminals 40, vias 24, and wiring patterns 23 constituting the power supply path supplying power to the IC chip 10 are located at positions that do not overlap the analog circuit block 11 in a planar view. This improves isolation between the power supply path and the analog circuit block 11, reduces the impact of the high-frequency signals processed by the analog circuit block 11 on the power supply path, and thus suppresses the generation of spurious signals in the power supply path.

[0049] In the semiconductor package 1 of this embodiment, the IC chip 10 has a plurality of analog circuit blocks 11, and the metal pads 12, the metal terminals 40, the vias 24, and the wiring patterns 23 are arranged in positions that overlap in a plan view in an area between at least two of the plurality of analog circuit blocks 11 that are adjacent to each other.

[0050] In this case, not only can the isolation between the power supply path of this embodiment, i.e., the metal pad 12, the metal terminal 40, the via 24, and the wiring pattern 23, and the analog circuit block 11 be improved, but it can also be possible to utilize the area between two adjacent analog circuit blocks 11 to arrange the above components, thereby making it possible to miniaturize the semiconductor package 1.

[0051] In the semiconductor package 1 of this embodiment, the metal terminals 40 and the vias 24 are arranged on a straight line L1 that extends in a direction perpendicular to the opposing direction of the two analog circuit blocks 11 in a plan view. In this case, the metal terminals 40 and the vias 24 can be arranged between the two analog circuit blocks 11 when they are closest to each other, which makes it possible to further miniaturize the semiconductor package 1.

[0052] The semiconductor package 1 of this embodiment is formed with a plurality of metal terminals 40 and a plurality of vias 24. In this case, when power is supplied, the current value flowing through one metal terminal 40 and one via 24 can be reduced, thereby suppressing heat generation and the like that accompanies the supply of a large current.

[0053] In the semiconductor package 1 of this embodiment, the plurality of metal terminals 40 and the plurality of vias 24 are alternately arranged at equal intervals in a direction perpendicular in plan view to the opposing direction of the two analog circuit blocks 11. In this case, the influence of the two analog circuit blocks 11 on the metal terminals 40 and the vias 24 can be equally reduced and leveled, and localized generation of unwanted waves in the metal terminals 40 and the vias 24 can be suppressed.

[0054] In the semiconductor package 1 of this embodiment, the metal pads 12, metal terminals 40, vias 24, and wiring patterns 23 are arranged in the center position in a plan view between the two analog circuit blocks 11. In this case, the power supply paths of this embodiment are spaced at equal distances from the two analog circuit blocks 11, and the influences of the two analog circuit blocks 11 can be equally reduced and leveled out.

[0055] In the semiconductor package 1 of this embodiment, the metal terminals 40 and the vias 24 are arranged in different positions from each other in a plan view. In a so-called stacked structure in which the metal terminals 40 and the vias 24 are arranged in the same position from a plan view, the connection between the metal terminals 40 and the vias 24 may become unstable if the package is subjected to a temperature cycle in which the ambient temperature repeatedly changes between high and low temperatures. However, because the metal terminals 40 and the vias 24 of this embodiment are arranged in different positions from each other in a plan view, the occurrence of connection instability when such a temperature cycle is applied can be suppressed, thereby improving the reliability of the semiconductor package 1 during long-term use.

[0056] The phased array antenna module 3 (high frequency module) of this embodiment includes the above-described semiconductor package 1 and a substrate 2 (module substrate) having a phased array antenna 105 and on which the semiconductor package 1 is mounted. In this case, it is possible to obtain a high frequency module such as the phased array antenna module 3 that can improve isolation between the power supply path and the analog circuit block 11 of this embodiment.

[0057] The following describes Modifications 1 to 3 of the above embodiment. Note that the same components as those in the above embodiment are given the same reference numerals, and their description may be omitted.

[0058] 5 is a plan view of a semiconductor package 1A according to a first modification of the above embodiment. In the first modification, the metal pads 12, metal terminals 40, vias 24, and wiring pattern 23 of the semiconductor package 1A are arranged in positions relative to one analog circuit block 11 so as not to overlap the analog circuit block 11 in a plan view. For example, the metal pads 12, metal terminals 40, vias 24, and wiring pattern 23 are arranged closer to the outer periphery of the semiconductor package 1A than the analog circuit block 11 in a plan view.

[0059] Even in this case, the isolation between the power supply path of this embodiment and the analog circuit block 11 can be improved, and the impact of the high-frequency signal being processed by the analog circuit block 11 on the power supply path can be reduced, thereby suppressing the generation of unwanted waves in the power supply path.

[0060] 6 is a plan view of a semiconductor package 1B according to a second modification of the embodiment. The substrate 20 (not shown in FIG. 6; see FIG. 4 ) of the semiconductor package 1B has peripheral vias 27 connected to the wiring pattern 23 and arranged closer to the outer periphery of the semiconductor package 1B in a plan view than the multiple analog circuit blocks 11. The peripheral vias 27 are not arranged on a straight line L1 passing through the vias 24 and metal terminals 40 arranged in the region between two analog circuit blocks 11.

[0061] Unlike the metal terminals 40 and the vias 24, the peripheral vias 27 are not disposed in the region between two adjacent analog circuit blocks 11, but are disposed at positions that do not overlap with the plurality of analog circuit blocks 11 in a plan view, thereby suppressing the influence of high-frequency signals from the plurality of analog circuit blocks 11. Furthermore, the use of the peripheral vias 27 can improve the degree of freedom in designing the power supply paths in the semiconductor package 1B.

[0062] 7 is a schematic diagram of a semiconductor package 1C according to a third modification of the embodiment. Note that FIG. 7 corresponds to a view of the semiconductor package 1C as seen from the arrow IV-IV direction in FIG. 3 described above. The semiconductor package 1C includes a substrate 20A instead of the substrate 20 of the above embodiment. In addition to the first wiring layer 21 and the second wiring layer 22, the substrate 20A also includes a third wiring layer 28 laminated on the underside of the second wiring layer 22.

[0063] A wiring pattern 29 is disposed on the upper surface of the third wiring layer 28. The lower ends of two vias 26 in the second wiring layer 22 are connected to the upper surface of the wiring pattern 29. In addition, two vias 30 are provided in the third wiring layer 28, penetrating the third wiring layer 28 in the vertical direction. The upper ends of the two vias 30 are connected to the wiring pattern 29, and the lower ends of the two vias 30 are connected to the metal layer 54. Thus, in the third modification example, power can be supplied to the circuit of the IC chip 10 via the vias 30 and the wiring pattern 29. The number of vias 30 may be one or three or more.

[0064] A GND solid pattern 31 is disposed on the third wiring layer 28 at a position different from the wiring pattern 29. That is, the GND solid pattern 31 is formed on at least one of the wiring layers 21, 22, and 28. The GND solid pattern 31 is electrically grounded. In the third modification, the GND solid pattern 31 overlaps with the two metal pads 12, the metal terminal 40, the two vias 24, and the wiring pattern 23 in a plan view.

[0065] A plurality of RF bumps 51 for inputting and outputting high-frequency signals are provided on the underside of the substrate 20A, i.e., the underside of the third wiring layer 28. These RF bumps 51 are located so as to overlap the GND plane pattern 31 in a plan view. That is, the GND plane pattern 31 is disposed between the two metal pads 12, the two metal terminals 40, the two vias 24, the wiring pattern 23, and the plurality of RF bumps 51. This prevents high-frequency signals passing through the RF bumps 51 from affecting the metal terminals 40 and the vias 24 and generating unwanted waves. The placement of the GND plane pattern 31 improves the design freedom for the placement of the RF bumps 51. Furthermore, by appropriately setting the placement area of ​​the GND plane pattern 31, when the semiconductor package 1C is mounted on the substrate 2 (see FIG. 2), it is possible to prevent high-frequency signals passing through the substrate 2 from affecting the metal terminals 40 and the vias 24 and generating unwanted waves.

[0066] In the third modification, the GND solid pattern 31 is arranged so as to overlap in a planar view with all of the two metal pads 12, the two metal terminals 40, the two vias 24, and the wiring pattern 23. However, this is not limited to this, and the area in which the GND solid pattern 31 is formed may be adjusted depending on the arrangement of components (e.g., RF bumps 51) that are provided below the substrate 20A and through which high-frequency signals pass. That is, the GND solid pattern 31 may be arranged so as to overlap in a planar view with at least some of the components among at least a portion of the metal pads 12, at least a portion of the metal terminals 40, at least a portion of the vias 24, and at least a portion of the wiring pattern 23.

[0067] Although preferred embodiments of the present disclosure have been described and explained above, these are merely examples of the present disclosure and are not intended to limit the present disclosure. Additions, omissions, substitutions, and other modifications may be made within the scope of the present disclosure. The present disclosure should not be considered limited by the above description, but is limited only by the claims. Furthermore, components in the above embodiments may be replaced with known components as appropriate without departing from the spirit of the present disclosure.

[0068] 1, 1A, 1B, 1C...semiconductor package, 2...substrate (module substrate), 3...phased array antenna module (high frequency module), 10...IC chip, 11...analog circuit block, 12...metal pad, 20, 20A...substrate, 23...wiring pattern, 24...via, 27...periphery-arranged via, 31...GND solid pattern, 40...metal terminal, 51...RF bump (external connection terminal), L1...straight line

Claims

1. A semiconductor package comprising an IC chip having an analog circuit block and a substrate on which the IC chip is mounted, wherein the IC chip has metal pads electrically connected to a power supply, and metal terminals are connected to the metal pads, and the substrate has vias and a wiring pattern connecting the vias and the metal terminals, and the metal pads, the metal terminals, the vias, and the wiring pattern are positioned so as not to overlap the analog circuit block in a planar view.

2. The semiconductor package according to claim 1, wherein the IC chip has a plurality of the analog circuit blocks, and the metal pads, the metal terminals, the vias, and the wiring pattern are arranged in positions that overlap in a planar view with an area between at least two of the plurality of analog circuit blocks that are adjacent to each other.

3. The semiconductor package according to claim 2, wherein the metal terminals and the vias are arranged on a straight line extending in a direction perpendicular to the opposing direction of the two analog circuit blocks in a plan view.

4. The semiconductor package according to claim 2 or 3, wherein a plurality of said metal terminals and a plurality of said vias are formed.

5. The semiconductor package according to claim 4, wherein the plurality of metal terminals and the plurality of vias are alternately arranged at equal intervals in a direction perpendicular to the opposing direction of the two analog circuit blocks in a plan view.

6. The semiconductor package according to any one of claims 2 to 5, wherein the metal pad, the metal terminal, the via, and the wiring pattern are arranged at a central position in a plan view between the two analog circuit blocks.

7. A semiconductor package according to any one of claims 2 to 6, wherein the substrate has peripherally located vias connected to the wiring pattern and located closer to the outer edge of the package in a plan view than the multiple analog circuit blocks, and the peripherally located vias are not located on a straight line passing through the metal terminals and the vias located in the area between the two analog circuit blocks.

8. A semiconductor package according to any one of claims 1 to 7, wherein the substrate has a plurality of wiring layers, and a GND solid pattern is formed on at least one of the plurality of wiring layers, and the GND solid pattern overlaps at least a portion of the metal pads, at least a portion of the metal terminals, at least a portion of the vias, and at least a portion of the wiring patterns in a planar view.

9. The semiconductor package according to claim 8, further comprising an external connection terminal for inputting and outputting high-frequency signals, which is arranged at a position overlapping the GND solid pattern in a plan view.

10. The semiconductor package according to any one of claims 1 to 9, wherein the metal terminal and the via are arranged at different positions from each other in a plan view.

11. A high frequency module comprising: a semiconductor package according to any one of claims 1 to 10; and a second substrate having an antenna and on which the semiconductor package is mounted.

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