Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface at a peripheral surface layer part of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region at the peripheral surface layer part of the main surface; and a shield region, which divides at least a portion of the first region into a region on an end-part side of the chip and a region on an inner-part side of the chip at the peripheral edge surface layer part of the main surface, and which has a resistance value higher than the resistance value of the first region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Applications Nos. 2024-073068, 2024-073069, and 2024-073070, filed with the Japan Patent Office on April 26, 2024, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US20220231160A1) discloses a semiconductor device having a superjunction structure.

[0003] US Patent Application Publication No. 2022 / 0231160

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface portion of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region in the peripheral surface portion of the main surface; and a shielding region dividing at least a portion of the first region in the peripheral surface portion of the main surface into a region on an end side of the chip and a region on an inner side of the chip.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface portion of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region in the peripheral surface portion of the main surface; and a shielding region of a second conductivity type dividing at least a portion of the first region in the peripheral surface portion of the main surface into a region on an end side of the chip and a region on an inner side of the chip.

[0007] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface portion of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region in the peripheral surface portion of the main surface; and a shielding region in the peripheral surface portion of the main surface dividing at least a portion of the first region into a region on an end side of the chip and a region on an inner side of the chip, the shielding region having a resistance value higher than a resistance value of the first region.

[0008] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface portion of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region in the peripheral surface portion of the main surface; and an insulating shielding region dividing at least a portion of the first region in the peripheral surface portion of the main surface into a region on an end side of the chip and a region on an inner side of the chip.

[0009] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface portion of the main surface; a second region of a second conductivity type extending in the first direction adjacent to the first region in the peripheral surface portion of the main surface; and a shielding region extending in a second direction along the main surface in the peripheral surface portion of the main surface and dividing at least a portion of the first region.

[0010] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing a layout example of a surface layer portion of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region. FIG. 5 is an enlarged plan view showing another main portion of the active region. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is a cross-sectional perspective view showing a main portion of an active region. FIG. 10 is a cross-sectional view taken along line XX in FIG. 1. FIG. 11 is an enlarged plan view showing a peripheral surface layer portion according to a first layout example. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 11. FIG. 14 is an enlarged plan view showing a peripheral surface layer portion according to a second layout example. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 . FIG. 16 is an enlarged plan view showing a peripheral surface layer portion according to a third layout example. FIG. 17 is a plan view showing an example layout of the surface layer portion of the first main surface of a semiconductor device according to the second embodiment. FIG. 18 is an enlarged plan view showing the peripheral surface layer portion according to the first layout example. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18 . FIG. 21 is an enlarged plan view showing the peripheral surface layer portion according to the second layout example. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21 . FIG. 23 is an enlarged plan view showing the peripheral surface layer portion according to the third layout example. FIG. 24 is an enlarged plan view showing the peripheral surface layer portion according to a fourth layout example. FIG. 25 is a plan view showing an example layout of the surface layer portion of the first main surface of a semiconductor device according to the third embodiment. FIG. 26 is an enlarged plan view showing the peripheral surface layer portion according to the first layout example. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 26. Fig. 29 is an enlarged plan view showing the peripheral surface layer portion according to the second layout example. Fig. 30 is a cross-sectional view taken along line XXX-XXX shown in Fig. 29. Fig. 31 is an enlarged plan view showing the peripheral surface layer portion according to the third layout example. Fig. 32 is an enlarged plan view showing the peripheral surface layer portion according to the fourth layout example.FIG. 33 is a sectional perspective view showing a main portion of a semiconductor device according to a fourth embodiment. FIG. 34 is a sectional perspective view showing a main portion of a semiconductor device according to a fifth embodiment. FIG. 35 is a plan view showing a main portion of a semiconductor device according to a sixth embodiment. FIG. 36 is a sectional view taken along line XXXVI-XXXVI shown in FIG. 35. FIG. 37 is a sectional perspective view showing a main portion of an active region. FIG. 38 is a sectional perspective view showing a main portion of a semiconductor device according to a seventh embodiment. FIG. 39 is a plan view showing a semiconductor device according to an eighth embodiment. FIG. 40 is a sectional view taken along line XL-XL shown in FIG. 39. FIG. 41 is a plan view showing an example layout of a surface layer portion of a first main surface. FIG. 42 is an enlarged plan view showing a peripheral surface layer portion according to a first modified example. FIG. 43 is a sectional view taken along line XLIII-XLIII shown in FIG. 42. FIG. 44 is an enlarged plan view showing a peripheral surface layer portion according to a second modified example. FIG. 45 is a sectional view taken along line XLV-XLV shown in FIG. 44. Fig. 46 is an enlarged plan view showing a peripheral surface layer portion according to a third modified example. Fig. 47 is a cross-sectional view taken along line XLVII-XLVII shown in Fig. 46. Fig. 48 is an enlarged plan view showing a peripheral surface layer portion according to a fourth modified example. Fig. 49 is a cross-sectional view taken along line XLIX-XLIX shown in Fig. 48. Fig. 50 is an enlarged plan view showing a peripheral surface layer portion according to a fifth modified example. Fig. 51 is a cross-sectional view taken along line LI-LI shown in Fig. 50. Fig. 52 is a cross-sectional view showing an upper insulating film applied to each of the above-described embodiments (including each modified example).

[0012] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0013] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0014] In this specification, terms such as "first," "second," and "third" are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.

[0015] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0016] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0017] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a surface layer portion of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of an active region 8. Fig. 5 is an enlarged plan view showing another main portion of the active region 8.

[0018] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is a cross-sectional perspective view showing a main part of the active region 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 1. FIG. 11 is an enlarged plan view showing a peripheral surface layer part according to the first layout example. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 11.

[0019] 1 to 13, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure as an example of a device structure (functional device). The transistor structure has a trench gate vertical structure.

[0020] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0021] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0022] Hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes. Of course, the chip 2 may also include a cubic crystal or a polycrystal. For example, the chip 2 may include a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystal.

[0023] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth end portions 5A to 5D connected to the first main surface 3 and the second main surface 4. The first to fourth end portions 5A to 5D may also be referred to as "first to fourth side surfaces (5A to 5D)." The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0024] The first main surface 3 and the second main surface 4 are formed by the c-plane of the SiC single crystal. The first main surface 3 may be formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 may be formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0025] The first end 5A extends in the first direction X. The second end 5B is connected to the first end 5A and extends in a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third end 5C is connected to the second end 5B and extends in the first direction X. The fourth end 5D is connected to the first end 5A and the third end 5C and extends in the second direction Y.

[0026] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. The first direction X may be the m-axis direction, and the second direction Y may be the a-axis direction. The first direction X may be a direction intersecting both the a-axis direction and the m-axis direction, and the second direction Y may be a direction intersecting both the a-axis direction and the m-axis direction.

[0027] Hereinafter, the direction extending along the first main surface 3 may be referred to as the “horizontal direction.” The horizontal direction is a direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0028] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-axis angle from a vertical line along the vertical direction Z toward the off-axis direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-axis angle with respect to the horizontal plane.

[0029] The off-direction is preferably the a-axis direction of the SiC single crystal (first direction X in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0030] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0031] The chip 2 includes an n-type first layer 6 formed in a region on the second main surface 4 side. The first layer 6 may also be referred to as a "first semiconductor layer (region)," a "drain layer (region)," or the like. The first layer 6 extends in a layered form along the second main surface 4, forming a lower layer portion of the chip 2. The first layer 6 is formed over the entire second main surface 4, and forms parts of the second main surface 4 of the chip 2 and first to fourth end portions 5A to 5D of the chip 2.

[0032] The first layer 6 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the first layer 6 is a SiC substrate including a hexagonal SiC single crystal. The first layer 6 includes a 4H—SiC single crystal and has the off-orientation and off-angle described above. The first layer 6 may also include other polytypes. The first layer 6 may also include a 3C—SiC polycrystal.

[0033] The first layer 6 may have a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the first layer 6 may be adjusted by a single pentavalent element. The first layer 6 preferably contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the first layer 6 is adjusted by nitrogen as a pentavalent element.

[0034] The first layer 6 may have a thickness greater than 0 μm and less than 500 μm. The thickness of the first layer 6 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 1 μm, 1 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, 400 μm to 450 μm, and 450 μm to 500 μm.

[0035] The chip 2 includes an n-type second layer 7 formed in a region of the chip 2 on the first main surface 3 side relative to the first layer 6. The second layer 7 may also be referred to as a "second semiconductor layer (region)," a "drain layer (region)," a "drift layer (region)," or the like. The second layer 7 is stacked on the first layer 6 and forms an upper layer portion of the chip 2. The second layer 7 extends in a layered manner along the first main surface 3 (first layer 6) and forms part of the first main surface 3 of the chip 2 and first to fourth end portions 5A to 5D of the chip 2.

[0036] The second layer 7 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the second layer 7 is a SiC layer including a hexagonal SiC single crystal. In this embodiment, the second layer 7 is an epitaxial layer including a 4H—SiC single crystal (hexagonal), and has the off-orientation and off-angle described above. The second layer 7 may include another polytype. The second layer 7 may have a polytype different from that of the first layer 6.

[0037] The second layer 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first layer 6. The n-type impurity concentration of the second layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0038] The n-type impurity concentration of the second layer 7 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the second layer 7 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The second layer 7 preferably contains a pentavalent element other than phosphorus. The second layer 7 preferably contains at least nitrogen as a pentavalent element. When the second layer 7 contains two or more pentavalent elements, the second layer 7 preferably contains at least two of nitrogen, arsenic, and antimony.

[0039] The second layer 7 has a thickness less than that of the first layer 6. The thickness of the second layer 7 may be greater than 0 μm and less than 25 μm. The thickness of the second layer 7 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0040] The semiconductor device 1A includes an active region 8 set on the first main surface 3. The active region 8 includes a device structure (transistor structure) and is a region where an output current (drain current) is generated. The active region 8 is set on an inner portion of the first main surface 3 and spaced apart from the periphery (first to fourth ends 5A to 5D) of the first main surface 3. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0041] The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be equal to or greater than 0.5 and less than 1. The area ratio may have a value belonging to at least one of the ranges of 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, 0.9 to 0.95, and 0.95 to less than 1.

[0042] The semiconductor device 1A includes an outer region 9 set outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include a device structure (transistor structure). The outer region 9 is set in the peripheral portion of the first main surface 3. The outer region 9 is provided in a region between the peripheral edge of the first main surface 3 and the active region 8. The outer region 9 extends in a strip shape along the active region 8 in a plan view, and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0043] The semiconductor device 1A includes a p-type body region 10 formed in the active region 8 in a surface layer portion of the first main surface 3. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0044] The body region 10 is formed in the active region 8 at a distance from the periphery (first to fourth ends 5A to 5D) of the first main surface 3, and is not formed in the outer region 9. In this embodiment, the body region 10 is formed in the surface portion of the second layer 7 throughout the entire active region 8, and replaces the conductivity type of the second layer 7 from n-type to p-type. The body region 10 extends in a layered form along the first main surface 3 in the surface portion of the second layer 7.

[0045] The body region 10 is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 across a part of the second layer 7. The body region 10 may be formed at a distance from a depth position of an intermediate portion of the second layer 7 toward the first main surface 3. The body region 10 may have a portion located closer to the first layer 6 than the depth position of the intermediate portion of the second layer 7.

[0046] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in an inner portion of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 15 as a control potential.

[0047] The multiple gate structures 15 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 9. The multiple gate structures 15 are arranged in stripes extending in the first direction X (= the a-axis direction) in a plan view. That is, the multiple gate structures 15 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. The extending direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.

[0048] The gate structure 15 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the gate structure 15 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the gate structure 15 is preferably less than or equal to 5 μm.

[0049] The spacing between the gate structures 15 may be less than the width of the gate structures 15. The spacing between the gate structures 15 may be greater than the width of the gate. The spacing between the gate structures 15 may be greater than 0 μm and equal to or less than 10 μm.

[0050] The spacing between the gate structures 15 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0051] The plurality of gate structures 15 are formed at intervals from the bottom of the second layer 7 toward the first main surface 3, and face the first layer 6 across a part of the second layer 7. The plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 15 may be formed in a shape tapering toward the bottom of the second layer 7.

[0052] The side walls of the plurality of gate structures 15 define an open end curved in an arc shape (circular arc shape) together with the first main surface 3. The side walls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 15 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15.

[0053] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 may extend substantially flat in the horizontal direction. The bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0054] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0055] The gate structure 15 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 15 is less than the thickness of the second layer 7. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm.

[0056] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0057] Each of the plurality of gate structures 15 includes a trench 16, an insulating film 17, a buried electrode 18, and a buried insulator 19. The trench 16 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the gate structure 15.

[0058] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 17 may include a silicon oxide film containing an oxide of the chip 2 (second layer 7). The insulating film 17 may include a silicon oxide film containing an oxide other than the oxide of the chip 2.

[0059] The insulating film 17 covers the wall surface of the trench 16. In this embodiment, the insulating film 17 has an upper end located on the bottom wall side of the trench 16 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 16.

[0060] The upper end of the insulating film 17 is preferably located closer to the opening of the trench 16 than the depth position of the intermediate portion of the trench 16. The thickness of the portion of the insulating film 17 covering the sidewall of the trench 16 may be greater than the thickness of the portion of the insulating film 17 covering the bottom wall of the trench 16.

[0061] The thickness of the insulating film 17 may be 10 nm or more and 250 nm or less. The thickness of the insulating film 17 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0062] The buried electrode 18 includes either or both of a metal and a non-metal conductor. The buried electrode 18 may include conductive polysilicon. In this case, the buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 is preferably made of n-type conductive polysilicon.

[0063] The buried electrode 18 is buried in the trench 16 via the insulating film 17 and faces the second layer 7 via the insulating film 17. The buried electrode 18 has an electrode surface exposed from the trench 16. The electrode surface is formed at a distance from the height position of the first main surface 3 to the bottom wall side of the trench 16. The electrode surface is located on the first main surface 3 side with respect to the depth position of the intermediate portion of the trench 16. The electrode surface may be located on the bottom wall side of the trench 16 with respect to the depth position of the intermediate portion of the trench 16. The electrode surface may have a recess recessed toward the bottom wall side.

[0064] The buried insulator 19 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 19 may include an insulating material of the same type as or different from the insulating material of the insulating film 17. In this form, the buried insulator 19 includes a silicon oxide film having properties different from the properties of the insulating film 17.

[0065] The buried insulator 19 may have a single layer structure or a multilayer structure including at least one of an NSG (nondoped silicate glass) film, a PSG (phosphorus silicon glass) film, and a BPSG (boron phosphorus silicon glass) film. The NSG film is a silicon oxide film with no impurities added, the PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron.

[0066] The buried insulator 19 preferably has a single-layer structure or a multilayer structure including at least an NSG film. The buried insulator 19 may have a multilayer structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The buried insulator 19 may have a multilayer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The buried insulator 19 may have a single-layer structure or a multilayer structure including a silicon oxide film containing an oxide of the buried electrode 18.

[0067] The buried insulator 19 covers the buried electrode 18 within the trench 16. In this embodiment, the buried insulator 19 is buried in the trench 16 via the insulating film 17, and is in contact with the insulating film 17 and the buried electrode 18 within the trench 16. In other words, the buried insulator 19 has a portion that faces the chip 2 in the horizontal direction with the insulating film 17 interposed therebetween.

[0068] The buried insulator 19 has an insulating surface exposed from the trench 16. The insulating surface is formed at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 16, and exposes a part of the chip 2 from the opening end of the trench 16. The insulating surface is located on the opening side of the trench 16 relative to the depth position of the intermediate portion of the trench 16. The insulating surface may also be located on the bottom wall side of the trench 16 relative to the depth position of the intermediate portion of the trench 16.

[0069] The insulating surface exposes the upper end of the insulating film 17. In this embodiment, the insulating surface is flat and continuous with the upper end of the insulating film 17. That is, the insulating surface is formed flush with the upper end of the insulating film 17. The insulating surface may be located closer to the first main surface 3 or closer to the bottom wall of the trench 16 than the upper end of the insulating film 17. The insulating surface may be formed flush with the first main surface 3 together with the upper end of the insulating film 17.

[0070] The buried insulator 19 may cover the upper end of the insulating film 17 and may be in direct contact with the chip 2 on the sidewall of the trench 16. In this form, the insulating surface has a recessed portion that sinks from the sidewall of the trench 16 toward the inside of the trench 16. The insulating surface may also have a protruding portion that protrudes from the sidewall of the trench 16 toward the inside of the trench 16.

[0071] In this embodiment, the buried insulator 19 has a thickness greater than that of the insulating film 17. The thickness of the buried insulator 19 is preferably less than that of the buried electrode 18. The ratio of the thickness of the buried insulator 19 to the depth of the trench 16 may be greater than 0 and less than 0.5. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0072] The semiconductor device 1A includes a plurality of n-type source regions 20 formed in the surface layer portion of the first main surface 3 in the active region 8. The source regions 20 have a higher n-type impurity concentration than the n-type impurity concentration of the second layer 7. The n-type impurity concentration of the source regions 20 is higher than the p-type impurity concentration of the body region 10.

[0073] The source regions 20 are formed in regions between the gate structures 15 in the surface layer portion of the body region 10. The source regions 20 are formed at intervals in the first direction X following the extension direction of the gate structures 15, and are adjacent to two gate structures 15 corresponding to each other in the second direction Y.

[0074] In this embodiment, the source regions 20 extend in strip shapes in the first direction X in accordance with the extension direction of the corresponding gate structures 15. In the first direction X, the length of the source regions 20 is greater than the spacing between the gate structures 15.

[0075] With respect to the plurality of source regions 20 on one side and the other side formed on both sides of the plurality of gate structures 15, the plurality of source regions 20 on the other side face the plurality of source regions 20 on the one side in the second direction Y. Of course, the plurality of source regions 20 on the other side may face a region between the plurality of source regions 20 on the one side in the second direction Y.

[0076] The plurality of source regions 20 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second layer 7 via a part of the body region 10. The plurality of source regions 20 may have portions located on the bottom wall side of the plurality of gate structures 15 with respect to the depth position of the intermediate portions of the plurality of gate structures 15. The plurality of source regions 20 may be formed at intervals from the depth position of the intermediate portions of the plurality of gate structures 15 toward the first main surface 3.

[0077] The plurality of source regions 20 have a portion located on the first main surface 3 side of the electrode surface of the buried electrode 18 and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the buried electrode 18. The plurality of source regions 20 have a portion located on the first main surface 3 side of the insulating surface of the buried insulator 19 and a portion located on the bottom wall side of the gate structure 15 with respect to the insulating surface of the buried insulator 19.

[0078] The plurality of source regions 20 have portions facing corresponding buried electrodes 18 in the horizontal direction and portions facing corresponding buried insulators 19. The plurality of source regions 20 face corresponding buried electrodes 18 and corresponding buried insulators 19 via corresponding insulating films 17. In this embodiment, the plurality of source regions 20 have portions exposed from the opening ends of the trenches 16.

[0079] The plurality of source regions 20 have a depth greater than the thickness between the bottom of the body region 10 and the bottom of the plurality of source regions 20. The depth of the plurality of source regions 20 may be less than the thickness between the bottom of the body region 10 and the bottom of the plurality of source regions 20.

[0080] The semiconductor device 1A includes a plurality of p-type contact regions 21 formed in the active region 8 in a surface layer portion of the first main surface 3. The contact regions 21 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0081] The plurality of contact regions 21 are formed in regions between the plurality of gate structures 15 in the surface layer portion of the body region 10, respectively, to increase the p-type impurity concentration of the body region 10. The plurality of contact regions 21 extend in layers along the first main surface 3. The plurality of contact regions 21 are formed at intervals in the first direction X following the extension direction of the plurality of gate structures 15, and are adjacent to two gate structures 15 corresponding to each other in the second direction Y.

[0082] The plurality of contact regions 21 are respectively interposed in regions between the plurality of source regions 20 in the first direction X. The plurality of contact regions 21 may be connected to the plurality of source regions 20 in the first direction X. The plurality of contact regions 21 may be formed at intervals from the plurality of source regions 20 in the first direction X and may face the plurality of source regions 20 via parts of the body region 10.

[0083] With respect to the plurality of contact regions 21 on one side and the other side formed on both sides of the plurality of gate structures 15, the plurality of contact regions 21 on the other side face the plurality of contact regions 21 on the one side in the second direction Y. Of course, the plurality of contact regions 21 on the other side may face the region (the plurality of source regions 20) between the plurality of contact regions 21 on the one side in the second direction Y.

[0084] The plurality of contact regions 21 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second layer 7 via a part of the body region 10. The plurality of contact regions 21 may have portions located on the bottom wall side of the plurality of gate structures 15 with respect to the depth position of the intermediate portions of the plurality of gate structures 15. The plurality of contact regions 21 may be formed at intervals from the depth position of the intermediate portions of the plurality of gate structures 15 toward the first main surface 3.

[0085] The plurality of contact regions 21 have a portion located on the first main surface 3 side of the electrode surface of the buried electrode 18 and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the buried electrode 18. The plurality of contact regions 21 have a portion located on the first main surface 3 side of the insulating surface of the buried insulator 19 and a portion located on the bottom wall side of the gate structure 15 with respect to the insulating surface of the buried insulator 19.

[0086] The plurality of contact regions 21 have portions facing the corresponding buried electrodes 18 in the horizontal direction and portions facing the corresponding buried insulators 19. The plurality of contact regions 21 face the corresponding buried electrodes 18 and the corresponding buried insulators 19 via the corresponding insulating films 17. In this embodiment, the plurality of contact regions 21 have portions exposed from the opening ends of the trenches 16.

[0087] The contact region 21 may have a depth greater than the depth of the source region 20. The depth of the contact region 21 may be less than the depth of the source region 20. The depth of the contact region 21 may be greater than the thickness between the bottom of the body region 10 and the bottom of the contact region 21. The depth of the contact region 21 may be less than the thickness between the bottom of the body region 10 and the bottom of the contact region 21.

[0088] The lengths of the contact regions 21 in the first direction X are adjusted according to the channel area to be formed. The channel area is the total planar area of ​​the source regions 20. The channel area increases or decreases depending on the ratio of the total planar area of ​​the contact regions 21. It is preferable that the total planar area of ​​the contact regions 21 is less than the channel area.

[0089] The contact regions 21 may extend in a strip shape in the first direction X in a plan view, following the extension direction of the gate structures 15. The lengths of the contact regions 21 in the first direction X may be equal to or different from one another. The length of the contact regions 21 may be greater or smaller than the width of the gate structure 15. The length of the contact regions 21 may be greater or smaller than the spacing between the gate structures 15.

[0090] The semiconductor device 1A includes a plurality of p-type well regions 22 formed in the active region 8 in a surface layer portion of the first main surface 3. The well regions 22 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the well regions 22 may be approximately equal to the p-type impurity concentration of the contact region 21. The p-type impurity concentration of the well regions 22 may be higher or lower than the p-type impurity concentration of the contact region 21.

[0091] The multiple well regions 22 are formed in regions along the multiple gate structures 15, respectively, and replace the conductivity type of the second layer 7 from n-type to p-type. The multiple well regions 22 are formed at intervals in the first direction X in a one-to-many correspondence with the corresponding gate structures 15. The multiple well regions 22 are formed in regions adjacent to the multiple contact regions 21 in the second direction Y, respectively, and are interposed in regions between the multiple source regions 20 in the first direction X.

[0092] Each of the multiple well regions 22 has a bottom wall portion that runs along the bottom wall of the corresponding gate structure 15 and a side wall portion that runs along the side wall of the corresponding gate structure 15. The bottom wall portion is connected to the bottom wall of the corresponding gate structure 15 and faces the buried electrode 18 via the insulating film 17. The bottom wall portion has a width greater than the width of the corresponding gate structure 15 and extends out on both sides of the corresponding gate structure 15. The bottom wall portion is formed at a distance from the bottom of the second layer 7 toward the first main surface 3.

[0093] The sidewall portion extends along the sidewall of the corresponding gate structure 15 and faces the buried electrode 18 via the insulating film 17. The sidewall portion is connected to the bottom wall portion on the bottom wall side of the gate structure 15. The sidewall portion has a width less than the thickness of the bottom wall portion. The width of the sidewall portion is the horizontal width based on the sidewall of the gate structure 15.

[0094] The semiconductor device 1A includes a p-type outer well region 23 formed in a surface layer portion of the first main surface 3 in the outer region 9 (periphery of the first main surface 3). A source potential is applied to the outer well region 23. The outer well region 23 is formed in the second layer 7 and converts the conductivity type of the second layer 7 from n-type to p-type. The p-type impurity concentration of the outer well region 23 may be higher or lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the outer well region 23 is lower than the p-type impurity concentration of the contact region 21.

[0095] The outer well region 23 is formed in a surface portion of the second layer 7 and extends in a layered manner along the first main surface 3. The outer well region 23 is formed at an interval from the periphery of the first main surface 3 to the inward side of the first main surface 3 (toward the active region 8). The outer well region 23 extends in a strip shape along the active region 8 in a plan view and surrounds the active region 8.

[0096] In this embodiment, the outer well region 23 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the multiple gate structures 15. The outer well region 23 may have an edge portion that connects the band-like extending portion in the first direction X and the band-like extending portion in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer well region 23 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0097] The inner edge of the outer well region 23 defines the boundary between the active region 8 and the outer region 9. The outer edge of the outer well region 23 is formed at a distance from the periphery of the first main surface 3 and extends approximately parallel to the inner edge of the outer well region 23. The inner edge of the outer well region 23 may be connected to ends of the multiple gate structures 15. The inner edge of the outer well region 23 may be connected to the body region 10.

[0098] The outer well region 23 is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 via a part of the second layer 7. The outer well region 23 may be formed at a distance from the depth position of the intermediate part of the second layer 7 toward the first main surface 3, or may have a portion located closer to the bottom of the second layer 7 than the depth position of the intermediate part of the second layer 7.

[0099] In this embodiment, the outer well region 23 has a depth less than the depth of the plurality of gate structures 15. The depth of the outer well region 23 may be greater than the depth of the plurality of gate structures 15. The depth of the outer well region 23 may be approximately equal to the depth of the body region 10. The depth of the outer well region 23 may be greater or less than the depth of the body region 10.

[0100] The semiconductor device 1A includes a plurality of p-type first regions 25 formed in a surface layer portion of the first main surface 3. The first regions 25 may also be referred to as "first impurity regions," "first pillar regions," "first column regions," etc. The first regions 25 are formed in the second layer 7 and convert the conductivity type of the second layer 7 from n-type to p-type.

[0101] The p-type impurity concentration of the first region 25 may be higher or lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the first region 25 is lower than the p-type impurity concentration of the contact region 21. The p-type impurity concentration of the first region 25 may be higher or lower than the p-type impurity concentration of the outer well region 23.

[0102] The plurality of first regions 25 are formed in the surface layer portion of the first main surface 3 in the inner portion (active region 8) of the first main surface 3 and in the peripheral portion (outer region 9) of the first main surface 3. Hereinafter, the surface layer portion in the inner portion of the first main surface 3 will be referred to as the "inner surface layer portion," and the surface layer portion in the peripheral portion of the first main surface 3 will be referred to as the "peripheral surface layer portion."

[0103] The first regions 25 are formed in stripes extending in the first direction X in both the inner surface layer portion and the peripheral surface layer portion. Specifically, the first regions 25 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. That is, the extension direction of the first regions 25 coincides with the extension direction of the gate structures 15. Furthermore, the extension direction of the first regions 25 coincides with the off-direction of the SiC single crystal.

[0104] The first region 25 may have a width that is approximately equal to the width of the gate structure 15. The width of the first region 25 may be greater than or less than the width of the gate structure 15. The width of the first region 25 may be greater than 0 μm and less than or equal to 10 μm.

[0105] The width of the first region 25 may be in at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the gate structure 15 is preferably 5 μm or less.

[0106] The spacing between the multiple first regions 25 may have a width that is approximately equal to the spacing between the gate structures 15. The spacing between the first regions 25 may be larger or smaller than the spacing between the gate structures 15. The spacing between the first regions 25 may be greater than 0 μm and equal to or smaller than 10 μm.

[0107] The spacing of the first region 25 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more and less than 1 μm, 1 μm or more and less than 2 μm, 2 μm or more and less than 3 μm, 3 μm or more and less than 4 μm, 4 μm or more and less than 5 μm, 5 μm or more and less than 6 μm, 6 μm or more and less than 7 μm, 7 μm or more and less than 8 μm, 8 μm or more and less than 9 μm, and 9 μm or more and less than 10 μm.

[0108] The first region 25 has a depth greater than the depth of the gate structure 15. The depth of the first region 25 is defined by the distance between the first major surface 3 and the bottom of the first region 25. The depth of the first region 25 may be greater than 0 μm and less than or equal to 10 μm.

[0109] The depth of the first region 25 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more and less than 1 μm, 1 μm or more and less than 2 μm, 2 μm or more and less than 3 μm, 3 μm or more and less than 4 μm, 4 μm or more and less than 5 μm, 5 μm or more and less than 6 μm, 6 μm or more and less than 7 μm, 7 μm or more and less than 8 μm, 8 μm or more and less than 9 μm, and 9 μm or more and less than 10 μm.

[0110] 6 to 8, in this embodiment, the plurality of first regions 25 are formed in regions of the inner surface layer portion that overlap with the plurality of gate structures 15. Specifically, the plurality of first regions 25 are formed at intervals that are approximately equal to the intervals between the plurality of gate structures 15, and are formed in a one-to-one correspondence with the plurality of gate structures 15.

[0111] The multiple first regions 25 are each formed in the shape of a pillar extending vertically from the bottom walls of the multiple gate structures 15 toward the bottom of the second layer 7. The multiple first regions 25 are formed at intervals from the bottom of the second layer 7 toward the bottom wall of the corresponding gate structure 15, and face the first layer 6 across a part of the second layer 7. Of course, the multiple first regions 25 may cross the boundary between the first layer 6 and the second layer 7 and have their bottoms located in the first layer 6.

[0112] The plurality of first regions 25 are respectively connected to the bottom walls of the corresponding gate structures 15 and face the corresponding buried electrodes 18 via the corresponding insulating films 17. The plurality of first regions 25 are connected to the plurality of well regions 22 in portions along the bottom walls of the corresponding gate structures 15. As a result, the plurality of first regions 25 are electrically connected to the body region 10 and the plurality of contact regions 21 via the plurality of well regions 22.

[0113] The multiple first regions 25 extend from the inner surface portion across the outer well region 23 to the peripheral surface portion, and have a portion electrically connected to the outer well region 23. In this embodiment, the multiple first regions 25 have a depth greater than the depth of the outer well region 23. The depth of the multiple first regions 25 may be approximately equal to the depth of the outer well region 23. The depth of the multiple first regions 25 may be smaller than the depth of the outer well region 23.

[0114] 11 , the multiple first regions 25 are arranged in stripes extending in the first direction X in the peripheral surface layer portion. In this embodiment, the multiple first regions 25 are each formed in a strip shape extending from the second end 5B to the fourth end 5D, and are exposed from both the second end 5B and the fourth end 5D. In the regions of the outer region 9 along the first end 5A and the third end 5C, the multiple first regions 25 have facing portions facing the active region 8 in the second direction Y and non-facing portions not facing the active region 8 in the second direction Y.

[0115] The first regions 25 extend in a pillar shape in the peripheral surface portion from the first main surface 3 toward the bottom of the second layer 7. The first regions 25 have a portion located on the first main surface 3 side relative to the depth positions of the bottom walls of the gate structures 15 in the peripheral surface portion, and a portion located on the bottom side of the second layer 7 relative to the depth positions of the bottom walls of the gate structures 15.

[0116] The portions of the first regions 25 exposed from the second end 5B are spaced apart in the second direction Y and extend in a pillar shape in the thickness direction. The portions of the first regions 25 exposed from the fourth end 5D are spaced apart in the second direction Y and extend in a pillar shape in the thickness direction.

[0117] The first regions 25 have upper and lower ends in the peripheral surface portion. The upper ends of the first regions 25 are exposed from the first main surface 3. Of course, the upper ends of the first regions 25 may be formed at intervals from the first main surface 3 toward the bottom of the second layer 7. The lower ends of the first regions 25 are formed at intervals from the bottom of the second layer 7 toward the first main surface 3, and face the first layer 6 with a portion of the second layer 7 in between.

[0118] Each of the multiple first regions 25 may be formed by a single p-type impurity region extending along an axial channel of the SiC single crystal (second layer 7). The axial channel is a region (channel) in the SiC single crystal where the interatomic distance is relatively large and is surrounded by atomic rows that form a crystal axis extending in the stacking direction. In other words, the axial channel is a region in which the horizontal interatomic distance (atomic density) is sparse and extends in the thickness direction.

[0119] The axial channel is preferably a region surrounded by a row of atoms along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1," "a2," "a3," and "c" are all expressed as 0 to 2 (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0120] The axial channel may be composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the plurality of first regions 25 may extend along the c-axis as the axial channel and have the off direction and off angle described above. In other words, the plurality of first regions 25 may be inclined from the vertical axis toward the off direction by the off angle. The plurality of first regions 25 preferably have a thickness of at least 0.5 μm or more and a concentration decrease rate of 50% or less within a thickness range of 0.5 μm.

[0121] The first regions 25 may each be formed by a plurality of p-type impurity regions arranged in a pillar shape so as to be connected to each other in the thickness direction. The number of impurity regions may be 2 or more and 10 or less. The number of impurity regions may be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0122] The semiconductor device 1A includes a plurality of n-type second regions 26 formed in a surface layer portion of the first main surface 3. The second regions 26 may also be referred to as "second impurity regions," "second pillar regions," "second column regions," etc. The second regions 26 are formed in the second layer 7. In this embodiment, the second regions 26 are formed using a portion of the second layer 7, and have an n-type impurity concentration that is approximately equal to the n-type impurity concentration of the second layer 7. The n-type impurity concentration of the second regions 26 may be higher than the n-type impurity concentration of the second layer 7.

[0123] The second regions 26 are formed on both sides of the first regions 25 in the second direction Y. That is, the second regions 26 are formed in stripes extending in the first direction X. Specifically, the second regions 26 each extend in a strip shape in the first direction X and are arranged alternately with the first regions 25 in the second direction Y.

[0124] The extension direction of the second regions 26 coincides with the extension direction of the first regions 25 (the gate structures 15). The extension direction of the second regions 26 also coincides with the off-direction of the SiC single crystal. The second regions 26 are formed in the inner surface layer portion of the first main surface 3 and the peripheral surface layer portion of the first main surface 3, following the layout of the first regions 25.

[0125] The second region 26 has a width corresponding to the spacing between the multiple first regions 25. The width of the second region 26 may be approximately equal to the width of the first region 25. The width of the second region 26 may be larger or smaller than the width of the first region 25. The second region 26 may have a width approximately equal to the width of the gate structure 15. The width of the second region 26 may be larger or smaller than the width of the gate structure 15.

[0126] The width of the second region 26 may be greater than 0 μm and less than or equal to 10 μm. The width of the second region 26 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the second region 26 is preferably less than or equal to 5 μm.

[0127] The spacing between the multiple second regions 26 corresponds to the width of the first regions 25. The spacing between the second regions 26 may be approximately equal to the spacing between the first regions 25. The spacing between the second regions 26 may be larger or smaller than the spacing between the first regions 25. The spacing between the second regions 26 may be approximately equal to the spacing between the gate structures 15. The spacing between the second regions 26 may be larger or smaller than the spacing between the gate structures 15.

[0128] The interval between the second regions 26 may be greater than 0 μm and less than or equal to 10 μm. The interval between the second regions 26 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0129] In this embodiment, the second region 26 has a depth corresponding to the depth of the second layer 7. The depth of the second region 26 is defined by the distance between the first major surface 3 and the bottom of the first region 25. That is, the depth of the second region 26 is greater than the depth of the gate structure 15. When the n-type impurity concentration of the second region 26 is higher than the n-type impurity concentration of the second layer 7, the depth of the second region 26 may be greater or smaller than the depth of the gate structure 15.

[0130] The depth of the second region 26 may be greater than 0 μm and less than or equal to 10 μm. The depth of the second region 26 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0131] 6 to 8, in this embodiment, the plurality of second regions 26 are formed in the inner surface layer portion in regions between the plurality of gate structures 15. Specifically, the plurality of second regions 26 are formed at intervals approximately equal to the intervals between the plurality of gate structures 15, and are formed in a one-to-one correspondence with the regions between the plurality of gate structures 15.

[0132] The second regions 26 are each formed in a pillar shape extending vertically in the thickness direction of the second layer 7. The second regions 26 have a portion located on the first main surface 3 side of the bottom walls of the gate structures 15, and a portion located on the bottom side of the second layer 7 side of the bottom walls of the gate structures 15. The second regions 26 form pn junctions with the first regions 25 in regions below the bottom walls of the gate structures 15.

[0133] The second regions 26, together with the source regions 20, define a channel that serves as a current path in a region on the bottom side of the body region 10. The channel may have a channel length greater than 0 nm and not greater than 500 nm. The channel length is the distance between the bottom of the body region 10 and the bottom of the source region 20.

[0134] The channel length may have a value belonging to at least one of the ranges of greater than 0 nm and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or more and 450 nm or more and 500 nm or less. The channel length is preferably 300 nm or less.

[0135] The second regions 26 form a first superjunction structure SJ1 in an inner surface portion, which has charge balance with the first regions 25. The charge balance state is a state in which a depletion layer extending from one of the first regions 25 and a depletion layer extending from the other of the first regions 25 are connected by the second region 26.

[0136] 11 , the second regions 26 extend from the inner surface layer portion to the peripheral surface layer portion across the outer well region 23. The second regions 26 are arranged in stripes extending in the first direction X in the peripheral surface layer portion.

[0137] In this embodiment, the plurality of second regions 26 are each formed in a strip shape extending from the second end 5B to the fourth end 5D, and are exposed from both the second end 5B and the fourth end 5D. In the region of the outer region 9 along the first end 5A and the third end 5C, the plurality of second regions 26 have facing portions facing the active region 8 in the second direction Y and non-facing portions not facing the active region 8 in the second direction Y.

[0138] The second regions 26 each extend in a pillar shape in the peripheral surface portion from the first main surface 3 toward the bottom of the second layer 7. The second regions 26 have a portion located on the first main surface 3 side relative to the depth positions of the bottom walls of the gate structures 15 in the peripheral surface portion, and a portion located on the bottom side of the second layer 7 relative to the depth positions of the bottom walls of the gate structures 15.

[0139] The second regions 26 have upper and lower ends in the peripheral surface portion. The upper ends of the second regions 26 are exposed from the first main surface 3. The lower ends of the second regions 26 are connected to the first layer 6.

[0140] The second regions 26 form pn junctions with the first regions 25 in the peripheral surface layer portion. The second regions 26 form a second superjunction structure SJ2 in the peripheral surface layer portion, which has charge balance with the first regions 25. The charge balance state is a state in which a depletion layer extending from one first region 25 and a depletion layer extending from the other first region 25 are connected by the second region 26.

[0141] When the n-type impurity concentration of the second region 26 is higher than the n-type impurity concentration of the second layer 7, the multiple second regions 26 may each be formed by a single n-type impurity region extending along the axial channel of the SiC single crystal (second layer 7).

[0142] In this case, the second regions 26 may extend along the c-axis as the axial channel and have the off-axis direction and off-axis angle described above. In other words, the second regions 26 may be tilted from the vertical axis toward the off-axis direction by the off-axis angle. The second regions 26 preferably have a thickness of at least 0.5 μm or more and a concentration decrease rate of 50% or less within a thickness range of 0.5 μm.

[0143] The second regions 26 may each be formed by a plurality of n-type impurity regions arranged in a pillar shape so as to be connected to each other in the thickness direction. The number of impurity regions may be 2 or more and 10 or less. The number of impurity regions may be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0144] The semiconductor device 1A includes at least one (in this embodiment, multiple) shield regions 30 formed in the peripheral surface layer portion (see FIG. 3 ). The multiple shield regions 30 include one or multiple (in this embodiment, one) shield regions 30 on one side (the second end 5B side) and one or multiple (in this embodiment, one) shield regions 30 on the other side (the fourth end 5D side).

[0145] The other shield region 30 has the same configuration as the one shield region 30 except for the location. The configuration of the one shield region 30 will be specifically described below. The configuration of the other shield region 30 can be obtained by replacing the "second end 5B" with the "fourth end 5D" in the following description.

[0146] In this embodiment, the shield region 30 is composed of an n-type impurity region. In this embodiment, the shield region 30 is formed using a part of the second layer 7, and has an n-type impurity concentration that is approximately equal to the n-type impurity concentration of the second layer 7. The n-type impurity concentration of the shield region 30 may be higher than the n-type impurity concentration of the second layer 7. The n-type impurity concentration of the shield region 30 may be lower than the n-type impurity concentration of the second layer 7.

[0147] The shield region 30 is formed in a region between the second end 5B and the active region 8. Specifically, the shield region 30 is formed in a region between the second end 5B and the outer well region 23. The shield region 30 is formed at a distance from the second end 5B on the outer well region 23 side (active region 8 side), and is formed at a distance from the outer well region 23 (active region 8) on the second end 5B side.

[0148] The shield region 30 is formed in a region overlapping at least a portion of at least one first region 25, and divides the at least one first region 25 into a first portion 25a on the peripheral edge side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2. The shield region 30 restricts the movement of carriers (specifically, holes) in the first direction X from the first portion 25a to the second portion 25b.

[0149] The shield region 30 extends in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The shield region 30 has a portion that crosses at least one first region 25 in the second direction Y and contacts a plurality of second regions 26 adjacent to it in the second direction Y.

[0150] In this embodiment, the shield region 30 crosses the plurality of first regions 25 and the plurality of second regions 26 in the second direction Y. In other words, the shield region 30 divides the plurality of first regions 25 into first portions 25a on the peripheral edge side (second end portion 5B side) of the chip 2 and second portions 25b on the inner side of the chip 2.

[0151] The shield region 30 also divides the second regions 26 into first portions 26a on the peripheral side (second end 5B side) of the chip 2 and second portions 26b on the inner side of the chip 2. The shield region 30 is formed integrally with the first portions 26a and second portions 26b of the second regions 26, and divides the second regions 26 into multiple crossroads.

[0152] The shield region 30 is formed in a region facing the active region 8 (plurality of gate structures 15) at least in the first direction X. In this embodiment, the shield region 30 has a facing portion facing the active region 8 in the first direction X, and a non-facing portion that extends from the facing portion toward the periphery of the first main surface 3 and does not face the active region 8 in the first direction X.

[0153] In this embodiment, the shield region 30 is formed in a strip shape extending from the first end 5A to the third end 5C and is exposed from both the first end 5A and the third end 5C. The shield region 30 may be formed spaced apart from either or both of the first end 5A and the third end 5C. The shield region 30 is connected to the plurality of second regions 26 in a region of the outer region 9 closer to the first end 5A, and is connected to the plurality of second regions 26 in a region of the outer region 9 closer to the third end 5C.

[0154] That is, the one and other shield regions 30 are connected to the plurality of second regions 26 in the region of the outer region 9 on the first end 5A side, and are connected to the plurality of second regions 26 in the region of the outer region 9 on the third end 5C side. That is, in this embodiment, the one and other shield regions 30, together with the plurality of second regions 26, form an n-type impurity region that annularly surrounds the active region 8.

[0155] The shield region 30 may have a width greater than the width of the first region 25. The width of the shield region 30 may be smaller than the width of the first region 25. The width of the shield region 30 may be greater than the width of the second region 26. The width of the shield region 30 may be smaller than the width of the second region 26. The width of the shield region 30 may be greater than the width of the gate structure 15. The width of the shield region 30 may be smaller than the width of the gate structure 15.

[0156] The width of the shield region 30 may be greater than 0 μm and less than or equal to 10 μm. The width of the shield region 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0157] The shield region 30 has a depth corresponding to the depth of the second layer 7. The depth of the shield region 30 is greater than the depth of the gate structure 15. When the shield region 30 has a higher n-type impurity concentration than the second layer 7, the shield region 30 may be formed at a distance from the bottom of the second layer 7 toward the first main surface 3. Of course, the shield region 30 may traverse the first layer 6 and the second layer 7 and have its bottom located within the first layer 6.

[0158] The depth of the shield region 30 may be greater than 0 μm and less than or equal to 25 μm. The depth of the shield region 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0159] The shield region 30 may be formed with an end spacing of more than 0 μm and not more than 200 μm from the second end 5B. The end spacing may have a value belonging to at least one of the ranges of more than 0 μm and not more than 5 μm, 5 μm to 10 μm, 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, and 175 μm to 200 μm.

[0160] Fig. 14 is an enlarged plan view showing the peripheral surface layer portion according to the second layout example. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. Referring to Figs. 14 and 15, in this embodiment, the multiple shield regions 30 include multiple shield regions 30 on one side (the second end 5B side) and multiple shield regions 30 on the other side (the fourth end 5D side). The configuration of one of the multiple shield regions 50 will be described below.

[0161] The multiple shield regions 30 are formed at intervals in the first direction X in a region between the second end 5B and the active region 8. Specifically, the multiple shield regions 30 are formed at intervals in the first direction X in a region between the second end 5B and the outer well region 23. The multiple shield regions 30 are formed at intervals from the second end 5B on the outer well region 23 side (active region 8 side), and are formed at intervals from the outer well region 23 (active region 8) on the second end 5B side.

[0162] The multiple shield regions 30 are each formed in an area that overlaps at least a portion of at least one first region 25, and divide the at least one first region 25 into a first portion 25a on the peripheral side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2.

[0163] The multiple shield regions 30 each extend in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The multiple shield regions 30 each have a portion that crosses at least one first region 25 in the second direction Y and contacts multiple second regions 26 adjacent to them in the second direction Y.

[0164] In this embodiment, the multiple shield regions 30 cross the multiple first regions 25 and the multiple second regions 26 in the second direction Y. That is, the multiple shield regions 30 divide the multiple first regions 25 into first portions 25 a and second portions 25 b, and partition the multiple second regions 26 into first portions 26 a and second portions 26 b. The multiple shield regions 30 are formed integrally with the first portions 26 a and second portions 26 b of the multiple second regions 26, and partition multiple crossroads.

[0165] The multiple shield regions 30 are formed in regions facing the active region 8 (the multiple gate structures 15) at least in the first direction X. In this embodiment, the multiple shield regions 30 have facing portions facing the active region 8 in the first direction X and non-facing portions that extend from the facing portions toward the periphery of the first main surface 3 and do not face the active region 8 in the first direction X.

[0166] In this embodiment, the multiple shielding regions 30 are formed in a strip shape extending from the first end 5A to the third end 5C, and are exposed from both the first end 5A and the third end 5C. The multiple shielding regions 30 may be formed at intervals from either or both of the first end 5A and the third end 5C.

[0167] The one and other multiple shield regions 30 are connected to the multiple second regions 26 in the region on the first end 5A side and the region on the third end 5C side. That is, in this embodiment, the one and other multiple shield regions 30, together with the multiple second regions 26, form multiple n-type impurity regions that annularly surround the active region 8.

[0168] The spacing between the shield regions 30 may be greater or smaller than the spacing between the first regions 25. The spacing between the shield regions 30 may be greater or smaller than the spacing between the second regions 26. The spacing between the shield regions 30 may be greater or smaller than the spacing between the gate structures 15.

[0169] The spacing between the shield regions 30 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the shield regions 30 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0170] 16 is an enlarged plan view showing the peripheral surface portion according to the third layout example. Referring to FIG. 16, the plurality of first regions 25 may penetrate the second layer 7 to reach the first layer 6. In this embodiment, the plurality of first regions 25 have bottoms located in the surface portion of the first layer 6 and are electrically connected to the first layer 6 and the second layer 7. The plurality of first regions 25 may also penetrate the second layer 7 in the inner surface portion to reach the first layer 6.

[0171] Although specific illustration is omitted, in this embodiment, the second regions 26 extend in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6 in the regions between the first regions 25. The second regions 26 have upper ends exposed from the first main surface 3 and lower ends connected to the first layer 6.

[0172] In this embodiment, the multiple shielding regions 30 extend in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6. The multiple shielding regions 30 have upper ends exposed from the first main surface 3 and lower ends connected to the first layer 6. The multiple shielding regions 30 may have a layout similar to the first layout example or the second layout example.

[0173] 10 again, the semiconductor device 1A includes a main surface insulating film 31 that selectively covers the first main surface 3. The main surface insulating film 31 may also be referred to as a "surface insulating film," an "outer surface insulating film," or the like. The main surface insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0174] The main surface insulating film 31 may include a silicon oxide film containing an oxide of the chip 2 (second layer 7). The main surface insulating film 31 may include a silicon oxide film containing an oxide other than the oxide of the chip 2. The main surface insulating film 31 may include the same type of insulator as the insulating film 17.

[0175] The main surface insulating film 31 selectively covers the first main surface 3 in the active region 8 and the outer region 9. The main surface insulating film 31 covers the first main surface 3 in the peripheral portion of the active region 8 in a film-like manner, exposing the plurality of gate structures 15. Specifically, the main surface insulating film 31 is connected to the plurality of insulating films 17, and exposes the plurality of buried insulators 19.

[0176] The main surface insulating film 31 covers the first main surface 3 in the outer region 9. Specifically, the main surface insulating film 31 covers the first regions 25, the second regions 26, and the shield regions 30 in the outer region 9. The main surface insulating film 31 covers the entire areas of the shield regions 30.

[0177] The main surface insulating film 31 is continuous with the first to fourth end portions 5A to 5D. The main surface insulating film 31 may be formed at intervals inward from the first to fourth end portions 5A to 5D, exposing the plurality of first regions 25 and the plurality of second regions 26 from the peripheral edge portion of the first main surface 3. The main surface insulating film 31 may have a thickness approximately equal to that of the plurality of insulating films 17.

[0178] The thickness of the main surface insulating film 31 may be 10 nm or more and 250 nm or less. The thickness of the main surface insulating film 31 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0179] The semiconductor device 1A includes one or more (one in this embodiment) gate wirings 32 selectively routed on the first main surface 3 in the outer region 9. The gate wiring 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 32 preferably has the same conductive material as the buried electrode 18.

[0180] The gate wiring 32 is electrically connected to the plurality of gate structures 15 and applies a gate potential to the plurality of gate structures 15. The gate wiring 32 is arranged on the main surface insulating film 31 at a distance from the periphery of the first main surface 3 toward the inside of the first main surface 3 (toward the active region 8), and faces the first main surface 3 via the main surface insulating film 31. The gate wiring 32 is arranged at a distance from the plurality of shield regions 30 toward the inside of the first main surface 3 (toward the active region 8).

[0181] The gate wiring 32 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y, and intersects (specifically, is perpendicular to) ends of the plurality of gate structures 15. In this embodiment, the gate wiring 32 is formed in the shape of an endless polygonal ring (for example, a square ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (the plurality of gate structures 15).

[0182] The gate wiring 32 may be formed in a strip shape with ends. The gate wiring 32 may have an edge portion that connects the strip-like portion extending in the first direction X and the strip-like portion extending in the second direction Y in a plan view, in an arc shape (preferably a quarter arc shape).

[0183] The gate wiring 32 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 32 is mechanically and electrically connected to ends of the multiple gate structures 15. Specifically, the inner edge portion of the gate wiring 32 is mechanically and electrically connected to the multiple buried electrodes 18 in the multiple trenches 16. In this embodiment, the gate wiring 32 is formed integrally with the multiple buried electrodes 18 as an extension portion of the multiple buried electrodes 18.

[0184] The semiconductor device 1A includes an insulating interlayer film 33 covering the first main surface 3. The interlayer film 33 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 33 may have a single-layer structure or a multilayer structure including at least one of an NSG film, a PSG film, and a BPSG film.

[0185] The interlayer film 33 preferably has a single layer structure or a laminated structure including at least an NSG film. The interlayer film 33 may have a laminated structure including an NSG film and a PSG film laminated in this order from the chip 2 side. The interlayer film 33 may have a laminated structure including an NSG film, a PSG film, and a BPSG film laminated in this order from the chip 2 side. The interlayer film 33 may include the same type of insulator as the buried insulator 19.

[0186] The interlayer film 33 covers the main surface insulating film 31 in the active region 8 and the outer region 9. The interlayer film 33 covers the plurality of gate structures 15 in the peripheral portion of the active region 8. Specifically, the interlayer film 33 extends from above the main surface insulating film 31 into the plurality of trenches 16 and covers the plurality of buried electrodes 18 in the plurality of trenches 16.

[0187] The interlayer film 33 is connected to the plurality of buried insulators 19 in the trench 16. In this embodiment, the interlayer film 33 is integrally formed with the plurality of buried insulators 19. The connection portions of the interlayer film 33 to the plurality of buried insulators 19 may be regarded as part of the plurality of buried insulators 19 or as part of the interlayer film 33.

[0188] The interlayer film 33 covers the first main surface 3 in the outer region 9 via the main surface insulating film 31. Specifically, the interlayer film 33 covers the first regions 25, the second regions 26, and the shield regions 30 via the main surface insulating film 31. The interlayer film 33 covers the entire areas of the shield regions 30 via the main surface insulating film 31.

[0189] The interlayer film 33 covers the gate wiring 32 in the outer region 9. The interlayer film 33 is continuous with the first to fourth end portions 5A to 5D. The outer edge portion of the interlayer film 33 is formed at a distance inward from the first to fourth end portions 5A to 5D, and may expose either or both of the peripheral portion of the first main surface 3 and the main surface insulating film 31.

[0190] The interlayer film 33 has a thickness greater than that of the main surface insulating film 31. The thickness of the interlayer film 33 may be 0.1 μm or more and 5 μm or less. The thickness of the interlayer film 33 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0191] The semiconductor device 1A includes one or more (one in this embodiment) source openings 34 formed in the interlayer film 33 in the active region 8. The source openings 34 penetrate the main surface insulating film 31 and the interlayer film 33, and collectively expose the multiple gate structures 15. Specifically, the source openings 34 expose the multiple buried insulators 19, the body region 10, the multiple source regions 20, and the multiple contact regions 21.

[0192] The semiconductor device 1A includes one or more (multiple in this embodiment) gate openings 35 formed in an interlayer film 33. The multiple gate openings 35 penetrate the interlayer film 33 and selectively expose the gate wiring 32. In this embodiment, the multiple gate openings 35 extend in a strip shape following the extension direction of the gate wiring 32.

[0193] The multiple gate openings 35 may be formed at intervals along the extension direction of the gate wiring 32. The multiple gate openings 35 may be formed in a polygonal or circular shape in a plan view. For example, the multiple gate structures 15 may be formed in a quadrangular or hexagonal shape in a plan view.

[0194] The plurality of gate openings 35 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. The plurality of gate openings 35 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view. Of course, the semiconductor device 1A may include one gate opening 35 extending along the gate wiring 32.

[0195] The semiconductor device 1A includes one or more (in this embodiment, multiple) outer openings 36 formed in the interlayer film 33. The multiple outer openings 36 are formed at intervals from the gate wiring 32 toward the periphery of the first main surface 3. The multiple outer openings 36 penetrate the interlayer film 33 and selectively expose the outer well region 23.

[0196] The multiple outer openings 36 are formed at intervals along the extension direction of the outer well region 23. In this embodiment, the multiple outer openings 36 may extend in a strip shape following the extension direction of the outer well region 23. The multiple outer openings 36 may be formed in a polygonal or circular shape in a plan view. For example, the multiple outer openings 36 may be formed in a quadrangular or hexagonal shape in a plan view.

[0197] The outer openings 36 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view. The outer openings 36 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view. Of course, the semiconductor device 1A may include one outer opening 36 extending along the outer well region 23.

[0198] The semiconductor device 1A includes a source electrode 40 disposed on the first main surface 3. The source electrode 40 may also be referred to as a "first main electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source pad electrode," or the like. The source electrode 40 is disposed on an interlayer film 33. The source electrode 40 is disposed at an interval from the multiple shield regions 30 on the inner side of the first main surface 3 (toward the active region 8).

[0199] In this embodiment, the source electrode 40 has a first pad portion 40a, a second pad portion 40b, and a third pad portion 40c. The first pad portion 40a has a relatively large planar area and forms the main body of the source electrode 40. In this embodiment, the first pad portion 40a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and is located closer to the third end portion 5C than the center of the first main surface 3.

[0200] The second pad portion 40b has a planar area smaller than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 40a in the first direction X (the end on the second end 5B side) toward the first end 5A. The third pad portion 40c has a planar area smaller than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 40a in the second direction Y (the end on the fourth end 5D side) toward the first end 5A, and faces the second pad portion 40b in the second direction Y.

[0201] The planar area of ​​the third pad portion 40c may be approximately equal to the planar area of ​​the second pad portion 40b. The planar area of ​​the third pad portion 40c may be larger or smaller than the planar area of ​​the second pad portion 40b. Either or both of the second pad portion 40b and the third pad portion 40c may be used as a terminal portion for monitoring current.

[0202] The source electrode 40 does not necessarily have to have both the second pad portion 40 b and the third pad portion 40 c at the same time, and may have only one of the second pad portion 40 b and the third pad portion 40 c. The source electrode 40 may be composed of only the first pad portion 40 a, and may not have both the second pad portion 40 b and the third pad portion 40 c.

[0203] The source electrode 40 extends from above the interlayer film 33 into the source opening 34 and collectively covers the region within the source opening 34 in a film-like manner. The source electrode 40 is electrically insulated from the plurality of gate structures 15 within the source opening 34 and is mechanically and electrically connected to the body region 10, the plurality of source regions 20, and the plurality of contact regions 21.

[0204] In this embodiment, the source electrode 40 has a layered structure including a base electrode 41 and a main electrode 42. The base electrode 41 extends from above the interlayer film 33 into the source opening 34 and collectively covers the area within the source opening 34 in a film-like manner. The base electrode 41 has a portion that covers the interlayer film 33 in a film-like manner, a portion that covers the wall surface of the source opening 34 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner.

[0205] The base electrode 41 collectively covers the plurality of gate structures 15 within the source opening 34. The base electrode 41 is mechanically and electrically connected to the body region 10, the plurality of source regions 20, and the plurality of contact regions 21 on the first main surface 3. The base electrode 41 covers insulating surfaces of the plurality of buried insulators 19 within the plurality of trenches 16, and is electrically isolated from the plurality of buried electrodes 18.

[0206] The base electrode 41 has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 33. The peripheral portion of the base electrode 41 is drawn from the active region 8 to the outer region 9 and faces a part of the gate wiring 32 via the interlayer film 33. The peripheral portion of the base electrode 41 is formed at a distance from the outer edge of the gate wiring 32 toward the inner edge of the gate wiring 32. The peripheral portion of the base electrode 41 may be located inward from the middle portion of the gate wiring 32.

[0207] The base electrode 41 may have a layered structure including multiple metal films or a single-layer structure including a single metal film. For example, the base electrode 41 may have a layered structure including a Ti film and a TiN film stacked in this order from the first main surface 3 side. For example, the base electrode 41 may have a single-layer structure including a Ti film or a TiN film.

[0208] The thickness of the base electrode 41 may be greater than 0 nm and less than or equal to 500 nm. The thickness of the base electrode 41 may have a value belonging to at least one of the ranges of 0 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0209] The main electrode 42 is made of a different conductor from that of the base electrode 41. In this embodiment, the main electrode 42 is made of an aluminum alloy. The aluminum alloy may include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0210] The main electrode 42 covers the base electrode 41 in a film-like manner and extends into the source opening 34 from above the interlayer film 33. The main electrode 42 has a portion that covers the interlayer film 33 in a film-like manner via the base electrode 41, a portion that covers the wall surface of the source opening 34 in a film-like manner via the base electrode 41, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 41.

[0211] The main electrode 42 collectively covers the plurality of gate structures 15 within the source opening 34 via the base electrode 41. The main electrode 42 is electrically connected to the body region 10, the plurality of source regions 20, and the plurality of contact regions 21 via the base electrode 41.

[0212] The main electrode 42 has a peripheral portion that faces the ends of the plurality of gate structures 15 via the interlayer film 33. The peripheral portion of the main electrode 42 is drawn from the active region 8 to the outer region 9 and faces a part of the gate wiring 32 via the interlayer film 33. The peripheral portion of the main electrode 42 is formed at a distance from the outer edge of the gate wiring 32 toward the inner edge of the gate wiring 32. The peripheral portion of the main electrode 42 may be located inward from the middle of the gate wiring 32.

[0213] The main electrode 42 has a thickness greater than that of the base electrode 41. In this embodiment, the thickness of the main electrode 42 is greater than that of the interlayer film 33. The thickness of the main electrode 42 may be less than that of the interlayer film 33.

[0214] The thickness of the main electrode 42 may be greater than 0 μm and less than 5 μm. The thickness of the main electrode 42 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0215] The semiconductor device 1A includes source finger electrodes 43 extending from the source electrode 40 onto the first main surface 3. The source finger electrodes 43 may also be referred to as "source wiring," "source fingers," etc. The source finger electrodes 43 transmit the source potential applied to the source electrode 40 to other regions.

[0216] The source finger electrodes 43 are arranged at intervals from the multiple shield regions 30 on the inner side (active region 8 side) of the first main surface 3. The source finger electrodes 43 are drawn out from the source electrode 40 onto the interlayer film 33 and routed in a strip shape along the source electrode 40. The source finger electrodes 43 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0217] In this embodiment, the source finger electrode 43 is formed in an endless polygonal ring shape (e.g., a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 40. The source finger electrode 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0218] The source finger electrodes 43 extend into the plurality of outer openings 36 from above the interlayer film 33, and are mechanically and electrically connected to the outer well region 23 within the plurality of outer openings 36. As a result, the source potential applied to the source electrode 40 is applied to the outer well region 23 and the plurality of first regions 25 via the source finger electrodes 43.

[0219] Like the source electrode 40, the source finger electrode 43 has a layered structure including a base electrode 41 and a main electrode 42 layered in this order from the first main surface 3. The base electrode 41 collectively covers the region of the interlayer film 33 where the multiple outer openings 36 are formed, and extends from above the interlayer film 33 into the multiple outer openings 36.

[0220] The base electrode 41 has a portion that covers the insulating surface of the interlayer film 33 in a film-like manner, a portion that covers the wall surfaces of the plurality of outer openings 36 in a film-like manner, and a portion that covers the outer well region 23 in the plurality of outer openings 36 in a film-like manner. The base electrode 41 is mechanically and electrically connected to the outer well region 23 in the plurality of outer openings 36.

[0221] The main electrode 42 covers the region of the interlayer film 33 where the plurality of outer openings 36 are formed via the base electrode 41 , and extends from above the interlayer film 33 into the plurality of outer openings 36 .

[0222] The main electrode 42 has a portion that coats the interlayer film 33 in a film form via the base electrode 41, a portion that coats the wall surfaces of the plurality of outer openings 36 in a film form via the base electrode 41, and a portion that coats the outer well region 23 in a film form via the base electrode 41 within the plurality of outer openings 36. The main electrode 42 is electrically connected to the outer well region 23 via the base electrode 41 within the plurality of outer openings 36.

[0223] The semiconductor device 1A includes a gate electrode 44 disposed on the first main surface 3. The gate electrode 44 may also be referred to as a "second main electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate pad electrode," or the like. The gate electrode 44 is disposed on the interlayer film 33 at a distance from the source electrode 40 and the source finger electrodes 43. The gate electrode 44 is disposed at a distance from the multiple shield regions 30 on the inner side of the first main surface 3 (toward the active region 8).

[0224] The gate electrode 44 is disposed in a region on the first end 5A side of the first pad 40a, and faces the center of the first end 5A and the first pad 40a in the second direction Y. The gate electrode 44 is interposed in a region between the second pad 40b and the third pad 40c, and faces both the second pad 40b and the third pad 40c in the first direction X.

[0225] The gate electrode 44 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 44 has a planar area smaller than that of the source electrode 40. The planar area of ​​the gate electrode 44 is smaller than that of the first pad portion 40a. The planar area of ​​the gate electrode 44 may be larger or smaller than that of the second pad portion 40b (third pad portion 40c).

[0226] In this embodiment, the gate electrode 44 does not have a direct electrical connection to the gate wiring 32. Of course, the gate electrode 44 may be mechanically and electrically connected to the gate wiring 32 via one or more gate openings 35. Although not shown, the gate electrode 44, like the source electrode 40, includes a base electrode 41 and a main electrode 42 laminated in this order from the interlayer film 33 side.

[0227] The semiconductor device 1A includes a gate finger electrode 45 extending from the gate electrode 44 onto the first main surface 3. The gate finger electrode 45 may also be referred to as a "gate wiring 32," a "gate finger," or the like. The gate finger electrode 45 transmits the gate potential applied to the gate electrode 44 to other regions.

[0228] The gate finger electrodes 45 are arranged at intervals from the multiple shield regions 30 on the inner side (active region 8 side) of the first main surface 3. The gate finger electrodes 45 are arranged on the interlayer film 33 at intervals from the source electrode 40 and the source finger electrodes 43. The gate finger electrodes 45 are drawn from the gate electrode 44 to the region between the source electrode 40 and the source finger electrodes 43, and are routed in a strip shape along the source electrode 40.

[0229] The gate finger electrode 45 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y. In this embodiment, the gate finger electrode 45 is formed in a strip shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 40.

[0230] The gate finger electrode 45 is disposed closer to the periphery of the first main surface 3 than both end portions of the plurality of gate structures 15. The gate finger electrode 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0231] The gate finger electrodes 45 extend from above the interlayer film 33 into the plurality of gate openings 35, and are mechanically and electrically connected to the gate wiring 32 within the plurality of gate openings 35. As a result, the gate potential applied to the gate electrode 44 is applied to the plurality of gate structures 15 via the gate wiring 32 and the gate finger electrodes 45.

[0232] The gate finger electrode 45 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 45 is formed at a distance from the ends of the multiple gate structures 15 toward the peripheral side of the first main surface 3, and faces the first main surface 3 in the stacking direction. In other words, the gate finger electrode 45 does not face the multiple gate structures 15 in the stacking direction.

[0233] The inner edge of the gate finger electrode 45 is disposed on the gate wiring 32. The inner edge of the gate finger electrode 45 faces the peripheral edge of the source electrode 40 in the horizontal direction above the gate wiring 32. The inner edge of the gate finger electrode 45 is located closer to the peripheral edge of the first main surface 3 than the middle part of the gate wiring 32. The outer edge of the gate finger electrode 45 is drawn out from above the gate wiring 32 to the peripheral edge of the first main surface 3, and faces the first main surface 3 in the stacking direction.

[0234] Like the gate electrode 44, the gate finger electrode 45 has a layered structure including a base electrode 41 and a main electrode 42 layered in this order from the first main surface 3. The base electrode 41 collectively covers the region of the interlayer film 33 where the multiple gate openings 35 are formed, and extends from above the interlayer film 33 into the multiple gate openings 35.

[0235] The base electrode 41 has a portion that covers the insulating surface of the interlayer film 33 in a film-like manner, a portion that covers the wall surfaces of the plurality of gate openings 35 in a film-like manner, and a portion that covers the gate wiring 32 in the plurality of gate openings 35 in a film-like manner. The base electrode 41 is mechanically and electrically connected to the gate wiring 32 in the plurality of gate openings 35.

[0236] The main electrode 42 covers the region of the interlayer film 33 where the plurality of gate openings 35 are formed via the base electrode 41 , and extends from above the interlayer film 33 into the plurality of gate openings 35 .

[0237] The main electrode 42 has a portion that coats the interlayer film 33 in a film form via the base electrode 41, a portion that coats the wall surfaces of the plurality of gate openings 35 in a film form via the base electrode 41, and a portion that coats the gate wiring 32 in a film form via the base electrode 41 within the plurality of gate openings 35. The main electrode 42 is electrically connected to the gate wiring 32 via the base electrode 41 within the plurality of gate openings 35.

[0238] The semiconductor device 1A includes a drain electrode 46 covering the second main surface 4. The drain electrode 46 may also be referred to as a "third main electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain pad electrode," or the like. The drain electrode 46 is mechanically and electrically connected to the first layer 6. The drain electrode 46 forms ohmic contact with the first layer 6.

[0239] The drain electrode 46 faces the multiple shield regions 30 in the thickness direction. The drain electrode 46 may cover the entire second main surface 4 and be continuous with the periphery (first to fourth ends 5A to 5D) of the second main surface 4. The drain electrode 46 may also partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0240] A breakdown voltage that can be applied between the source electrode 40 and the drain electrode 46 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0241] As described above, the semiconductor device 1A may include the chip 2, the p-type first region 25, the plurality of n-type second regions 26, and the shield region 30. The chip 2 may have a first main surface 3. The first region 25 may extend in a first direction X along the first main surface 3 at a peripheral surface layer portion of the first main surface 3. The plurality of second regions 26 may extend in the first direction X on both sides of the first region 25 at a peripheral surface layer portion of the first main surface 3.

[0242] The shield region 30 may divide at least a part of the first region 25 into a region on the edge side of the chip 2 and a region on the inner side of the chip 2 in the peripheral surface layer portion of the first main surface 3. In this embodiment, the shield region 30 includes an impurity region having n-type conductivity.

[0243] This configuration provides a semiconductor device 1A with a novel layout. In this semiconductor device 1A, when a low potential (e.g., source potential) is applied to the first region 25 and a high potential (e.g., drain potential) is applied to the second region 26, a depletion layer spreads from the first region 25. When the depletion layer reaches the edge of the chip 2, carriers are generated from the rough portion at the edge of the chip 2, causing a leakage current through the first region 25.

[0244] In this regard, according to the configuration of the semiconductor device 1A, the depletion layer that spreads from the first region 25 in the region on the edge side of the chip 2 is suppressed by the shield region 30. Furthermore, carriers generated from the edge of the chip 2 are recombined with carriers in the shield region 30. In other words, the shield region 30 restricts the movement of carriers from the edge of the chip 2 to the inside of the chip 2 via the first region 25. This reduces the leakage current via the first region 25 and improves the electrical characteristics.

[0245] The chip 2 may include SiC. This configuration provides a semiconductor device 1A as a novel SiC semiconductor device. The semiconductor device 1A appropriately improves electrical characteristics due to the physical properties of SiC. Since SiC semiconductor devices are used in a relatively high voltage environment, the effect of suppressing leakage current by the shield region 30 is effective.

[0246] The first region 25 may be exposed from the edge of the chip 2. With this configuration, the semiconductor device 1A has a structure that makes it easy for depletion to occur at the edge of the chip 2. In this regard, the shield region 30 appropriately suppresses depletion at the edge of the chip 2. In this case, the multiple second regions 26 may be exposed from the edge. The shield region 30 may be formed at an interval from the edge of the chip 2. With this configuration, depletion at the edge of the chip 2 is appropriately suppressed.

[0247] The first region 25 may extend vertically in the thickness direction of the chip 2. The multiple second regions 26 may extend vertically in the thickness direction. The shield region 30 may extend vertically in the thickness direction. According to this configuration, in a configuration in which a depletion layer spreads from the vertically extending first region 25 in the horizontal direction along the first main surface 3, depletion at the end of the chip 2 is appropriately suppressed by the shield region 30.

[0248] The shield region 30 may extend in the second direction Y along the first main surface 3 and intersect with the first region 25. The shield region 30 may cross the first region 25 in the second direction Y and have portions that contact multiple second regions 26. With these configurations, the shield region 30 intersects with the direction in which the leakage current flows, thereby appropriately shielding the leakage current path.

[0249] The plurality of first regions 25 may be formed in a surface layer portion of the periphery of the first main surface 3. In this case, one or more shield regions 30 may separate at least a portion of the plurality of first regions 25 from the end portion of the chip 2. According to this configuration, the shield region 30 suppresses a depletion layer that spreads from the plurality of first regions 25 in the region on the end portion of the chip 2, and at the same time, the shield region 30 blocks a leakage current path via the plurality of first regions 25.

[0250] The semiconductor device 1A may include an active region 8 and an outer region 9. The active region 8 may be provided in an inner portion of the chip 2. The outer region 9 may be provided in a peripheral portion of the chip 2. The first region 25 may be formed in both the active region 8 and the outer region 9. The plurality of second regions 26 may be formed in both the active region 8 and the outer region 9.

[0251] The shield region 30 may be formed in the outer region 9. According to this configuration, the leakage current from the outer region 9 to the active region 8 is appropriately suppressed by the shield region 30. This improves the reliability (electrical characteristics) of the active region 8.

[0252] The shield region 30 may have a facing portion facing the active region 8 in the first direction X and a non-facing portion not facing the active region 8 in the first direction X. With this configuration, the leakage current reaching the active region 8 is appropriately shielded in both the facing portion and the non-facing portion of the shield region 30.

[0253] At least one first region 25 may extend in the first direction X in the outer region 9 and face the active region 8 in the second direction Y. At least one second region 26 may extend in the first direction X in the outer region 9 and face the active region 8 in the second direction Y. According to this configuration, the second region 26 arranged in a region on the second direction Y side of the active region 8 functions as a shield region (30). This allows the second region 26 to shield leakage current from the end of the chip 2 toward the active region 8 along the second direction Y.

[0254] The shield region 30 may have a portion connected to the first region 25, which has a portion facing the active region 8 in the second direction Y. The shield region 30 may have a portion connected to the second region 26, which has a portion facing the active region 8 in the second direction Y.

[0255] The semiconductor device 1A may include a transistor structure formed in the active region 8. This configuration suppresses leakage current flowing into the transistor structure, improving the reliability (electrical characteristics) of the transistor structure. The transistor structure may have a trench-type gate structure 15.

[0256] The semiconductor device 1A may include a p-type outer well region 23. The outer well region 23 may be formed in a surface layer portion of the first main surface 3 along the active region 8, and may separate the active region 8 from the outer region 9. In this case, the first region 25 may be electrically connected to the outer well region 23. With this configuration, the leakage current path from the end of the chip 2 to the outer well region 23 can be appropriately shielded by the shield region 30.

[0257] The chip 2 may have a stacked structure including an n-type first layer 6 (first semiconductor layer) and an n-type second layer 7 (second semiconductor layer), and may have a first main surface 3 formed by the second layer 7. The first region 25 may be formed in the second layer 7. A plurality of second regions 26 may be formed in the second layer 7. The shielding region 30 may be formed in the second layer 7. With this configuration, the movement of carriers from the end of the chip 2 to the interior of the chip 2 via the first region 25 in the second layer 7 is appropriately restricted by the shielding region 30.

[0258] The first region 25 may be formed in the second layer 7 at a distance from the first layer 6. The second region 26 may be formed in the second layer 7 at a distance from the first layer 6. The shielding region 30 may be formed in the second layer 7 at a distance from the first layer 6. The first region 25 may have a portion connected to the first layer 6. The second region 26 may have a portion connected to the second layer 7. The shielding region 30 may have a portion connected to the second layer 7.

[0259] The semiconductor device 1A may include a gate wiring 32. The gate wiring 32 may be formed at a distance from the shield region 30 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate wiring 32 on the shield region 30 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0260] The semiconductor device 1A may include a source electrode 40. The source electrode 40 may be disposed on the first main surface 3 and electrically connected to the first region 25. The source electrode 40 may be formed at a distance from the shield region 30 on the inward side of the first main surface 3. With this configuration, the electrical influence of the source electrode 40 on the shield region 30 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0261] The semiconductor device 1A may include source finger electrodes 43. The source finger electrodes 43 may be formed at intervals from the shield region 30 on the inward side of the first main surface 3. With this configuration, the electrical influence of the source finger electrodes 43 on the shield region 30 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0262] The semiconductor device 1A may include a gate electrode 44. The gate electrode 44 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate electrode 44 may be formed at a distance from the shield region 30 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate electrode 44 on the shield region 30 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0263] The semiconductor device 1A may include a gate finger electrode 45. The gate finger electrode 45 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate finger electrode 45 may be formed at a distance from the shield region 30 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate finger electrode 45 on the shield region 30 is reduced, and degradation of the function of the shield region 60 is appropriately suppressed.

[0264] The semiconductor device 1A may have a drain electrode 46. The drain electrode 46 may be disposed on the second main surface 4 and electrically connected to the second region 26. The drain electrode 46 may face the shield region 30 in the thickness direction.

[0265] The semiconductor device 1A may include a main surface insulating film 31 that covers the shield region 30 on the first main surface 3. According to this configuration, the main surface insulating film 31 reduces the electrical influence on the shield region 30.

[0266] The semiconductor device 1A may include an interlayer film 33 that covers the shield region 30 on the first main surface 3. The interlayer film 33 may cover the shield region 30 via the main surface insulating film 31. According to this configuration, the electrical influence on the shield region 30 is reduced by the interlayer film 33.

[0267] A conductor (e.g., polysilicon or metal) does not need to be disposed on the portion of the interlayer film 33 (main surface insulating film 31) that covers the shield region 30. With this configuration, the electrical influence on the shield region 30 is appropriately reduced.

[0268] Fig. 17 is a plan view showing a layout example of a surface layer portion of a first main surface 3 of a semiconductor device 1B according to a second embodiment. Fig. 18 is an enlarged plan view showing a peripheral surface layer portion according to the first layout example. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 18.

[0269] In this embodiment, the semiconductor device 1B includes at least one (in this embodiment, multiple) trench-insulated (insulating) shield region 50 in the peripheral surface layer portion instead of the shield region 30. The shield region 50 may be referred to as a "shield structure." The multiple shield regions 50 include one or multiple (one in this embodiment) shield regions 50 on one side (the second end 5B side) and one or multiple (one in this embodiment) shield regions 50 on the other side (the fourth end 5D side).

[0270] The other shield region 50 has the same configuration as the one shield region 50 except for the location. The configuration of the one shield region 50 will be specifically described below. The configuration of the other shield region 50 can be obtained by replacing the "second end 5B" with the "fourth end 5D" in the following description.

[0271] The shield region 50 is formed in a region between the second end 5B and the active region 8. Specifically, the shield region 50 is formed in a region between the second end 5B and the outer well region 23. The shield region 50 is formed at a distance from the second end 5B on the outer well region 23 side (active region 8 side), and is formed at a distance from the outer well region 23 (active region 8) on the second end 5B side.

[0272] The shield region 50 is formed in a region overlapping at least a portion of at least one first region 25, and divides the at least one first region 25 into a first portion 25a on the peripheral edge side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2. The shield region 50 restricts movement of the carrier in the first direction X from the first portion 25a to the second portion 25b.

[0273] The shield region 50 extends in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The shield region 50 has portions that cross at least one first region 25 in the second direction Y and contact multiple second regions 26 adjacent to each other in the second direction Y.

[0274] In this embodiment, the shield region 50 crosses the multiple first regions 25 and the multiple second regions 26 in the second direction Y. That is, the shield region 50 divides the multiple first regions 25 into first portions 25a on the peripheral side (second end 5B side) of the chip 2 and second portions 25b on the inner side of the chip 2. The shield region 50 also divides the multiple second regions 26 into first portions 26a on the peripheral side (second end 5B side) of the chip 2 and second portions 26b on the inner side of the chip 2.

[0275] Specifically, the shield region 50 electrically insulates the first portion 25 a and the second portion 25 b in the region between the plurality of second regions 26, and restricts the movement of carriers in the first direction X from the first portion 25 a to the second portion 25 b. The shield region 50 also electrically insulates the first portion 26 a and the second portion 26 b in the region between the plurality of first regions 25.

[0276] The shield region 50 is formed in a region facing the active region 8 (plurality of gate structures 15) at least in the first direction X. In this embodiment, the shield region 50 has a facing portion facing the active region 8 in the first direction X, and a non-facing portion that extends from the facing portion toward the periphery of the first main surface 3 and does not face the active region 8 in the first direction X.

[0277] In this embodiment, the shielding region 50 is formed in a strip shape extending from the first end 5A to the third end 5C, and is exposed from both the first end 5A and the third end 5C. The shielding region 50 may be formed spaced apart from either or both of the first end 5A and the third end 5C.

[0278] The shield region 50 may have a width greater than the width of the first region 25. The width of the shield region 50 may be smaller than the width of the first region 25. The width of the shield region 50 may be greater than the width of the second region 26. The width of the shield region 50 may be smaller than the width of the second region 26. The width of the shield region 50 may be greater than the width of the gate structure 15. The width of the shield region 50 may be smaller than the width of the gate structure 15.

[0279] The width of the shield region 50 may be greater than 0 μm and less than or equal to 10 μm. The width of the shield region 50 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0280] The shield region 50 is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 across a part of the second layer 7. The shield region 50 is formed approximately perpendicular to the first main surface 3. The shield region 50 may be formed in a tapered shape toward the bottom of the second layer 7. The sidewalls (long sides) of the shield region 50 are formed by the a-plane of the SiC single crystal. The sidewalls (long sides) of the shield region 50 may be formed by the m-plane of the SiC single crystal depending on the extension direction of the shield region 50.

[0281] The sidewalls of the shield region 50, together with the first main surface 3, define an open end curved in an arc (circular arc). The bottom wall of the shield region 50 is formed by the c-plane (Si-plane) of the SiC single crystal. The bottom wall of the shield region 50 preferably extends substantially flat in the horizontal direction. The bottom wall of the shield region 50 may also be curved in an arc toward the second main surface 4.

[0282] The inclination angle (absolute value) of the sidewall (long side) of the shield region 50 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0283] The shield region 50 has a depth greater than the depth of the second region 26, and has a bottom located closer to the first layer 6 than the bottom of the second region 26. The shield region 50 may have a depth less than the depth of the second region 26, and may have a bottom located closer to the first main surface 3 than the bottom of the second region 26. The depth of the shield region 50 is greater than the depth of the gate structure 15. The depth of the shield region 50 may be smaller than the depth of the gate structure 15.

[0284] The depth of the shield region 50 may be greater than 0 μm and less than or equal to 25 μm. The depth of the shield region 50 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0285] The shield region 50 may be formed with an end spacing of more than 0 μm and not more than 200 μm from the second end 5B. The end spacing may have a value belonging to at least one of the ranges of more than 0 μm and not more than 5 μm, 5 μm to 10 μm, 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, and 175 μm to 200 μm.

[0286] In this embodiment, the shield region 50 includes a shield trench 51, a shield insulating film 52, and a shield insulator 53. The shield trench 51 is formed in the first main surface 3 and defines the sidewall and bottom wall of the shield region 50. The shield trench 51 exposes a plurality of first regions 25 and a plurality of second regions 26 from the sidewall.

[0287] The shield insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The shield insulating film 52 may include a silicon oxide film containing an oxide of the chip 2 (second layer 7). The shield insulating film 52 may include a silicon oxide film containing an oxide other than the oxide of the chip 2. The shield insulating film 52 may include the same type of insulating material as the insulating film 17.

[0288] The shield insulating film 52 coats the wall surfaces (side walls and bottom wall) of the shield trench 51. In this embodiment, the shield insulating film 52 coats the plurality of first regions 25 and the plurality of second regions 26 on the side walls of the shield trench 51, and coats the second layer 7 on the bottom wall of the shield trench 51.

[0289] The shield insulating film 52 may have a thickness approximately equal to that of the insulating film 17. The thickness of the shield insulating film 52 may be greater or less than that of the insulating film 17. The thickness of the portion of the shield insulating film 52 that covers the sidewall of the shield trench 51 may be greater than the thickness of the portion of the shield insulating film 52 that covers the bottom wall of the shield trench 51.

[0290] The thickness of the shield insulating film 52 may be 10 nm or more and 250 nm or less. The thickness of the shield insulating film 52 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0291] The shield insulator 53 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The shield insulator 53 may include an insulating material of the same type as or different from the insulating material of the shield insulating film 52.

[0292] The shield insulator 53 may have a single-layer structure or a multi-layer structure including at least one of an NSG film, a PSG film, and a BPSG film. The shield insulator 53 preferably has a single-layer structure or a multi-layer structure including at least an NSG film. The shield insulator 53 may have a multi-layer structure including an NSG film and a PSG film stacked in this order from the chip 2 side.

[0293] The shield insulator 53 may have a layered structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side (the wall surface side of the shield trench 51). The shield insulator 53 may have a single-layer structure or a layered structure including a silicon oxide film. The shield insulator 53 may include the same type of insulating material as the insulating material of the buried insulator 19.

[0294] The shield insulator 53 is embedded in the shield trench 51 via the shield insulating film 52. In this embodiment, the shield insulator 53 covers the plurality of first regions 25 and the plurality of second regions 26 on the sidewall of the shield trench 51 via the shield insulating film 52, and covers the second layer 7 on the bottom wall of the shield trench 51 via the shield insulating film 52.

[0295] The shield insulator 53 covers the plurality of first regions 25 and the plurality of second regions 26 via the shield insulating film 52. The shield region 50 does not necessarily have to have the shield insulating film 52. In this case, the shield insulator 53 may be directly embedded in the shield trench 51 and directly cover the plurality of first regions 25 and the plurality of second regions 26.

[0296] As in the case of the semiconductor device 1A, the aforementioned main surface insulating film 31 covers the first main surface 3 in the outer region 9. Specifically, the main surface insulating film 31 covers the plurality of first regions 25 and the plurality of second regions 26 in the outer region 9. The main surface insulating film 31 is connected to the plurality of shield insulating films 52 and exposes the plurality of shield insulators 53.

[0297] The main surface insulating film 31 is continuous with the first to fourth end portions 5A to 5D. The main surface insulating film 31 may be formed at intervals inward from the first to fourth end portions 5A to 5D, exposing the peripheral edge portion of the first main surface 3. The main surface insulating film 31 may have a thickness substantially equal to that of the plurality of shield insulating films 52.

[0298] As in the case of the semiconductor device 1A, the aforementioned interlayer film 33 covers the main surface insulating film 31 in a film form in the outer region 9. Specifically, the interlayer film 33 covers the first regions 25 and the second regions 26 in the outer region 9 via the main surface insulating film 31. The interlayer film 33 extends from above the main surface insulating film 31 onto the shield insulators 53 and covers the shield insulators 53.

[0299] The interlayer film 33 is connected to the plurality of shield insulators 53 within the plurality of shield trenches 51. In this embodiment, the interlayer film 33 is integrally formed with the plurality of shield insulators 53. The connection portions of the interlayer film 33 to the plurality of shield insulators 53 may be considered as part of the plurality of shield insulators 53 or may be considered as part of the interlayer film 33.

[0300] The portions of the interlayer film 33 that cover the multiple shield trenches 51 have recesses that are recessed toward the bottom walls of the multiple shield trenches 51. Of course, the interlayer film 33 may be formed separately from the multiple shield insulators 53 and cover the insulating surfaces of the multiple shield insulators 53 within the multiple shield trenches 51.

[0301] The interlayer film 33 is continuous with the first to fourth end portions 5A to 5D. The outer edge portion of the interlayer film 33 is formed at a distance inward from the first to fourth end portions 5A to 5D, and may expose either or both of the peripheral portion of the first main surface 3 and the main surface insulating film 31.

[0302] Fig. 21 is an enlarged plan view showing a peripheral surface layer portion according to the second layout example. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21. Referring to Figs. 21 and 22, in this embodiment, the multiple shield regions 50 include multiple shield regions 50 on one side (the second end 5B side) and multiple shield regions 50 on the other side (the fourth end 5D side). The configuration of one of the multiple shield regions 50 will be described below.

[0303] The multiple shield regions 50 are formed at intervals in the first direction X in a region between the second end 5B and the active region 8. Specifically, the multiple shield regions 50 are formed at intervals in the first direction X in a region between the second end 5B and the outer well region 23. The multiple shield regions 50 are formed at intervals from the second end 5B on the outer well region 23 side (active region 8 side), and are formed at intervals from the outer well region 23 (active region 8) on the second end 5B side.

[0304] The multiple shield regions 50 are each formed in an area that overlaps at least a portion of at least one first region 25, and divide the at least one first region 25 into a first portion 25a on the peripheral side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2.

[0305] The multiple shield regions 50 each extend in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The multiple shield regions 50 each have a portion that crosses at least one first region 25 in the second direction Y and contacts multiple second regions 26 adjacent to them in the second direction Y.

[0306] In this embodiment, the multiple shield regions 50 cross the multiple first regions 25 and the multiple second regions 26 in the second direction Y. That is, the multiple shield regions 50 divide the multiple first regions 25 into first portions 25 a and second portions 25 b, and divide the multiple second regions 26 into first portions 26 a and second portions 26 b.

[0307] The multiple shield regions 50 are formed in regions facing the active region 8 (the multiple gate structures 15) at least in the first direction X. In this embodiment, the multiple shield regions 50 have facing portions facing the active region 8 in the first direction X and non-facing portions that extend from the facing portions toward the periphery of the first main surface 3 and do not face the active region 8 in the first direction X.

[0308] In this embodiment, the multiple shielding regions 50 are formed in a strip shape extending from the first end 5A to the third end 5C, and are exposed from both the first end 5A and the third end 5C. The multiple shielding regions 50 may be formed at intervals from either or both of the first end 5A and the third end 5C.

[0309] The spacing between the shield regions 50 may be greater or less than the spacing between the first regions 25. The spacing between the shield regions 50 may be greater or less than the spacing between the second regions 26. The spacing between the shield regions 50 may be greater or less than the spacing between the gate structures 15.

[0310] The spacing between the shield regions 50 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the shield regions 50 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0311] 23 is an enlarged plan view showing the peripheral surface portion according to the third layout example. Referring to FIG. 23, the plurality of first regions 25 may penetrate the second layer 7 to reach the first layer 6. In this embodiment, the plurality of first regions 25 have bottoms located in the surface portion of the first layer 6 and are electrically connected to the first layer 6 and the second layer 7. The plurality of first regions 25 may also penetrate the second layer 7 in the inner surface portion to reach the first layer 6.

[0312] Although specific illustration is omitted, in this embodiment, the second regions 26 extend in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6 in the regions between the first regions 25. The second regions 26 have upper ends exposed from the first main surface 3 and lower ends connected to the first layer 6.

[0313] In this embodiment, the shield region 50 extends in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6. In this embodiment, the shield region 50 penetrates the second layer 7 and has a bottom wall located in the surface portion of the first layer 6. The shield insulating film 52 covers the multiple first regions 25 and the multiple second regions 26 on the sidewalls of the shield trench 51, and covers the first layer 6 on the bottom wall of the shield trench 51.

[0314] The shield insulator 53 covers the plurality of first regions 25 and the plurality of second regions 26 on the sidewall of the shield trench 51 via the shield insulating film 52, and covers the first layer 6 on the bottom wall of the shield trench 51 via the shield insulating film 52. Of course, the shield insulator 53 may directly cover the first layer 6, the plurality of first regions 25, and the plurality of second regions 26.

[0315] 24 is an enlarged plan view showing the peripheral surface layer portion according to layout example 4. Referring to Fig. 24, in this embodiment, the plurality of shield regions 50 includes a plurality of first shield regions 50A arranged in a region on the first direction X side of the active region 8, and a plurality of second shield regions 50B arranged in a region on the second direction Y side of the active region 8.

[0316] The plurality of first shield regions 50A correspond to the shield regions 50 according to the first layout example. The plurality of first shield regions 50A may have the second layout example or the third layout example.

[0317] The multiple second shield regions 50B include one or more (one in this embodiment) second shield regions 50B on one side (the first end 5A side) and one or more (one in this embodiment) second shield regions 50B on the other side (the third end 5C side). The configuration of the second shield region 50B on one side will be described in detail below. The configuration of the second shield region 50B on the other side can be obtained by replacing "first end 5A" with "third end 5C" in the following description.

[0318] Similar to the first shield region 50A, the second shield region 50B includes a shield trench 51, a shield insulating film 52, and a shield insulator 53. The second shield region 50B is formed in a region between the multiple first shield regions 50A and extends in a direction different from the extension direction of the multiple first shield regions 50A. In this embodiment, the second shield region 50B extends in a strip shape in the first direction X. In other words, the second shield region 50B extends in the same direction as the extension direction of the multiple gate structures 15, the multiple first regions 25, and the multiple second regions 26.

[0319] The second shield region 50B is formed in a region facing the active region 8 (plurality of gate structures 15) at least in the second direction Y. In this embodiment, the second shield region 50B has a facing portion facing the active region 8 in the second direction Y, and a non-facing portion that extends from the facing portion toward the periphery of the first main surface 3 and does not face the active region 8 in the second direction Y.

[0320] In this embodiment, the second shield region 50B is formed at a distance from the second end 5B and the fourth end 5D in the first direction X. Of course, the second shield region 50B may be exposed from either or both of the second end 5B and the fourth end 5D.

[0321] The second shield region 50B is connected to the plurality of first shield regions 50A. That is, the shield trenches 51, the shield insulating films 52, and the shield insulators 53 of the second shield region 50B are connected to the shield trenches 51, the shield insulating films 52, and the shield insulators 53 of the plurality of first shield regions 50A, respectively.

[0322] The second shield region 50B has a width approximately equal to that of the first shield region 50A. Of course, the width of the second shield region 50B may be larger or smaller than that of the first shield region 50A. The width of the second shield region 50B may be larger than that of the gate structure 15. The width of the second shield region 50B may be smaller than that of the gate structure 15.

[0323] The second shield region 50B may have a width greater than the width of the first region 25. The width of the second shield region 50B may be smaller than the width of the first region 25. The width of the second shield region 50B may be greater than the width of the second region 26. The width of the second shield region 50B may be smaller than the width of the second region 26.

[0324] The width of second shield region 50B may be greater than 0 μm and less than or equal to 10 μm. The width of second shield region 50B may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0325] The second shield region 50B is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 across a part of the second layer 7. The second shield region 50B is formed substantially perpendicular to the first main surface 3. The second shield region 50B may be formed in a tapered shape toward the bottom of the second layer 7.

[0326] The sidewalls of the second shield region 50B define an open end curved in an arc shape (circular arc) together with the first main surface 3. The bottom wall of the second shield region 50B is formed by the c-plane (Si-plane) of the SiC single crystal. The bottom wall of the second shield region 50B preferably extends substantially flat in the horizontal direction. The bottom wall of the second shield region 50B may be curved in an arc shape toward the second main surface 4.

[0327] The inclination angle (absolute value) of the sidewall (long side) of the second shield region 50B relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0328] The second shield region 50B has a depth greater than the depth of the second region 26 and a bottom located closer to the first layer 6 than the bottom of the second region 26. The second shield region 50B may have a depth less than the depth of the second region 26 and a bottom located closer to the first main surface 3 than the bottom of the second region 26.

[0329] The depth of the second shield region 50B may be approximately equal to the depth of the first shield region 50A. Of course, the depth of the second shield region 50B may be greater or less than the depth of the first shield region 50A. The depth of the second shield region 50B is greater than the depth of the gate structure 15. The depth of the shield region 50B may be less than the depth of the gate structure 15.

[0330] The depth of second shield region 50B may be greater than 0 μm and less than or equal to 25 μm. The depth of second shield region 50B may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0331] The second shield region 50B on the other side is connected to the plurality of first shield regions 50A, similar to the second shield region 50B on one side, so that the plurality of shield regions 50 are formed in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 8 (the plurality of gate structures 15).

[0332] The second shield region 50B may be applied to the second layout example (see FIGS. 21 and 22). That is, a plurality of first shield regions 50A may be arranged at intervals in the first direction X, and a plurality of second shield regions 50B may be arranged at intervals in the second direction Y. In this case, a plurality of annular shield regions 50 surrounding the active region 8 (a plurality of gate structures 15) may be composed of a plurality of first shield regions 50A and a plurality of second shield regions 50B.

[0333] The second shield region 50B may be applied to a third layout example (see FIG. 23 ). That is, the second shield region 50B may have a bottom wall located within the first layer 6.

[0334] As described above, semiconductor device 1B may include chip 2, p-type first region 25, multiple n-type second regions 26, and shield region 50. Chip 2 may have first main surface 3. First region 25 may extend in a first direction X along first main surface 3 at a peripheral surface layer portion of first main surface 3. Multiple second regions 26 may extend in first direction X on both sides of first region 25 at a peripheral surface layer portion of first main surface 3.

[0335] The shield region 50 may divide at least a part of the first region 25 into a region on the edge side of the chip 2 and a region on the inner side of the chip 2 in the peripheral surface layer portion of the first main surface 3. In this embodiment, the shield region 50 has insulating properties.

[0336] This configuration provides a semiconductor device 1B with a novel layout. In this semiconductor device 1B, when a low potential (e.g., source potential) is applied to the first region 25 and a high potential (e.g., drain potential) is applied to the second region 26, a depletion layer spreads from the first region 25. When the depletion layer reaches the edge of the chip 2, carriers are generated from the rough portion at the edge of the chip 2, causing a leakage current through the first region 25.

[0337] In this regard, according to the configuration of the semiconductor device 1B, the depletion layer that spreads from the first region 25 in the region on the edge side of the chip 2 is suppressed by the shield region 50. In addition, the leakage current path of carriers generated from the edge of the chip 2 is blocked by the shield region 50. In other words, the shield region 50 restricts the movement of carriers from the edge of the chip 2 to the inner part of the chip 2 via the first region 25. This reduces the leakage current via the first region 25, improving the electrical characteristics.

[0338] The chip 2 may include SiC. This configuration provides a semiconductor device 1B as a novel SiC semiconductor device. The electrical characteristics of this semiconductor device 1B are appropriately improved due to the physical properties of SiC. Since SiC semiconductor devices are used in a relatively high voltage environment, the effect of suppressing leakage current by the shield region 50 is effective.

[0339] The shield region 50 may have a trench isolation structure. The shield region 50 may include a shield trench 51 and a shield insulator 53. The shield trench 51 may be formed in the first main surface 3. The shield insulator 53 may be buried in the shield trench 51. With this configuration, the leakage current path can be appropriately blocked by the trench isolation structure.

[0340] The shield region 50 may have a shield insulating film 52. The shield insulating film 52 may cover the wall surface of the shield trench 51 in the form of a film. In this case, the shield insulator 53 may be embedded in the shield trench 51 via the shield insulating film 52. Of course, the shield insulator 53 may also be embedded directly in the shield trench 51.

[0341] The first region 25 may be exposed from the edge of the chip 2. With this configuration, the semiconductor device 1B has a structure that is prone to depletion at the edge of the chip 2. In this regard, the shield region 50 properly blocks the leakage current path that originates at the edge of the chip 2. In this case, the multiple second regions 26 may be exposed from the edge. The shield region 50 may be formed at intervals from the edge of the chip 2. With this configuration, the leakage current path that originates at the edge of the chip 2 is properly blocked.

[0342] The first region 25 may extend vertically in the thickness direction of the chip 2. The multiple second regions 26 may extend vertically in the thickness direction. The shield region 50 may extend vertically in the thickness direction. According to this configuration, in a configuration in which a depletion layer spreads from the vertically extending first region 25 in the horizontal direction along the first main surface 3, depletion at the end of the chip 2 is appropriately suppressed by the shield region 50. In addition, a leakage current path originating from the end of the chip 2 is appropriately blocked by the vertically extending shield region 50.

[0343] The shield region 50 may extend in the second direction Y along the first main surface 3 and intersect with the first region 25. The shield region 50 may cross the first region 25 in the second direction Y and have portions that contact multiple second regions 26. With these configurations, the shield region 50 intersects with the direction in which the leakage current flows, thereby appropriately blocking the leakage current path.

[0344] A plurality of first regions 25 may be formed in the surface layer of the peripheral edge of the first main surface 3. In this case, one or more shield regions 50 may separate at least a portion of the plurality of first regions 25 from the edge of the chip 2. According to this configuration, the leakage current path via the plurality of first regions 25 is appropriately blocked by the shield regions 50.

[0345] The semiconductor device 1B may include an active region 8 and an outer region 9. The active region 8 may be provided in an inner portion of the chip 2. The outer region 9 may be provided in a peripheral portion of the chip 2. In this case, the first region 25 may be formed in both the active region 8 and the outer region 9. The plurality of second regions 26 may be formed in both the active region 8 and the outer region 9.

[0346] The shield region 50 may be formed in the outer region 9. According to this configuration, the leakage current from the outer region 9 to the active region 8 is appropriately blocked by the shield region 50. This improves the reliability (electrical characteristics) of the active region 8.

[0347] The shield region 50 may have a facing portion facing the active region 8 in the first direction X and a non-facing portion not facing the active region 8 in the first direction X. With this configuration, the leakage current reaching the active region 8 is appropriately blocked at both the facing portion and the non-facing portion of the shield region 50.

[0348] At least one first region 25 may extend in the first direction X in the outer region 9 and face the active region 8 in the second direction Y. In this case, at least one second region 26 may extend in the first direction X in the outer region 9 following the extension direction of the first region 25 and face the active region 8 in the second direction Y.

[0349] According to this configuration, the second region 26 arranged in the region on the second direction Y side of the active region 8 functions as a shield region (30). This allows the second region 26 to block leakage current from the end of the chip 2 in the second direction Y.

[0350] The shield region 50 may have a portion connected to the first region 25, which has a portion facing the active region 8 in the second direction Y. The shield region 50 may have a portion connected to the second region 26, which has a portion facing the active region 8 in the second direction Y.

[0351] The semiconductor device 1B may include a transistor structure formed in the active region 8. This configuration suppresses leakage current flowing into the transistor structure, improving the reliability (electrical characteristics) of the transistor structure. The transistor structure may have a trench-type gate structure 15.

[0352] The semiconductor device 1B may include a p-type outer well region 23. The outer well region 23 may be formed in a surface layer portion of the first main surface 3 along the active region 8, and may separate the active region 8 from the outer region 9. In this case, the first region 25 may be electrically connected to the outer well region 23. With this configuration, the leakage current path from the end of the chip 2 to the outer well region 23 can be appropriately blocked by the shield region 50.

[0353] The chip 2 may have a stacked structure including an n-type first layer 6 (first semiconductor layer) and an n-type second layer 7 (second semiconductor layer), and may have a first main surface 3 formed by the second layer 7. The first region 25 may be formed in the second layer 7. The plurality of second regions 26 may be formed in the second layer 7. The shield region 50 may be formed in the second layer 7. With this configuration, the movement of carriers from the end of the chip 2 to the interior of the chip 2 via the first region 25 in the second layer 7 can be appropriately blocked by the shield region 50.

[0354] The first region 25 may be formed in the second layer 7 at a distance from the first layer 6. The second region 26 may be formed in the second layer 7 at a distance from the first layer 6. The shielding region 50 may be formed in the second layer 7 at a distance from the first layer 6. The first region 25 may have a portion connected to the first layer 6. The second region 26 may have a portion connected to the second layer 7. The shielding region 50 may have a portion connected to the second layer 7.

[0355] The semiconductor device 1B may include a gate wiring 32. The gate wiring 32 may be formed at a distance from the shield region 50 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate wiring 32 on the shield region 50 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0356] The semiconductor device 1B may include a source electrode 40. The source electrode 40 may be disposed on the first main surface 3 and electrically connected to the first region 25. The source electrode 40 may be formed at a distance from the shield region 50 on the inward side of the first main surface 3. With this configuration, the electrical influence of the source electrode 40 on the shield region 50 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0357] Semiconductor device 1B may include source finger electrodes 43. Source finger electrodes 43 may be formed at intervals from shield region 50 on the inward side of first main surface 3. With this configuration, the electrical influence of source finger electrodes 43 on shield region 50 is reduced, and degradation of the function of shield region 60 is appropriately suppressed.

[0358] The semiconductor device 1B may include a gate electrode 44. The gate electrode 44 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate electrode 44 may be formed at a distance from the shield region 50 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate electrode 44 on the shield region 50 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0359] The semiconductor device 1B may include a gate finger electrode 45. The gate finger electrode 45 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate finger electrode 45 may be formed at a distance from the shield region 50 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate finger electrode 45 on the shield region 50 is reduced, and degradation of the function of the shield region 60 is appropriately suppressed.

[0360] The semiconductor device 1B may have a drain electrode 46. The drain electrode 46 may be disposed on the second main surface 4 and electrically connected to the second region 26. The drain electrode 46 may face the shield region 50 in the thickness direction.

[0361] The semiconductor device 1B may include a main surface insulating film 31 that covers the shield region 50 on the first main surface 3. According to this configuration, the main surface insulating film 31 reduces the electrical influence on the shield region 50.

[0362] The semiconductor device 1B may include an interlayer film 33 that covers the shield region 50 on the first main surface 3. The interlayer film 33 may cover the shield region 50 via the main surface insulating film 31. According to this configuration, the electrical influence on the shield region 50 is reduced by the interlayer film 33.

[0363] A conductor (e.g., polysilicon or metal) does not need to be disposed on the portion of the interlayer film 33 (main surface insulating film 31) that covers the shield region 50. With this configuration, the electrical influence on the shield region 50 is appropriately reduced.

[0364] Fig. 25 is a plan view showing a layout example of a surface layer portion of a first main surface 3 of a semiconductor device 1C according to a third embodiment. Fig. 26 is an enlarged plan view showing a peripheral surface layer portion according to the first layout example. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 26.

[0365] The semiconductor device 1C includes, in the peripheral surface layer portion, at least one (multiple in this embodiment) high-resistance shield region 60 instead of the shield region 30. The multiple shield regions 60 include one or more (one in this embodiment) shield regions 60 on one side (the second end 5B side) and one or more (one in this embodiment) shield regions 60 on the other side (the fourth end 5D side).

[0366] The other shield region 60 has the same configuration as the one shield region 60 except for the location. The configuration of the one shield region 60 will be specifically described below. The configuration of the other shield region 60 can be obtained by replacing "second end 5B" with "fourth end 5D" in the following description.

[0367] The shield region 60 has a resistance value higher than the resistance value of the plurality of first regions 25. The resistance value of the shield region 60 is also higher than the resistance value of the plurality of second regions 26. In other words, the resistance value of the shield region 60 is higher than the resistance value of the second layer 7.

[0368] In this embodiment, the shield region 60 includes crystal defects introduced into the second layer 7 in the peripheral surface layer portion, and has a trap level that captures carriers. The shield region 60 has a recombination center density higher than the recombination center density of the plurality of first regions 25 and the recombination center density of the plurality of second regions 26, and captures and eliminates carriers traveling from the second end 5B of the chip 2 toward the inner portion of the chip 2.

[0369] For example, the crystal defect density of the shield region 60 is higher than the p-type impurity concentration of the first region 25. For example, the crystal defect density of the shield region 60 is higher than the n-type impurity concentration of the second region 26 (second layer 7). The crystal defect density of the shield region 60 is 1×10 １４ cm －３ 1x10 or more ２２ cm －３ It may be the following:

[0370] The crystal defect density of the shield region 60 is 1×10 １４ cm －３ 1x10 or more １５ cm －３ Below, 1 x 10 １５ cm －３ 1x10 or more １６ cm －３ Below, 1 x 10 １６ cm －３ 1x10 or more １７ cm －３ Below, 1 x 10 １７ cm －３ 1x10 or more １８ cm －３ Below, 1 x 10１８ cm －３ 1x10 or more １９ cm －３ Below, 1 x 10 １９ cm －３ 1x10 or more ２０ cm －３ Below, 1 x 10 ２０ cm －３ 1x10 or more ２１ cm －３ Below, and 1 x 10 ２１ cm －３ 1x10 or more ２２ cm －３ It may have a value that falls within at least one of the following ranges:

[0371] For example, the shield region 60 may be formed by irradiating the second layer 7 with charged particles to introduce crystal defects caused by the charged particles into the second layer 7. For example, the charged particles may include at least one of protons (H+), helium (He), helium 3 (3He++), helium 4 (4He++), argon (Ar), and an electron beam. Protons are an example of the first heavy particle, and helium 3 and helium 4 are examples of the second heavy particle.

[0372] Of course, the charged particles may contain either or both of a trivalent element and a pentavalent element. In other words, the shield region 60 may have n-type conductivity or p-type conductivity as long as it has a trap level that captures carriers moving from the second end 5B of the chip 2 toward the inside of the chip 2.

[0373] The shield region 60 is formed in the region between the second end 5B and the active region 8. Specifically, the shield region 60 is formed in the region between the second end 5B and the outer well region 23. The shield region 60 is formed at a distance from the second end 5B on the outer well region 23 side (active region 8 side), and is formed at a distance from the outer well region 23 (active region 8) on the second end 5B side.

[0374] The shield region 60 is formed in a region overlapping at least a portion of at least one first region 25, and divides the at least one first region 25 into a first portion 25a on the peripheral edge side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2. The shield region 60 restricts movement of the carrier in the first direction X from the first portion 25a to the second portion 25b.

[0375] The shield region 60 extends in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The shield region 60 has portions that cross at least one first region 25 in the second direction Y and contact multiple second regions 26 adjacent to each other in the second direction Y.

[0376] In this embodiment, the shield region 60 crosses the multiple first regions 25 and the multiple second regions 26 in the second direction Y. That is, the shield region 60 divides the multiple first regions 25 into first portions 25a on the peripheral side (second end 5B side) of the chip 2 and second portions 25b on the inner side of the chip 2. The shield region 60 also divides the multiple second regions 26 into first portions 26a on the peripheral side (second end 5B side) of the chip 2 and second portions 26b on the inner side of the chip 2.

[0377] Specifically, the shield region 60 separates the first portion 25 a and the second portion 25 b in the region between the plurality of second regions 26, and restricts the movement of carriers from the first portion 25 a to the second portion 25 b in the first direction X. The shield region 60 also separates the first portion 26 a and the second portion 26 b in the region between the plurality of first regions 25.

[0378] The shield region 60 is formed in a region facing the active region 8 (plurality of gate structures 15) at least in the first direction X. In this embodiment, the shield region 60 has a facing portion facing the active region 8 in the first direction X, and a non-facing portion that extends from the facing portion toward the periphery of the first main surface 3 and does not face the active region 8 in the first direction X.

[0379] In this embodiment, the shielding region 60 is formed in a strip shape extending from the first end 5A to the third end 5C, and is exposed from both the first end 5A and the third end 5C. The shielding region 60 may be formed spaced apart from either or both of the first end 5A and the third end 5C.

[0380] The shield region 60 may have a width greater than the width of the first region 25. The width of the shield region 60 may be smaller than the width of the first region 25. The width of the shield region 60 may be greater than the width of the second region 26. The width of the shield region 60 may be smaller than the width of the second region 26. The width of the shield region 60 may be greater than the width of the gate structure 15. The width of the shield region 60 may be smaller than the width of the gate structure 15.

[0381] The width of the shield region 60 may be greater than 0 μm and less than or equal to 10 μm. The width of the shield region 60 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0382] The shield region 60 is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 across a part of the second layer 7. Of course, the shield region 60 may traverse the first layer 6 and the second layer 7 and have its bottom located within the first layer 6.

[0383] The shield region 60 has a depth greater than the depth of the second region 26, and has a bottom located closer to the first layer 6 than the bottom of the second region 26. The shield region 60 may have a depth less than the depth of the second region 26, and may have a bottom located closer to the first main surface 3 than the bottom of the second region 26. The depth of the shield region 60 is greater than the depth of the gate structure 15. The depth of the shield region 60 may be smaller than the depth of the gate structure 15.

[0384] The depth of the shield region 60 may be greater than 0 μm and less than or equal to 25 μm. The depth of the shield region 60 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0385] The shield region 60 may be formed with an end spacing of more than 0 μm and not more than 200 μm from the second end 5B. The end spacing may have a value belonging to at least one of the ranges of more than 0 μm and not more than 5 μm, 5 μm to 10 μm, 10 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, and 175 μm to 200 μm.

[0386] As in the case of the semiconductor device 1A, the aforementioned main surface insulating film 31 covers the first main surface 3 in the outer region 9. Specifically, the main surface insulating film 31 covers the plurality of first regions 25, the plurality of second regions 26, and the plurality of shield regions 60 in the outer region 9.

[0387] The main surface insulating film 31 is continuous with the first to fourth end portions 5A to 5D. The main surface insulating film 31 may be formed at intervals inward from the first to fourth end portions 5A to 5D, exposing the peripheral edge portion of the first main surface 3. The main surface insulating film 31 may have a thickness substantially equal to that of the plurality of shield insulating films 52.

[0388] As in the case of the semiconductor device 1A, the interlayer film 33 described above covers the main surface insulating film 31 in a film form in the outer region 9. Specifically, the interlayer film 33 covers the first regions 25, the second regions 26, and the shield regions 60 in the outer region 9 via the main surface insulating film 31.

[0389] The interlayer film 33 is continuous with the first to fourth end portions 5A to 5D. The outer edge portion of the interlayer film 33 is formed at a distance inward from the first to fourth end portions 5A to 5D, and may expose either or both of the peripheral portion of the first main surface 3 and the main surface insulating film 31.

[0390] Fig. 29 is an enlarged plan view showing a peripheral surface layer portion according to the second layout example. Fig. 30 is a cross-sectional view taken along line XXX-XXX shown in Fig. 29. Referring to Figs. 29 and 30, in this embodiment, the multiple shield regions 60 include multiple shield regions 60 on one side (the second end 5B side) and multiple shield regions 60 on the other side (the fourth end 5D side). The configuration of one of the multiple shield regions 60 will be described below.

[0391] The multiple shield regions 60 are formed at intervals in the first direction X in a region between the second end 5B and the active region 8. Specifically, the multiple shield regions 60 are formed at intervals in the first direction X in a region between the second end 5B and the outer well region 23. The multiple shield regions 60 are formed at intervals from the second end 5B on the outer well region 23 side (active region 8 side), and are formed at intervals from the outer well region 23 (active region 8) on the second end 5B side.

[0392] The multiple shield regions 60 are each formed in an area that overlaps at least a portion of at least one first region 25, and divide the at least one first region 25 into a first portion 25a on the peripheral side (second end 5B side) of the chip 2 and a second portion 25b on the inner side of the chip 2.

[0393] The multiple shield regions 60 each extend in a strip shape in the second direction Y along the first main surface 3 so as to intersect with at least one first region 25. The multiple shield regions 60 each have a portion that crosses at least one first region 25 in the second direction Y and contacts multiple second regions 26 adjacent to them in the second direction Y.

[0394] In this embodiment, the multiple shield regions 60 cross the multiple first regions 25 and the multiple second regions 26 in the second direction Y. That is, the multiple shield regions 60 divide the multiple first regions 25 into first portions 25 a and second portions 25 b, and divide the multiple second regions 26 into first portions 26 a and second portions 26 b.

[0395] The multiple shield regions 60 are formed in regions facing the active region 8 (the multiple gate structures 15) at least in the first direction X. In this embodiment, the multiple shield regions 60 have facing portions facing the active region 8 in the first direction X and non-facing portions that extend from the facing portions toward the periphery of the first main surface 3 and do not face the active region 8 in the first direction X.

[0396] In this embodiment, the multiple shielding regions 60 are formed in a strip shape extending from the first end 5A to the third end 5C, and are exposed from both the first end 5A and the third end 5C. The multiple shielding regions 60 may be formed at intervals from either or both of the first end 5A and the third end 5C.

[0397] The spacing between the shield regions 60 may be greater or smaller than the spacing between the first regions 25. The spacing between the shield regions 60 may be greater or smaller than the spacing between the second regions 26. The spacing between the shield regions 60 may be greater or smaller than the spacing between the gate structures 15.

[0398] The spacing between the shield regions 60 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the shield regions 60 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0399] 31 is an enlarged plan view showing the peripheral surface portion according to the third layout example. Referring to FIG. 31 , the plurality of first regions 25 may penetrate the second layer 7 to reach the first layer 6. In this embodiment, the plurality of first regions 25 have bottoms located in the surface portion of the first layer 6 and are electrically connected to the first layer 6 and the second layer 7. The plurality of first regions 25 may also penetrate the second layer 7 in the inner surface portion to reach the first layer 6.

[0400] Although specific illustration is omitted, in this embodiment, the second regions 26 extend in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6 in the regions between the first regions 25. The second regions 26 have upper ends exposed from the first main surface 3 and lower ends connected to the first layer 6.

[0401] In this embodiment, the shield region 60 extends in a pillar shape across the entire thickness range between the first main surface 3 and the first layer 6. In this embodiment, the shield region 60 penetrates the second layer 7 and has a bottom wall located on the surface of the first layer 6.

[0402] 32 is an enlarged plan view showing the peripheral surface layer portion according to layout example 4. Referring to Fig. 32, in this embodiment, the plurality of shield regions 60 includes a plurality of first shield regions 60A arranged in a region on the first direction X side of the active region 8, and a plurality of second shield regions 60B arranged in a region on the second direction Y side of the active region 8.

[0403] The plurality of first shield regions 60A correspond to the shield regions 60 according to the first layout example. The plurality of first shield regions 60A may have the second or third layout example.

[0404] The multiple second shield regions 60B include one or more (one in this embodiment) second shield regions 60B on one side (the side of the first end 5A) and one or more (one in this embodiment) second shield regions 60B on the other side (the side of the third end 5C). The configuration of the second shield region 60B on one side will be described in detail below. The configuration of the second shield region 60B on the other side can be obtained by replacing "first end 5A" with "third end 5C" in the following description.

[0405] The second shield region 60B is formed in a region between the multiple first shield regions 60A and extends in a direction different from the extending direction of the multiple first shield regions 60A. In this embodiment, the second shield region 60B extends in a strip shape in the first direction X. In other words, the second shield region 60B extends in the same direction as the extending direction of the multiple gate structures 15, the multiple first regions 25, and the multiple second regions 26.

[0406] The second shield region 60B is formed in a region facing the active region 8 (plurality of gate structures 15) at least in the second direction Y. In this embodiment, the second shield region 60B has a facing portion facing the active region 8 in the second direction Y, and a non-facing portion that extends from the facing portion toward the periphery of the first main surface 3 and does not face the active region 8 in the second direction Y.

[0407] In this embodiment, the second shield region 60B is formed at a distance from the second end 5B and the fourth end 5D in the first direction X. Of course, the second shield region 60B may be exposed from either or both of the second end 5B and the fourth end 5D. The second shield region 60B is connected to a plurality of first shield regions 60A.

[0408] The second shield region 60B has a width approximately equal to that of the first shield region 60A. Of course, the width of the second shield region 60B may be larger or smaller than that of the first shield region 60A. The width of the second shield region 60B may be larger than that of the gate structure 15. The width of the second shield region 60B may be smaller than that of the gate structure 15.

[0409] The second shield region 60B may have a width greater than the width of the first region 25. The width of the second shield region 60B may be smaller than the width of the first region 25. The width of the second shield region 60B may be greater than the width of the second region 26. The width of the second shield region 60B may be smaller than the width of the second region 26.

[0410] The width of second shield region 60B may be greater than 0 μm and less than or equal to 10 μm. The width of second shield region 60B may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0411] The second shield region 60B is formed at a distance from the bottom of the second layer 7 toward the first main surface 3, and faces the first layer 6 across a part of the second layer 7. The second shield region 60B has a depth greater than the depth of the second region 26, and has a bottom located closer to the first layer 6 than the bottom of the second region 26. The second shield region 60B may have a depth less than the depth of the second region 26, and have a bottom located closer to the first main surface 3 than the bottom of the second region 26.

[0412] The depth of the second shield region 60B may be approximately equal to the depth of the first shield region 60A. Of course, the depth of the second shield region 60B may be greater or less than the depth of the first shield region 60A. The depth of the second shield region 60B is greater than the depth of the gate structure 15. The depth of the shield region 60B may be less than the depth of the gate structure 15.

[0413] The depth of second shield region 60B may be greater than 0 μm and less than or equal to 25 μm. The depth of second shield region 60B may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, 12.5 μm to 15 μm, 15 μm to 17.5 μm, 17.5 μm to 20 μm, 20 μm to 22.5 μm, and 22.5 μm to 25 μm.

[0414] The second shield region 60B on the other side is connected to the plurality of first shield regions 60A, similar to the second shield region 60B on one side, so that the plurality of shield regions 60 are formed in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 8 (the plurality of gate structures 15).

[0415] The second shield region 60B may be applied to a second layout example (see FIGS. 29 and 30 ). That is, a plurality of first shield regions 60A may be arranged at intervals in the first direction X, and a plurality of second shield regions 60B may be arranged at intervals in the second direction Y. In this case, a plurality of annular shield regions 60 surrounding the active region 8 (a plurality of gate structures 15) may be composed of a plurality of first shield regions 60A and a plurality of second shield regions 60B.

[0416] The second shield region 60B may be applied to a third layout example (see FIG. 31 ). That is, the second shield region 60B may have a bottom wall located within the first layer 6.

[0417] As described above, the semiconductor device 1C may include the chip 2, the p-type first region 25, the plurality of n-type second regions 26, and the shield region 60. The chip 2 may have a first main surface 3. The first region 25 may extend in a first direction X along the first main surface 3 at a peripheral surface layer portion of the first main surface 3. The plurality of second regions 26 may extend in the first direction X on both sides of the first region 25 at a peripheral surface layer portion of the first main surface 3.

[0418] The shield region 60 may divide at least a part of the first region 25 into a region on the edge side of the chip 2 and a region on the inner side of the chip 2 in the peripheral surface layer portion of the first main surface 3. In this embodiment, the shield region 50 includes a high resistance region.

[0419] This configuration provides a semiconductor device 1C with a novel layout. In this semiconductor device 1C, when a low potential (e.g., source potential) is applied to the first region 25 and a high potential (e.g., drain potential) is applied to the second region 26, a depletion layer spreads from the first region 25. When the depletion layer reaches the edge of the chip 2, carriers are generated from the rough portion at the edge of the chip 2, causing a leakage current through the first region 25.

[0420] In this regard, according to the configuration of the semiconductor device 1C, the depletion layer that spreads from the first region 25 in the region on the edge side of the chip 2 is suppressed by the shield region 60. In addition, the movement of carriers generated from the edge of the chip 2 is restricted by the shield region 60. This reduces the leakage current through the first region 25 and improves the electrical characteristics.

[0421] The shield region 60 may have a trap level due to crystal defects introduced into the chip 2. In this case, the trap level of the shield region 60 is higher than the trap level of the first region 25. The shield region 60 may have a crystal defect density higher than the impurity concentration of the first region 25. According to these configurations, carriers generated from the end of the chip 2 are captured by the shield region 60, and leakage current through the first region 25 is suppressed.

[0422] The chip 2 may include SiC. This configuration provides a semiconductor device 1C as a novel SiC semiconductor device. The electrical characteristics of this semiconductor device 1C are appropriately improved due to the physical properties of SiC. Since SiC semiconductor devices are used in a relatively high voltage environment, the effect of suppressing leakage current by the shield region 60 is effective.

[0423] The first region 25 may be exposed from the edge of the chip 2. With this configuration, the semiconductor device 1C has a structure that is prone to depletion at the edge of the chip 2. In this regard, the shield region 60 appropriately suppresses leakage current originating from the edge of the chip 2. In this case, the multiple second regions 26 may be exposed from the edge. The shield region 60 may be formed at intervals from the edge of the chip 2. With this configuration, leakage current originating from the edge of the chip 2 is appropriately suppressed.

[0424] The first region 25 may extend vertically in the thickness direction of the chip 2. The multiple second regions 26 may extend vertically in the thickness direction. The shield region 60 may extend vertically in the thickness direction. According to this configuration, in a configuration in which a depletion layer spreads from the vertically extending first region 25 in the horizontal direction along the first main surface 3, depletion at the end of the chip 2 is appropriately suppressed by the shield region 60. Furthermore, leakage current originating from the end of the chip 2 is appropriately suppressed by the vertically extending shield region 50.

[0425] The shield region 60 may extend in the second direction Y along the first main surface 3 and intersect with the first region 25. The shield region 60 may cross the first region 25 in the second direction Y and have portions that contact multiple second regions 26. With these configurations, the shield region 60 intersects with the direction in which the leakage current flows, thereby appropriately suppressing the leakage current.

[0426] The plurality of first regions 25 may be formed in the surface layer of the peripheral edge of the first main surface 3. In this case, one or more shield regions 60 may separate at least a portion of the plurality of first regions 25 from the edge of the chip 2. According to this configuration, the shield regions 60 appropriately suppress leakage current passing through the plurality of first regions 25.

[0427] The semiconductor device 1C may include an active region 8 and an outer region 9. The active region 8 may be provided in an inner portion of the chip 2. The outer region 9 may be provided in a peripheral portion of the chip 2. In this case, the first region 25 may be formed in both the active region 8 and the outer region 9. The plurality of second regions 26 may be formed in both the active region 8 and the outer region 9.

[0428] The shield region 60 may be formed in the outer region 9. According to this configuration, the leakage current from the outer region 9 to the active region 8 is appropriately suppressed by the shield region 60. This improves the reliability (electrical characteristics) of the active region 8.

[0429] The shield region 60 may have a facing portion facing the active region 8 in the first direction X and a non-facing portion not facing the active region 8 in the first direction X. With this configuration, leakage current reaching the active region 8 is appropriately suppressed in both the facing portion and the non-facing portion of the shield region 60.

[0430] At least one first region 25 may extend in the first direction X in the outer region 9 and face the active region 8 in the second direction Y. In this case, at least one second region 26 may extend in the first direction X in the outer region 9 following the extension direction of the first region 25 and face the active region 8 in the second direction Y.

[0431] According to this configuration, the second region 26 arranged in the region on the second direction Y side of the active region 8 functions as a shield region (30). This allows the second region 26 to block leakage current from the end of the chip 2 in the second direction Y.

[0432] The shield region 60 may have a portion connected to the first region 25, which has a portion facing the active region 8 in the second direction Y. The shield region 60 may have a portion connected to the second region 26, which has a portion facing the active region 8 in the second direction Y.

[0433] The semiconductor device 1C may include a transistor structure formed in the active region 8. This configuration suppresses leakage current flowing into the transistor structure, improving the reliability (electrical characteristics) of the transistor structure. The transistor structure may have a trench-type gate structure 15.

[0434] The semiconductor device 1C may include a p-type outer well region 23. The outer well region 23 may be formed in a surface layer portion of the first main surface 3 along the active region 8, and may separate the active region 8 from the outer region 9. In this case, the first region 25 may be electrically connected to the outer well region 23. With this configuration, the leakage current path from the end of the chip 2 to the outer well region 23 can be appropriately blocked by the shield region 50.

[0435] The chip 2 may have a stacked structure including an n-type first layer 6 (first semiconductor layer) and an n-type second layer 7 (second semiconductor layer), and may have a first main surface 3 formed by the second layer 7. The first region 25 may be formed in the second layer 7. The plurality of second regions 26 may be formed in the second layer 7. The shield region 60 may be formed in the second layer 7. With this configuration, the movement of carriers from the end of the chip 2 to the interior of the chip 2 via the first region 25 in the second layer 7 can be appropriately suppressed by the shield region 60.

[0436] The first region 25 may be formed in the second layer 7 at a distance from the first layer 6. The second region 26 may be formed in the second layer 7 at a distance from the first layer 6. The shielding region 60 may be formed in the second layer 7 at a distance from the first layer 6. The first region 25 may have a portion connected to the first layer 6. The second region 26 may have a portion connected to the second layer 7. The shielding region 60 may have a portion connected to the second layer 7.

[0437] The semiconductor device 1C may include a gate wiring 32. The gate wiring 32 may be formed at a distance from the shield region 60 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate wiring 32 on the shield region 60 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0438] The semiconductor device 1C may include a source electrode 40. The source electrode 40 may be disposed on the first main surface 3 and electrically connected to the first region 25. The source electrode 40 may be formed at a distance from the shield region 60 on the inward side of the first main surface 3. With this configuration, the electrical influence of the source electrode 40 on the shield region 60 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0439] The semiconductor device 1C may include source finger electrodes 43. The source finger electrodes 43 may be formed at intervals from the shield region 60 on the inward side of the first main surface 3. With this configuration, the electrical influence of the source finger electrodes 43 on the shield region 60 is reduced, and deterioration of the function of the shield region 60 is appropriately suppressed.

[0440] The semiconductor device 1C may include a gate electrode 44. The gate electrode 44 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate electrode 44 may be formed at a distance from the shield region 60 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate electrode 44 on the shield region 60 is reduced, and degradation of the function of the shield region 60 is appropriately suppressed.

[0441] The semiconductor device 1C may include a gate finger electrode 45. The gate finger electrode 45 may be disposed on the first main surface 3 and electrically connected to the gate structure 15. The gate finger electrode 45 may be formed at a distance from the shield region 60 on the inward side of the first main surface 3. With this configuration, the electrical influence of the gate finger electrode 45 on the shield region 60 is reduced, and degradation of the function of the shield region 60 is appropriately suppressed.

[0442] The semiconductor device 1C may have a drain electrode 46. The drain electrode 46 may be disposed on the second main surface 4 and electrically connected to the second region 26. The drain electrode 46 may face the shield region 60 in the thickness direction.

[0443] The semiconductor device 1C may include a main surface insulating film 31 that covers the shield region 60 on the first main surface 3. According to this configuration, the main surface insulating film 31 reduces the electrical influence on the shield region 60.

[0444] The semiconductor device 1C may include an interlayer film 33 that covers the shield region 60 on the first main surface 3. The interlayer film 33 may cover the shield region 60 via the main surface insulating film 31. According to this configuration, the electrical influence on the shield region 60 is reduced by the interlayer film 33.

[0445] A conductor (e.g., polysilicon or metal) does not need to be disposed on the portion of the interlayer film 33 (main surface insulating film 31) that covers the shield region 60. With this configuration, the electrical influence on the shield region 60 is appropriately reduced.

[0446] 33 is a cross-sectional perspective view showing a main portion of a semiconductor device 1D according to the fourth embodiment. Referring to FIG. 33, the semiconductor device 1D has a configuration obtained by modifying the layout of the plurality of first regions 25 and the plurality of second regions 26 in the configuration of the semiconductor device 1A (see FIGS. 1 to 16). Specifically, the plurality of first regions 25 are formed in regions between the plurality of gate structures 15, spaced apart from the plurality of gate structures 15 in the second direction Y.

[0447] In this embodiment, the plurality of first regions 25 each have a portion located on the first main surface 3 side relative to the depth positions of the bottom walls of the plurality of gate structures 15, and a portion located on the bottom side of the second layer 7 relative to the depth positions of the bottom walls of the plurality of gate structures 15. The plurality of first regions 25 are connected to the body region 10 in a region between the plurality of gate structures 15.

[0448] In this embodiment, the plurality of second regions 26 are respectively formed in regions between the plurality of first regions 25, and are respectively connected to corresponding gate structures 15 in a one-to-one correspondence. In this embodiment, the plurality of second regions 26 each have a portion located on the first main surface 3 side with respect to the depth positions of the bottom walls of the plurality of gate structures 15, and a portion located on the bottom side of the second layer 7 with respect to the depth positions of the bottom walls of the plurality of gate structures 15. The plurality of second regions 26 form channels together with the plurality of source regions 20.

[0449] Other structures of the semiconductor device 1D are similar to those of the semiconductor device 1A. The configuration of the semiconductor device 1B (see FIGS. 17 to 24) may be applied to the configuration of the semiconductor device 1D. The configuration of the semiconductor device 1C (see FIGS. 25 to 32) may be applied to the configuration of the semiconductor device 1D.

[0450] 34 is a cross-sectional perspective view showing a main portion of a semiconductor device 1E according to a fifth embodiment. Referring to FIG. 34, the semiconductor device 1E has a configuration in which the layout of the plurality of gate structures 15 in the configuration of the semiconductor device 1A (see FIGS. 1 to 16) is modified. Specifically, the plurality of gate structures 15 are arranged at intervals in the first direction X and extend in a strip shape in the second direction Y.

[0451] In this embodiment, the multiple first regions 25 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple first regions 25 intersect (orthogonal in this embodiment) with the multiple gate structures 15 in the active region 8. Similarly, the multiple second regions 26 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple second regions 26 intersect (orthogonal in this embodiment) with the multiple gate structures 15 in the active region 8.

[0452] Other structures of the semiconductor device 1E are similar to those of the semiconductor device 1A. The configuration of the semiconductor device 1B (see FIGS. 17 to 24) may be applied to the configuration of the semiconductor device 1E. The configuration of the semiconductor device 1C (see FIGS. 25 to 32) may be applied to the configuration of the semiconductor device 1E.

[0453] Fig. 35 is a plan view showing a main part of a semiconductor device 1F according to a sixth embodiment. Fig. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in Fig. 35. Fig. 37 is a cross-sectional perspective view showing a main part of an active region 8. The semiconductor device 1F has a configuration in which the trench gate type transistor structure in the active region 8 of the semiconductor device 1A (see Figs. 1 to 16) is changed to a planar gate type transistor structure.

[0454] The semiconductor device 1F includes a plurality of p-type body regions 10 formed in the active region 8 in a surface layer portion of the first main surface 3. The plurality of body regions 10 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 9. The plurality of body regions 10 are arranged in stripes extending in the first direction X in a plan view.

[0455] That is, the body regions 10 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. The extending direction of the body regions 10 coincides with the off-direction of the SiC single crystal. The body regions 10 are formed in a surface layer portion of the second layer 7 and extend in layers along the first main surface 3.

[0456] The spacing between the plurality of body regions 10 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the body regions 10 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0457] The widths of the body regions 10 may be greater than 0 μm and less than 10 μm. The widths of the body regions 10 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0458] The semiconductor device 1F includes a plurality of n-type source regions 20 formed in the surface layer portions of the plurality of body regions 10. The plurality of source regions 20 are formed at intervals in the second direction Y from both edges of the corresponding body region 10 toward the inner portions of the corresponding body region 10.

[0459] The plurality of source regions 20 are formed at intervals in the second direction Y in the surface layer portion of the corresponding body region 10, and extend in a strip shape in the first direction X. The plurality of source regions 20 may be formed at intervals in the first direction X following the extension direction of the corresponding body region 10.

[0460] The semiconductor device 1F includes a plurality of p-type contact regions 21 formed in regions different from the plurality of source regions 20 in the surface layer portion of the corresponding body region 10. The plurality of contact regions 21 are interposed in regions between the plurality of source regions 20 in the surface layer portion of the corresponding body region 10, and are electrically connected to the body region 10.

[0461] The plurality of contact regions 21 extend in a strip shape along the extension direction of the corresponding body region 10 (source region 20). The plurality of contact regions 21 are formed at intervals from the bottom of the corresponding body region 10 toward the first main surface 3, and face the second layer 7 with a part of the corresponding body region 10 sandwiched therebetween.

[0462] In this embodiment, the contact region 21 has a width less than that of the plurality of source regions 20. The width of the contact region 21 may be greater than that of the plurality of source regions 20. In this embodiment, the plurality of contact regions 21 have a thickness greater than that of the plurality of source regions 20, and have bottoms located closer to the bottom of the body region 10 than the bottoms of the plurality of source regions 20.

[0463] The semiconductor device 1F includes a plurality of n-type surface drift regions 63 formed in a surface layer portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 63 are each made of a part of the second layer 7. Of course, the plurality of surface drift regions 63 may have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 7, or may have an n-type impurity concentration lower than the n-type impurity concentration of the second layer 7.

[0464] The surface drift regions 63 are partitioned into stripes extending in the first direction X in regions between adjacent body regions 10 in the surface portion of the second layer 7. In other words, the surface drift regions 63 are arranged at intervals in the second direction Y and each extend in a strip shape in the first direction X.

[0465] The semiconductor device 1F includes a plurality of p-type channel regions 64 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 64 are partitioned into regions between the plurality of source regions 20 and the plurality of surface drift regions 63 (second layer 7) in the surface layer portions of the plurality of body regions 10. The plurality of channel regions 64 form a current path extending horizontally along the first main surface 3.

[0466] The semiconductor device 1F includes a plurality of planar gate structures 65 (planar electrode type) arranged on the first main surface 3 in the active region 8. The plurality of gate structures 65 are arranged in stripes extending in the first direction X. That is, the plurality of gate structures 65 are arranged at intervals in the second direction Y and each extend in a strip shape in the first direction X. The extension direction of the plurality of gate structures 65 coincides with the off-direction of the SiC single crystal.

[0467] The plurality of gate structures 65 are each disposed on at least one channel region 64 (periphery of the body region 10) and control inversion and non-inversion of the channel region 64. The plurality of gate structures 65 cover at least one peripheral portion of the body region 10, at least one source region 20, and one surface drift region 63, respectively.

[0468] In this embodiment, the plurality of gate structures 65 extend across the peripheries of two adjacent body regions 10 and cover the plurality of channel regions 64. Specifically, the plurality of gate structures 65 extend across one and the other body regions 10 and cover the two source regions 20, one surface drift region 63, and two channel regions 64.

[0469] Each of the multiple gate structures 65 has a stacked structure including a planar insulating film 66 and a planar electrode 67. The planar insulating film 66 may be referred to as a "gate insulating film," and the planar electrode 67 may be referred to as a "gate electrode" or a "planar gate electrode."

[0470] The planar insulating film 66 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 66 has a single-layer structure made of a silicon oxide film. The planar insulating film 66 preferably includes a silicon oxide film containing an oxide of the second layer 7.

[0471] The planar insulating film 66 covers the first main surface 3 in a film-like shape. The planar insulating film 66 extends in a strip shape in the second direction Y. The planar insulating film 66 is disposed on at least one channel region 64 (periphery of the body region 10). The planar insulating film 66 covers the periphery of at least one body region 10, at least one source region 20, and one surface drift region 63.

[0472] In this embodiment, the planar insulating film 66 extends across the peripheries of two adjacent body regions 10. Specifically, the planar insulating film 66 extends across one and the other body regions 10, and covers two source regions 20, one surface drift region 63, and two channel regions 64.

[0473] The planar electrode 67 is disposed on the planar insulating film 66. A gate potential as a control potential is applied to the planar electrode 67. The planar electrode 67 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0474] The planar electrode 67 covers the first main surface 3 in a film form via the planar insulating film 66, and faces at least one channel region 64 (peripheral portion of the body region 10). The planar electrode 67 extends in a strip shape in the second direction Y. In this embodiment, the planar electrode 67 is formed at a distance inward from the peripheral edge of the planar insulating film 66, exposing the peripheral portion of the planar insulating film 66.

[0475] The planar electrode 67 covers the periphery of at least one body region 10, at least one source region 20, and one surface drift region 63 via the planar insulating film 66. The planar electrode 67 spans the peripheries of two adjacent body regions 10. Specifically, the planar electrode 67 spans one and the other body regions 10 and faces two source regions 20, one surface drift region 63, and two channel regions 64 via the planar insulating film 66.

[0476] The semiconductor device 1F includes the above-described plurality of first regions 25 formed in the active region 8 (inner surface layer portion) and the outer region 9 (peripheral surface layer portion). The plurality of first regions 25 may have a layout according to the first embodiment (see FIGS. 1 to 16), a layout according to the second embodiment (see FIGS. 17 to 24), or a layout according to the third embodiment (see FIGS. 25 to 32).

[0477] The first regions 25 extend in a strip shape in the first direction X in the inner surface layer portion, and are formed at intervals in the second direction Y. In this embodiment, the first regions 25 are formed in regions below the body regions 10 in the active region 8. In this embodiment, the first regions 25 are formed in regions overlapping the body regions 10.

[0478] Specifically, the first regions 25 are formed at intervals approximately equal to the intervals between the body regions 10, and are formed in a one-to-one correspondence with the body regions 10. The first regions 25 are each formed in the shape of a pillar that extends vertically from the bottom of the body regions 10 toward the bottom of the second layer 7.

[0479] The first regions 25 are formed at intervals from the bottom of the second layer 7 toward the bottom of the corresponding body region 10, and face the first layer 6 across a part of the second layer 7. Of course, the first regions 25 may have a portion located within the first layer 6. The first regions 25 are each connected to the corresponding body region 10.

[0480] The semiconductor device 1F includes the above-mentioned plurality of second regions 26 formed in the active region 8 (inner surface layer portion) and the outer region 9 (peripheral surface layer portion). The plurality of second regions 26 may have a layout according to the first embodiment (see FIGS. 1 to 16), a layout according to the second embodiment (see FIGS. 17 to 24), or a layout according to the third embodiment (see FIGS. 25 to 32).

[0481] The second regions 26 extend in a strip shape in the first direction X in the inner surface layer portion, and are formed at intervals in the second direction Y. In this embodiment, the second regions 26 are formed in regions that overlap the surface drift regions 63. Specifically, the second regions 26 are formed at intervals that are approximately equal to the intervals between the body regions 10.

[0482] The second regions 26 are formed in one-to-one correspondence with the surface drift regions 63. The second regions 26 are formed in the shape of pillars extending vertically from the surface drift regions 63 toward the bottom of the second layer 7. The second regions 26 are connected to the corresponding surface drift regions 63.

[0483] In this embodiment, the second regions 26 have a depth corresponding to the thickness of the second layer 7. Of course, the second regions 26 may be formed at intervals from the bottom of the second layer 7 toward the bottom of the corresponding body region 10. The second regions 26 may have portions located within the first layer 6.

[0484] The semiconductor device 1F includes a plurality of shield regions 30 according to the first embodiment formed in the outer region 9 (peripheral surface layer portion) (see FIGS. 1 to 16). The semiconductor device 1F may also include the shield regions 30 according to the first to third layout examples.

[0485] The semiconductor device 1F may include a plurality of shield regions 50 according to the second embodiment (see FIGS. 17 to 24). The semiconductor device 1F may include a plurality of shield regions 50 according to the first to fourth layout examples. The semiconductor device 1F may include a plurality of shield regions 60 according to the third embodiment (see FIGS. 25 to 32). The semiconductor device 1F may include a shield region 60 according to the first to fourth layout examples.

[0486] The semiconductor device 1F includes the aforementioned main surface insulating film 31. The main surface insulating film 31 covers the first main surface 3 in the active region 8 in a film form and is connected to the plurality of planar insulating films 66. The main surface insulating film 31 is formed integrally with the plurality of planar insulating films 66, and together with the plurality of planar insulating films 66 form one insulating film 17.

[0487] The semiconductor device 1F includes the aforementioned gate wiring 32 (not shown). In this embodiment, the gate wiring 32 is mechanically and electrically connected to a plurality of planar electrodes 67 (gate structures 65). In this embodiment, the gate wiring 32 is integrally formed with the plurality of planar electrodes 67.

[0488] The semiconductor device 1F includes the above-described interlayer film 33. The interlayer film 33 covers the plurality of gate structures 65 in the active region 8. Specifically, the interlayer film 33 covers the plurality of planar insulating films 66 and the plurality of planar electrodes 67, and electrically insulates the plurality of planar electrodes 67.

[0489] The semiconductor device 1F includes the aforementioned source openings 34, the aforementioned gate openings 35, and the aforementioned outer openings 36. The source openings 34 are formed in a one-to-one correspondence in regions between the planar electrodes 67, and extend in strip shapes in the first direction X following the extension direction of the planar electrodes 67. The source openings 34 penetrate the planar insulating film 66 and the interlayer film 33, and expose the source regions 20 and the contact regions 21, respectively.

[0490] The source openings 34 may be formed in a one-to-many correspondence in the region between the planar electrodes 67. In this case, the source openings 34 may be formed at intervals along the extension direction of the planar electrodes 67. In this case, the source openings 34 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in a plan view.

[0491] The semiconductor device 1F includes the aforementioned source electrode 40, source finger electrodes 43, gate electrode 44, gate finger electrodes 45, and drain electrode 46. In this embodiment, the source electrode 40 is disposed on the interlayer film 33 and extends into the plurality of source openings 34 from above the interlayer film 33. The source electrode 40 is electrically connected to the plurality of body regions 10, the plurality of source regions 20, and the plurality of contact regions 21 in the plurality of source openings 34.

[0492] 38 is a cross-sectional perspective view showing a main portion of a semiconductor device 1G according to a seventh embodiment. Referring to FIG. 38, the semiconductor device 1G has a configuration in which the layout of the active regions 8 of the semiconductor device 1F is modified. Specifically, the body regions 10 are arranged at intervals in the first direction X and extend in a strip shape in the second direction Y.

[0493] The source regions 20 are arranged at intervals in the first direction X in the surface layer portion of the corresponding body region 10, and each extend in a strip shape in the second direction Y. The contact regions 21 are arranged at intervals in the first direction X in the surface layer portion of the corresponding body region 10, and each extend in a strip shape in the second direction Y. The gate structures 65 are arranged at intervals in the first direction X, and each extend in a strip shape in the second direction Y.

[0494] The multiple first regions 25 extend in strips in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple first regions 25 intersect (orthogonal in this embodiment) the multiple body regions 10 and the multiple gate structures 65 in the active region 8.

[0495] The second regions 26 extend in strips in the first direction X and are arranged at intervals in the second direction Y. That is, the second regions 26 intersect (orthogonal in this embodiment) the body regions 10 and the gate structures 65 in the active region 8.

[0496] Fig. 39 is a plan view showing a semiconductor device 1H according to an eighth embodiment. Fig. 40 is a cross-sectional view taken along line XL-XL shown in Fig. 39. Fig. 41 is a plan view showing an example layout of a surface layer portion of the first main surface 3. With reference to Figs. 39 to 41, the semiconductor device 1H is a semiconductor rectifier having a diode structure as an example of a device structure (functional device). The diode structure has a vertical structure.

[0497] Similar to the semiconductor device 1A, the semiconductor device 1H includes a chip 2, a first layer 6, a second layer 7, an active region 8, an outer region 9, and an outer well region 23. In this embodiment, the active region 8 includes a device structure (diode structure) and is a region where an output current (forward current) is generated. In this embodiment, the outer region 9 does not include a device structure (diode structure).

[0498] The outer well region 23 is formed in the outer region 9 at a distance from the periphery of the first main surface 3. The outer well region 23 extends in a strip shape along the active region 8. The outer well region 23 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the outer well region 23 is formed in the shape of an endless polygonal ring (for example, a quadrangular ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the inner portion of the first main surface 3.

[0499] The semiconductor device 1H includes a plurality of first regions 25 formed in the active region 8 (inner surface layer portion) and the outer region 9 (peripheral surface layer portion). The plurality of first regions 25 may have a layout according to the first embodiment (see FIGS. 1 to 16), a layout according to the second embodiment (see FIGS. 17 to 24), or a layout according to the third embodiment (see FIGS. 25 to 32).

[0500] The semiconductor device 1H includes a plurality of second regions 26 formed in the active region 8 (inner surface layer portion) and the outer region 9 (peripheral surface layer portion). The plurality of second regions 26 may have a layout according to the first embodiment (see FIGS. 1 to 16), a layout according to the second embodiment (see FIGS. 17 to 24), or a layout according to the third embodiment (see FIGS. 25 to 32).

[0501] The semiconductor device 1H includes a plurality of shield regions 30 according to the first embodiment formed in the outer region 9 (peripheral surface layer portion) (see FIGS. 1 to 16). The semiconductor device 1H may also include the shield regions 30 according to the first to third layout examples.

[0502] The semiconductor device 1H may include a plurality of shield regions 50 according to the second embodiment (see FIGS. 17 to 24). The semiconductor device 1H may include a plurality of shield regions 50 according to the first to fourth layout examples. The semiconductor device 1H may include a plurality of shield regions 60 according to the third embodiment (see FIGS. 25 to 32). The semiconductor device 1H may include a plurality of shield regions 60 according to the first to fourth layout examples.

[0503] The semiconductor device 1H includes the above-described interlayer film 33 that selectively covers the first main surface 3. The interlayer film 33 selectively covers the first main surface 3 in the outer region 9. The interlayer film 33 covers the outer edge of the outer well region 23 in the outer region 9, leaving the inner edge of the outer well region 23 exposed.

[0504] The interlayer film 33 covers the plurality of first regions 25, the plurality of second regions 26, and the plurality of shield regions 30. In this embodiment, the interlayer film 33 is continuous with the periphery of the first main surface 3. Of course, the interlayer film 33 may be formed at a distance from the periphery of the first main surface 3, with the second layer 7 exposed from the periphery of the first main surface 3.

[0505] The interlayer film 33 has a contact opening 70 that exposes the first main surface 3 in the active region 8. The contact opening 70 exposes the plurality of first regions 25 and the plurality of second regions 26. In this form, the contact opening 70 has an opening wall positioned above the outer well region 23, exposing the inner edge of the outer well region 23.

[0506] The semiconductor device 1H includes an anode electrode 71 disposed on the first main surface 3. The anode electrode 71 may also be referred to as a "first main surface electrode," a "first terminal (electrode)," a "first pad (electrode)," or the like. The anode electrode 71 is disposed at a distance from the periphery of the first main surface 3. The anode electrode 71 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the first main surface 3 in a plan view.

[0507] The anode electrode 71 extends into the contact opening 70 from above the interlayer film 33 and is mechanically and electrically connected to the first main surface 3 within the contact opening 70. Specifically, the anode electrode 71 is mechanically and electrically connected to the plurality of first regions 25, the plurality of second regions 26, and the outer well region 23. The anode electrode 71 forms a Schottky junction with the plurality of second regions 26.

[0508] As a result, a diode structure is formed that includes the anode electrode 71 as an anode region and the plurality of second regions 26 as cathode regions. In this embodiment, the diode structure is a Schottky barrier diode structure. The plurality of second regions 26 may form a JBS structure (Junction Barrier Schottky structure) together with the plurality of first regions 25.

[0509] The semiconductor device 1H includes the aforementioned cathode electrode 72 disposed on the second main surface 4. The cathode electrode 72 may also be referred to as a "second main surface electrode," a "second terminal (electrode)," a "second pad (electrode)," or the like. The cathode electrode 72 is mechanically and electrically connected to the first layer 6. The cathode electrode 72 forms ohmic contact with the first layer 6.

[0510] The cathode electrode 72 faces the plurality of shield regions 30 in the thickness direction. The cathode electrode 72 may cover the entire second main surface 4 and be continuous with the periphery (first to fourth ends 5A to 5D) of the second main surface 4. The cathode electrode 72 may also cover part of the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0511] The breakdown voltage that can be applied between the anode electrode 71 and the cathode electrode 72 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0512] The following describes first to third modified examples of the peripheral surface layer portion. In the following, an example in which the first to third modified examples are applied to semiconductor device 1A is described. However, the first to third modified examples may also be applied to any one of semiconductor devices 1B to 1H.

[0513] Fig. 42 is an enlarged plan view showing a peripheral surface layer portion according to a first modified example. Fig. 43 is a cross-sectional view taken along line XLIII-XLIII shown in Fig. 42. With reference to Fig. 42 and Fig. 43, semiconductor device 1A may include a shield structure integrally having shield region 30 according to the first embodiment and shield region 50 according to the second embodiment.

[0514] The shield region 30 may have a layout according to any one of the first to third layout examples (see FIGS. 1 to 16). The shield region 50 may have a layout according to any one of the first to fourth layout examples (see FIGS. 17 to 24).

[0515] The shield region 50 is formed inward of the shield region 30. The shield region 50 faces the first portion 25 a of the first region 25 with a portion of the shield region 30 in between, and faces the second portion 25 b of the first region 25 with a portion of the shield region 30 in between.

[0516] The shield region 50 faces the first portion 26a of the second region 26 across a portion of the shield region 30, and faces the second portion 26b of the second region 26 across a portion of the shield region 50. The depth of the shield region 50 may be greater or less than the depth of the shield region 30.

[0517] Fig. 44 is an enlarged plan view showing a peripheral surface layer portion according to a second modified example. Fig. 45 is a cross-sectional view taken along line XLV-XLV shown in Fig. 44. With reference to Figs. 44 and 45, semiconductor device 1A may include a shield structure integrally having shield region 30 according to the first mode and shield region 60 according to the third mode.

[0518] The shield region 30 may have a layout according to any one of the first to third layout examples (see FIGS. 1 to 16). The shield region 60 may have a layout according to any one of the first to fourth layout examples (see FIGS. 25 to 32).

[0519] The shield region 60 is formed inward of the shield region 30. The shield region 60 faces the first portion 25 a of the first region 25 with a portion of the shield region 30 in between, and faces the second portion 25 b of the first region 25 with a portion of the shield region 30 in between.

[0520] The shield region 60 faces the first portion 26 a of the second region 26 across a portion of the shield region 30, and faces the second portion 26 b of the second region 26 across a portion of the shield region 60. The depth of the shield region 60 may be greater or less than the depth of the shield region 30.

[0521] Fig. 46 is an enlarged plan view showing a peripheral surface layer portion according to a third modified example. Fig. 47 is a cross-sectional view taken along line XLVII-XLVII shown in Fig. 46. With reference to Figs. 46 and 47, semiconductor device 1A may include a shield structure integrally having shield region 50 according to the second embodiment and shield region 60 according to the third embodiment.

[0522] The shield region 50 may have a layout according to any one of the first to fourth layout examples (see FIGS. 17 to 24). The shield region 60 may have a layout according to any one of the first to fourth layout examples (see FIGS. 25 to 32).

[0523] The shield region 50 is formed inside the shield region 60. The shield region 50 faces the first portion 25 a of the first region 25 with a portion of the shield region 60 in between, and faces the second portion 25 b of the first region 25 with a portion of the shield region 60 in between.

[0524] The shield region 50 faces the first portion 26a of the second region 26 across a portion of the shield region 60, and faces the second portion 26b of the second region 26 across a portion of the shield region 60. The depth of the shield region 50 may be greater or less than the depth of the shield region 60.

[0525] Fig. 48 is an enlarged plan view showing a peripheral surface layer portion according to a fourth modified example. Fig. 49 is a cross-sectional view taken along line XLIX-XLIX shown in Fig. 48. With reference to Fig. 48 and Fig. 49, semiconductor device 1A may include a shield structure integrally having shield region 30 according to the first mode, shield region 50 according to the second mode, and shield region 60 according to the third mode.

[0526] The shield region 30 may have a layout according to any one of the first to third layout examples (see FIGS. 1 to 16). The shield region 50 may have a layout according to any one of the first to fourth layout examples (see FIGS. 17 to 24). The shield region 60 may have a layout according to any one of the first to fourth layout examples (see FIGS. 25 to 32).

[0527] The shield region 60 is formed inward of the shield region 30. The shield region 60 faces the first portion 25a of the first region 25 across a portion of the shield region 30, and faces the second portion 25b of the first region 25 across a portion of the shield region 30. The shield region 60 faces the first portion 26a of the second region 26 across a portion of the shield region 30, and faces the second portion 26b of the second region 26 across a portion of the shield region 30. The depth of the shield region 60 may be greater or smaller than the depth of the shield region 30.

[0528] The shield region 50 is formed inside the shield region 60. The shield region 50 faces the first portion 25 a of the first region 25 across a portion of the shield region 30 and a portion of the shield region 60, and faces the second portion 25 b of the first region 25 across a portion of the shield region 30 and a portion of the shield region 60.

[0529] The shield region 50 faces the first portion 26a of the second region 26, with a portion of the shield region 30 and a portion of the shield region 60 sandwiched therebetween, and faces the second portion 26b of the second region 26, with a portion of the shield region 30 and a portion of the shield region 60 sandwiched therebetween. The depth of the shield region 50 may be greater or less than the depth of the shield region 30. The depth of the shield region 50 may be greater or less than the depth of the shield region 60.

[0530] Fig. 50 is an enlarged plan view showing a peripheral surface layer portion according to a fifth modified example. Fig. 51 is a cross-sectional view taken along line LI-LI shown in Fig. 50. With reference to Fig. 50 and Fig. 51, semiconductor device 1A may include at least two of shield region 30 according to the first embodiment, shield region 50 according to the second embodiment, and shield region 60 according to the third embodiment.

[0531] The shield region 30 may have a layout according to any one of the first to third layout examples (see FIGS. 1 to 16). The shield region 50 may have a layout according to any one of the first to fourth layout examples (see FIGS. 17 to 24). The shield region 60 may have a layout according to any one of the first to fourth layout examples (see FIGS. 25 to 32).

[0532] In this embodiment, the shield region 30 according to the first embodiment, the shield region 50 according to the second embodiment, and the shield region 60 according to the third embodiment are arranged in this order from the periphery of the first main surface 3 toward the inside of the first main surface 3. The shield region 30 according to the first embodiment, the shield region 50 according to the second embodiment, and the shield region 60 according to the third embodiment may be arranged in any order.

[0533] The shield region 50 is formed at a distance from the shield region 30 in the first direction X, and faces the shield region 30 across some of the multiple first regions 25 and some of the multiple second regions 26. The depth of the shield region 50 may be greater or smaller than the depth of the shield region 30.

[0534] The shield region 60 is formed at a distance from the shield region 50 in the first direction X, and faces the shield region 50 across some of the multiple first regions 25 and some of the multiple second regions 26. The depth of the shield region 50 may be greater or less than the depth of the shield region 30. The depth of the shield region 60 may be greater or less than the depth of the shield region 50.

[0535] Of course, the shield region 60 may be formed at a distance from the shield region 30 in the first direction X and may face the shield region 30 across some of the multiple first regions 25 and some of the multiple second regions 26.

[0536] 52 is a cross-sectional view showing an upper insulating film 80 applied to each of the above-described embodiments (including each of the modified examples). The above-described semiconductor devices 1A to 1H may further include an insulating upper insulating film 80 that covers the interlayer film 33. The upper insulating film 80 covers the shield regions 30, 50, and 60 via the interlayer film 33. The upper insulating film 80 is preferably formed at an interval inward from the first to fourth end portions 5A to 5D, exposing the interlayer film 33.

[0537] The upper insulating film 80 may cover the peripheral portion of the source electrode 40 and have a first pad opening (source pad opening) that exposes an inner portion of the source electrode 40. The upper insulating film 80 may cover the peripheral portion of the gate electrode 44 and have a second pad opening (gate pad opening) that exposes an inner portion of the gate electrode 44. The upper insulating film 80 may cover the entire area of ​​the source finger electrodes 43. The upper insulating film 80 may cover the entire area of ​​the gate finger electrodes 45.

[0538] The upper insulating film 80 may have a single layer structure made of an insulating inorganic film 81 (inorganic insulating film) or an insulating organic film 82 (organic insulating film). The upper insulating film 80 may have a laminated structure including the insulating inorganic film 81 and the insulating organic film 82 laminated in this order from the interlayer film 33 side.

[0539] The inorganic film 81 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic film 81 preferably includes an insulating material different from the insulating material of the interlayer film 33. The inorganic film 81 may be a silicon nitride film or a silicon oxynitride film.

[0540] The inorganic film 81 may have a thickness less than that of the interlayer film 33. Of course, the inorganic film 81 may have a thickness greater than that of the interlayer film 33. The inorganic film 81 may have a thickness less than that of the source electrode 40 (gate electrode 44, anode electrode 71). Of course, the inorganic film 81 may have a thickness greater than that of the source electrode 40 (gate electrode 44, anode electrode 71).

[0541] The organic film 82 may include a positive-type photosensitive resin or a negative-type photosensitive resin, and may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0542] The organic film 82 may have a thickness greater than that of the interlayer film 33. The organic film 82 may have a thickness greater than that of the source electrode 40 (gate electrode 44, anode electrode 71). The organic film 82 may have a thickness greater than or less than that of the second layer 7. The organic film 82 may have a thickness less than that of the chip 2.

[0543] The above-described embodiments (including modifications) can be implemented in other forms. The features (including modifications) of the semiconductor devices 1A to 1H described above can be combined as appropriate. Therefore, the semiconductor devices 1A to 1H may include two, three, four, five, six, seven, or eight of the features of the semiconductor devices 1A to 1H.

[0544] In the above-described embodiments, examples have been shown in which the trench transistor structure, the planar transistor structure, and the diode structure are formed on separate chips 2 (first main surface 3). However, the trench transistor structure, the planar transistor structure, and the diode structure may be fabricated on a common chip 2 (first main surface 3).

[0545] A structure including both a trench type transistor structure and a planar type transistor structure may be employed. A structure including both a trench type transistor structure and a diode structure may be employed. A structure including both a planar type transistor structure and a diode structure may be employed. A structure including all of a trench type transistor structure, a planar type transistor structure, and a diode structure may be employed.

[0546] In each of the above-described embodiments, a structure in which the conductivity type of the n-type semiconductor region is inverted to p-type and the conductivity type of the p-type semiconductor region is inverted to n-type may be adopted. A specific configuration in this case can be obtained by replacing n-type with p-type and p-type with n-type in the above description and accompanying drawings.

[0547] In the above-described embodiments, the first layer 6 is of n-type. However, the conductivity type of the first layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure.

[0548] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," etc., as necessary.

[0549] [A1] A semiconductor device (1A-1H) including: a chip (2) having a main surface (3); a first region (25) of a first conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) in a peripheral surface layer portion of the main surface (3); a plurality of second regions (26) of a second conductivity type (n-type / p-type) extending in the first direction (X / Y) on both sides of the first region (25) in the peripheral surface layer portion of the main surface (3); and a shielding region (30, 50, 60) dividing at least a portion of the first region (25) in the peripheral surface layer portion of the main surface (3) into a region on an end (5A-5D) side of the chip (2) and a region on an inner side of the chip (2).

[0550] [A2] The semiconductor device (1A to 1H) according to A1, wherein the chip (2) includes SiC.

[0551] [A3] A semiconductor device (1A to 1H) according to A1 or A2, wherein the first region (25) is exposed from the end (5A to 5D), and the plurality of second regions (26) are exposed from the end (5A to 5D).

[0552] [A4] The semiconductor device (1A to 1H) according to any one of A1 to A3, wherein the shield region (30, 50, 60) is formed at a distance from the end portion (5A to 5D).

[0553] [A5] A semiconductor device (1A-1H) described in any one of A1 to A4, wherein the first region (25) extends vertically in the thickness direction (Z) of the chip (2), the plurality of second regions (26) extend vertically in the thickness direction (Z), and the shield region (30, 50, 60) extends vertically in the thickness direction (Z).

[0554] [A6] A semiconductor device (1A to 1H) described in any one of A1 to A5, wherein the shield region (30, 50, 60) extends in a second direction (Y / X) along the main surface (3) and intersects with the first region (25).

[0555] [A7] The semiconductor device (1A to 1H) described in A6, wherein the shield region (30, 50, 60) crosses the first region (25) in the second direction (Y / X) and has a portion that contacts multiple second regions (26).

[0556] [A8] A semiconductor device (1A to 1H) according to any one of A1 to A7, wherein the shield region (30, 50, 60) includes a second conductivity type (n-type / p-type) impurity region (30).

[0557] [A9] The semiconductor device (1A to 1H) according to any one of A1 to A8, wherein the shielding region (30, 50, 60) includes an insulator (52, 53).

[0558] [A10] A semiconductor device (1A to 1H) according to any one of A1 to A9, wherein the shield region (30, 50, 60) includes a high resistance region (60) having a resistance value higher than the resistance value of the first region (25).

[0559] [A11] A semiconductor device (1A-1H) according to any one of A1 to A10, wherein a plurality of the first regions (25) are formed at intervals in the surface layer portion of the peripheral portion of the main surface (3), and one or more of the shield regions (30, 50, 60) separate at least a portion of the plurality of first regions (25) from the end portions (5A-5D).

[0560] [A12] The chip (2) has a laminated structure including a first layer (6) of a second conductivity type (n-type / p-type) and a second layer (7) of a second conductivity type (n-type / p-type), has the main surface (3) formed by the second layer (7), the first region (25) is formed in the second layer (7), a plurality of the second regions (26) are formed in the second layer (7), and the shielding region (30, 50, 60) is formed in the second layer (7), a semiconductor device (1A to 1H) described in any one of A1 to A11.

[0561] [A13] A semiconductor device (1A to 1H) according to A12, wherein the first region (25) is formed in the second layer (7) at a distance from the first layer (6), and the shield region (30, 50, 60) is formed in the second layer (7) at a distance from the first layer (6).

[0562] [A14] A semiconductor device (1A-1H) according to any one of A1 to A13, further comprising an active region (8) provided in the inner part of the chip (2) and an outer region (9) provided in the peripheral part of the chip (2), wherein the first region (25) is formed in both the active region (8) and the outer region (9), a plurality of second regions (26) are formed in both the active region (8) and the outer region (9), and the shield region (30, 50, 60) is formed in the outer region (9).

[0563] [A15] The semiconductor device (1A to 1H) according to A14, further comprising a transistor structure formed in the active region (8).

[0564] [A16] The semiconductor device (1A to 1H) according to A15, wherein the transistor structure has a trench-type gate structure (15).

[0565] [A17] The semiconductor device (1A to 1H) according to A15, wherein the transistor structure has a planar gate structure (65).

[0566] [A18] The semiconductor device (1A to 1H) according to any one of A14 to A17, further including a diode structure formed in the active region (8).

[0567] [A19] A semiconductor device (1A to 1H) according to any one of A14 to A18, further comprising a well region (23) of a first conductivity type (p-type / n-type) formed in a surface layer portion of the main surface (3) along the active region (8) and dividing the active region (8) and the outer region (9), wherein the first region (25) is electrically connected to the well region (23).

[0568] [A20] A semiconductor device (1A-1H) including: a chip (2) having a main surface (3); a first region (25) of a first conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) in a peripheral surface layer portion of the main surface (3); a plurality of second regions (26) of a second conductivity type (n-type / p-type) extending in the first direction (X / Y) on both sides of the first region (25) in the peripheral surface layer portion of the main surface (3); and a shield region (30) of a second conductivity type (n-type / p-type) dividing at least a portion of the first region (25) in the peripheral surface layer portion of the main surface (3) into a region on an end (5A-5D) side of the chip (2) and a region on an inner side of the chip (2).

[0569] [B1] A semiconductor device (1A-1H) including: a chip (2) having a main surface (3); a first region (25) of a first conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) in a peripheral surface layer portion of the main surface (3); a plurality of second regions (26) of a second conductivity type (n-type / p-type) extending in the first direction (X / Y) on both sides of the first region (25) in the peripheral surface layer portion of the main surface (3); and an insulating shield region (50) that divides at least a portion of the first region (25) in the peripheral surface layer portion of the main surface (3) into a region on an end (5A-5D) side of the chip (2) and a region on an inner side of the chip (2).

[0570] [B2] The semiconductor device (1A to 1H) according to B1, wherein the chip (2) includes SiC.

[0571] [B3] The semiconductor device (1A to 1H) described in B1 or B2, wherein the first region (25) is exposed from the end (5A to 5D), and the plurality of second regions (26) are exposed from the end (5A to 5D).

[0572] [B4] The semiconductor device (1A to 1H) according to any one of B1 to B3, wherein the shield region (50) is formed at a distance from the end portion (5A to 5D).

[0573] [B5] A semiconductor device (1A to 1H) described in any one of B1 to B4, wherein the first region (25) extends vertically in the thickness direction (Z) of the chip (2), the plurality of second regions (26) extend vertically in the thickness direction (Z), and the shield region (50) extends vertically in the thickness direction (Z).

[0574] [B6] A semiconductor device (1A to 1H) according to any one of B1 to B5, wherein the shield region (50) extends in a second direction (Y / X) along the main surface (3) and intersects with the first region (25).

[0575] [B7] The semiconductor device (1A-1H) described in B6, wherein the shield region (50) crosses the first region (25) in the second direction (Y / X) and has a portion that contacts multiple second regions (26).

[0576] [B8] A semiconductor device (1A to 1H) according to any one of B1 to B7, wherein the shielding region (50) includes a trench (51) formed in the main surface (3) and an insulator (53) buried in the trench (51).

[0577] [B9] A semiconductor device (1A to 1H) according to B8, wherein the trench (51) has a wall surface that exposes the first region (25) and the second region (26), and the insulator (53) covers the first region (25) and the second region (26) within the trench (51).

[0578] [B10] A semiconductor device (1A to 1H) according to B8 or B9, wherein the shield region (50) includes an insulating film (52) covering the wall surface of the trench (51), and the insulator (53) is buried in the trench (51) via the insulating film (52).

[0579] [B11] A semiconductor device (1A-1H) according to any one of B1 to B10, wherein a plurality of the first regions (25) are formed at intervals in the surface layer portion of the peripheral portion of the main surface (3), and one or more of the shield regions (50) separate at least a portion of the plurality of first regions (25) from the end portions (5A-5D).

[0580] [B12] The chip (2) has a laminated structure including a first layer (6) of a second conductivity type (n-type / p-type) and a second layer (7) of a second conductivity type (n-type / p-type), has the main surface (3) formed by the second layer (7), the first region (25) is formed in the second layer (7), a plurality of the second regions (26) are formed in the second layer (7), and the shield region (50) is formed in the second layer (7), a semiconductor device (1A to 1H) described in any one of B1 to B11.

[0581] [B13] The semiconductor device (1A-1H) according to B12, wherein the first region (25) is formed in the second layer (7) at a distance from the first layer (6), and the shield region (50) is formed in the second layer (7) at a distance from the first layer (6).

[0582] [B14] A semiconductor device (1A to 1H) according to any one of B1 to B13, further comprising an active region (8) provided in the inner part of the chip (2) and an outer region (9) provided on the periphery of the chip (2), wherein the first region (25) is formed in both the active region (8) and the outer region (9), a plurality of second regions (26) are formed in both the active region (8) and the outer region (9), and the shield region (50) is formed in the outer region (9).

[0583] [B15] The semiconductor device (1A to 1H) according to B14, further comprising a transistor structure formed in the active region (8).

[0584] [B16] The semiconductor device (1A to 1H) according to B15, wherein the transistor structure has a trench-type gate structure (15).

[0585] [B17] The semiconductor device (1A to 1H) according to B15, wherein the transistor structure has a planar gate structure (65).

[0586] [B18] The semiconductor device (1A to 1H) according to any one of B14 to B17, further comprising a diode structure formed in the active region (8).

[0587] [B19] A semiconductor device (1A to 1H) according to any one of B14 to B18, further comprising a well region (23) of a first conductivity type (p-type / n-type) formed in a surface layer portion of the main surface (3) along the active region (8) and dividing the active region (8) and the outer region (9), wherein the first region (25) is electrically connected to the well region (23).

[0588] [B20] A semiconductor device (1A to 1H) according to any one of B1 to B19, further comprising an electrode (40) disposed on the main surface (3) and electrically connected to the first region (25).

[0589] [C1] A semiconductor device (1A-1H) including: a chip (2) having a main surface (3); a first region (25) of a first conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) in a peripheral surface layer portion of the main surface (3); a plurality of second regions (26) of a second conductivity type (n-type / p-type) extending in the first direction (X / Y) on both sides of the first region (25) in the peripheral surface layer portion of the main surface (3); and a shielding region (60) that divides at least a portion of the first region (25) in the peripheral surface layer portion of the main surface (3) into a region on the end (5A-5D) side of the chip (2) and a region on the inner side of the chip (2), and has a resistance value higher than that of the first region (25).

[0590] [C2] The semiconductor device (1A to 1H) according to C1, wherein the chip (2) includes SiC.

[0591] [C3] A semiconductor device (1A to 1H) according to C1 or C2, wherein the first region (25) is exposed from the end (5A to 5D), and the plurality of second regions (26) are exposed from the end (5A to 5D).

[0592] [C4] The semiconductor device (1A to 1H) according to any one of C1 to C3, wherein the shielding region (60) is formed at a distance from the end portion (5A to 5D).

[0593] [C5] A semiconductor device (1A to 1H) described in any one of C1 to C4, wherein the first region (25) extends vertically in the thickness direction (Z) of the chip (2), the plurality of second regions (26) extend vertically in the thickness direction (Z), and the shield region (60) extends vertically in the thickness direction (Z).

[0594] [C6] A semiconductor device (1A to 1H) described in any one of C1 to C5, wherein the shield region (60) extends in a second direction (Y / X) along the main surface (3) and intersects with the first region (25).

[0595] [C7] A semiconductor device (1A to 1H) described in C6, wherein the shield region (60) crosses the first region (25) in the second direction (Y / X) and has a portion that contacts multiple second regions (26).

[0596] [C8] A semiconductor device (1A to 1H) according to any one of C1 to C7, wherein the shield region (60) includes crystal defects introduced into the chip (2) and has a trap level that captures carriers.

[0597] [C9] The semiconductor device (1A to 1H) according to C8, wherein the trap level of the shield region (60) is higher than the trap level of the first region (25).

[0598] [C10] The semiconductor device (1A to 1H) according to C8 or C9, wherein the shield region (60) has a crystal defect density higher than the impurity concentration of the first region (25).

[0599] [C11] A semiconductor device (1A-1H) according to any one of C1 to C10, wherein a plurality of the first regions (25) are formed at intervals on the surface layer of the peripheral portion of the main surface (3), and one or more of the shield regions (60) separate at least a portion of the plurality of first regions (25) from the end portions (5A-5D).

[0600] [C12] The chip (2) has a laminated structure including a first layer (6) of a second conductivity type (n-type / p-type) and a second layer (7) of a second conductivity type (n-type / p-type), has the main surface (3) formed by the second layer (7), the first region (25) is formed in the second layer (7), a plurality of the second regions (26) are formed in the second layer (7), and the shield region (60) is formed in the second layer (7), a semiconductor device (1A to 1H) described in any one of C1 to C11.

[0601] [C13] The semiconductor device (1A-1H) described in C12, wherein the first region (25) is formed in the second layer (7) at a distance from the first layer (6), and the shield region (60) is formed in the second layer (7) at a distance from the first layer (6).

[0602] [C14] A semiconductor device (1A to 1H) according to any one of C1 to C13, further comprising an active region (8) provided in the inner part of the chip (2) and an outer region (9) provided on the periphery of the chip (2), wherein the first region (25) is formed in both the active region (8) and the outer region (9), a plurality of second regions (26) are formed in both the active region (8) and the outer region (9), and the shield region (60) is formed in the outer region (9).

[0603] [C15] The semiconductor device (1A to 1H) according to C14, further comprising a transistor structure formed in the active region (8).

[0604] [C16] The semiconductor device (1A to 1H) according to C15, wherein the transistor structure has a trench-type gate structure (15).

[0605] [C17] The semiconductor device (1A to 1H) according to C15, wherein the transistor structure has a planar gate structure (65).

[0606] [C18] The semiconductor device (1A to 1H) according to any one of C14 to C17, further comprising a diode structure formed in the active region (8).

[0607] [C19] A semiconductor device (1A to 1H) according to any one of C14 to C18, further comprising a well region (23) of a first conductivity type (p-type / n-type) formed in a surface layer portion of the main surface (3) along the active region (8) and dividing the active region (8) and the outer region (9), wherein the first region (25) is electrically connected to the well region (23).

[0608] [C20] A semiconductor device (1A to 1H) according to any one of C1 to C19, further comprising an electrode (40) disposed on the main surface (3) and electrically connected to the first region (25).

[0609] [D1] A semiconductor device (1A-1H) including: a chip (2) having a main surface (3); a first region (25) of a first conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) in a peripheral surface layer portion of the main surface (3); a second region (26) of a second conductivity type (n-type / p-type) extending in the first direction (X / Y) adjacent to the first region (25) in the peripheral surface layer portion of the main surface (3); and a shielding region (30, 50, 60) extending in a second direction (Y / X) along the main surface (3) in the peripheral surface layer portion of the main surface (3) and dividing at least a portion of the first region (25).

[0610] [D2] The semiconductor device (1A to 1H) according to D1, wherein the chip (2) includes SiC.

[0611] [D3] The semiconductor device (1A to 1H) according to D1 or D2, further comprising gate wiring (32) arranged in a line on the main surface (3).

[0612] [D4] The semiconductor device (1A to 1H) according to D3, wherein the gate wiring (32) is arranged on the inner side of the main surface (3) relative to the shielding region (30, 50, 60).

[0613] [D5] The semiconductor device (1A to 1H) according to D3 or D4, wherein the gate wiring (32) includes a non-metallic conductor.

[0614] [D6] A semiconductor device (1A to 1H) according to any one of D1 to D5, further comprising a source electrode (40) arranged in a pad shape on the main surface (3).

[0615] [D7] The semiconductor device (1A to 1H) according to D6, wherein the source electrode (40) is arranged on the inner side of the main surface (3) relative to the shielding region (30, 50, 60).

[0616] [D8] The semiconductor device (1A to 1H) according to D6 or D7, wherein the source electrode (40) contains a metal.

[0617] [D9] The semiconductor device (1A to 1H) according to any one of D1 to D8, further comprising source finger electrodes (43) arranged in lines on the main surface (3).

[0618] [D10] The semiconductor device (1A to 1H) according to D9, wherein the source finger electrode (43) is arranged on the inner side of the main surface (3) relative to the shielding region (30, 50, 60).

[0619] [D11] The semiconductor device (1A to 1H) according to D9 or D10, wherein the source finger electrode (43) includes a metal.

[0620] [D12] The semiconductor device (1A to 1H) according to any one of D1 to D11, further comprising a gate electrode (44) arranged in a pad shape on the main surface (3).

[0621] [D13] The semiconductor device (1A to 1H) according to D12, wherein the gate electrode (44) is arranged on the inner side of the main surface (3) relative to the shield region (30, 50, 60).

[0622] [D14] The semiconductor device (1A to 1H) according to D12 or D13, wherein the gate electrode (44) contains a metal.

[0623] [D15] The semiconductor device (1A to 1H) according to any one of D1 to D14, further comprising gate finger electrodes (45) arranged in a line on the main surface (3).

[0624] [D16] The semiconductor device (1A to 1H) according to D15, wherein the gate finger electrode (45) is arranged on the inner side of the main surface (3) relative to the shielding region (30, 50, 60).

[0625] [D17] The semiconductor device (1A to 1H) according to D15 or D16, wherein the gate finger electrode (45) contains a metal.

[0626] [D18] The semiconductor device (1A to 1H) according to any one of D1 to D17, further comprising an insulating film (31, 33) covering the shield region (30, 50, 60) on the main surface (3).

[0627] [D19] A semiconductor device (1A to 1H) according to any one of D1 to D18, in which no conductor is arranged on the portion of the insulating film (31, 33) that covers the shield region (30, 50, 60).

[0628] [D20] A semiconductor device (1A to 1H) according to any one of D1 to D19, further comprising an insulating organic film (82) covering the shielding region (30, 50, 60) on the main surface (3).

[0629] The above [A1] to [A20], [B1] to [B20], [C1] to [C20], and [D1] to [D20] can be appropriately combined with each other.

[0630] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0631] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 1G Semiconductor device 1H Semiconductor device 2 Chip 3 First main surface 5A First end 5B Second end 5C Third end 5D Fourth end 6 First layer 7 Second layer 8 Active region 9 Outer region 22 Chip 23 Outer well region 25 First region 26 Second region 30 Shield region 31 Main surface insulating film 33 Interlayer film 40 Source electrode 40 Source electrode 43 Source finger electrode 44 Gate electrode 45 Gate finger electrode 50 Shield region 51 Shield trench 52 Shield insulating film 53 Shield insulator 60 Shield region 80 Upper insulating film 81 Inorganic film 82 Organic film X First direction Y Second direction Z Vertical direction (thickness direction)

Claims

1. A semiconductor device comprising: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface in a peripheral surface layer portion of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region in the peripheral surface layer portion of the main surface; and a shielding region in the peripheral surface layer portion of the main surface dividing at least a portion of the first region into a region on the edge side of the chip and a region on the inner side of the chip, the shielding region having a resistance higher than that of the first region.

2. The semiconductor device according to claim 1, wherein the chip comprises SiC.

3. The semiconductor device according to claim 1 or 2, wherein the first region is exposed from the end portion, and the plurality of second regions are exposed from the end portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the shielding region is formed at a distance from the edge.

5. A semiconductor device according to any one of claims 1 to 4, wherein the first region extends vertically in the thickness direction of the chip, the plurality of second regions extend vertically in the thickness direction, and the shield region extends vertically in the thickness direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein the shield region extends in a second direction along the main surface so as to intersect with the first region.

7. The semiconductor device according to claim 6, wherein said shield region crosses said first region in said second direction and has a plurality of portions contacting said second region.

8. The semiconductor device according to any one of claims 1 to 7, wherein the shield region includes crystal defects introduced into the chip and has a trap level that captures carriers.

9. The semiconductor device according to claim 8, wherein the trap level in the shield region is higher than the trap level in the first region.

10. The semiconductor device according to claim 8 or 9, wherein said shield region has a crystal defect density higher than the impurity concentration of said first region.

11. A semiconductor device according to any one of claims 1 to 10, wherein a plurality of said first regions are formed in a surface layer portion of the peripheral portion of said main surface, and one or more said shield regions separate at least a portion of said plurality of said first regions from said end portion.

12. A semiconductor device according to any one of claims 1 to 11, wherein the chip has a laminated structure including a first semiconductor layer of a second conductivity type and a second semiconductor layer of the second conductivity type, and has the main surface formed by the second semiconductor layer, the first region is formed in the second semiconductor layer, a plurality of the second regions are formed in the second semiconductor layer, and the shield region is formed in the second semiconductor layer.

13. The semiconductor device according to claim 12, wherein the first region is formed in the second semiconductor layer at a distance from the first semiconductor layer, and the shield region is formed in the second semiconductor layer at a distance from the first semiconductor layer.

14. The semiconductor device according to any one of claims 1 to 13, further comprising: an active region provided in an inner portion of the chip; and an outer region provided on the periphery of the chip; the first region is formed in both the active region and the outer region; a plurality of second regions are formed in both the active region and the outer region; and the shield region is formed in the outer region.

15. The semiconductor device of claim 14, further comprising a transistor structure formed in said active region.

16. The semiconductor device according to claim 15, wherein the transistor structure has a trench-type gate structure.

17. The semiconductor device according to claim 15, wherein the transistor structure has a planar gate structure.

18. The semiconductor device according to any one of claims 14 to 17, further comprising a diode structure formed in the active region.

19. The semiconductor device according to any one of claims 14 to 18, further comprising a well region of a first conductivity type formed in a surface layer portion of said main surface along said active region and separating said active region and said outer region, said first region being electrically connected to said well region.

20. The semiconductor device according to any one of claims 1 to 19, further comprising an electrode disposed on said main surface and electrically connected to said first region.

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