Data processing method and apparatus, and system

Abstract

Embodiments of the present application disclose a data processing method and apparatus, and a system. The method comprises: performing PCS processing on a first bit set from a plurality of bits to obtain a second bit set, wherein half of bits in the second bit set are first-type bits, and the other half of the bits in the second bit set are second-type bits; performing first interleaving on the second bit set and a third bit set from the plurality of bits other than the first bit set to obtain a fourth bit set 1 and a fourth bit set 2; then, performing FEC encoding by using fifth bit sets as granularity, wherein for example, a fifth bit set 1 comprises at least one said fourth bit set 1, the fifth bit set 2 comprises at least one said fourth bit set 2, and FEC encoding is separately performed on the two fifth bit sets to obtain two sixth bit sets; separately performing second interleaving on the two sixth bit sets to obtain two seventh bit sets; and performing third interleaving on the two seventh bit sets to obtain eighth bit sets.

Description

A data processing method, device and system

[0001] The present application claims priority to the Chinese Patent Application No. 202410533964.6, filed on April 29, 2024, and entitled "A data processing method, device and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, in particular to a data processing method, device and system. BACKGROUND

[0003] Under the continuous promotion of 5G, cloud computing, big data, artificial intelligence, etc., high-speed optical transmission networks are developing towards large capacity, packetization and intelligentization. Coherent optical communication systems use the amplitude, phase, polarization and frequency of light waves to carry information. In order to combat optical signal distortion caused by dispersion, polarization-related damage, noise, nonlinear effects and other factors during transmission and maintain long-distance transmission, coherent optical communication systems usually need to use efficient forward error correction (FEC) codes to combat optical damage during optical transmission to maintain a low enough bit error rate during long-distance transmission. For example, the current 400ZR+ and 800ZR adopt open FEC codes (OpenFEC), referred to as OFEC codes, with an overhead (OH) of 15.3%, and the performance is about 2.0E-2 when soft decision decoding is used.

[0004] In order to improve spectral efficiency, multi-level quadrature amplitude modulation (QAM) is usually used, such as 16QAM, 32QAM, 64QAM or even higher QAM. The traditional QAM modulation corresponds to each constellation point on the signal constellation diagram. The probability constellation shaping (PCS) processing technology changes the probability of occurrence of the constellation points while keeping the constellation point positions unchanged, so as to improve the system transmission performance. As a modulation format optimization technology, PCS processing technology has the advantages of approaching Shannon limit and flexible variability, and has been widely studied and applied. The existing data processing and transmission method using OFEC encoding mainly uses traditional QAM modulation, which cannot be applied to future scenarios using PCS processing technology, and is a problem that needs to be solved in the future. SUMMARY

[0005] The embodiments of the present application provide a data processing method, device and system, which adopts DP-64QAM modulation and combines FEC coding, interleaving and PCS technology, ensures simple overall data processing operation, low complexity and low power consumption, improves spectrum utilization and transmission performance of the system, and meets future metropolitan telecommunication transmission and metropolitan DCI interconnection scenarios.

[0006] In a first aspect, the embodiments of the present application provide a data processing method. Specifically, a first bit set in a plurality of bits is processed by PCS to obtain a second bit set. One half of the bits in the second bit set is a first type of bit, and the other half of the bits in the second bit set is a second type of bit. The second bit set and a third bit set in the plurality of bits except the first bit set are interleaved to obtain two fourth bit sets. The bit distribution manners of the two fourth bit sets are different, and are distinguished as fourth bit set 1 and fourth bit set 2 for convenience, the fourth bit set 1 can correspond to the fourth bit set 2i in the following embodiments, and the fourth bit set 2 can correspond to the fourth bit set 2i+1 in the following embodiments. Then, FEC coding is performed on a fifth bit set as a granularity, for example, the fifth bit set 1 includes at least one fourth bit set 1, and the fifth bit set 2 includes at least one fourth bit set 2, and the two fifth bit sets are respectively coded by FEC to obtain two sixth bit sets, and the sixth bit set includes the check bits generated by FEC coding. Next, the two sixth bit sets are respectively interleaved to obtain two seventh bit sets. Further, the two seventh bit sets are interleaved to obtain an eighth bit set. In a specific scenario, the fifth bit set includes 42 rows and 7 columns, a total of 294 bit subsets, of which 42 rows and 6 columns, a total of 252 bit subsets each include 16 rows and 16 columns, a total of 256 bits, and 42 rows and 1 column, a total of 42 bit subsets each include 16 rows and 15 columns, a total of 240 bits, and the sixth bit set and the seventh bit set each include 42 rows and 8 columns, a total of 336 bit subsets, and each bit subset includes 16 rows and 16 columns, a total of 256 bits.

[0007] It should be noted that the 12 consecutive bits in the eighth bit set are used for mapping to obtain one dual-polarization symbol, and the dual-polarization symbol includes a first polarization symbol and a second polarization symbol, and the first polarization symbol can also be denoted as an X polarization symbol, and the second polarization symbol can also be denoted as a Y polarization symbol. Two bits of the 12 bits used for mapping to the first polarization symbol come from the first type of bits, two bits of the 12 bits used for mapping to the first polarization symbol come from the second type of bits, and two bits of the 12 bits used for mapping to the first polarization symbol come from the third bit set or the check bits of the FEC encoding. Two bits of the 12 bits used for mapping to the second polarization symbol come from the first type of bits, two bits of the 12 bits used for mapping to the second polarization symbol come from the second type of bits, and two bits of the 12 bits used for mapping to the second polarization symbol come from the third bit set or the check bits of the FEC encoding. It should be understood that the above “two bits come from the third bit set or the check bits of the FEC encoding” means that the two bits come from at least one of the third bit set and the check bits of the FEC encoding. For example, the two bits can both come from the third bit set; for another example, the two bits can both come from the check bits of the FEC encoding; for another example, one bit comes from the third bit set and the other bit comes from the check bits of the FEC encoding.

[0008] In this embodiment, for future metropolitan area telecommunication transmission and metropolitan area DCI interconnection scenarios, DP-64QAM will be adopted in combination with FEC encoding and PCS processing technology to meet longer transmission distances. The introduction of PCS processing requires that, in the symbol mapping operation, the symbol bits mapped to one modulation symbol are equally probable 0 and 1, and the amplitude bits mapped to one modulation symbol are not equally probable 0 and 1. More specifically, the probabilities of the levels 1, 3, 5, and 7 corresponding to the amplitude bits mapped to one modulation symbol are not exactly the same. The probabilities of the levels 1, 3, 5, and 7 appearing are jointly determined by the two amplitude bits, both of which come from the second bit set. If the two amplitude bits are not distinguished in processing, the probabilities of 0 and 1 appearing in the two amplitude bits must be the same, resulting in the probabilities of the levels 3 and 5 appearing being the same, and the probabilities of the four levels appearing deviating from the distribution corresponding to the best probability constellation shaping in theory. If the two amplitude bits are processed separately, the probabilities of 0 and 1 appearing in the two amplitude bits can be allowed to be different, resulting in the probabilities of the levels 3 and 5 appearing being different, and the probabilities of the four levels appearing being closer to the distribution corresponding to the best probability constellation shaping in theory, so that the overall performance is further improved.

[0009] Taking OFEC encoding as an example, in order to avoid affecting the existing OFEC encoding and OFEC interleaver, a new interleaver is introduced after OFEC encoding and before symbol mapping operation, so that the 0 and 1 bits obtained after PCS processing can be mapped to the amplitude bits of the modulation symbol, the probability of the constellation point is changed while the position of the constellation point is kept unchanged, the constellation point is non-uniformly distributed, and the overall performance is improved, so as to meet the demand of longer transmission distance in the future.

[0010] In some possible embodiments, the error bit rate of the first type of bits is less than the error bit rate of the second type of bits. It should be understood that the distance between different constellation points of the first type of bits on the constellation diagram is greater than the distance between different constellation points of the second type of bits. That is, if the first type of bits is 0, the level can only be 7 or 5; if the second type of bits is 0, the level is 7; if the second type of bits is 1, the level is 5. If the first type of bits is 1, the level can only be 3 or 1; if the second type of bits is 0, the level is 3; if the second type of bits is 1, the level is 1. Therefore, the first type of bits can tolerate noise better, and has a smaller error probability than the second type of bits.

[0011] In some possible embodiments, the probability of the first type of bits taking the value 1 is P cs0；1 , the probability of the first type of bits taking the value 0 is P cs0；0 , the probability of the second type of bits taking the value 1 is P cs1；1 , and the probability of the second type of bits taking the value 0 is P cs1；0 . The difference between the sum of the probabilities of levels 1 and 3 and the sum of the probabilities of levels 5 and 7 is |P cs0；1 -P cs0；0 |, and the difference between the sum of the probabilities of levels 1 and 5 and the sum of the probabilities of levels 3 and 7 is |P cs1；1 -P cs1；0 |. Wherein, when |P cs0；1 -P cs0；0 |≥|P cs1；1 -P cs1；0 |, according to the theoretically best distribution, the probabilities of levels 1, 3, 5 and 7 decrease in turn, so as to achieve the lowest average symbol energy.

[0012] In some possible embodiments, the first bit set includes L PCS first bit subsets, and the PCS processing of the first bit set to obtain the second bit set includes: performing first PCS sub-processing on k pcs_0 bits in each first bit subset to obtain n pcs_0 first bits; and performing second PCS sub-processing on the other k pcs_1Each bit is processed by the second PCS subprocess to obtain n. pcs_1 The first bit; for n pcs_0 The first bit and n pcs_1 Perform bit mapping on the first bit to obtain n pcs_0 The second bit and n pcs_1 The second bit. Where, n pcs_0 The second bit includes the first type of bit, n pcs_1 The second bit includes a second type of bit, k pcs_0 and k pcs_1 All are integers greater than or equal to 1, n pcs_0 >k pcs_0 n pcs_1 >k pcs_1 n pcs_0 =n pcs_1 It should be understood that the probabilities of 0 and 1 appearing in the first and second types of bits may be different. Therefore, it is advisable to process them separately using the first and second PCS sub-processes to facilitate the distinction between the first and second types of bits. By designing the bit mapping, it is beneficial to reduce the number of erroneous bits under the same symbol error rate. Furthermore, PCS processing can be implemented through multiple PCS sub-processes, which helps to reduce the complexity of PCS processing, and the implementation of a single PCS sub-process is simpler.

[0013] In some possible implementations, for n pcs_0 The first bit and n pcs_1 Perform bit mapping on the first bit to obtain n pcs_0 The second bit and n pcs_1 The second bit includes: obtaining n pcs_0 Bits a and n in the first bit pcs_1 Bit b from the first bit is used to perform bit mapping on bits a and b to obtain bits a and a∧b. Where n pcs_0 The second bit includes bits a, n pcs_1 The second bit consists of bits a∧b, where ∧ represents the XOR operation. It should be understood that this bit mapping rule ensures that the constellation diagram satisfies the Gray mapping, where the Hamming distance between the bit values ​​corresponding to adjacent constellation points is 1, i.e., the minimum Hamming distance, which is beneficial for performance improvement. Furthermore, the XOR operation is a relatively simple way to satisfy this relationship.

[0014] In some possible implementations, n pcs_0 The probability P that the first bit is 1 cs0；1 The probability P of a bit being 0 cs0；0 P cs0；0 +P cs0；1 =1. n pcs_1The probability P that a first bit takes the value 1 cs1；1 The probability P that a bit takes the value 0 cs1；0 , P cs1；0 + P cs1；1 = 1. The value 1 of a bit corresponds to a level with a smaller average amplitude, for example, level 1 and level 3 in the first type of bits, and for example, level 1 and level 5 in the second type of bits. The value 0 of a bit corresponds to a level with a larger average amplitude, for example, level 5 and level 7 in the first type of bits, and for example, level 3 and level 7 in the second type of bits. It should be understood that in a PCS with better performance, the probability of occurrence of low levels is higher, and therefore, the probability of the value 1 of a bit is higher than the probability of the value 0 of a bit, which is conducive to achieving the lowest average symbol energy and thus improving performance.

[0015] In some possible implementation manners, k pcs_0 < k pcs_1 , P cs0；1 > P cs1；1 , P cs0；0 < P cs1；0 . Alternatively, k pcs_0 = k pcs_1 , P cs0；1 = P cs1；1 , P cs0；0 = P cs1；0 . This is conducive to achieving the lowest average symbol energy and thus improving performance.

[0016] In some possible implementation manners, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, the seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, a total of 336 second bit subsets, each second bit subset includes 16 rows and 16 columns, a total of 256 bits, and a bit distribution pattern of the second bit subset is used to represent positions of bits from the first type of bits in the second bit subset, positions of bits from the second type of bits in the second bit subset, and positions of bits from the third bit set or the check bits of the FEC encoding in the second bit subset. The bit distribution patterns of the second bit subsets of different rows in the two seventh bit sets are introduced as follows. Through this design manner, interleaving between square matrices can be matched to be processed in an 8-bit granularity, and the overall data processing operation can be facilitated to be simple, low in complexity, and low in power consumption.

[0017] The bit distribution patterns of the second bit subsets of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the seventh bit set 1 are first bit distribution patterns.

[0018] The bit distribution pattern of the second bit subsets of the 1st, 4th, 7th, 10th, 13th, 16th, 19th, 21st, 24th, 27th, 30th, 33rd, 36th and 39th rows in the 7th bit set 1 is the second bit distribution pattern.

[0019] The bit distribution pattern of the second bit subsets of the 2nd, 5th, 8th, 11th, 14th, 17th, 20th, 22nd, 25th, 28th, 31st, 34th, 37th and 40th rows in the 7th bit set 1 is the third bit distribution pattern.

[0020] The bit distribution pattern of the second bit subsets of the 0th, 3rd, 6th, 9th, 12th, 15th, 18th, 23rd, 26th, 29th, 32nd, 35th, 38th and 41st rows in the 7th bit set 2 is the third bit distribution pattern.

[0021] The bit distribution pattern of the second bit subsets of the 1st, 4th, 7th, 10th, 13th, 16th, 19th, 21st, 24th, 27th, 30th, 33rd, 36th and 39th rows in the 7th bit set 2 is the first bit distribution pattern.

[0022] The bit distribution pattern of the second bit subsets of the 2nd, 5th, 8th, 11th, 14th, 17th, 20th, 22nd, 25th, 28th, 31st, 34th, 37th and 40th rows in the 7th bit set 2 is the second bit distribution pattern.

[0023] Specifically, the first bit distribution pattern is shown in FIG. 23(a), the second bit distribution pattern is shown in FIG. 23(b), and the third bit distribution pattern is shown in FIG. 23(c).

[0024] In some possible implementation, the second interleaving on the two sixth bit sets respectively to obtain two seventh bit sets comprises: fourth interleaving on the two sixth bit sets respectively to obtain two ninth bit sets, wherein the two ninth bit sets comprise a ninth bit set 1 and a ninth bit set 2, the ninth bit set 1 and the ninth bit set 2 each comprise 42 rows and 8 columns, that is, 336 third bit subsets, and each third bit subset comprises 16 rows and 16 columns, that is, 256 bits; and fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used for interleaving 16 bits in each row of each third bit subset in the ninth bit set. That is, the operation of the second interleaving can be implemented in two steps, that is, the fourth interleaving and the fifth interleaving, and the fifth interleaving can be understood as a way of in-row interleaving bits in each row of the second bit subset, and the flexibility of the implementation of the scheme is improved through the design.

[0025] In some possible implementation, the bit distribution pattern of the third bit subset is used to represent the positions of the bits from the first type of bits in the third bit subset, the positions of the bits from the second type of bits in the third bit subset, and the positions of the bits from the third bit set or the check bits of the FEC encoding in the third bit subset. The bit distribution patterns of the third bit subsets in different rows in the two ninth bit sets are introduced below, and the design can match the processing of the inter-matrix interleaving with 8 bits as the granularity, and is beneficial to ensuring that the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0026] The bit distribution pattern of the third bit subsets in the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the ninth bit set 1 is the fourth bit distribution pattern;

[0027] The bit distribution pattern of the third bit subsets in the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the ninth bit set 1 is the fifth bit distribution pattern;

[0028] The bit distribution pattern of the third bit subsets in the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the ninth bit set 1 is the sixth bit distribution pattern;

[0029] The bit distribution pattern of the third subset of bits in the 0th row, 3rd row, 6th row, 9th row, 12th row, 15th row, 18th row, 23rd row, 26th row, 29th row, 32nd row, 35th row, 38th row and 41st row in the 9th bit set 2 is the sixth bit distribution pattern;

[0030] The bit distribution pattern of the third subset of bits in the 1st row, 4th row, 7th row, 10th row, 13th row, 16th row, 19th row, 21st row, 24th row, 27th row, 30th row, 33rd row, 36th row and 39th row in the 9th bit set 2 is the fourth bit distribution pattern;

[0031] The bit distribution pattern of the third subset of bits in the 2nd row, 5th row, 8th row, 11th row, 14th row, 17th row, 20th row, 22nd row, 25th row, 28th row, 31st row, 34th row, 37th row and 40th row in the 9th bit set 2 is the fifth bit distribution pattern.

[0032] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c). Alternatively, the fourth bit distribution pattern is shown in FIG. 28(a), the fifth bit distribution pattern is shown in FIG. 28(b), and the sixth bit distribution pattern is shown in FIG. 28(c). Alternatively, the fourth bit distribution pattern is shown in FIG. 49(a), the fifth bit distribution pattern is shown in FIG. 49(b), and the sixth bit distribution pattern is shown in FIG. 49(c).

[0033] In some possible implementation, the 2 sixth bit sets include a sixth bit set 1 and a sixth bit set 2, each of the sixth bit set 1 and the sixth bit set 2 includes 42 rows and 8 columns of 336 fourth bit subsets, and each of the fourth bit subsets includes 16 rows and 16 columns of 256 bits. In the 42 rows and 8 columns of 336 fourth bit subsets, the bits in the fourth bit subsets in the 0th column to the 4th column are from the second bit set and the third bit set, the bits in the fourth bit subset in the 5th column and the bits in the 0th column to the 14th column in the fourth bit subset in the 6th column are from the second bit set, and the bits in the 15th column in the fourth bit subset in the 6th column and the bits in the fourth bit subset in the 7th column are check bits for FEC encoding. This implementation provides a bit distribution manner in the sixth bit set, i.e., where each part of bits in the sixth bit set comes from, and guarantees the implementation effect of the scheme.

[0034] In some possible implementation manners, the bit distribution pattern of the fourth bit subset is used to represent the positions of the bits from the first type of bits in the fourth bit subset, the positions of the bits from the second type of bits in the fourth bit subset, and the positions of the bits from the third bit set or the check bits of the FEC encoding in the fourth bit subset. The bit distribution patterns of the fourth bit subset of different rows in the two sixth bit sets are introduced as follows, and by this design manner, the interleaving between the square matrices can be processed in the granularity of 8 bits, and the overall data processing operation can be facilitated to be simple, low in complexity, and low in power consumption.

[0035] The bit distribution pattern of the fourth bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row of the 0th column to the 3rd column in the first sixth bit set is a fourth bit distribution pattern.

[0036] The bit distribution pattern of the fourth bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row of the 0th column to the 3rd column in the first sixth bit set is a fifth bit distribution pattern.

[0037] The bit distribution pattern of the fourth bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row of the 0th column to the 3rd column in the first sixth bit set is a sixth bit distribution pattern.

[0038] The bit distribution pattern of the fourth bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row of the 0th column to the 3rd column in the second sixth bit set is a sixth bit distribution pattern.

[0039] The bit distribution pattern of the fourth bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row of the 0th column to the 3rd column in the second sixth bit set is a fourth bit distribution pattern.

[0040] The bit distribution pattern of the fourth bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row of the 0th column to the 3rd column in the second sixth bit set is a fifth bit distribution pattern.

[0041] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c).

[0042] In some possible implementation manners, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, the seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, a total of 336 second bit subsets, each second bit subset includes 16 rows and 16 columns, a total of 256 bits, and a bit distribution pattern of the second bit subset is used to represent positions of bits from the first type of bits in the second bit subset, positions of bits from the second type of bits in the second bit subset, and positions of bits from the third bit set or the check bits of the FEC encoding in the second bit subset. The bit distribution patterns of the second bit subsets of different rows in the two seventh bit sets are introduced as follows. In this way, the interleaving between the square matrices is processed in a granularity of 16 bits, and the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0043] The bit distribution pattern of the second bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the seventh bit set 1 is the first bit distribution pattern.

[0044] The bit distribution pattern of the second bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the seventh bit set 1 is the second bit distribution pattern.

[0045] The bit distribution pattern of the second bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the seventh bit set 1 is the third bit distribution pattern.

[0046] The bit distribution pattern of the second bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the seventh bit set 2 is the second bit distribution pattern.

[0047] The bit distribution pattern of the second bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row and the 41st row in the 7th bit set 2 is the third bit distribution pattern.

[0048] The bit distribution pattern of the second bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row and the 39th row in the 7th bit set 2 is the first bit distribution pattern.

[0049] Specifically, the first bit distribution pattern is shown in FIG. 23(a), the second bit distribution pattern is shown in FIG. 23(b), and the third bit distribution pattern is shown in FIG. 23(c).

[0050] In some possible implementation, the second interleaving on the two sixth bit sets respectively to obtain the two seventh bit sets comprises: fourth interleaving on the two sixth bit sets respectively to obtain two ninth bit sets, wherein the two ninth bit sets comprise a ninth bit set 1 and a ninth bit set 2, and each of the ninth bit set 1 and the ninth bit set 2 comprises 42 rows and 8 columns, i.e. 336 third bit subsets, and each third bit subset comprises 16 rows and 16 columns, i.e. 256 bits. Fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used for interleaving 16 bits in each row of each third bit subset in the ninth bit set.

[0051] In some possible implementation, the bit distribution pattern of the third bit subset is used to represent the position of the bit from the first type of bit in the third bit subset, the position of the bit from the second type of bit in the third bit subset, and the position of the bit from the third bit set or the check bit of the FEC encoding in the third bit subset. The bit distribution patterns of the third bit subsets of different rows in the two ninth bit sets are introduced as follows, and by this design, the interleaving between square matrices can be processed in 16-bit granularity, and the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0052] The bit distribution pattern of the third bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row and the 40th row in the ninth bit set 1 is the fourth bit distribution pattern.

[0053] The bit distribution pattern of the third subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-third row, the twenty-sixth row, the twenty-ninth row, the thirty-second row, the thirty-fifth row, the thirty-eighth row, and the forty-first row in the ninth bit set 1 is the fifth bit distribution pattern.

[0054] The bit distribution pattern of the third subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row in the ninth bit set 1 is the sixth bit distribution pattern.

[0055] The bit distribution pattern of the third subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-third row, the twenty-sixth row, the twenty-ninth row, the thirty-second row, the thirty-fifth row, the thirty-eighth row, and the forty-first row in the ninth bit set 2 is the sixth bit distribution pattern.

[0056] The bit distribution pattern of the third subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row in the ninth bit set 2 is the fourth bit distribution pattern.

[0057] The bit distribution pattern of the third subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row in the ninth bit set 2 is the fourth bit distribution pattern.

[0058] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c).

[0059] In some possible implementation, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2, each of the sixth bit set 1 and the sixth bit set 2 includes 42 rows and 8 columns of 336 fourth bit subsets, and each of the fourth bit subsets includes 16 rows and 16 columns of 256 bits. In the 42 rows and 8 columns of 336 fourth bit subsets, the bits in the fourth bit subsets in the first column to the fourth column are from the second bit set and the third bit set, the bits in the fourth bit subset in the fifth column and the bits in the fourth bit subset in the sixth column from the zero column to the fourteenth column are from the second bit set, the bits in the fourth bit subset in the fifteenth column in the sixth column and the bits in the fourth bit subset in the seventh column are check bits for FEC encoding.

[0060] In some possible implementation manners, the bit distribution pattern of the fourth bit subset is used to represent the positions of the bits from the first type of bits in the fourth bit subset, the positions of the bits from the second type of bits in the fourth bit subset, and the positions of the bits from the third bit set or the check bits of the FEC encoding in the fourth bit subset. The bit distribution patterns of the fourth bit subset of different rows in the two sixth bit sets are introduced as follows, and by this design manner, the interleaving between the square matrices can be processed in a granularity of 16 bits, and the overall data processing operation can be facilitated to be simple, low in complexity, and low in power consumption.

[0061] The bit distribution pattern of the fourth bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row of the 0th column to the 3rd column in the first sixth bit set is a fourth bit distribution pattern.

[0062] The bit distribution pattern of the fourth bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row of the 0th column to the 3rd column in the first sixth bit set is a fifth bit distribution pattern.

[0063] The bit distribution pattern of the fourth bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row of the 0th column to the 3rd column in the first sixth bit set is a sixth bit distribution pattern.

[0064] The bit distribution pattern of the fourth bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row of the 0th column to the 3rd column in the second sixth bit set is a fifth bit distribution pattern.

[0065] The bit distribution pattern of the fourth bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row of the 0th column to the 3rd column in the second sixth bit set is a sixth bit distribution pattern.

[0066] The bit distribution pattern of the fourth bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row of the 0th column to the 3rd column in the second sixth bit set is a fourth bit distribution pattern.

[0067] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c).

[0068] In some possible implementation, the 0th bit, the 2nd bit, the 4th bit, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the first polarization symbol, and the 1st bit, the 3rd bit, the 5th bit, the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second polarization symbol.

[0069] In some possible implementation, the 0th bit, the 2nd bit and the 4th bit of the 12 bits are used to map to the first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 1st bit, the 3rd bit and the 5th bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol. The 2nd bit, the 3rd bit, the 8th bit and the 9th bit are from the first type of bits, and the 4th bit, the 5th bit, the 10th bit and the 11th bit are from the second type of bits. Here, a specific mapping rule 1 of mapping 12 bits to obtain a dual-polarization symbol is provided, which improves the realizability of the scheme.

[0070] In some possible implementation, the 0th bit, the 4th bit and the 6th bit of the 12 bits are used to map to the first component of the first polarization symbol, the 2nd bit, the 8th bit and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 1st bit, the 5th bit and the 7th bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 3rd bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol. The 4th bit, the 5th bit, the 8th bit and the 9th bit are from the first type of bits, and the 6th bit, the 7th bit, the 10th bit and the 11th bit are from the second type of bits. Here, another specific mapping rule 2 of mapping 12 bits to obtain a dual-polarization symbol is provided, which enriches the implementation of the scheme.

[0071] In some possible implementation manners, the 8th bit, the 0th bit and the 2nd bit of the 12 bits are used for mapping to the first component of the first polarization symbol, the 10th bit, the 4th bit and the 6th bit of the 12 bits are used for mapping to the second component of the first polarization symbol, the 9th bit, the 1st bit and the 3rd bit of the 12 bits are used for mapping to the first component of the second polarization symbol, and the 11th bit, the 5th bit and the 7th bit of the 12 bits are used for mapping to the second component of the second polarization symbol. The 0th bit, the 1st bit, the 4th bit and the 5th bit are from the first type of bits, and the 2nd bit, the 3rd bit, the 6th bit and the 7th bit are from the second type of bits. Another specific mapping rule 3 for mapping 12 bits to obtain a dual-polarization symbol is provided herein, which enriches the implementation manners of the scheme.

[0072] In some possible implementation manners, the 4th bit, the 0th bit and the 2nd bit of the 12 bits are used for mapping to the first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used for mapping to the second component of the first polarization symbol, the 5th bit, the 1st bit and the 3rd bit of the 12 bits are used for mapping to the first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used for mapping to the second component of the second polarization symbol. The 0th bit, the 1st bit, the 8th bit and the 9th bit are from the first type of bits, and the 2nd bit, the 3rd bit, the 10th bit and the 11th bit are from the second type of bits. Another specific mapping rule 4 for mapping 12 bits to obtain a dual-polarization symbol is provided herein, which enriches the implementation manners of the scheme.

[0073] In some possible implementation manners, the 0th bit, the 1st bit, the 2nd bit, the 3rd bit, the 4th bit and the 5th bit of the 12 bits are used for mapping to the first polarization symbol, and the 6th bit, the 7th bit, the 8th bit, the 9th bit, the 10th bit and the 11th bit of the 12 bits are used for mapping to the second polarization symbol.

[0074] In some possible implementation manners, the 0th bit, the 1st bit and the 2nd bit of the 12 bits are used to map to a first component of a first polarization symbol, the 3rd bit, the 4th bit and the 5th bit of the 12 bits are used to map to a second component of the first polarization symbol, the 6th bit, the 7th bit and the 8th bit of the 12 bits are used to map to a first component of a second polarization symbol, and the 9th bit, the 10th bit and the 11th bit of the 12 bits are used to map to a second component of the second polarization symbol. The 1st bit, the 4th bit, the 7th bit and the 10th bit are from a first type of bits, and the 2nd bit, the 5th bit, the 8th bit and the 11th bit are from a second type of bits.

[0075] In some possible implementation manners, a polarization direction of the first polarization symbol and a polarization direction of the second polarization symbol are mutually orthogonal. The first component is an I component, and the second component is a Q component; or, the first component is a Q component, and the second component is an I component.

[0076] In some possible implementation manners, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. The third interleaving on the two seventh bit sets to obtain the eighth bit set includes: intra-square matrix interleaving on the seventh bit set 1 to obtain a tenth bit set 1, intra-square matrix interleaving on the seventh bit set 2 to obtain a tenth bit set 2, and the tenth bit set 1 and the tenth bit set 2 each include 42 rows and 8 columns, i.e., 336 fifth bit subsets, and each fifth bit subset includes 16 rows and 16 columns, i.e., 256 bits. Inter-square matrix interleaving on the tenth bit set 1 and the tenth bit set 2 to obtain the eighth bit set, and the eighth bit set includes 84 rows and 8 columns, i.e., 672 fifth bit subsets. Here, a specific implementation manner of the third interleaving is provided, i.e., the third interleaving includes intra-square matrix interleaving and inter-square matrix interleaving, which improves practicability of the scheme.

[0077] In some possible implementation manners, the first bit set includes a first bit set 1 and a first bit set 2. The PCS processing on the first bit set in the plurality of bits to obtain the second bit set includes: PCS processing on the first bit set 1 to obtain a second bit set 1, and PCS processing on the first bit set 2 to obtain a second bit set 2, and the second bit set includes the second bit set 1 and the second bit set 2. It should be understood that the two PCS processes are implemented, which is beneficial to reducing complexity of a single PCS process, and hardware implementation of the single PCS process is simpler.

[0078] In some possible implementation manners, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving of the second bit set and the third bit set other than the first bit set in the plurality of bits to obtain the fourth bit set 1 and the fourth bit set 2 includes: first interleaving the second bit set 1, the second bit set 2, the third bit set 1 and the third bit set 2 to obtain the fourth bit set 1 and the fourth bit set 2.

[0079] In some possible implementation manners, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving of the second bit set and the third bit set other than the first bit set in the plurality of bits to obtain the fourth bit set 1 and the fourth bit set 2 includes: first interleaving the second bit set 1 and the third bit set 1 to obtain the fourth bit set 1, and first interleaving the second bit set 2 and the third bit set 2 to obtain the fourth bit set 2. It should be understood that the first interleaving is divided into two to reduce the complexity of a single first interleaving, and the hardware implementation of a single first interleaving is simpler.

[0080] In some possible implementation manners, the first interleaving of the second bit set and the third bit set other than the first bit set in the plurality of bits to obtain the fourth bit set 1 and the fourth bit set 2 includes: first interleaving the second bit set 1, the second bit set 2 and the third bit set to obtain the fourth bit set 1 and the fourth bit set 2.

[0081] In some possible implementation manners, the first type of amplitude bits mapped to the dual-polarization symbol are from the first type of bits, the second type of amplitude bits mapped to the dual-polarization symbol are from the second type of bits, and the sign bits mapped to the dual-polarization symbol are from the third bit set or the check bits of the FEC encoding.

[0082] In some possible implementation manners, the data processing method is applied to scenarios including an Ethernet, an optical transport network and space optical communication.

[0083] In a second aspect, an embodiment of the present application provides a data processing apparatus. The data processing apparatus comprises: a PCS unit, a first interleaving unit, an FEC encoding unit, a second interleaving unit and a third interleaving unit. The PCS unit is configured to: perform probability constellation shaping (PCS) processing on a first bit set in a plurality of bits to obtain a second bit set, half of the bits in the second bit set being first type bits and the other half of the bits in the second bit set being second type bits. The first interleaving unit is configured to: perform first interleaving on the second bit set and a third bit set in the plurality of bits other than the first bit set to obtain a fourth bit set 1 and a fourth bit set 2. The FEC encoding unit is configured to: perform forward error correction (FEC) encoding on two fifth bit sets respectively to obtain two sixth bit sets, a fifth bit set 1 in the two fifth bit sets comprising at least one fourth bit set 1, and a fifth bit set 2 in the two fifth bit sets comprising at least one fourth bit set 2. The second interleaving unit is configured to: perform second interleaving on the two sixth bit sets respectively to obtain two seventh bit sets. The third interleaving unit is configured to: perform third interleaving on the two seventh bit sets to obtain an eighth bit set.

[0084] It should be noted that 12 consecutive bits in the eighth bit set are used for mapping to obtain one dual-polarization symbol, the dual-polarization symbol comprising a first polarization symbol and a second polarization symbol, the first polarization symbol can also be denoted as an X polarization symbol, and the second polarization symbol can also be denoted as a Y polarization symbol. A first group of 2 bits in the 12 bits for mapping to the first polarization symbol is from the first type bits, a second group of 2 bits in the 12 bits for mapping to the first polarization symbol is from the second type bits, and a third group of 2 bits in the 12 bits for mapping to the first polarization symbol is from the third bit set or a check bit of the FEC encoding. A first group of 2 bits in the 12 bits for mapping to the second polarization symbol is from the first type bits, a second group of 2 bits in the 12 bits for mapping to the second polarization symbol is from the second type bits, and a third group of 2 bits in the 12 bits for mapping to the second polarization symbol is from the third bit set or a check bit of the FEC encoding.

[0085] In some possible implementation manners, an error bit rate of the first type bits is less than an error bit rate of the second type bits.

[0086] In some possible implementation manners, a probability of a bit in the first type bits being 1 is P 0；1 , a probability of a bit in the first type bits being 0 is P 0；0 , a probability of a bit in the second type bits being 1 is P 1；1 , a probability of a bit in the second type bits being 0 is P 1；0 , P 0；1 -P 0；0 is greater than or equal to P1；1 -P 1；0 the absolute value of the difference between the two values.

[0087] In some possible implementation, the first bit set includes L PCS first bit subsets. The PCS unit is specifically configured to: perform a first PCS sub-process on k pcs_0 bits of each first bit subset to obtain n pcs_0 first bits; perform a second PCS sub-process on another k pcs_1 bits of each first bit subset to obtain n pcs_1 first bits; perform bit mapping on the n pcs_0 first bits and the n pcs_1 first bits to obtain n pcs_0 second bits and n pcs_1 second bits. The n pcs_0 second bits include first type bits, and the n pcs_1 second bits include second type bits, k pcs_0 and k pcs_1 are integers greater than or equal to 1, n pcs_0 >k pcs_0 , n pcs_1 >k pcs_1 , n pcs_0 =n pcs_1 .

[0088] In some possible implementation, the PCS unit is specifically configured to: obtain a bit a in the n pcs_0 first bits and a bit b in the n pcs_1 first bits, and perform bit mapping on the bit a and the bit b to obtain a bit a and a bit a∧b. The n pcs_0 second bits include the bit a, and the n pcs_1 second bits include the bit a∧b, and ∧ represents XOR operation.

[0089] In some possible implementation, a probability P pcs_0 that a bit in the n cs0；1 first bits takes a value of 1 is greater than a probability P cs0；0 that the bit takes a value of 0, and P cs0；0 +P cs0；1 =1. A probability P pcs_1 that a bit in the n cs1；1 first bits takes a value of 1 is greater than a probability P cs1；0 that the bit takes a value of 0, and P cs1；0 +P cs1；1 =1.

[0090] In some possible implementation, k pcs_0 <kpcs_1 , P cs0；1 > P cs1；1 , P cs0；0 < P cs1；0 Alternatively, k pcs_0 = k pcs_1 , P cs0；1 = P cs1；1 , P cs0；0 = P cs1；0 .

[0091] In some possible implementation manners, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, the seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, a total of 336 second bit subsets, the second bit subset includes 16 rows and 16 columns, a total of 256 bits, and a bit distribution pattern of the second bit subset is used to represent positions of bits from the first type of bits in the second bit subset, positions of bits from the second type of bits in the second bit subset, and positions of bits from the third bit set or the check bits of the FEC encoding in the second bit subset. The bit distribution patterns of the second bit subsets of different rows in the two seventh bit sets are introduced as follows, and by this design manner, the interleaving between square matrices can be processed in an 8-bit granularity, and the overall data processing operation can be facilitated to be simple, low in complexity, and low in power consumption.

[0092] The bit distribution pattern of the second bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the seventh bit set 1 is the first bit distribution pattern.

[0093] The bit distribution pattern of the second bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the seventh bit set 1 is the second bit distribution pattern.

[0094] The bit distribution pattern of the second bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the seventh bit set 1 is the third bit distribution pattern.

[0095] The bit distribution pattern of the second bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the seventh bit set 2 is the third bit distribution pattern.

[0096] The bit distribution pattern of the second subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row in the seventh bit set 2 is the first bit distribution pattern.

[0097] The bit distribution pattern of the second subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-second row, the twenty-fifth row, the twenty-eighth row, the thirty-first row, the thirty-fourth row, the thirty-seventh row, and the fortieth row in the seventh bit set 2 is the second bit distribution pattern.

[0098] Specifically, the first bit distribution pattern is shown in FIG. 23(a), the second bit distribution pattern is shown in FIG. 23(b), and the third bit distribution pattern is shown in FIG. 23(c).

[0099] In some possible implementation, the second interleaving unit is specifically configured to: perform fourth interleaving on the two sixth bit sets respectively to obtain two ninth bit sets, wherein the two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, the ninth bit set 1 and the ninth bit set 2 each include 42 rows and 8 columns, that is, 336 third bit subsets, and each third bit subset includes 16 rows and 16 columns, that is, 256 bits; and perform fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used to interleave 16 bits in each row of each third bit subset in the ninth bit set.

[0100] In some possible implementation, the bit distribution pattern of the third bit subset is used to represent the positions of bits from the first type of bits in the third bit subset, the positions of bits from the second type of bits in the third bit subset, and the positions of bits from the third bit set or the check bits of the FEC encoding in the third bit subset. The bit distribution patterns of the third bit subsets in different rows in the two ninth bit sets are introduced below. In this way, the interleaving between the square matrices can be processed in 8-bit granularity, and the overall data processing operation can be simple, the complexity can be low, and the power consumption can be low.

[0101] The bit distribution pattern of the third bit subset in the zeroth row, the third row, the sixth row, the ninth row, the twelfth row, the fifteenth row, the eighteenth row, the twenty-third row, the twenty-sixth row, the twenty-ninth row, the thirty-second row, the thirty-fifth row, the thirty-eighth row, and the forty-first row in the ninth bit set 1 is the fourth bit distribution pattern.

[0102] The bit distribution pattern of the third subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row of the ninth bit set 1 is the fifth bit distribution pattern;

[0103] The bit distribution pattern of the third subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-second row, the twenty-fifth row, the twenty-eighth row, the thirty-first row, the thirty-fourth row, the thirty-seventh row, and the fortieth row of the ninth bit set 1 is the sixth bit distribution pattern;

[0104] The bit distribution pattern of the third subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row of the ninth bit set 2 is the fourth bit distribution pattern;

[0105] The bit distribution pattern of the third subset of bits in the first row, the fourth row, the seventh row, the tenth row, the thirteenth row, the sixteenth row, the nineteenth row, the twenty-first row, the twenty-fourth row, the twenty-seventh row, the thirtieth row, the thirty-third row, the thirty-sixth row, and the thirty-ninth row of the ninth bit set 2 is the fourth bit distribution pattern;

[0106] The bit distribution pattern of the third subset of bits in the second row, the fifth row, the eighth row, the eleventh row, the fourteenth row, the seventeenth row, the twentieth row, the twenty-second row, the twenty-fifth row, the twenty-eighth row, the thirty-first row, the thirty-fourth row, the thirty-seventh row, and the fortieth row of the ninth bit set 2 is the fifth bit distribution pattern.

[0107] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c). Alternatively, the fourth bit distribution pattern is shown in FIG. 28(a), the fifth bit distribution pattern is shown in FIG. 28(b), and the sixth bit distribution pattern is shown in FIG. 28(c). Alternatively, the fourth bit distribution pattern is shown in FIG. 49(a), the fifth bit distribution pattern is shown in FIG. 49(b), and the sixth bit distribution pattern is shown in FIG. 49(c).

[0108] In some possible implementation manners, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2, the sixth bit set 1 and the sixth bit set 2 each include 42 rows and 8 columns, that is, 336 fourth bit subsets, and the fourth bit subset includes 16 rows and 16 columns, that is, 256 bits. In the 42 rows and 8 columns, that is, 336 fourth bit subsets, the bits in the fourth bit subsets in the 0th column to the 4th column are from the second bit set and the third bit set, the bits in the fourth bit subset in the 5th column and the bits in the 0th column to the 14th column in the fourth bit subset in the 6th column are from the second bit set, the bits in the 15th column in the fourth bit subset in the 6th column and the bits in the fourth bit subset in the 7th column are check bits for FEC encoding.

[0109] In some possible implementation manners, the bit distribution pattern of the fourth bit subset is used to represent the positions of the bits from the first type of bits in the fourth bit subset, the positions of the bits from the second type of bits in the fourth bit subset, and the positions of the bits from the third bit set or the check bits for FEC encoding in the fourth bit subset. The bit distribution patterns of the fourth bit subsets in different rows in the two sixth bit sets are described below. In this way, the interleaving between the square matrices is processed in 8-bit granularity, and the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0110] The bit distribution pattern of the fourth bit subsets in the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the 0th column to the 3rd column in the sixth bit set 1 is a fourth bit distribution pattern.

[0111] The bit distribution pattern of the fourth bit subsets in the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the 0th column to the 3rd column in the sixth bit set 1 is a fifth bit distribution pattern.

[0112] The bit distribution pattern of the fourth bit subsets in the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the 0th column to the 3rd column in the sixth bit set 1 is a sixth bit distribution pattern.

[0113] The bit distribution pattern of the fourth bit subsets in the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the 0th column to the 3rd column in the sixth bit set 2 is a sixth bit distribution pattern.

[0114] The bit distribution pattern of the fourth subset of bits of the 1st row, 4th row, 7th row, 10th row, 13th row, 16th row, 19th row, 21st row, 24th row, 27th row, 30th row, 33rd row, 36th row, and 39th row of the 0th column to the 3rd column in the sixth bit set 2 is a fourth bit distribution pattern.

[0115] The bit distribution pattern of the fourth subset of bits of the 1st row, 4th row, 7th row, 10th row, 13th row, 16th row, 19th row, 21st row, 24th row, 27th row, 30th row, 33rd row, 36th row, and 39th row of the 0th column to the 3rd column in the sixth bit set 2 is a fourth bit distribution pattern.

[0116] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c).

[0117] In some possible implementation, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, each of the seventh bit set 1 and the seventh bit set 2 includes 42 rows and 8 columns, a total of 336 second subsets of bits, each of the second subsets of bits includes 16 rows and 16 columns, a total of 256 bits, and the bit distribution pattern of the second subset of bits is used to represent the positions of the bits from the first type of bits, the positions of the bits from the second type of bits, and the positions of the bits from the third bit set or the check bits of the FEC encoding in the second subset of bits. The bit distribution patterns of the second subsets of bits of different rows in the two seventh bit sets are introduced as follows. In this way, the interleaving between the square matrices can be processed in 16-bit granularity, and the overall data processing operation can be simple, the complexity can be low, and the power consumption can be low.

[0118] The bit distribution pattern of the second subset of bits of the 0th row, 3rd row, 6th row, 9th row, 12th row, 15th row, 18th row, 22nd row, 25th row, 28th row, 31st row, 34th row, 37th row, and 40th row in the seventh bit set 1 is a first bit distribution pattern.

[0119] The bit distribution pattern of the second subset of bits of the 1st row, 4th row, 7th row, 10th row, 13th row, 16th row, 19th row, 23rd row, 26th row, 29th row, 32nd row, 35th row, 38th row, and 41st row in the seventh bit set 1 is a second bit distribution pattern.

[0120] The bit distribution pattern of the second bit subsets of the 2nd row, 5th row, 8th row, 11th row, 14th row, 17th row, 20th row, 21st row, 24th row, 27th row, 30th row, 33rd row, 36th row and 39th row in the 7th bit set 1 is the third bit distribution pattern.

[0121] The bit distribution pattern of the second bit subsets of the 0th row, 3rd row, 6th row, 9th row, 12th row, 15th row, 18th row, 22nd row, 25th row, 28th row, 31st row, 34th row, 37th row and 40th row in the 7th bit set 2 is the second bit distribution pattern.

[0122] The bit distribution pattern of the second bit subsets of the 1st row, 4th row, 7th row, 10th row, 13th row, 16th row, 19th row, 23rd row, 26th row, 29th row, 32nd row, 35th row, 38th row and 41st row in the 7th bit set 2 is the third bit distribution pattern.

[0123] The bit distribution pattern of the second bit subsets of the 2nd row, 5th row, 8th row, 11th row, 14th row, 17th row, 20th row, 21st row, 24th row, 27th row, 30th row, 33rd row, 36th row and 39th row in the 7th bit set 2 is the first bit distribution pattern.

[0124] Specifically, the first bit distribution pattern is shown in FIG. 23(a), the second bit distribution pattern is shown in FIG. 23(b), and the third bit distribution pattern is shown in FIG. 23(c).

[0125] In some possible implementation, the second interleaving unit is specifically configured to: perform fourth interleaving on the two sixth bit sets respectively to obtain two ninth bit sets, wherein the two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, the ninth bit set 1 and the ninth bit set 2 each include 42 rows and 8 columns, i.e., 336 third bit subsets, and each third bit subset includes 16 rows and 16 columns, i.e., 256 bits; and perform fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used for interleaving 16 bits in each row of each third bit subset in the ninth bit set.

[0126] In some possible implementation manners, the bit distribution pattern of the third bit subset is used to represent the positions of the bits from the first type of bits in the third bit subset, the positions of the bits from the second type of bits in the third bit subset, and the positions of the bits from the third bit set or the check bits of the FEC encoding in the third bit subset. The bit distribution patterns of the third bit subsets of different rows in the two ninth bit sets are introduced as follows, and by this design manner, the interleaving between the square matrices can be processed in a granularity of 16 bits, and the overall data processing operation can be facilitated to be simple, low in complexity, and low in power consumption.

[0127] The bit distribution pattern of the third bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the first ninth bit set is the fourth bit distribution pattern.

[0128] The bit distribution pattern of the third bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the first ninth bit set is the fifth bit distribution pattern.

[0129] The bit distribution pattern of the third bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the first ninth bit set is the sixth bit distribution pattern.

[0130] The bit distribution pattern of the third bit subset of the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the second ninth bit set is the fifth bit distribution pattern.

[0131] The bit distribution pattern of the third bit subset of the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the second ninth bit set is the sixth bit distribution pattern.

[0132] The bit distribution pattern of the third bit subset of the 2nd row, the 5th row, the 8th row, the 11th row, the 14th row, the 17th row, the 20th row, the 21st row, the 24th row, the 27th row, the 30th row, the 33rd row, the 36th row, and the 39th row in the second ninth bit set is the fourth bit distribution pattern.

[0133] Specifically, the fourth bit distribution pattern is shown in Fig. 11(a), the fifth bit distribution pattern is shown in Fig. 11(b), and the sixth bit distribution pattern is shown in Fig. 11(c). Alternatively, the fourth bit distribution pattern is shown in Fig. 28(a), the fifth bit distribution pattern is shown in Fig. 28(b), and the sixth bit distribution pattern is shown in Fig. 28(c). Alternatively, the fourth bit distribution pattern is shown in Fig. 49(a), the fifth bit distribution pattern is shown in Fig. 49(b), and the sixth bit distribution pattern is shown in Fig. 49(c).

[0134] In some possible implementation, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2, each of which includes 42 rows and 8 columns, i.e., 336 fourth bit subsets, and each fourth bit subset includes 16 rows and 16 columns, i.e., 256 bits. In the 42 rows and 8 columns, i.e., 336 fourth bit subsets, the bits in the fourth bit subsets in the 0th column to the 4th column are from the second bit set and the third bit set, the bits in the fourth bit subset in the 5th column and the bits in the 0th column to the 14th column in the fourth bit subset in the 6th column are from the second bit set, and the bits in the 15th column in the fourth bit subset in the 6th column and the bits in the fourth bit subset in the 7th column are check bits for FEC encoding.

[0135] In some possible implementation, the bit distribution pattern of the fourth bit subset is used to represent the positions of the bits from the first type of bits in the fourth bit subset, the positions of the bits from the second type of bits in the fourth bit subset, and the positions of the bits from the third bit set or the check bits for FEC encoding in the fourth bit subset. The bit distribution patterns of the fourth bit subsets in different rows in the two sixth bit sets are described below. In this way, the interleaving between the square matrices is processed in 16-bit granularity, and the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0136] The bit distribution pattern of the fourth bit subset in the 0th row, the 3rd row, the 6th row, the 9th row, the 12th row, the 15th row, the 18th row, the 22nd row, the 25th row, the 28th row, the 31st row, the 34th row, the 37th row, and the 40th row in the 0th column to the 3rd column in the sixth bit set 1 is the fourth bit distribution pattern.

[0137] The bit distribution pattern of the fourth bit subset in the 1st row, the 4th row, the 7th row, the 10th row, the 13th row, the 16th row, the 19th row, the 23rd row, the 26th row, the 29th row, the 32nd row, the 35th row, the 38th row, and the 41st row in the 0th column to the 3rd column in the sixth bit set 1 is the fifth bit distribution pattern.

[0138] The bit distribution pattern of the fourth subset of bits in the 2nd, 5th, 8th, 11th, 14th, 17th, 20th, 21st, 24th, 27th, 30th, 33rd, 36th, and 39th rows of the 0th to 3rd columns in the sixth bit set 1 is a sixth bit distribution pattern.

[0139] The bit distribution pattern of the fourth subset of bits in the 0th, 3rd, 6th, 9th, 12th, 15th, 18th, 22nd, 25th, 28th, 31st, 34th, 37th, and 40th rows of the 0th to 3rd columns in the sixth bit set 2 is a fifth bit distribution pattern.

[0140] The bit distribution pattern of the fourth subset of bits in the 1st, 4th, 7th, 10th, 13th, 16th, 19th, 23rd, 26th, 29th, 32nd, 35th, 38th, and 41st rows of the 0th to 3rd columns in the sixth bit set 2 is a sixth bit distribution pattern.

[0141] The bit distribution pattern of the fourth subset of bits in the 2nd, 5th, 8th, 11th, 14th, 17th, 20th, 21st, 24th, 27th, 30th, 33rd, 36th, and 39th rows of the 0th to 3rd columns in the sixth bit set 2 is a fourth bit distribution pattern.

[0142] Specifically, the fourth bit distribution pattern is shown in FIG. 11(a), the fifth bit distribution pattern is shown in FIG. 11(b), and the sixth bit distribution pattern is shown in FIG. 11(c).

[0143] In some possible implementations, the 0th, 2nd, 4th, 6th, 8th, and 10th bits of the 12 bits are used to map to the first polarization symbol, and the 1st, 3rd, 5th, 7th, 9th, and 11th bits of the 12 bits are used to map to the second polarization symbol.

[0144] In some possible implementation manners, the 0th bit, the 2nd bit and the 4th bit of the 12 bits are used for mapping to the first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used for mapping to the second component of the first polarization symbol, the 1st bit, the 3rd bit and the 5th bit of the 12 bits are used for mapping to the first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used for mapping to the second component of the second polarization symbol. The 2nd bit, the 3rd bit, the 8th bit and the 9th bit are from the first type of bits, and the 4th bit, the 5th bit, the 10th bit and the 11th bit are from the second type of bits. A specific mapping rule 1 for mapping the 12 bits to obtain a dual-polarization symbol is provided herein, and the implementability of the scheme is improved.

[0145] In some possible implementation manners, the 0th bit, the 4th bit and the 6th bit of the 12 bits are used for mapping to the first component of the first polarization symbol, the 2nd bit, the 8th bit and the 10th bit of the 12 bits are used for mapping to the second component of the first polarization symbol, the 1st bit, the 5th bit and the 7th bit of the 12 bits are used for mapping to the first component of the second polarization symbol, and the 3rd bit, the 9th bit and the 11th bit of the 12 bits are used for mapping to the second component of the second polarization symbol. The 4th bit, the 5th bit, the 8th bit and the 9th bit are from the first type of bits, and the 6th bit, the 7th bit, the 10th bit and the 11th bit are from the second type of bits. Another specific mapping rule 2 for mapping the 12 bits to obtain a dual-polarization symbol is provided herein, and the implementability of the scheme is enriched.

[0146] In some possible implementation manners, the 8th bit, the 0th bit and the 2nd bit of the 12 bits are used for mapping to the first component of the first polarization symbol, the 10th bit, the 4th bit and the 6th bit of the 12 bits are used for mapping to the second component of the first polarization symbol, the 9th bit, the 1st bit and the 3rd bit of the 12 bits are used for mapping to the first component of the second polarization symbol, and the 11th bit, the 5th bit and the 7th bit of the 12 bits are used for mapping to the second component of the second polarization symbol. The 0th bit, the 1st bit, the 4th bit and the 5th bit are from the first type of bits, and the 2nd bit, the 3rd bit, the 6th bit and the 7th bit are from the second type of bits. Another specific mapping rule 3 for mapping the 12 bits to obtain a dual-polarization symbol is provided herein, and the implementability of the scheme is enriched.

[0147] In some possible implementation manners, the 4th bit, the 0th bit and the 2nd bit of the 12 bits are used for mapping to a first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used for mapping to a second component of the first polarization symbol, the 5th bit, the 1st bit and the 3rd bit of the 12 bits are used for mapping to a first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used for mapping to a second component of the second polarization symbol. The 0th bit, the 1st bit, the 8th bit and the 9th bit are from the first type of bits, and the 2nd bit, the 3rd bit, the 10th bit and the 11th bit are from the second type of bits. Another specific mapping rule 4 for mapping 12 bits to obtain a dual-polarization symbol is provided herein, which enriches the implementation manners of the scheme.

[0148] In some possible implementation manners, the 0th bit, the 1st bit, the 2nd bit, the 3rd bit, the 4th bit and the 5th bit of the 12 bits are used for mapping to the first polarization symbol, and the 6th bit, the 7th bit, the 8th bit, the 9th bit, the 10th bit and the 11th bit of the 12 bits are used for mapping to the second polarization symbol.

[0149] In some possible implementation manners, the 0th bit, the 1st bit and the 2nd bit of the 12 bits are used for mapping to a first component of the first polarization symbol, the 3rd bit, the 4th bit and the 5th bit of the 12 bits are used for mapping to a second component of the first polarization symbol, the 6th bit, the 7th bit and the 8th bit of the 12 bits are used for mapping to a first component of the second polarization symbol, and the 9th bit, the 10th bit and the 11th bit of the 12 bits are used for mapping to a second component of the second polarization symbol. The 1st bit, the 4th bit, the 7th bit and the 10th bit are from the first type of bits, and the 2nd bit, the 5th bit, the 8th bit and the 11th bit are from the second type of bits.

[0150] In some possible implementation manners, the polarization direction of the first polarization symbol and the polarization direction of the second polarization symbol are orthogonal to each other. The first component is an I-path component, and the second component is a Q-path component; or the first component is a Q-path component, and the second component is an I-path component.

[0151] In some possible implementation manners, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. The third interleaving unit is specifically configured to perform intra-square interleaving on the seventh bit set 1 to obtain a tenth bit set 1, and perform intra-square interleaving on the seventh bit set 2 to obtain a tenth bit set 2, where the tenth bit set 1 and the tenth bit set 2 each include 42 rows and 8 columns, that is, 336 fifth bit subsets, and each fifth bit subset includes 16 rows and 16 columns, that is, 256 bits. The tenth bit set 1 and the tenth bit set 2 are subjected to inter-square interleaving to obtain an eighth bit set, and the eighth bit set includes 84 rows and 8 columns, that is, 672 fifth bit subsets.

[0152] In some possible implementation manners, the first bit set includes a first bit set 1 and a first bit set 2. The PCS unit is specifically configured to perform PCS processing on the first bit set 1 to obtain a second bit set 1, and perform PCS processing on the first bit set 2 to obtain a second bit set 2, where the second bit set includes the second bit set 1 and the second bit set 2.

[0153] In some possible implementation manners, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving unit is specifically configured to perform first interleaving on the second bit set 1, the second bit set 2, the third bit set 1 and the third bit set 2 to obtain a fourth bit set 1 and a fourth bit set 2.

[0154] In some possible implementation manners, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving unit is specifically configured to perform first interleaving on the second bit set 1 and the third bit set 1 to obtain a fourth bit set 1, and perform first interleaving on the second bit set 2 and the third bit set 2 to obtain a fourth bit set 2.

[0155] In some possible implementation manners, the first interleaving unit is specifically configured to perform first interleaving on the second bit set 1, the second bit set 2 and the third bit set to obtain a fourth bit set 1 and a fourth bit set 2.

[0156] In some possible implementation manners, the first type of amplitude bits mapped to the dual-polarization symbol are from the first type of bits, the second type of amplitude bits mapped to the dual-polarization symbol are from the second type of bits, and the symbol bits mapped to the dual-polarization symbol are from the third bit set or the check bits of the FEC encoding.

[0157] In some possible implementation manners, the data processing method is applied to scenarios including an Ethernet, an optical transport network and space optical communication.

[0158] In a third aspect, an embodiment of the present application provides a chip, which is configured to execute the method as described in any of the embodiments of the first aspect.

[0159] In a fourth aspect, an embodiment of the present application provides an optical module. The optical module comprises a processor and an interface. The processor is configured to perform the method according to any one of the embodiments of the first aspect, and the interface is configured to transmit a signal from the processor. For example, the interface is configured to transmit the signal from the processor or transmit a received signal to the processor.

[0160] In some possible implementation, the interface is an electrical interface, and the processor is configured to transmit an electrical signal via the interface. For example, the processor performs the method according to any one of the embodiments of the first aspect and performs data processing on the eighth bit set to obtain a superframe, and transmits the superframe via the interface. The data processing includes symbol mapping, polarization division and framing. In the embodiment of the present application, the framing can also be referred to as DSP framing, and the superframe can also be referred to as DSP superframe.

[0161] In some possible implementation, the interface is an optical interface, and the optical module further comprises a modulator. For example, the processor performs the method according to any one of the embodiments of the first aspect and performs data processing on the eighth bit set to obtain a superframe, and the modulator performs signal processing such as electro-optical conversion according to the superframe to obtain an optical signal, and then transmits the optical signal via the interface. The data processing includes symbol mapping, polarization division and framing.

[0162] In a fifth aspect, an embodiment of the present application provides a sending device. The sending device comprises a host device and an optical module according to any one of the embodiments of the fourth aspect. The optical module is configured to generate an optical signal according to data from the host device, and transmit the optical signal.

[0163] In a sixth aspect, an embodiment of the present application provides a device. The device comprises a processor and an interface. The processor is configured to perform the method according to any one of the embodiments of the first aspect, and the interface is configured to transmit a signal from the processor. For example, the interface is configured to transmit the signal from the processor or transmit a received signal to the processor. The device can be a router, a switch, a server or an optical transport network device.

[0164] In a seventh aspect, an embodiment of the present application provides a communication system. The communication system comprises the sending device according to the fifth aspect and a receiving device. The sending device is configured to transmit an optical signal to the receiving device.

[0165] In an eighth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are executed by a computer, the method according to any one of the embodiments of the first aspect is implemented.

[0166] In a ninth aspect, the present application provides a computer program product, which comprises program instructions for implementing the method introduced in any of the embodiments of the first aspect when the computer program product is executed. BRIEF DESCRIPTION OF DRAWINGS

[0167] Fig. 1 is a schematic diagram of a communication system to which embodiments of the present application are applied;

[0168] Fig. 2 is a schematic diagram of a structure of a data frame;

[0169] Fig. 3 is a schematic diagram of an embodiment of first data processing in the present application;

[0170] Fig. 4(a) is a schematic diagram of an embodiment of second data processing in the present application;

[0171] Fig. 4(b) is a schematic diagram of an embodiment of second data processing in the present application;

[0172] Fig. 5(a) is a schematic diagram of an embodiment of third data processing in the present application;

[0173] Fig. 5(b) is a schematic diagram of another embodiment of third data processing in the present application;

[0174] Fig. 5(c) is a schematic diagram of still another embodiment of third data processing in the present application;

[0175] Fig. 6(a) is a schematic diagram of an embodiment of PCS processing and first interleaving in the present application;

[0176] Fig. 6(b) is a schematic diagram of another embodiment of PCS processing and first interleaving in the present application;

[0177] Fig. 6(c) is a schematic diagram of still another embodiment of PCS processing and first interleaving in the present application;

[0178] Fig. 6(d) is a schematic diagram of still another embodiment of PCS processing and first interleaving in the present application;

[0179] Fig. 6(e) is a schematic diagram of an embodiment of PCS processing comprising multiple PCS sub-processes in the present application;

[0180] Fig. 6(f) is a schematic diagram of another embodiment of PCS processing comprising multiple PCS sub-processes in the present application;

[0181] Fig. 7 is a schematic diagram of a 7-column bit block per row in the present application;

[0182] Fig. 8 is a schematic diagram of a fifth bit set in the present application;

[0183] Figure 9 is a schematic diagram of a 16x16 bit block according to an embodiment of the application;

[0184] Figure 10 is a schematic diagram of a 16x15 bit block according to an embodiment of the application;

[0185] Figure 11(a) is a schematic diagram of a first bit pattern according to an embodiment of the application;

[0186] Figure 11(b) is a schematic diagram of a second bit pattern according to an embodiment of the application;

[0187] Figure 11(c) is a schematic diagram of a third bit pattern according to an embodiment of the application;

[0188] Figure 12(a) is a schematic diagram of a fourth bit pattern according to an embodiment of the application;

[0189] Figure 12(b) is a schematic diagram of a fifth bit pattern according to an embodiment of the application;

[0190] Figure 12(c) is a schematic diagram of a sixth bit pattern according to an embodiment of the application;

[0191] Figure 12(d) is a schematic diagram of another fourth bit pattern according to an embodiment of the application;

[0192] Figure 12(e) is a schematic diagram of another fifth bit pattern according to an embodiment of the application;

[0193] Figure 12(f) is a schematic diagram of another sixth bit pattern according to an embodiment of the application;

[0194] Figure 12(g) is a schematic diagram of yet another fourth bit pattern and fifth bit pattern according to an embodiment of the application;

[0195] Figure 12(h) is a schematic diagram of yet another sixth bit pattern according to an embodiment of the application;

[0196] Figure 13 is a schematic diagram of a seventh bit pattern, an eighth bit pattern and a ninth bit pattern according to an embodiment of the application;

[0197] Figure 14 is a schematic diagram of a tenth bit pattern, an eleventh bit pattern and a twelfth bit pattern according to an embodiment of the application;

[0198] Figure 15 is a schematic diagram of an embodiment of data processing of two first bit streams according to an embodiment of the application;

[0199] Figure 16 is a schematic diagram of a bit block with 8 columns per row according to an embodiment of the application;

[0200] Figure 17 shows a schematic diagram of a sixth bit set according to an embodiment of the application;

[0201] Figure 18 is a schematic diagram of a thirteenth bit pattern, a fourteenth bit pattern and a fifteenth bit pattern according to an embodiment of the application;

[0202] Figure 19(a) is a schematic diagram of a sixteenth bit pattern according to an embodiment of the application;

[0203] Figure 19(b) is a schematic diagram of a seventeenth bit pattern according to an embodiment of the application;

[0204] Figure 19(c) is a schematic diagram of an eighteenth bit pattern according to an embodiment of the application;

[0205] Figure 20 is a schematic diagram of a ninth bit set according to an embodiment of the application;

[0206] Figure 21 is a schematic diagram of a seventh bit set according to an embodiment of the application;

[0207] Figure 22 is a schematic diagram of an embodiment of fifth interleaving according to an embodiment of the application;

[0208] Figure 23(a) is a schematic diagram of a nineteenth bit pattern according to an embodiment of the application;

[0209] Figure 23(b) is a schematic diagram of a twentieth bit pattern according to an embodiment of the application;

[0210] Figure 23(c) is a schematic diagram of a twenty-first bit pattern according to an embodiment of the application;

[0211] Figure 24 is a schematic diagram of an embodiment of intra-matrix interleaving according to an embodiment of the application;

[0212] Figure 25(a) is a schematic diagram of a twenty-second bit pattern according to an embodiment of the application;

[0213] Figure 25(b) is a schematic diagram of a twenty-third bit pattern according to an embodiment of the application;

[0214] Figure 25(c) is a schematic diagram of a twenty-fourth bit pattern according to an embodiment of the application;

[0215] Figure 26 is a schematic diagram of an embodiment of inter-matrix interleaving according to an embodiment of the application;

[0216] Figure 27 is a schematic diagram of a bit set after inter-matrix interleaving according to an embodiment of the application;

[0217] Figure 28(a) is a schematic diagram of another first bit pattern according to an embodiment of the application;

[0218] Figure 28(b) is a schematic diagram of another second bit pattern according to an embodiment of the application;

[0219] Figure 28(c) is a schematic view of another third bit pattern in embodiments of the application;

[0220] Figure 29 is a schematic view of another fifth bit pattern in embodiments of the application;

[0221] Figure 30 is a schematic view of another seventh bit pattern, eighth bit pattern and ninth bit pattern in embodiments of the application;

[0222] Figure 31 is a schematic view of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in embodiments of the application;

[0223] Figure 32 is a schematic view of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in embodiments of the application;

[0224] Figure 33(a) is a schematic view of another sixteenth bit pattern in embodiments of the application;

[0225] Figure 33(b) is a schematic view of another seventeenth bit pattern in embodiments of the application;

[0226] Figure 33(c) is a schematic view of another eighteenth bit pattern in embodiments of the application;

[0227] Figure 34(a) is a schematic view of another fourth bit pattern in embodiments of the application;

[0228] Figure 34(b) is a schematic view of another sixth bit pattern in embodiments of the application;

[0229] Figure 35 is a schematic view of another seventh bit pattern, eighth bit pattern and ninth bit pattern in embodiments of the application;

[0230] Figure 36 is a schematic view of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in embodiments of the application;

[0231] Figure 37 is a schematic view of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in embodiments of the application;

[0232] Figure 38(a) is a schematic view of another sixteenth bit pattern in embodiments of the application;

[0233] Figure 38(b) is a schematic view of another seventeenth bit pattern in embodiments of the application;

[0234] Figure 38(c) is a schematic view of another eighteenth bit pattern in embodiments of the application;

[0235] Figure 39 is a schematic view of another fifth bit pattern in embodiments of the application;

[0236] FIG. 40 is a diagram of another seventh, eighth and ninth bit pattern according to an embodiment of the present application;

[0237] FIG. 41 is a diagram of another tenth, eleventh and twelfth bit pattern according to an embodiment of the present application;

[0238] FIG. 42 is a diagram of another thirteenth, fourteenth and fifteenth bit pattern according to an embodiment of the present application;

[0239] FIG. 43(a) is a diagram of another sixteenth bit pattern according to an embodiment of the present application;

[0240] FIG. 43(b) is a diagram of another seventeenth bit pattern according to an embodiment of the present application;

[0241] FIG. 43(c) is a diagram of another eighteenth bit pattern according to an embodiment of the present application;

[0242] FIG. 44(a) is a diagram of another fifth bit pattern according to an embodiment of the present application;

[0243] FIG. 44(b) is a diagram of another sixth bit pattern according to an embodiment of the present application;

[0244] FIG. 45 is a diagram of another seventh, eighth and ninth bit pattern according to an embodiment of the present application;

[0245] FIG. 46 is a diagram of another tenth, eleventh and twelfth bit pattern according to an embodiment of the present application;

[0246] FIG. 47 is a diagram of another thirteenth, fourteenth and fifteenth bit pattern according to an embodiment of the present application;

[0247] FIG. 48(a) is a diagram of another sixteenth bit pattern according to an embodiment of the present application;

[0248] FIG. 48(b) is a diagram of another seventeenth bit pattern according to an embodiment of the present application;

[0249] FIG. 48(c) is a diagram of another eighteenth bit pattern according to an embodiment of the present application;

[0250] FIG. 49(a) is a diagram of another first bit pattern according to an embodiment of the present application;

[0251] FIG. 49(b) is a diagram of another second bit pattern according to an embodiment of the present application;

[0252] FIG. 49(c) is a diagram of another third bit pattern according to an embodiment of the present application;

[0253] Figure 50 is a schematic diagram of an application scenario of the second data processing in the embodiment of the present application;

[0254] Figure 51(a) is a schematic diagram of a bit distribution of the last 69-bit column in the sixth bit set 2i in the embodiment of the present application;

[0255] Figure 51(b) is a schematic diagram of another bit distribution of the last 69-bit column in the sixth bit set 2i+1 in the embodiment of the present application;

[0256] Figure 52 is a schematic diagram of the third bit data d scr mapping and distributing to N PCS:FEC "PCS+FEC" modules;

[0257] Figure 53 is a schematic diagram of another embodiment of the inter-square interleaving in the embodiment of the present application;

[0258] Figure 54 is a schematic diagram of an application scenario of the second data processing in the embodiment of the present application;

[0259] Figure 55 is a schematic diagram of a structure of a data processing apparatus in the embodiment of the present application;

[0260] Figure 56 is a schematic diagram of a structure of an optical module in the embodiment of the present application;

[0261] Figure 57 is a schematic diagram of a structure of a sending device in the embodiment of the present application. DETAILED DESCRIPTION

[0262] The embodiment of the present application provides a data processing method, apparatus and system, which adopts DP-64QAM modulation and combines FEC encoding, interleaving and PCS technology, guarantees simple overall data processing operation, low complexity and low power consumption, improves spectrum utilization and transmission performance of the system, and meets future metropolitan telecommunication transmission and metropolitan DCI interconnection scenarios.

[0263] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and are not intended to limit a specific order or sequence. It should be understood that the above-described terms can be interchanged under appropriate circumstances, so that the embodiments described in the present application can be implemented in an order other than that described in the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units need not be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0264] FIG. 1 is a schematic diagram of a communication system to which embodiments of the present application are applied. As shown in FIG. 1, at the transmitting end, a data source provides a data stream to be transmitted, and a transmitting data processor receives the data stream. The transmitting data processor first performs data processing including PCS processing, encoding, interleaving, modulation, DSP framing on the data stream to obtain a symbol data stream, and then sends the symbol data stream to a transmitting signal processor for signal processing, and then transmits the processed data stream to a receiving device through a channel. After the receiving device receives a distorted signal due to noise or other impairments in the channel, the distorted signal is sent to a receiving signal processor for dispersion compensation, synchronization, phase recovery, etc., and then sent to a receiving data processor for demodulation, deinterleaving, decoding, etc., to recover the original data, and then sends the recovered data to a data sink.

[0265] It should be noted that the bit set and the bit subset in the specification and claims of the present application are concepts introduced for the convenience of description. In actual applications, the data stream is a whole and is not divided, and each bit set and bit subset can be regarded as one or more bits in the data stream. It should be understood that the bit set and the bit subset can also be presented in the form of a matrix, an array, a sequence, etc., and the specific form is not limited here.

[0266] It should be noted that the data processing method provided by the present application can be divided into three parts, which are respectively referred to as "first data processing", "second data processing" and "third data processing". The "first data processing", "second data processing" and "third data processing" will be described in detail below. FIG. 2 is a schematic diagram of the structure of a data frame. As shown in FIG. 2, the data frame includes multiple rows of bits, and each row includes q bits. It should be understood that the present application does not limit the specific type of the data frame. In some specific applications, the integer q is an integer multiple of 257, and typically q is 10280, 8224, 4112, or 2056, etc. In other specific applications, the integer q is an integer multiple of 128, for example, q is 128. FIG. 3 is a schematic diagram of one embodiment of the first data processing in the embodiments of the present application. As shown in FIG. 3, the first data processing includes Cyclic Redundancy Check (CRC), Pad insertion, and scrambling. In actual applications, at least one of the CRC and the Pad insertion can be performed. For example, the first data processing performs CRC check on the first bit data and inserts bits to obtain second bit data, and performs scrambling to obtain third bit data. For another example, the first data processing performs CRC check on the first bit data and performs scrambling to obtain third bit data. For another example, the first data processing inserts bits to obtain second bit data from the first bit data, and performs scrambling to obtain third bit data.

[0267] Figure 4(a) is a schematic diagram of one embodiment of the second data processing in the embodiments of the present application. As shown in Figure 4(a), a plurality of bits are obtained from the third bit data outputted after the first data processing, and are polled into L second data sub-processes (i.e., second data sub-process 0, second data sub-process 1, …, second data sub-process L-1), for example, e bits are inputted into each second data sub-process. After the L second data sub-processes, L data streams can be obtained, and then the L data streams are merged to obtain the output of the second data processing, i.e., the fourth bit data in Figure 4(a), wherein L is an integer greater than 0.

[0268] Figure 4(b) is a schematic diagram of one embodiment of the second data sub-process in the embodiments of the present application. As shown in Figure 4(b), the operation of the second data sub-process i (i = 0, 1, …, L-1) includes PCS processing and first interleaving (i.e., “PCS processing and first interleaving i” in Figure 4(b)), FEC encoding (i.e., “FEC encoding 2i” and “FEC encoding 2i+1” in Figure 4(b)), second interleaving (i.e., “second interleaving 2i” and “second interleaving 2i+1” in Figure 4(b)), and third interleaving (i.e., “third interleaving i” in Figure 4(b)). The third interleaving includes intra-block interleaving (i.e., “intra-block interleaving 2i” and “intra-block interleaving 2i+1” in Figure 4(b)) and inter-block interleaving (i.e., “inter-block interleaving i” in Figure 4(b)). The third interleaving is also called block interleaving. It should be understood that the various interleaving operations mentioned in the embodiments of the present application can also have other names in different scenarios, for example, the interleaving can also be called permutation or reordering, etc.

[0269] Specifically, the second data sub-process obtains a plurality of bits, and performs PCS processing and first interleaving to obtain two first bit streams, performs FEC encoding on the two first bit streams to obtain two second bit streams, performs second interleaving on the two second bit streams to obtain two third bit streams, and performs third interleaving on the two third bit streams to obtain a fourth bit stream, i.e., one output data stream of the second data sub-process. It should be understood that in some possible scenarios, the second interleaving can be one operation, or the second interleaving can also be divided into fourth interleaving and fifth interleaving, which will be described in detail below.

[0270] The L second data sub-processing output bit streams are merged to obtain one second data processing output bit stream. The second data processing output bit stream includes a plurality of fourth bit data. Typically, the merging operation obtains S bits from each second data sub-processing output bit stream to obtain a total of S*L bits as the S*L consecutive bits in the second data processing output bit stream. The merging operation can be referred to as block merging or multiplexing (MUX). It should be noted that when L=1, i.e., there is only one second data sub-processing output bit stream, the second data processing output bit stream can be obtained without merging. As an example, L can be 2 or 4 or 8, etc., which is not limited here.

[0271] FIG. 5(a) is a schematic diagram of one embodiment of the third data processing in the embodiments of the present application. As shown in FIG. 5(a), the fourth bit data is subjected to symbol mapping and polarization distribution to obtain a dual-polarization symbol sequence, wherein the symbol mapping and polarization distribution map every 12 bits in the fourth bit data into one dual-polarization symbol. Further, the dual-polarization symbol sequence is subjected to DSP framing operation. Specifically, at least one sequence of frame alignment word sequence (FAW sequence), training sequence, reserved field and pilot sequence is inserted in the X polarization direction and Y polarization direction, respectively, to obtain the dual-polarization symbol sequence to be transmitted.

[0272] It should be noted that the frame alignment symbol is used for frame synchronization alignment, the training symbol is used for link training, the pilot symbol is used for carrier phase recovery, and the reserved symbol is used for future use and innovation. The value of the reserved symbol can be known and constant, or randomized. The value of the reserved symbol can also be referred to as a pattern. In some specific embodiments, the super-frame can also be referred to as a multi-frame, the reserved symbol can also be referred to as a fixed stuff (FS), and the frame alignment symbol can also be referred to as a multi-frame alignment signal (MFAS).

[0273] It should be noted that the DSP framing operation shown in Fig. 5(a) is operated on a symbol, and the DSP framing operation can also be operated on a bit, as shown in Fig. 5(b) and Fig. 5(c). Fig. 5(b) is a schematic diagram of another embodiment of the third data processing in the embodiment of the present application. As shown in Fig. 5(b), the DSP framing operation can also insert the bits corresponding to the frame synchronization symbol sequence, the training symbol sequence, the reserved symbol sequence and the pilot symbol sequence into the fourth bit data before symbol mapping, and then the same superframe as the operation of Fig. 5(a) can be obtained after symbol mapping and polarization division. Fig. 5(c) is a schematic diagram of still another embodiment of the third data processing in the embodiment of the present application. As shown in Fig. 5(c), the DSP framing operation can also insert the bits corresponding to the frame synchronization symbol sequence, the training symbol sequence, the reserved symbol sequence and the pilot symbol sequence into the fourth bit data before polarization division and symbol mapping, and then the same superframe as the operation of Fig. 5(a) can also be obtained; it should be understood that there can be other framing operations, which will not be described herein.

[0274] As shown in Fig. 4(a) and Fig. 4(b), the third interleaving output bit streams are merged to obtain fourth bit data, and the fourth bit data is subjected to symbol mapping and polarization division to obtain dual-polarization symbols. Specifically, the L third interleaving output bit streams are polled and merged in groups of 12 bits, and then subjected to symbol mapping (i.e., 12 bits output from the third interleaving 0 are mapped into one dual-polarization modulation symbol, then 12 bits output from the third interleaving 1 are mapped into one dual-polarization modulation symbol, and so on until 12 bits output from the third interleaving L-1 are mapped into one dual-polarization modulation symbol). For the case of using dual-polarization 64QAM modulation (DP-64QAM), symbol mapping and polarization division map every 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11) to obtain 1 DP-64QAM symbol. One dual-polarization symbol contains an X-polarization symbol and a Y-polarization symbol, wherein the X-polarization and the Y-polarization are orthogonal to each other, the X-polarization symbol includes an I-direction component and a Q-direction component on the X-polarization, and the Y-polarization symbol includes an I-direction component and a Q-direction component on the Y-polarization. For each signaling dimension (also referred to as signal component), X 10 11 I Q I Q ​​​​​The three bits are mapped to the corresponding symbol amplitudes as follows: (0,0,0)→-7, (0,0,1)→-5, (0,1,1)→-3, (0,1,0)→-1, (1,1,0)→+1, (1,1,1)→+3, (1,0,1)→+5, (1,0,0)→+7

[0275] It should be noted that the real part X I And the imaginary part X Q The complex number formed is used to represent the modulation symbol in the X-polarization direction, with the real part Y. I And the imaginary part Y Q The complex number formed is used to represent the modulation symbol in the Y-polarization direction. The dual-polarization symbol can be transmitted by transmitting the I-direction component X in the X-polarization direction. I X-polarization Q-direction component X Q Y-polarization component in the I direction I The Q-direction component Y in Y polarization Q Perform digital-to-analog conversion (DAC) to obtain the corresponding four analog signals.

[0276] It should be understood that the bits mapped to a dual-polarization symbol include amplitude bits and sign bits. Taking a DP-64QAM symbol as an example, 12 bits are mapped to a DP-64QAM symbol, of which 8 bits are amplitude bits and the other 4 bits are sign bits. These amplitude bits can be further divided into first-type amplitude bits and second-type amplitude bits, with the same number of first-type and second-type amplitude bits. Typically, the first-type amplitude bits have a lower bit error rate, while the second-type amplitude bits have a higher bit error rate. The amplitude bits are derived from the second bit set after PCS processing of the first bit set. Therefore, the bits in the second bit set can be divided into first-type and second-type bits, with the first-type amplitude bits originating from the first-type bits and the second-type amplitude bits originating from the second-type bits.

[0277] In some possible implementations, the probability that a bit in the first type of bit is 1 is P. 0；1 The probability that a bit in the first type of bit is 0 is P. 0；0 The probability that a bit in the second type of bit is 1 is P. 1；1 The probability that a bit in the second type of bit is 0 is P. 1；0 P 0；1 -P 0；0 The absolute value is greater than or equal to P 1；1 -P 1；0 The absolute value of.

[0278] As an example, for DP-64QAM, consider the following first symbol mapping scheme: (b0, b2, b4) is mapped to the in-phase component of a DP-64QAM symbol on X polarization, denoted as X I ; (b6, b8, b 10 ) is mapped to the quadrature-phase component of a DP-64QAM symbol on X polarization, denoted as X Q ; (b1, b3, b5) is mapped to the in-phase component of a DP-64QAM symbol on Y polarization, denoted as Y I ; (b7, b9, b 11 ) is mapped to the quadrature-phase component of a DP-64QAM symbol on Y polarization, denoted as Y Q At this time, b0 and b6 of the 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 ) are 2 sign bits in 64QAM on X polarization direction, b2, b4, b8 and b 10 are 4 amplitude bits in 64QAM on X polarization direction, where b2 and b8 are referred to as first type amplitude bits, and b4 and b 10 are referred to as second type amplitude bits; b1 and b7 are 2 sign bits in 64QAM on Y polarization direction, b3, b5, b9 and b 11 are 4 amplitude bits in 64QAM on Y polarization direction, where b3 and b9 are referred to as first type amplitude bits, and b5 and b 11 are referred to as second type amplitude bits.

[0279] As another example, for DP-64QAM, consider the following second symbol mapping scheme: (b0, b4, b6) is mapped to the in-phase component of a DP-64QAM symbol on X polarization, denoted as X I ; (b2, b8, b 10 ) is mapped to the quadrature-phase component of a DP-64QAM symbol on X polarization, denoted as X Q(b1,b5,b7) is mapped to the in-phase component of the DP-64QAM symbol in the Y-polarization direction, denoted as Y. I ;(b3,b9,b 11 The DP-64QAM symbol is mapped to the quadrature-phase component in the Q direction of Y polarization, denoted as Y. Q At this point, the 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b) 10 ,b 11 In the above, b0 and b2 are two sign bits in the 64QAM along the X-polarization direction, and b4, b6, b8, and b... 10 These are the four amplitude bits in 64QAM in the X-polarization direction, where b4 and b8 are called the first type amplitude bits, and b6 and b7 are called the second type amplitude bits. 10 These are called type II amplitude bits; b1 and b3 are two sign bits in the 64QAM along the Y-polarization direction, and b5, b7, b9, and b... 11 These are four amplitude bits in 64QAM in the Y-polarization direction, where b5 and b9 are called first-type amplitude bits, and b7 and b8 are called second-type amplitude bits. 11 This is called the second type of amplitude bit.

[0280] As another example, for DP-64QAM, consider the following third symbol mapping scheme: (b8,b0,b2) is mapped to the in-phase component of the DP-64QAM symbol in the X polarization direction, denoted as X. I ;(b 10 The components (b4, b6) are mapped to the quadrature-phase component in the Q direction of the DP-64QAM symbol on the X-polarization plane, denoted as X. Q (b9,b1,b3) is mapped to the in-phase component of the DP-64QAM symbol in the Y-polarization direction, denoted as Y. I ;(b 11 The components (b5, b7) are mapped to the quadrature-phase component in the Q direction of the DP-64QAM symbol in Y polarization, denoted as Y. Q At this point, the 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b) 10 ,b 11 b8 and b in ) 10b4 and b6 are 2 sign bits in 64QAM for the X polarization direction, b0, b2, b8 and b 11 b4 and b6 are 2 sign bits in 64QAM for the X polarization direction, b0, b2, b8 and b

[0281] As a further example, for DP-64QAM, consider the following fourth symbol mapping scheme: (b4, b0, b2) maps to the in-phase component of the DP-64QAM symbol on the X polarization, denoted as X I ; (b6, b8, b 10 ) maps to the quadrature-phase component of the DP-64QAM symbol on the X polarization, denoted as X Q ; (b5, b1, b3) maps to the in-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y I ; (b7, b9, b 11 ) maps to the quadrature-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y Q . In this case, b4 and b6 of the 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 ) are 2 sign bits in 64QAM for the X polarization direction, b0, b2, b8 and b 10 are 4 amplitude bits in 64QAM for the X polarization direction, where b0 and b8 are first-type amplitude bits, b2 and b 10 are second-type amplitude bits; b5 and b7 are 2 sign bits in 64QAM for the Y polarization direction, b1, b3, b9 and b 11 are 4 amplitude bits in 64QAM for the Y polarization direction, where b1 and b9 are first-type amplitude bits, b3 and b 11 are second-type amplitude bits.

[0282] As a further example, for DP-64QAM, consider the following fifth symbol mapping scheme: (b0, b1, b2) is mapped to the in-phase component of the DP-64QAM symbol on X polarization, denoted as X I ; (b3, b4, b5) is mapped to the quadrature-phase component of the DP-64QAM symbol on X polarization, denoted as X Q ; (b6, b7, b8) is mapped to the in-phase component of the DP-64QAM symbol on Y polarization, denoted as Y I ; (b9, b 10 , b 11 ) is mapped to the quadrature-phase component of the DP-64QAM symbol on Y polarization, denoted as Y Q . In this case, b0 and b3 of the 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 ) are 2 sign bits in 64QAM on X polarization, b1, b2, b4 and b5 are 4 amplitude bits in 64QAM on X polarization, where b1 and b4 are referred to as first type amplitude bits and b2 and b5 are referred to as second type amplitude bits; b6 and b9 are 2 sign bits in 64QAM on Y polarization, b7, b8, b 10 and b 11 are 4 amplitude bits in 64QAM on Y polarization, where b7 and b 10 are referred to as first type amplitude bits and b8 and b 11 are referred to as second type amplitude bits.

[0283] It is noted that for the first, second, third and fourth symbol mapping schemes, b0, b2, b4, b6, b8 and b 10 of the 12 bits are used to map to X polarization symbols, b1, b3, b5, b7, b9 and b 11 of the 12 bits are used to map to Y polarization symbols; for the fifth symbol mapping scheme, b0, b1, b2, b3, b4 and b5 of the 12 bits are used to map to X polarization symbols, b6, b7, b8, b9, b 10 and b 11The 4 bits of the 12 bits for mapping to the X-polarization symbol come from the second set of bits, and the other 2 bits of the 12 bits for mapping to the X-polarization symbol come from the third set of bits or the check bits of the FEC encoding; the 4 bits of the 12 bits for mapping to the Y-polarization symbol come from the second set of bits, and the other 2 bits of the 12 bits for mapping to the Y-polarization symbol come from the third set of bits or the check bits of the FEC encoding. It should be understood that the above "2 bits come from the third set of bits or the check bits of the FEC encoding" means that the 2 bits come from at least one of the third set of bits and the check bits of the FEC encoding. For example, the 2 bits can both come from the third set of bits; for another example, the 2 bits can both come from the check bits of the FEC encoding; for yet another example, 1 bit comes from the third set of bits and the other bit comes from the check bits of the FEC encoding.

[0284] The operations of each of the second data sub-processes i (i = 0, 1, …, L-1) will be described in detail below, taking the case of modulation using the first symbol mapping scheme as an example, where L is an integer greater than 0.

[0285] (1) PCS processing and first interleaving:

[0286] Figure 6(a) is a schematic diagram of one embodiment of the PCS processing and first interleaving in the embodiments of the present application. As shown in Figure 6(a), the "PCS processing and first interleaving i" specifically includes the operation of 1 PCS processing (i.e., "PCS processing i") and the operation of 1 first interleaving (i.e., "first interleaving i").

[0287] Specifically, first, e bits are obtained, where e is an integer greater than 0. A first set of bits i of the e bits is input into the "PCS processing i" to obtain a second set of bits i. Half the number of bits in the second set of bits i are used to generate the first type of amplitude bits, and the other half are used to generate the second type of amplitude bits. The second set of bits i is combined with a third set of bits i remaining after the first set of bits i is removed from the e bits, and the combination is input into the first interleaving i to shuffle the order to obtain 2 fourth sets of bits, i.e., a fourth set of bits 2i and a fourth set of bits 2i+1. It should be understood that the e bits are composed of the first set of bits i and the third set of bits i. It should be understood that, as shown in Figure 6(a), the first bit stream 2i output by the "PCS processing and first interleaving" can include multiple fourth sets of bits 2i; the first bit stream 2i+1 output by the "PCS processing and first interleaving" can include multiple fourth sets of bits 2i+1.

[0288] Typically, the number of bits of the fourth bit set 2i and the fourth bit set 2i+1 is 1776xk0bits, and the number of bits of the second bit set i is 8192xk0 / 3bits, wherein the number of bits of the second bit set i used to generate the first type of amplitude bits is 4096xk0 / 3, and the number of bits of the second bit set i used to generate the second type of amplitude bits is also 4096xk0 / 3. The number of bits of the third bit set i is 3552xk0-8192xk0 / 3bits, and the number of bits of the first bit set i is e-(3552xk0-8192xk0 / 3)bits, wherein k0 is an integer greater than 0 and is an integer multiple of 3. For example, k0=3, 6, 9, 12, …, 42, etc.

[0289] As an example, when k0=3, the first bit set i contains e-2464bits, and the second bit set i contains 8192bits, wherein 4096bits of the 8192bits are used to generate the first type of amplitude bits, and the remaining 4096bits are used to generate the second type of amplitude bits. The third bit set i contains 2464bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 5328bits. As another example, when k0=6, the first bit set i contains e-4928bits, and the second bit set i contains 16384bits, wherein 8192bits of the 16384bits are used to generate the first type of amplitude bits, and the remaining 8192bits are used to generate the second type of amplitude bits. The third bit set i contains 4928bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 10656bits. As yet another example, when k0=42, the first bit set i contains e-34496bits, and the second bit set i contains 114688bits, wherein 57344bits of the 114688bits are used to generate the first type of amplitude bits, and the remaining 57344bits are used to generate the second type of amplitude bits. The third bit set i contains 34496bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 74592bits.

[0290] Figure 6(b) is a schematic diagram of another embodiment of PCS processing and first interleaving in the embodiments of the present application. As shown in Figure 6(b), the “PCS processing and first interleaving i” specifically includes the operations of 2 PCS processes (i.e., “PCS process 2i” and “PCS process 2i+1”) and the operation of 1 first interleaving (i.e., “first interleaving i”). It should be understood that, compared with the embodiment of Figure 6(a), the embodiment of Figure 6(b) is divided into 2 PCS processes, which is beneficial to reduce the complexity of a single PCS process, and the hardware implementation of a single PCS process is simpler.

[0291] In particular, e bits are first obtained, where e is an integer greater than 1. The e bits include two first bit sets, i.e., a first bit set 2i and a first bit set 2i+1. The first bit set 2i is processed by a PCS process 2i to obtain a second bit set 2i, and the first bit set 2i+1 is processed by a PCS process 2i+1 to obtain a second bit set 2i+1. Half of the bits in the second bit set 2i (or the second bit set 2i+1) are used to generate the first type of amplitude bits, and the other half are used to generate the second type of amplitude bits. Typically, e is an even integer greater than 0, and the number of bits in the first bit set 2i and the first bit set 2i+1 is the same.

[0292] The e bits further include two third bit sets, i.e., a third bit set 2i and a third bit set 2i+1. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1, the third bit set 2i, and the third bit set 2i+1. The third bit set 2i, the third bit set 2i+1, the second bit set 2i, and the second bit set 2i+1 are all sent to a first interleaving i to be interleaved to obtain two fourth bit sets, i.e., a fourth bit set 2i and a fourth bit set 2i+1. It should be understood that, as shown in FIG. 6(b), the first bit stream 2i output by the PCS process and the first interleaving can include multiple fourth bit sets 2i, and the first bit stream 2i+1 output by the PCS process and the first interleaving can include multiple fourth bit sets 2i+1.

[0293] Typically, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is the same. More specifically, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is 1776×k0 bits, and the number of bits in the second bit set 2i and the second bit set 2i+1 is 4096×k0 / 3 bits, where the number of bits used to generate the first type of amplitude bits in the second bit set 2i (or the second bit set 2i+1) is 2048×k0 / 3, and the number of bits used to generate the second type of amplitude bits is also 2048×k0 / 3. The number of bits in the third bit set 2i and the third bit set 2i+1 is 1776×k0-4096×k0 / 3, and the number of bits in the first bit set 2i and the first bit set 2i+1 is e / 2-(1776×k0-4096×k0 / 3), where k0 is an integer greater than 0 and is an integer multiple of 3. For example, k0=3, 6, 9, 12, …, 42, etc.

[0294] As an example, consider e is an even number greater than 0, when k0= 3, the first bit set 2i and the first bit set 2i+1 each contains e / 2-1232 bits, the second bit set 2i and the second bit set 2i+1 each contains 4096 bits, where 2048 bits of the 4096 bits are used to generate the first type of amplitude bits and the remaining 2048 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contains 1232 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contains 5328 bits. As another example, when k0= 6, the first bit set 2i and the first bit set 2i+1 each contains e / 2-2464 bits, the second bit set 2i and the second bit set 2i+1 each contains 8192 bits, where 4096 bits of the 8192 bits are used to generate the first type of amplitude bits and the remaining 4096 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contains 2464 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contains 10656 bits. As yet another example, when k0= 42, the first bit set 2i and the first bit set 2i+1 each contains e / 2-17248 bits, the second bit set 2i and the second bit set 2i+1 each contains 57344 bits, where 28672 bits of the 57344 bits are used to generate the first type of amplitude bits and the remaining 28672 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contains 17248 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contains 74592 bits.

[0295] It should be understood that in the above examples, the first bit set 2i and the third bit set 2i together include e / 2 bits, and the first bit set 2i+1 and the third bit set 2i+1 together include e / 2 bits, that is, the input e bits are first divided into two paths each with e / 2 bits and then processed subsequently. In some other possible scenarios, the input e bits can also be divided into two paths in other proportions, that is, the number of bits included by the first bit set 2i and the third bit set 2i is different from the number of bits included by the first bit set 2i+1 and the third bit set 2i+1.

[0296] Figure 6(c) is a schematic diagram of another embodiment of PCS processing and first interleaving in the present application. As shown in Figure 6(c), "PCS processing and first interleaving i" includes the operation of 2 PCS processes (i.e., "PCS process 2i" and "PCS process 2i+1") and the operation of 2 first interleavings (i.e., "first interleaving 2i" and "first interleaving 2i+1"). It should be understood that, compared with the embodiments of Figure 6(a) and Figure 6(b), the implementation of 2 first interleavings in Figure 6(c) is advantageous in reducing the complexity of a single first interleaving, and the hardware implementation of a single first interleaving is simpler.

[0297] Specifically, e bits are first obtained, where e is an integer greater than 0. The e bits include 2 first bit sets, i.e., first bit set 2i and first bit set 2i+1. The first bit set 2i is subjected to the PCS process 2i to obtain the second bit set 2i, and the first bit set 2i+1 is subjected to the PCS process 2i+1 to obtain the second bit set 2i+1. Half of the bits in the second bit set 2i (or the second bit set 2i+1) are used to generate the first type of amplitude bits, and the other half are used to generate the second type of amplitude bits. Typically, e is an even integer greater than 0, and the number of bits in the first bit set 2i and the first bit set 2i+1 is the same.

[0298] The e bits further include 2 third bit sets, i.e., third bit set 2i and third bit set 2i+1. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1, the third bit set 2i, and the third bit set 2i+1.

[0299] The third bit set 2i and the second bit set 2i are input into the first interleaving 2i to interleave and disrupt the order to obtain 1 fourth bit set, i.e., fourth bit set 2i. The third bit set 2i+1 and the second bit set 2i+1 are input into the first interleaving 2i+1 to interleave and disrupt the order to obtain 1 fourth bit set, i.e., fourth bit set 2i+1. It should be understood that, as shown in Figure 6(c), the first bit stream 2i output by "PCS processing and first interleaving" can include multiple fourth bit sets 2i, and the first bit stream 2i+1 output by "PCS processing and first interleaving" can include multiple fourth bit sets 2i+1.

[0300] Typically, the fourth bit set 2i and the fourth bit set 2i+1 have the same number of bits. More specifically, the fourth bit set 2i and the fourth bit set 2i+1 each have 1776 x k0bits, the second bit set 2i and the second bit set 2i+1 each have 4096 x k0 / 3bits, wherein the second bit set 2i and the second bit set 2i+1 each have 2048 x k0 / 3bits for generating the first type of amplitude bits and 2048 x k0 / 3bits for generating the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each have 1776 x k0- 4096 x k0 / 3bits, and the first bit set 2i and the first bit set 2i+1 each have e / 2- (1776 x k0- 4096 x k0 / 3) bits, wherein k0is an integer greater than 0 and is an integer multiple of 3. For example, k0= 3, 6, 9, 12, …, 42, etc.

[0301] As an example, consider e is an even number greater than 0, when k0= 3, the first bit set 2i and the first bit set 2i+1 each contain e / 2- 1232 bits, the second bit set 2i and the second bit set 2i+1 each contain 4096 bits, wherein 2048 bits of the 4096 bits are used to generate the first type of amplitude bits and the remaining 2048 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contain 1232 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 5328 bits. As another example, when k0= 6, the first bit set 2i and the first bit set 2i+1 each contain e / 2- 2464 bits, the second bit set 2i and the second bit set 2i+1 each contain 8192 bits, wherein 4096 bits of the 8192 bits are used to generate the first type of amplitude bits and the remaining 4096 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contain 2464 bits, and the fourth bit set 2i and the fourth bit set 2i+1 contain 10656 bits. As yet another example, when k0= 42, the first bit set 2i and the first bit set 2i+1 each contain e / 2- 17248 bits, the second bit set 2i and the second bit set 2i+1 each contain 57344 bits, wherein 28672 bits of the 57344 bits are used to generate the first type of amplitude bits and the remaining 28672 bits are used to generate the second type of amplitude bits. The third bit set 2i and the third bit set 2i+1 each contain 17248 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 74592 bits.

[0302] It should be understood that in the above examples, the first bit set 2i and the third bit set 2i together include e / 2 bits, and the first bit set 2i+1 and the third bit set 2i+1 together include e / 2 bits, that is, the e input bits are first divided into two paths each with e / 2 bits and then processed subsequently.

[0303] Fig. 6(d) is a schematic diagram of still another embodiment of PCS processing and first interleaving in the present application. As shown in Fig. 6(d), the "PCS processing and first interleaving i" includes two PCS processes (i.e., "PCS process 2i" and "PCS process 2i+1") and one first interleaving (i.e., "first interleaving i"). It should be understood that compared with the embodiment of Fig. 6(a), the embodiment of Fig. 6(d) divides the PCS processing into two processes, which is advantageous to reduce the complexity of a single PCS process and to make the hardware implementation of a single PCS process simpler.

[0304] The "PCS processing and first interleaving" obtains e bits, where e is an integer greater than 0. The e bits include two first bit sets, i.e., a first bit set 2i and a first bit set 2i+1. The first bit set 2i is input into the "PCS process 2i" to obtain a second bit set 2i, and the first bit set 2i+1 is input into the "PCS process 2i+1" to obtain a second bit set 2i+1. Half of the bits in the second bit set 2i (or the second bit set 2i+1) are used to generate the first type of amplitude bits, and the other half are used to generate the second type of amplitude bits. Typically, e is an even integer greater than 0, and the number of bits in the first bit set 2i is the same as that in the first bit set 2i+1.

[0305] The e bits include one third bit set, i.e., a third bit set i. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1 and the third bit set i. The third bit set i, the second bit set 2i and the second bit set 2i+1 are input into the first interleaving i to be interleaved to obtain two fourth bit sets, i.e., a fourth bit set 2i and a fourth bit set 2i+1. It should be understood that as shown in Fig. 6(d), the first bit stream 2i output by the "PCS processing and first interleaving" can include multiple fourth bit sets 2i; and the first bit stream 2i+1 output by the "PCS processing and first interleaving" can include multiple fourth bit sets 2i+1.

[0306] Typically, the fourth bit set 2i and the fourth bit set 2i+1 have the same number of bits. More specifically, the fourth bit set 2i and the fourth bit set 2i+1 each have 1776 x k0bits, and the second bit set 2i and the second bit set 2i+1 each have 4096 x k0 / 3bits, where the second bit set 2i and the second bit set 2i+1 each have 2048 x k0 / 3bits for generating the first type of amplitude bits and 2048 x k0 / 3bits for generating the second type of amplitude bits. The third bit set i has bits, and the first bit set 2i and the first bit set 2i+1 each have e / 2-(1776 x k0- 4096 x k0 / 3) bits, where k0is an integer greater than 0 and is an integer multiple of 3, such as k0= 3, 6, 9, 12, …, 42, etc.

[0307] As an example, consider e to be an even number greater than 0, and k0= 3. The first bit set 2i and the first bit set 2i+1 each contain e / 2- 1232 bits, and the second bit set 2i and the second bit set 2i+1 each contain 4096 bits, where 2048 bits of the 4096 bits are used to generate the first type of amplitude bits and the remaining 2048 bits are used to generate the second type of amplitude bits. The third bit set contains 2464 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 5328 bits. As another example, when k0= 6, the first bit set 2i and the first bit set 2i+1 each contain e / 2- 2464 bits, and the second bit set 2i and the second bit set 2i+1 each contain 8192 bits, where 4096 bits of the 8192 bits are used to generate the first type of amplitude bits and the remaining 4096 bits are used to generate the second type of amplitude bits. The third bit set contains 4928 bits, and the fourth bit set 2i and the fourth bit set 2i+1 contain 10656 bits. As yet another example, when k0= 42, the first bit set 2i and the first bit set 2i+1 each contain e / 2- 17248 bits, and the second bit set 2i and the second bit set 2i+1 each contain 57344 bits, where 28672 bits of the 57344 bits are used to generate the first type of amplitude bits and the remaining 28672 bits are used to generate the second type of amplitude bits. The third bit set contains 34496 bits, and the fourth bit set 2i and the fourth bit set 2i+1 each contain 74592 bits.

[0308] In some possible embodiments, the PCS process shown in FIG. 6(a), FIG. 6(b), FIG. 6(c), and FIG. 6(d) can further include a plurality of PCS sub-processes. FIG. 6(e) is a schematic diagram of an embodiment in which the PCS process includes a plurality of PCS sub-processes. As shown in FIG. 6(e), the PCS process includes L PCS groups of PCS sub-processes, each group of PCS sub-processes including one PCS sub-process 0 and one PCS sub-process 1, where L PCS is an integer greater than 0. The PCS sub-process 0 processes the input k pcs_0 bits to obtain n pcs_0 output bits with uneven distribution of values 0 and 1. The PCS sub-process 1 processes the input k pcs_1 bits to obtain n pcs_1 output bits with uneven distribution of values 0 and 1. Wherein, n pcs_0 > k pcs_0 , n pcs_1 > k pcs_1 , and n pcs_0 = n pcs_1 . Typically, the probability P pcs_0 of the n cs0；1 output bits having a value of 1 is greater than the probability P cs0；0 of the n cs0；0 output bits having a value of 0, and P cs0；1 + P pcs_1 = 1; the probability P cs1；1 of the n cs1；0 output bits having a value of 1 is greater than the probability P cs1；0 of the n cs1；1 output bits having a value of 0, and P pcs_0 + P pcs_1 = 1. Without loss of generality, it is assumed that k cs0；1 ≤ k cs1；1 , P cs0；0 ≥ P cs1；0 , and P pcs_0 ≤ P .

[0309] Consider that in symbol mapping (i.e., modulation), Gray mapping is used, for example, two bits (0, 0) are mapped to the largest amplitude 7 with a probability of P7; two bits (0, 1) are mapped to the second largest amplitude 5 with a probability of P5; two bits (1, 1) are mapped to the third largest amplitude 3 with a probability of P3; and two bits (1, 0) are mapped to the smallest amplitude 1 with a probability of P1. In order to make P1≥ P3≥ P5≥ P7, n pcs_0 output bits and n pcs_1The two output bits are also subjected to bit mapping. The bit mapping is used to map the two input bits (a, b) to two output bits (a, a^b), where ^ represents the exclusive OR operation. That is, one of the bits after bit mapping is used as the first type of bit in the second set of bits, which is mapped to the first type of amplitude bit of the dual polarization symbol; the other bit after bit mapping is used as the second type of bit in the second set of bits, which is mapped to the second type of amplitude bit of the dual polarization symbol. More specifically, the two bits (0, 0) are mapped to (0, 0), the two bits (0, 1) are mapped to (0, 1), the two bits (1, 0) are mapped to (1, 1), and the two bits (1, 1) are mapped to (1, 0).

[0310] As an example, bit a comes from the n pcs_0 output bits, and bit b comes from the n pcs_1 output bits. At this time, P1 = P cs0；1 × P cs1；1 , P3 = P cs0；1 × P cs1；0 , P5 = P cs0；0 × P cs1；1 , P7 = P cs0；0 × P cs1；0 , and P1≥P3≥P5≥P7. In some specific applications, k pcs_0 < k pcs_1 , P cs0；1 > P cs1；1 , P cs0 ; 0 < P cs1 ; 0, P1>P3>P5>P7. In other specific applications, k pcs_0 = k pcs_1 , P cs0 ; 1 = P cs1；1 , P cs0；0 = P cs1；0 , P1>P3=P5>P7.

[0311] Figure 6(f) is another example of PCS processing including multiple PCS sub-processes in embodiments of the present application. In some specific applications, the PCS processing includes L PCS = 4 groups of PCS sub-processes and 4 bit mappings corresponding to the 4 groups of PCS sub-processes, as shown in Figure 6(f). Among the 8 data streams output by the 4 bit mappings, the bits in one data stream (e.g., the mapping output data stream 0 in Figure 6(f)) are all used to generate the first type of amplitude bit on the signal dimension (also referred to as the component) X I , and the bits in one data stream (e.g., the mapping output data stream 1 in Figure 6(f)) are all used to generate the second type of amplitude bit on the signal dimension X ISecond type of amplitude bits on X, bits in one data stream (e.g., mapped output data stream 2 in FIG. 6(f)) are all used to generate X Q First type of amplitude bits on X, bits in one data stream (e.g., mapped output data stream 3 in FIG. 6(f)) are all used to generate X Q Second type of amplitude bits on Y, bits in one data stream (e.g., mapped output data stream 4 in FIG. 6(f)) are all used to generate Y I First type of amplitude bits on Y, bits in one data stream (e.g., mapped output data stream 5 in FIG. 6(f)) are all used to generate Y I Second type of amplitude bits on Y, bits in one data stream (e.g., mapped output data stream 6 in FIG. 6(f)) are all used to generate Y Q First type of amplitude bits on Y, bits in one data stream (e.g., mapped output data stream 7 in FIG. 6(f)) are all used to generate Y Q Second type of amplitude bits on Y.

[0312] In some application scenarios, PCS sub-processing 0 and PCS sub-processing 1 can be implemented by using a lookup table (LUT), and in some specific applications, the lookup table LUT processing can also be implemented by using a plurality of sub-lookup tables, the number of input bits of the sub-lookup tables can be different, and the number of output bits can also be different. At this time, the PCS processing is also called PCS LUT processing. It should be noted that the PCS processing can also be called a distribution matcher (DM). In some specific applications, the first interleaving can be called a block mapping (Block Map), and can also be called a pre-FEC interleaving (pre-FEC interleaver), and can also be called a pre-FEC permutation (pre-FEC Permutation).

[0313] It should be noted that, as shown in FIG. 6(a), FIG. 6(b), FIG. 6(c) and FIG. 6(d), the first bit stream contains a plurality of fourth bit sets. Each fourth bit set can be distributed in the form of containing a plurality of rows of bit blocks, wherein each row contains 7 columns of bit blocks. The bits in each of the bit blocks are continuous. It should be understood that, in some possible scenarios, the bit block can also be referred to as a bit subset, and the bit block is a specific implementation form of the row-column distribution of the bit subset. Further, if the number of rows and the number of columns of the bit block are the same, the bit block can also be referred to as a bit square block, a square block or a square, for example, the bit block containing 16 rows and 16 columns appearing in the present application can also be referred to as a bit square block, a square block or a square. It should be understood that, in the embodiments of the present application, the bit set, the bit subset, the bit block and the like related to the row-column distribution are counted from the 0th row and the 0th column. It should also be understood that, in the embodiments of the present application, the rows and columns related to the bit set refer to the bit subset or the bit block distributed in rows and columns, and in the embodiments of the present application, the rows and columns related to the bit subset or the bit block refer to the bits distributed in rows and columns, wherein the rows and columns in the bit subset or the bit block can also be referred to as bit rows and bit columns.

[0314] FIG. 7 is a schematic diagram of 7 columns of bit blocks per row in the embodiments of the present application. As shown in FIG. 7, the 0th, 1st, 2nd, 3rd, 4th and 5th column bit blocks each contain 16 rows of bits and 16 columns of bits, a total of 256 bits, and the 6th column bit block contains 16 rows of bits and 15 columns of bits, a total of 240 bits. That is, 7 columns of bit blocks per row contain a total of 1776 bits. It should be noted that the bit block containing 16 rows of bits and 16 columns of bits, a total of 256 bits, can be referred to as a square block, or a square.

[0315] It should be noted that, in some specific applications, the operation of the first interleaving in the “PCS processing and first interleaving” is performed with a granularity of 149184 or 74592 bits. In other specific applications, the operation of the first interleaving in the “PCS processing and first interleaving” is performed with a granularity of 10656 bits, at this time, the first interleaving is time-varying, that is, the interleaving operation of 10656 bits at different times is different; in other specific applications, the operation of the first interleaving in the “PCS processing and first interleaving” is performed with a granularity of 21312 bits, at this time, the first interleaving is time-varying, that is, the interleaving operation of 21312 bits at different times is different. It should be understood that, as shown in FIG. 6(c), the interleaving operation of the first interleaving 2i and the first interleaving 2i+1 is different.

[0316] It should be noted that the first bit stream contains a plurality of fifth bit sets, and each fifth bit set contains 42 rows and 7 columns of bit blocks, each of which contains 16 rows and 7 columns of bits, and each of the first 6 columns contains 16 rows and 16 columns of bits, and each of the last 1 column contains 16 rows and 15 columns of bits. Each row of bit blocks contains 7 bit blocks, and the total number of bits is 1776 bits, which can be referred to as shown in FIG. 7. The bits in each of the bit blocks are continuous.

[0317] It should be noted that in some specific applications, the 42 rows and 7 columns of bit blocks in the fifth bit set, that is, 74592 bits, are composed of one or more fourth bit sets.

[0318] FIG. 8 is a schematic diagram of a fifth bit set in an embodiment of the present application. As shown in FIG. 8, the fifth bit set can be in the form of a bit rectangular block. The bit block in the ith0row and the jth0column of the fifth bit set is denoted as where 0≤i0<42 and 0≤j0<7.

[0319] As shown in FIG. 8, each bit block in the first 6 columns (i.e., columns 0-5) of the fifth bit set contains 16 rows and 16 columns of bits, that is, where 0≤i0<42 and 0≤j0<6, is a square matrix containing 256 bits. In some specific applications, the bit block where 0≤i0<42 and 0≤j0<6, contains 256 bits in total in 16 rows and 16 columns, which are continuous on the first bit stream. FIG. 9 is a schematic diagram of a 16x16 bit block in an embodiment of the present application. As shown in FIG. 9, each bit block where 0≤i0<42 and 0≤j0<6, contains 256 bits in total in 16 rows and 16 columns, which are continuous on the first bit stream. FIG. 9 is a schematic diagram of a 16x16 bit block in an embodiment of the present application. As shown in FIG. 9, each bit block

[0320] As shown in FIG. 8, each bit block in the last column (i.e., column 6) of the fifth bit set contains 16 rows and 15 columns of bits, that is, where 0≤i0<42 and j0=6, is a bit block containing 240 bits. In some specific applications, the bit block The 240 bits in the 16 rows and 15 columns of the fifth bit set are continuous on the first bit stream. FIG. 10 is a schematic diagram of a 16x15 bit block according to an embodiment of the present application. As shown in FIG. 10, each bit block The bit in the r1th row and c1th column (0≤r1<16 and 0≤c1<15) of the fifth bit set (0≤i0<42 and j0=6) corresponds to the (15xr1+c1)th bit of the 240 continuous bits. For example, the bit in the r1th row and c1th column (r1=1 and c1=0) of the fifth bit set corresponds to the 15th bit of the 240 bits. For another example, the bit in the r1th row and c1th column (r1=2 and c1=3) of the fifth bit set corresponds to the 33rd bit of the 240 bits.

[0321] It should be noted that in some specific applications, the 42 rows and 7 columns of the 74592 bits in the fifth bit set are continuous on the first bit stream. Further, in some specific applications, the specific distribution of the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set on the first bit stream can be continuous distribution of 1 row of bit blocks with 1776 bits, for example, the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set are distributed on the first bit stream as follows: the 1776 bits of the 7 bit blocks of the fifth bit set are continuous on the first bit stream, where 0≤i0<42. In other specific applications, the specific distribution of the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set on the first bit stream can be continuous distribution of 2 rows of bit blocks with 3552 bits, for example, the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set are distributed on the first bit stream as follows: the 3552 bits of the 14 bit blocks of the fifth bit set are continuous on the first bit stream, where 0≤i1<21. In still other specific applications, the specific distribution of the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set on the first bit stream can be continuous distribution of 3 rows of bit blocks with 5328 bits, for example, the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set are distributed on the first bit stream as follows: the 5328 bits of the 21 bit blocks of the fifth bit set are continuous on the first bit stream, where 0≤i2<14. In still other specific applications, the specific distribution of the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set on the first bit stream can be continuous distribution of 6 rows of bit blocks with 10656 bits, for example, the 42 rows and 7 columns of the 294 bit blocks in the fifth bit set are distributed on the first bit stream as follows: the 10656 bits of the 42 bit blocks of the fifth bit set are continuous on the first bit stream, where 0≤i3<7.

[0322] As shown in FIG. 8, the bits in the fifth bit set are distributed as 294 bit blocks of 42 rows and 7 columns (0≤i0<42 and 0≤j0<7) and the specific bit pattern of (0≤i0<42 and 0≤j0<7) in the fifth bit set 2i+1 are not exactly the same. (0≤i0<42 and 0≤j0<5), part of bits from the second bit set after PCS processing and bits from the third bit set without PCS processing. The leftmost 5-column bit block in the fifth bit set, i.e., the bit block filled with shaded background shown in Fig. 8 (0≤i0<42 and 5≤j0<7), the remaining part of bits from the second bit set after PCS processing (i.e., without including bits from the third bit set).

[0323] It should be noted that the distribution of the specific bit blocks of the fifth bit set 2i on the first bit stream 2i and the fifth bit set 2i+1 on the first bit stream 2i+1 can be understood with reference to Fig. 8, but the specific bit pattern of each bit block is not exactly the same, that is, the specific bit pattern of the fifth bit set 2i is (0≤i0<42 and 0≤j0<7) and the specific bit pattern of (0≤i0<42 and 0≤j0<7) in the fifth bit set 2i+1 are not exactly the same. (0≤i0<42 and 0≤j0<7) and the specific bit pattern of (0≤i0<42 and 0≤j0<7) in the fifth bit set 2i+1 are not exactly the same.

[0324] It should be noted that the bit pattern (also referred to as bit distribution pattern) is used to describe the source and purpose of each bit in the bit block. The bit pattern is distributed in r rows and c columns, where r rows and c columns can be 16 rows and 16 columns, or 16 rows and 15 columns. More specifically, taking the first symbol mapping scheme as an example:

[0325] The part marked with the number "0" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b0 bit in the symbol mapping; this bit is from the third bit set without PCS processing or from the check bit of the FEC encoding, and is the symbol bit in X I on the symbol mapping;

[0326] The part marked with the number "1" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b1 bit in the symbol mapping; this bit is from the third bit set without PCS processing or from the check bit of the FEC encoding, and is the symbol bit in Y I on the symbol mapping;

[0327] The part marked with the number "2" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b2 bit in the symbol mapping; this bit is from the second bit set after PCS processing, and is the symbol bit in X Ithe first type of amplitude bits on the

[0328] The part marked with the number "3" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b3 bit in the symbol mapping; the bit is from the second bit set processed by the PCS and is X in the symbol mapping I the first type of amplitude bits on the

[0329] The part marked with the number "4" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b4 bit in the symbol mapping; the bit is from the second bit set processed by the PCS and is Y in the symbol mapping I the second type of amplitude bits on the

[0330] The part marked with the number "5" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b5 bit in the symbol mapping; the bit is from the second bit set processed by the PCS and is X in the symbol mapping I the second type of amplitude bits on the

[0331] The part marked with the number "6" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b6 bit in the symbol mapping; the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is Y in the symbol mapping Q the symbol bit on the

[0332] The part marked with the number "7" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b7 bit in the symbol mapping; the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is X in the symbol mapping Q the symbol bit on the

[0333] The part marked with the number "8" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b8 bit in the symbol mapping; the bit is from the second bit set processed by the PCS and is X in the symbol mapping Q the first type of amplitude bits on the

[0334] The part marked with the number "9" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b9 bit in the symbol mapping; the bit is from the second bit set processed by the PCS and is Y in the symbol mapping Q the first type of amplitude bits on the

[0335] In the bit pattern, the part marked with the number "10" in the r-th row and c-th column indicates that the bit in the r-th row and c-th column of the corresponding bit block is used as 'b' in the symbol mapping. 10 Bit; this bit is from the second set of bits processed by PCS, and serves as X in the symbol mapping. Q The second type of amplitude bit;

[0336] In the bit pattern, the part marked with the number "11" in the r-th row and c-th column indicates that the bit in the r-th row and c-th column of the corresponding bit block is used as b in the symbol mapping. 11 Bit; this bit is from the second set of bits processed by PCS, and serves as Y in the symbol mapping. Q The second type of amplitude bit.

[0337] The bit block patterns in the fifth bit set 2i and the fifth bit set 2i+1 are described below.

[0338] Referring to the 42-row, 7-column bit block diagram shown in Figure 8, the bit block in the fifth bit set 2i on the first bit stream 2i is described below. (0≤i0<42 and 0≤j0<7) pattern. Specifically, Figure 11(a) is a schematic diagram of a first bit pattern in an embodiment of this application; Figure 11(b) is a schematic diagram of a second bit pattern in an embodiment of this application; Figure 11(c) is a schematic diagram of a third bit pattern in an embodiment of this application; Figure 12(a) is a schematic diagram of a fourth bit pattern in an embodiment of this application; Figure 12(b) is a schematic diagram of a fifth bit pattern in an embodiment of this application; Figure 12(c) is a schematic diagram of a sixth bit pattern in an embodiment of this application; Figure 12(d) is a schematic diagram of another fourth bit pattern in an embodiment of this application; Figure 12(e) is a schematic diagram of another fifth bit pattern in an embodiment of this application; Figure 12(f) is a schematic diagram of another sixth bit pattern in an embodiment of this application; Figure 12(g) is a schematic diagram of yet another fourth bit pattern and fifth bit pattern in an embodiment of this application; Figure 12(h) is a schematic diagram of yet another sixth bit pattern in an embodiment of this application; Figure 13 is a schematic diagram of a seventh bit pattern, an eighth bit pattern and a ninth bit pattern in an embodiment of this application; Figure 14 is a schematic diagram of a tenth bit pattern, an eleventh bit pattern and a twelfth bit pattern in an embodiment of this application.

[0339] 1) For 0 ≤ i0 < 21 and i0%3 = 0, or 21 ≤ i0 < 42 and i0%3 = 2, i.e. i0 = 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0 = 0, 1, 2, 3: the corresponding 56 bit blocks The bit pattern uses the first bit pattern. As an example, the first bit pattern is shown in Figure 11(a), which contains a 16-row, 16-column bit block containing 32 bits labeled with the number "0", 32 bits labeled with the number "1", 32 bits labeled with the number "2", 32 bits labeled with the number "3", 16 bits labeled with the number "4", 16 bits labeled with the number "5", 16 bits labeled with the number "6", 16 bits labeled with the number "7", 16 bits labeled with the number "8", 16 bits labeled with the number "9", 16 bits labeled with the number "10", and 16 bits labeled with the number "11". That is, it contains 96 bits from the third bit set that has not been processed by PCS (and serves as the symbol bits in the symbol map), and 160 bits from the second bit set that has been processed by PCS (and serves as the amplitude bits in the symbol map). Of the 160 bits from the second bit set processed by PCS, 96 bits are used to generate first-type amplitude bits and 64 bits are used to generate second-type amplitude bits.

[0340] 2) For 0 ≤ i0 < 21 and i0%3 = 1, or 21 ≤ i0 < 42 and i0%3 = 0, i.e. i0 = 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0 = 0, 1, 2, 3: the corresponding 56 bit blocks The bit pattern uses the second bit pattern. As an example, the second bit pattern is shown in Figure 11(b), which contains a 16-row, 16-column bit block containing 16 bits labeled with the number "0", 16 bits labeled with the number "1", 16 bits labeled with the number "2", 16 bits labeled with the number "3", 32 bits labeled with the number "4", 32 bits labeled with the number "5", 32 bits labeled with the number "6", 32 bits labeled with the number "7", 16 bits labeled with the number "8", 16 bits labeled with the number "9", 16 bits labeled with the number "10", and 16 bits labeled with the number "11". That is, it contains 96 bits from the third bit set that has not been processed by PCS (and serves as the symbol bits in the symbol map), and 160 bits from the second bit set that has been processed by PCS (and serves as the amplitude bits in the symbol map). Of the 160 bits from the second set of bits processed by PCS, 64 bits are used to generate first-type amplitude bits and 96 bits are used to generate second-type amplitude bits.

[0341] 3) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0=0, 1, 2, 3, the corresponding 56 bit blocks The bit pattern of the 56 bit blocks corresponding to the third bit pattern is shown in Fig. 11(c). As an example, the third bit pattern comprises 16 rows and 16 columns of bit blocks, which contain 16 bits marked with the number "0", 16 bits marked with the number "1", 16 bits marked with the number "2", 16 bits marked with the number "3", 16 bits marked with the number "4", 16 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 32 bits marked with the number "8", 32 bits marked with the number "9", 32 bits marked with the number "10", and 32 bits marked with the number "11". That is, it contains 48 bits from the third bit set without PCS processing (and as the symbol bits in the symbol mapping), and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping). Among the 192 bits from the second bit set with PCS processing, 96 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0342] 4) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0=4, the corresponding 14 bit blocks The bit pattern of the 14 bit blocks corresponding to the fourth bit pattern is shown in Fig. 11(d).

[0343] As a specific embodiment, the fourth bit pattern is shown in FIG. 12(a), which includes 32 bits marked with the number "0", 24 bits marked with the number "1", 24 bits marked with the number "2", 24 bits marked with the number "3", 16 bits marked with the number "4", 10 bits marked with the number "5", 12 bits marked with the number "6", 14 bits marked with the number "7", 16 bits marked with the number "8", 14 bits marked with the number "9", 12 bits marked with the number "10", 58 bits marked with the number "11" in a 16-row 16-column bit block. That is, there are 82 bits from the third bit set without PCS processing (and as the sign bits in symbol mapping) and 174 bits from the second bit set with PCS processing (and as the amplitude bits in symbol mapping). Among the 174 bits from the second bit set with PCS processing, 78 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0344] As another specific embodiment, the fourth bit pattern is shown in FIG. 12(d), which includes 40 bits marked with the number "0", 24 bits marked with the number "1", 24 bits marked with the number "2", 24 bits marked with the number "3", 8 bits marked with the number "4", 6 bits marked with the number "5", 4 bits marked with the number "6", 10 bits marked with the number "7", 16 bits marked with the number "8", 18 bits marked with the number "9", 4 bits marked with the number "10", 78 bits marked with the number "11" in a 16-row 16-column bit block. That is, there are 78 bits from the third bit set without PCS processing (and as the sign bits in symbol mapping) and 178 bits from the second bit set with PCS processing (and as the amplitude bits in symbol mapping). Among the 178 bits from the second bit set with PCS processing, 82 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0345] As another specific embodiment, the fourth bit pattern is shown in FIG. 12(g), which includes 32 bits marked with the number "0", 16 bits marked with the number "1", 32 bits marked with the number "2", 32 bits marked with the number "3", 32 bits marked with the number "4", 32 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 0 bits marked with the number "8", 0 bits marked with the number "9", 0 bits marked with the number "10", and 48 bits marked with the number "11" in the 16x16 bit blocks. That is, there are 80 bits from the third bit set without PCS processing (and as the sign bits in the symbol mapping) and 176 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in total. Among the 176 bits from the second bit set with PCS processing, 64 bits are used to generate the first type of amplitude bits and 112 bits are used to generate the second type of amplitude bits.

[0346] 5) For 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0=4: the bit pattern of the corresponding 14 bit blocks adopts the fifth bit pattern.

[0347] As another specific embodiment, the fourth bit pattern is shown in FIG. 12(g), which includes 32 bits marked with the number "0", 16 bits marked with the number "1", 32 bits marked with the number "2", 32 bits marked with the number "3", 32 bits marked with the number "4", 32 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 0 bits marked with the number "8", 0 bits marked with the number "9", 0 bits marked with the number "10", and 48 bits marked with the number "11" in the 16x16 bit blocks. That is, there are 80 bits from the third bit set without PCS processing (and as the sign bits in the symbol mapping) and 176 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in total. Among the 176 bits from the second bit set with PCS processing, 64 bits are used to generate the first type of amplitude bits and 112 bits are used to generate the second type of amplitude bits.

[0348] As another specific embodiment, the fifth bit pattern is shown in Fig. 12(e), which contains 16 bits marked with the number "0", 18 bits marked with the number "1", 20 bits marked with the number "2", 22 bits marked with the number "3", 40 bits marked with the number "4", 40 bits marked with the number "5", 24 bits marked with the number "6", 32 bits marked with the number "7", 24 bits marked with the number "8", 6 bits marked with the number "9", 4 bits marked with the number "10", and 10 bits marked with the number "11" in the 16-by-16 bit block. That is, there are 90 bits from the third bit set without PCS processing (and as the sign bits in the symbol mapping) and 166 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in total. Among the 166 bits from the second bit set with PCS processing, 72 bits are used to generate the first type of amplitude bits and 94 bits are used to generate the second type of amplitude bits.

[0349] As another specific embodiment, the fifth bit pattern is shown in Fig. 12(e), which contains 16 bits marked with the number "0", 18 bits marked with the number "1", 20 bits marked with the number "2", 22 bits marked with the number "3", 40 bits marked with the number "4", 40 bits marked with the number "5", 24 bits marked with the number "6", 32 bits marked with the number "7", 24 bits marked with the number "8", 6 bits marked with the number "9", 4 bits marked with the number "10", and 10 bits marked with the number "11" in the 16-by-16 bit block. That is, there are 90 bits from the third bit set without PCS processing (and as the sign bits in the symbol mapping) and 166 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in total. Among the 166 bits from the second bit set with PCS processing, 72 bits are used to generate the first type of amplitude bits and 94 bits are used to generate the second type of amplitude bits.

[0350] 6) For 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0=4: the bit pattern of the corresponding 14 bit blocks adopts the sixth bit pattern.

[0351] As a specific embodiment, the sixth bit pattern is shown in Fig. 12(c), which includes 16 rows and 16 columns of bit blocks, and includes 16 bits marked with the number "0", 10 bits marked with the number "1", 12 bits marked with the number "2", 14 bits marked with the number "3", 16 bits marked with the number "4", 14 bits marked with the number "5", 12 bits marked with the number "6", 10 bits marked with the number "7", 32 bits marked with the number "8", 40 bits marked with the number "9", 40 bits marked with the number "10", and 40 bits marked with the number "11". That is, a total of 48 bits from the third bit set without PCS processing (and as symbol bits in symbol mapping), and 208 bits from the second bit set with PCS processing (and as amplitude bits in symbol mapping). Of the 208 bits from the second bit set with PCS processing, 98 bits are used to generate the first type of amplitude bits, and 110 bits are used to generate the second type of amplitude bits.

[0352] As another specific embodiment, the sixth bit pattern is shown in Fig. 12(f), which includes 16 rows and 16 columns of bit blocks, and includes 8 bits marked with the number "0", 6 bits marked with the number "1", 20 bits marked with the number "2", 18 bits marked with the number "3", 16 bits marked with the number "4", 18 bits marked with the number "5", 20 bits marked with the number "6", 6 bits marked with the number "7", 24 bits marked with the number "8", 40 bits marked with the number "9", 56 bits marked with the number "10", and 24 bits marked with the number "11". That is, a total of 40 bits from the third bit set without PCS processing (and as symbol bits in symbol mapping), and 216 bits from the second bit set with PCS processing (and as amplitude bits in symbol mapping). Of the 216 bits from the second bit set with PCS processing, 102 bits are used to generate the first type of amplitude bits, and 114 bits are used to generate the second type of amplitude bits.

[0353] As yet another specific implementation, a sixth bit pattern is shown in FIG. 12(h), which includes 0 bits labeled with the numeral "0", 16 bits labeled with the numeral "1", 0 bits labeled with the numeral "2", 0 bits labeled with the numeral "3", 0 bits labeled with the numeral "4", 0 bits labeled with the numeral "5", 16 bits labeled with the numeral "6", 16 bits labeled with the numeral "7", 64 bits labeled with the numeral "8", 64 bits labeled with the numeral "9", 64 bits labeled with the numeral "10", and 16 bits labeled with the numeral "11" in a 16-by-16 block of bits. That is, a total of 48 bits from the third set of bits (and as the sign bits in the symbol mapping) that are not processed by the PCS, and 208 bits from the second set of bits (and as the amplitude bits in the symbol mapping) that are processed by the PCS. Of the 208 bits from the second set of bits that are processed by the PCS, 128 bits are used to generate the first type of amplitude bits, and 80 bits are used to generate the second type of amplitude bits.

[0354] 7) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0=5: the corresponding 14-bit block As an example, a seventh bit pattern is shown in FIG. 13, which includes 0 bits labeled with the numeral "0", 0 bits labeled with the numeral "1", 32 bits labeled with the numeral "2", 32 bits labeled with the numeral "3", 32 bits labeled with the numeral "4", 32 bits labeled with the numeral "5", 0 bits labeled with the numeral "6", 0 bits labeled with the numeral "7", 32 bits labeled with the numeral "8", 32 bits labeled with the numeral "9", 32 bits labeled with the numeral "10", and 32 bits labeled with the numeral "11" in a 16-by-16 block of bits. That is, a total of 0 bits from the third set of bits (and as the sign bits in the symbol mapping) that are not processed by the PCS, and 256 bits from the second set of bits (and as the amplitude bits in the symbol mapping) that are processed by the PCS. Of the 256 bits from the second set of bits that are processed by the PCS, 128 bits are used to generate the first type of amplitude bits, and 128 bits are used to generate the second type of amplitude bits.

[0355] 8) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0=5: the corresponding 14-bit block The bit pattern uses an eighth-bit pattern. As an example, the eighth-bit pattern is shown in Figure 13.

[0356] 9) For 0 ≤ i0 < 21 and i0%3 = 2, or 21 ≤ i0 < 42 and i0%3 = 1, i.e. i0 = 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0 = 5: the corresponding 14 bit blocks The bit pattern uses the ninth bit pattern. As an example, the ninth bit pattern is shown in Figure 13.

[0357] 10) For 0 ≤ i0 < 21 and i0%3 = 0, or 21 ≤ i0 < 42 and i0%3 = 2, i.e. i0 = 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0 = 6: the corresponding 14 bit blocks The bit pattern uses the tenth bit pattern. As an example, the tenth bit pattern is shown in Figure 14, which contains a 16-row, 15-column bit block containing 0 bits labeled with the number "0", 0 bits labeled with the number "1", 32 bits labeled with the number "2", 32 bits labeled with the number "3", 32 bits labeled with the number "4", 32 bits labeled with the number "5", 0 bits labeled with the number "6", 0 bits labeled with the number "7", 32 bits labeled with the number "8", 32 bits labeled with the number "9", 32 bits labeled with the number "10", and 16 bits labeled with the number "11". That is, it contains 0 bits from the third bit set that has not been processed by PCS (and serves as the symbol bits in the symbol map), and 240 bits from the second bit set that has been processed by PCS (and serves as the amplitude bits in the symbol map). Of the 240 bits from the second bit set processed by PCS, 128 bits are used to generate the first type of amplitude bits and 112 bits are used to generate the second type of amplitude bits.

[0358] 11) For 0 ≤ i0 < 21 and i0%3 = 1, or 21 ≤ i0 < 42 and i0%3 = 0, i.e. i0 = 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0 = 6: the corresponding 14 bit blocks The bit pattern uses the eleventh bit pattern. As an example, the eleventh bit pattern is shown in Figure 14.

[0359] 12) For 0 ≤ i0 < 21 and i0%3 = 2, or 21 ≤ i0 < 42 and i0%3 = 1, i.e. i0 = 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0 = 6: the corresponding 14 bit blocks The bit pattern uses the twelfth bit pattern. As an example, the twelfth bit pattern is shown in Figure 14.

[0360] It should be noted that for the case where 0 ≤ i0 < 42 and j0 = 4, the corresponding 42 bit blocks The 42-bit block contains a total of 7840 bits from the second bit set (serving as amplitude bits in the symbol map) and 2912 bits from the third bit set (serving as sign bits in the symbol map). Further, the 42-bit block... In the context of each consecutive 3 rows of bit blocks, i.e., when 0 ≤ i2 < 14 and j0 = 4, the corresponding 3 bit blocks The 768 bits comprise 560 bits from the second bit set and 208 bits from the third bit set. In one specific implementation, the fourth bit pattern is shown in Figure 12(a), the fifth bit pattern in Figure 12(b), and the sixth bit pattern in Figure 12(c). In another specific implementation, the fourth bit pattern is shown in Figure 12(d), the fifth bit pattern in Figure 12(e), and the sixth bit pattern in Figure 12(f). In yet another specific implementation, the fourth bit pattern is shown in Figure 12(g), the fifth bit pattern in Figure 12(g), and the sixth bit pattern in Figure 12(h).

[0361] Referring to the schematic diagram of a 42-row, 7-column bit block shown in Figure 8, the bit block in the fifth bit set 2i+1 of the first bit stream 2i+1 is described below. (0≤i0<42 and 0≤j0<7) pattern.

[0362] 1) For 0 ≤ i0 < 21 and i0%3 = 0, or 21 ≤ i0 < 42 and i0%3 = 2, i.e. i0 = 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0 = 0, 1, 2, 3: the corresponding 56 bit blocks The bit pattern uses a third bit pattern. As an example, the third bit pattern is shown in Figure 11(c).

[0363] 2) For 0 ≤ i0 < 21 and i0%3 = 1, or 21 ≤ i0 < 42 and i0%3 = 0, i.e. i0 = 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0 = 0, 1, 2, 3: the corresponding 56 bit blocks The bit pattern uses the first bit pattern. As an example, the first bit pattern is shown in Figure 11(a).

[0364] 3) For 0 ≤ i0 < 21 and i0%3 = 2, or 21 ≤ i0 < 42 and i0%3 = 1, i.e. i0 = 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0 = 0, 1, 2, 3: the corresponding 56 bit blocks The bit pattern uses the second bit pattern. As an example, the second bit pattern is shown in Figure 11(b).

[0365] 4) For 0 ≤ i0 < 21 and i0%3 = 0, or 21 ≤ i0 < 42 and i0%3 = 2, i.e. i0 = 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0 = 4: the corresponding 14 bit blocks All bit patterns use the sixth bit pattern.

[0366] In one specific implementation, the sixth bit pattern is shown in Figure 12(c). In another specific implementation, the sixth bit pattern is shown in Figure 12(f). In yet another specific implementation, the sixth bit pattern is shown in Figure 12(h).

[0367] 5) For 0 ≤ i0 < 21 and i0%3 = 1, or 21 ≤ i0 < 42 and i0%3 = 0, i.e. i0 = 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0 = 4: the corresponding 14 bit blocks All bit patterns use the fourth bit pattern.

[0368] In one specific embodiment, the fourth bit pattern is shown in Figure 12(a). In another specific embodiment, the fourth bit pattern is shown in Figure 12(d). In yet another specific embodiment, the fourth bit pattern is shown in Figure 12(g).

[0369] 6) For 0 ≤ i0 < 21 and i0%3 = 2, or 21 ≤ i0 < 42 and i0%3 = 1, i.e. i0 = 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0 = 4: the corresponding 14 bit blocks All bit patterns use the fifth bit pattern.

[0370] As a specific embodiment, the fifth bit pattern is shown in Figure 12(b). As another specific embodiment, the fifth bit pattern is shown in Figure 12(e). As yet another specific embodiment, the fifth bit pattern is shown in Figure 12(g).

[0371] 7) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0=5: the corresponding 14-bit block adopts the ninth bit pattern. As an example, the ninth bit pattern is shown in Figure 13.

[0372] 8) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0=5: the corresponding 14-bit block adopts the seventh bit pattern. As an example, the seventh bit pattern is shown in Figure 13.

[0373] 9) For 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j0=5: the corresponding 14-bit block adopts the eighth bit pattern. As an example, the eighth bit pattern is shown in Figure 13.

[0374] 10) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j0=6: the corresponding 14-bit block adopts the twelfth bit pattern. As an example, the twelfth bit pattern is shown in Figure 14.

[0375] 11) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j0=6: the corresponding 14-bit block adopts the tenth bit pattern. As an example, the tenth bit pattern is shown in Figure 14.

[0376] 12) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2,5,8,11,14,17,20,22,25,28,31,34,37,40, and j0=6: the corresponding 14 bit blocks The bit pattern in the 42 bit blocks

[0377] It is noted that for the fifth bit set 2i and the fifth bit set 2i+1, when 0≤i0<42 and j0=4, the corresponding 42 bit blocks contain a total of 7840 bits from the second bit sets (as amplitude bits in the symbol mapping) and 2912 bits from the third bit sets (as sign bits in the symbol mapping). Further, each consecutive 3 row of the 42 bit blocks contain 768 bits, i.e., 0≤i2<14 and j0=4, of the corresponding 3 bit blocks contain 560 bits from the second bit sets and 208 bits from the third bit sets. As one implementation, the fourth bit pattern, the fifth bit pattern and the sixth bit pattern when the first symbol mapping is used are shown in Figures 12(a), 12(b) and 12(c), respectively. As another implementation, the fourth bit pattern, the fifth bit pattern and the sixth bit pattern when the first symbol mapping is used are shown in Figures 12(d), 12(e) and 12(f), respectively. As yet another implementation, the fourth bit pattern, the fifth bit pattern and the sixth bit pattern when the first symbol mapping is used are shown in Figures 12(g), 12(h) and 12(i), respectively.

[0378] It is further noted that for the fifth bit set 2i and the fifth bit set 2i+1, when 0≤i0<42 and 4≤j0<7, the corresponding 126 bit blocks contain a total of 28672 bits from the second bit sets (as amplitude bits in the symbol mapping) and 2912 bits from the third bit sets (as sign bits in the symbol mapping). Further, each consecutive 3 row of the 126 bit blocks contain 9 bit blocks The middle one contains 2048 bits from the second bit set (as amplitude bits in symbol mapping) and 208 bits from the third bit set (as sign bits in symbol mapping), where 0≤i2<14. And the above-mentioned 9 bit blocks contain 256 bits marked with the number "2" (as bits b2 in symbol mapping), 256 bits marked with the number "3" (as bits b3 in symbol mapping), 256 bits marked with the number "4" (as bits b4 in symbol mapping), 256 bits marked with the number "5" (as bits b5 in symbol mapping), 256 bits marked with the number "8" (as bits b8 in symbol mapping), 256 bits marked with the number "9" (as bits b9 in symbol mapping), 256 bits marked with the number "10" (as bits b10 in symbol mapping), and 256 bits marked with the number "11" (as bits b11 in symbol mapping) in total. Then, for 0≤i0<42 and j0=5, the specific patterns of the corresponding seventh bit pattern, eighth bit pattern and ninth bit pattern may not be consistent; for 0≤i0<42 and j0=6, the specific patterns of the corresponding tenth bit pattern, eleventh bit pattern and twelfth bit pattern may not be consistent. 10 11

[0379] For other possible specific patterns of the fourth bit pattern, the fifth bit pattern, the sixth bit pattern, the seventh bit pattern, the eighth bit pattern, the ninth bit pattern, the tenth bit pattern, the eleventh bit pattern and the twelfth bit pattern, the present application will not be repeated.

[0380] It should be noted that the bit blocks (or square matrices) in different figures in the present application are marked with the same shaded background, which does not mean that the patterns of these bit blocks are exactly the same, but is only a kind of graphical representation method. It should be noted that the bits in the second bit set after PCS processing are used as amplitude bits in symbol mapping (also called modulation), and the bits in the third bit set without PCS processing are used as sign bits in symbol mapping (also called modulation).

[0381] It should be noted that the bit block distribution of the fifth bit set 2i and the fifth bit set 2i+1 is shown in FIG. 8, but the specific bit blocks in the fifth bit set 2i and the fifth bit set 2i+1 are not exactly the same. More specifically, the distribution patterns of the bit blocks (0≤i1<42 and 0≤j1<5) are different, that is, the distribution positions of the amplitude bits and the sign bits in the bit blocks are different. It should be understood that the first bit stream 2i after "PCS processing and first interleaving" can include multiple fifth bit sets 2i, and the first bit stream 2i+1 can include multiple fifth bit sets 2i+1. ​​

[0382] (2) FEC encoding:

[0383] FIG. 15 is a schematic diagram of an embodiment of the present application for data processing of two first bit streams. As shown in FIG. 15, the FEC encoding 2i encodes the fifth bit set 2i in the first bit stream 2i to add check bits to obtain the sixth bit set 2i. The FEC encoding 2i+1 encodes the fifth bit set 2i+1 in the first bit stream 2i+1 to add check bits to obtain the sixth bit set 2i+1. It should be understood that the second bit stream 2i output by the FEC encoding can include a plurality of sixth bit sets 2i, and the second bit stream 2i+1 output by the FEC encoding can include a plurality of sixth bit sets 2i+1. It should be noted that the input processing granularity of the FEC encoding is K, and the corresponding output granularity is N, considering that K / N = 111 / 128, the encoding redundancy of the FEC encoding is N / K-1 = 15.3%. As an example, K = 3552, N = 4096, and the FEC encoding uses extended BCH (256, 239). The FEC encoding encodes and adds check bits to 3552 bits in each 2-bit row of the fifth bit set to obtain a total of 4096 encoded bits, and performs 21 operations to obtain the sixth bit set. The FEC encoding encodes and adds 17 parity bits to 111 bits in each bit row of the fifth bit set to obtain a total of 128 bits in a row of the sixth bit set. More specifically, 111 bits in a bit row in a bit block row (which can be considered as a bit block row at the current time) in the fifth bit set are combined with a total of 128 bits in a bit row in a plurality of bit block rows (which can be considered as bit block rows at previous times) in the fifth bit set to obtain a total of 111+128 = 239 bits, and the extended BCH (256, 239) encoding is performed to add 17 check bits to obtain 256 bits of a code word. It should be understood that the FEC encoding is a convolution algebra code, also known as a spatially coupled code.

[0384] It is to be noted that the second bit stream contains a plurality of sixth bit sets, and each of the sixth bit sets has 42 rows and 8 columns of bit blocks, each of which is a square matrix containing 16 rows and 16 columns of bits. Typically, 256 bits in each of the square matrices are continuous on the second bit stream. FIG. 16 is a schematic diagram of an embodiment of the present application showing 8 columns of bit blocks in each row. As shown in FIG. 16, each row of bit blocks contains 8 bit blocks, and the total number of bits is 2048 bits. It is to be understood that the operations of the fourth interleaving, the fifth interleaving, the intra-matrix interleaving and the inter-matrix interleaving are performed in the granularity of 42 rows and 8 columns of bit blocks from the FEC encoding until the third interleaving is completed. It is to be noted that in some specific applications, the fourth interleaving can be performed in the granularity of 3 rows and 8 columns of bit blocks, i.e., the fourth interleaving is time-varying, and the operations of 3 rows and 8 columns of bit blocks are different at different times; in other specific applications, the fourth interleaving can be performed in the granularity of 6 rows and 8 columns of bit blocks, i.e., the fourth interleaving is time-varying, and the operations of 6 rows and 8 columns of bit blocks are different at different times. For simplicity of description, the operations of the fourth interleaving, the fifth interleaving, the intra-matrix interleaving and the inter-matrix interleaving are performed in the granularity of 42 rows and 8 columns of bit blocks in the present application.

[0385] FIG. 17 is a schematic diagram of a sixth bit set according to an embodiment of the present application. As shown in FIG. 17, the sixth bit set is in the form of a rectangular block of bits. The square matrix at the i2th row and the j2th column of the sixth bit set is denoted as where 0≤i2<42 and 0≤j2<8.

[0386] In some specific applications, the bit block (0≤i0<42 and 0≤j1<8) contains 16 rows and 16 columns of bits, i.e., 256 bits, which are continuous on the second bit stream. More specifically, FIG. 9 shows a specific distribution, in which the bit at the r0th row and the c0th column (0≤r0<16 and 0≤c0<16) in each of the bit blocks (0≤i0<42 and 0≤j1<8) corresponds to the 16xr0+c0th bit of the 256 bits. For example, the bit at the r0=1th row and the c0=0th column in each of the bit blocks corresponds to the 16th bit of the 256 bits. For another example, the bit at the r0=2th row and the c0=3th column in each of the bit blocks corresponds to the 35th bit of the 256 bits.

[0387] It is to be noted that in some specific applications, the specific distribution of the 42 rows and 8 columns of bit blocks in the sixth bit set on the second bit stream can be continuous distribution of 1 row of bit blocks, i.e., 2048 bits, for example, the 42 rows and 8 columns of bit blocks in the sixth bit set The 8 bit blocks, totaling 2048 bits, are consecutive in the second bitstream, where 0 ≤ i0 < 42. In other specific applications, the 42 rows and 8 columns of the sixth bit set, totaling 336 bits, can be distributed consecutively in the second bitstream as 2 rows of bit blocks, totaling 4096 bits. For example, in the sixth bit set... The 16 bit blocks, totaling 4096 bits, are consecutive in the second bitstream, where 0 ≤ i1 < 21. In some specific applications, the 42 rows and 8 columns of the sixth bit set, totaling 336 bits, can be distributed consecutively in the second bitstream as 3 rows of bit blocks, totaling 6144 bits. For example, in the sixth bit set... The 24 bit blocks, totaling 6144 bits, are consecutive in the second bitstream, where 0 ≤ i² < 14. In some specific applications, the 42 rows and 8 columns (336 bits) of the sixth bit set can be distributed as 6 rows of consecutive bit blocks (12288 bits) in the second bitstream. For example, in the sixth bit set... The 48 bit blocks, totaling 12288 bits, are consecutive on the second bit stream, where 0 ≤ i3 < 7.

[0388] As shown in Figure 17, the bits in the sixth bit set are distributed in a 42-row, 8-column block of 336 bits. (0≤i0<42 and 0≤j1<8). The bits in the leftmost 5 columns (i.e., columns 0-4) of the sixth bit set, i.e., the bit block filled with the shaded background shown in Figure 17. (0≤i0<42 and 0≤j1<5), bits from the second bit set processed by PCS and bits from the third bit set not processed by PCS. The 5th column bit block in the sixth bit set. (0≤i0<42), and the 6th column bit block The leftmost 15-bit column (0≤i0<42), comprising 16+15=31 bits, consists of bits from the remaining bits in the second bit set processed by PCS (i.e., excluding bits from the third bit set). The 6th bit block in the 6th bit set... The rightmost bit column and the 7th bit block in (0≤i0<42) ((0≤i0<42), and the bits in the 1+16=17 bit column are from the FEC-encoded check bits.

[0389] It should be noted that the specific bit block distribution of the sixth bit set 2i on the second bit stream 2i and the sixth bit set 2i+1 on the second bit stream 2i+1 can be understood with reference to Figure 17, but the specific bit pattern of each bit block (square matrix) is not exactly the same, that is, the specific bit pattern of the sixth bit set 2i is not exactly the same as the specific bit pattern of the sixth bit set 2i+1. (0≤i0<42 and 0≤j1<8) and the specific bit pattern of the sixth bit set 2i+1 (0≤i0<42 and 0≤j1<8) is not exactly the same. The bit block (square matrix) pattern in the sixth bit set 2i and the sixth bit set 2i+1 will be introduced below. Figure 18 is a schematic diagram of a thirteenth bit pattern, a fourteenth bit pattern and a fifteenth bit pattern in an embodiment of the present application; Figure 19(a) is a schematic diagram of a sixteenth bit pattern in an embodiment of the present application; Figure 19(b) is a schematic diagram of a seventeenth bit pattern in an embodiment of the present application; and Figure 19(c) is a schematic diagram of an eighteenth bit pattern in an embodiment of the present application.

[0390] The bit block pattern in the sixth bit set 2i will be introduced below. (0≤i0<42 and 0≤j1<8).

[0391] 1) For 0≤i0<42 and 0≤j1<6, the bit pattern of the bit block (square matrix) in the sixth bit set 2i is the same as the bit block (square matrix) in the corresponding fifth bit set 2i before encoding.

[0392] 2) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, that is, i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j1=6: the corresponding 14 bit blocks (square matrices) The bit pattern of the thirteenth bit pattern is adopted. As an example, the thirteenth bit pattern is shown in FIG. 18, which contains 16 bits marked with the number "0", 0 bits marked with the number "1", 32 bits marked with the number "2", 32 bits marked with the number "3", 32 bits marked with the number "4", 32 bits marked with the number "5", 0 bits marked with the number "6", 0 bits marked with the number "7", 32 bits marked with the number "8", 32 bits marked with the number "9", 32 bits marked with the number "10", 16 bits marked with the number "11" in the 16 rows by 16 columns of bit blocks. That is, it contains 16 check bits from the FEC encoding (and as the symbol bits in the symbol mapping) and 240 bits from the second set of bits processed by the PCS (and as the amplitude bits in the symbol mapping) in total. Among the 240 bits from the second set of bits processed by the PCS, 128 bits are used to generate the first type of amplitude bits, and 112 bits are used to generate the second type of amplitude bits.

[0393] 3) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=6: the corresponding 14 bit blocks (square matrix) The bit pattern of the fourteenth bit pattern is adopted. As an example, the fourteenth bit pattern is shown in FIG. 18.

[0394] 4) For 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=6: the corresponding 14 bit blocks (square matrix) The bit pattern of the fifteenth bit pattern is adopted. As an example, the fifteenth bit pattern is shown in FIG. 18.

[0395] 5) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j1=7: the corresponding 14 bit blocks (square matrix) The bit pattern of the 16th bit set is the 16th bit pattern. As an example, the 16th bit pattern is shown in FIG. 19(a), which includes 256 check bits from the FEC encoding (and as the symbol bits in the symbol mapping) in 16 rows and 16 columns of bit blocks, wherein the 256 bits include 48 bits labeled with the numeral "0", 80 bits labeled with the numeral "1", 64 bits labeled with the numeral "6", and 64 bits labeled with the numeral "7".

[0396] 6) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=7: the corresponding 14 bit blocks (square matrix) The bit pattern of the 17th bit set is the 17th bit pattern. As an example, the 17th bit pattern is shown in FIG. 19(b), which includes 256 check bits from the FEC encoding (and as the symbol bits in the symbol mapping) in 16 rows and 16 columns of bit blocks, wherein the 256 bits include 48 bits labeled with the numeral "0", 64 bits labeled with the numeral "1", 80 bits labeled with the numeral "6", and 64 bits labeled with the numeral "7".

[0397] 7) For 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=7: the corresponding 14 bit blocks (square matrix) The bit pattern of the 18th bit set is the 18th bit pattern. As an example, the 18th bit pattern is shown in FIG. 19(c), which includes 256 check bits from the FEC encoding (and as the symbol bits in the symbol mapping) in 16 rows and 16 columns of bit blocks, wherein the 256 bits include 48 bits labeled with the numeral "0", 64 bits labeled with the numeral "1", 64 bits labeled with the numeral "6", and 80 bits labeled with the numeral "7".

[0398] The bit pattern of the 6th bit set 2i+1 is described below. (0≤i0<42 and 0≤j1<8).

[0399] 1) For 0≤i0<42 and 0≤j1<6, the bit pattern of the bit block (square matrix) in the 6th bit set 2i+1 is the same as that of the corresponding bit block (square matrix) in the 5th bit set 2i+1 before encoding.

[0400] 2) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j1=6: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the 15th bit pattern is adopted. As an example, the 15th bit pattern is shown in FIG. 18.

[0401] 3) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=6: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the 13th bit pattern is adopted. As an example, the 13th bit pattern is shown in FIG. 18.

[0402] 4) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=6: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the 14th bit pattern is adopted. As an example, the 14th bit pattern is shown in FIG. 18.

[0403] 5) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and j1=7: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the 18th bit pattern is adopted. As an example, the 18th bit pattern is shown in FIG. 19(c).

[0404] 6) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=7: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the 16th bit pattern is adopted. As an example, the 16th bit pattern is shown in FIG. 19(a).

[0405] 7) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=7: the bit pattern of the corresponding 14-bit block (square matrix) The bit pattern of the seventeenth bit set is the seventeenth bit pattern. As an example, the seventeenth bit pattern is shown in FIG. 19(b).

[0406] In some specific applications, one sixth bit set 2i in the second bit stream 2i is directly added with check bits from one fifth bit set 2i before encoding, and one sixth bit set 2i+1 in the second bit stream 2i+1 is directly added with check bits from one fifth bit set 2i+1 before encoding. More specifically, the bit data of the 0th-111th columns in one sixth bit set 2i in the second bit stream 2i is equal to the bit data of the 0th-111th columns in one fifth bit set 2i before encoding; and the bit data of the 0th-111th columns in one sixth bit set 2i+1 in the second bit stream 2i+1 is equal to the bit data of the 0th-111th columns in one fifth bit set 2i+1 before encoding.

[0407] It is noted that for the sixth bit set 2i and the sixth bit set 2i+1, when 0≤i0<42 and 4≤j1<8, the corresponding 168 bit blocks include a total of 28672 bits from the second bit set (as the amplitude bits in the symbol mapping) and 14336 bits from the third bit set without PCS processing or from the check bits of the FEC encoding (and as the sign bits in the symbol mapping). Further, the 168 bit blocks include a total of 28672 bits from the second bit set (as the amplitude bits in the symbol mapping) and 14336 bits from the third bit set without PCS processing or from the check bits of the FEC encoding (and as the sign bits in the symbol mapping). Further, the 168 bit blocks The 2048 bits from the second bit set (as amplitude bits in the symbol mapping) and 1024 bits from the third bit set (as check bits from FEC encoding) or from the third bit set without PCS processing (as symbol bits in the symbol mapping) in one of the 12 bit blocks (0≤j1<14). And the 256 bits marked with the number "0" (as bit b0 in the symbol mapping), 256 bits marked with the number "1" (as bit b1 in the symbol mapping), 256 bits marked with the number "2" (as bit b2 in the symbol mapping), 256 bits marked with the number "3" (as bit b3 in the symbol mapping), 256 bits marked with the number "4" (as bit b4 in the symbol mapping), 256 bits marked with the number "5" (as bit b5 in the symbol mapping), 256 bits marked with the number "6" (as bit b6 in the symbol mapping), and 256 bits marked with the number "7" (as bit b7 in the symbol mapping), 256 bits marked with the number "8" (as bit b8 in the symbol mapping), 256 bits marked with the number "9" (as bit b9 in the symbol mapping), 256 bits marked with the number "10" (as bit b 10 in the symbol mapping), and 256 bits marked with the number "11" (as bit b 11 in the symbol mapping) in one of the 12 bit blocks (0≤i0<42 and j1=6) can be different. The specific patterns of the thirteenth bit pattern, the fourteenth bit pattern, and the fifteenth bit pattern can be different from the examples shown in FIG. 19(a), FIG. 19(b), and FIG. 19(c) for 0≤i0<42 and j1=7.

[0408] Other possible specific patterns of the thirteenth bit pattern, the fourteenth bit pattern, the fifteenth bit pattern, the sixteenth bit pattern, the seventeenth bit pattern, and the eighteenth bit pattern are not described herein.

[0409] It should be further noted that the bit block (square matrix) distribution of the sixth bit set 2i and the sixth bit set 2i+1 is shown in FIG. 17, but the specific bit blocks in the bit block (0≤i0<42 and 0≤j1<8) are different, i.e., the distribution positions of the amplitude bits and the symbol bits in the bit block are different. It should be understood that the second bit stream 2i after "FEC encoding" can include multiple sixth bit sets 2i, and the second bit stream 2i+1 can include multiple sixth bit sets 2i+1.

[0410] (3) Second interleaving:

[0411] As shown in FIG. 15, the second interleaving can include two steps of fourth interleaving and fifth interleaving. More specifically, the second interleaving 2i includes the fourth interleaving 2i and the fifth interleaving 2i, and the second interleaving 2i+1 includes the fourth interleaving 2i+1 and the fifth interleaving 2i+1.

[0412] The sixth bit set 2i distributed as 42 rows and 8 columns of bit blocks in the second bit stream 2i is sent into the fourth interleaving 2i to obtain the ninth bit set 2i, and the ninth bit set 2i distributed as 42 rows and 8 columns of bit blocks is sent into the fifth interleaving 2i to obtain the seventh bit set 2i. Similarly, the sixth bit set 2i+1 distributed as 42 rows and 8 columns of bit blocks in the second bit stream 2i+1 is sent into the fourth interleaving 2i+1 to obtain the ninth bit set 2i+1, and the ninth bit set 2i+1 distributed as 42 rows and 8 columns of bit blocks is sent into the fifth interleaving 2i+1 to obtain the seventh bit set 2i+1. It should be understood that, as shown in FIG. 15, the fifth bit stream 2i output by the fourth interleaving 2i can include a plurality of ninth bit sets 2i, and the fifth bit stream 2i+1 output by the fourth interleaving 2i+1 can include a plurality of ninth bit sets 2i+1. The third bit stream 2i output by the fifth interleaving 2i can include a plurality of seventh bit sets 2i, and the third bit stream 2i+1 output by the fifth interleaving 2i+1 can include a plurality of seventh bit sets 2i+1.

[0413] The fourth interleaving and the fifth interleaving are described below respectively.

[0414] In some specific application scenarios, the fourth interleaving interleaves and disarranges the order of the bits in the 168 bit blocks from the j1=4th to the j1=7th in the sixth bit set (0≤i0<42 and 4≤j1<8) to obtain the ninth bit set, that is, does not change the bit positions of the 168 bit blocks from the j1=0th to the j1=3rd in the sixth bit set (0≤i0<42 and 0≤j1<4). Further, in some specific application scenarios, the fourth interleaving does not change the bit positions of some bit columns in the 4th column of the sixth bit set (0≤i0<42). For example, does not change the bit positions of the first (i.e., leftmost) some bit columns in the 4th column of the sixth bit set (0≤i0<42). For example, does not change the bit positions of the first (i.e., leftmost) some bit columns in the 4th column of the sixth bit set (0≤i0<42). For example, does not change the bit positions of the first (i.e., leftmost) some bit columns in the 4th column of the sixth bit set (0≤i0<42). For example, does not change the bit positions of the first (i.e., leftmost) some bit columns in the 4th column of the sixth bit set columns 10, 11, 12, 13, 14, 15, and combining The fourth interleaving is performed on the 54-bit columns.

[0415] Fig. 20 is a diagram of a ninth bit set in an embodiment of the present application. As shown in Fig. 20, the distribution of bits in the ninth bit set obtained after the fourth interleaving is 42 rows by 8 columns, i.e., 336 bit blocks. (0≤i0<42 and 0≤j1<8). It should be noted that the size of each of the 336 bit blocks (0≤i0<42 and 0≤j1<8) is 16 rows by 16 columns, i.e., 256 bits (16x16=256), as shown in Fig. 9. For simplicity of description, denotes a bit in the r0th row and the c0th column of the bit block in the i3th square row and the j3th square column, where 0≤r0<16 and 0≤c0<16. In some specific applications, the 256 bits in the 16 rows by 16 columns of the bit block are continuous on the fifth bit stream.

[0416] The bit block pattern in the ninth bit set 2i and the ninth bit set 2i+1 will be described below.

[0417] Referring to the diagram of the 42 rows by 8 columns of bit blocks shown in Fig. 20, the bit block pattern in the ninth bit set 2i on the fifth bit stream will be described below. (0≤i0<42 and 0≤j1<8).

[0418] 1) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks uses the first bit pattern. As an example, the first bit pattern is shown in Fig. 11(a).

[0419] 2) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks uses the second bit pattern. As an example, the second bit pattern is shown in Fig. 11(b).

[0420] 3) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The third bit pattern is used for the bit pattern of the 112 bit blocks. As an example, the third bit pattern is shown in Fig. 11(c).

[0421] Referring to the 42-row 8-column bit block diagram shown in Fig. 20, the following describes the bit pattern of the 112 bit blocks in the ninth bit set 2i+1 on the 2i+1th bit stream (0≤i3<42 and 0≤j3<8).

[0422] 1) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The third bit pattern is used for the bit pattern of the 112 bit blocks. As an example, the third bit pattern is shown in Fig. 11(c).

[0423] 2) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The first bit pattern is used for the bit pattern of the 112 bit blocks. As an example, the first bit pattern is shown in Fig. 11(a).

[0424] 3) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The second bit pattern is used for the bit pattern of the 112 bit blocks. As an example, the second bit pattern is shown in Fig. 11(b).

[0425] It should be noted that the bit block (square matrix) distribution of the ninth bit set 2i and the ninth bit set 2i+1 is shown in Fig. 20, but the specific bit block patterns contained therein are not exactly the same. More specifically, the bit block The distribution pattern of the seventh bit set is different from that of the ninth bit set, i.e., the distribution positions of the amplitude bits and the sign bits in the bit blocks are different. It should be understood that the third bit stream 2i after the fourth interleaving can include a plurality of ninth bit sets 2i, and the third bit stream 2i+1 can include a plurality of ninth bit sets 2i+1.

[0426] It should be noted that the bit pattern of the 8 bit blocks in each row of the sixth bit set obtained after the FEC encoding is not exactly the same, and the fourth interleaving makes the bit pattern of the 8 bit blocks in each row of the ninth bit set the same. In some specific applications, the fourth interleaving can also be referred to as post-FEC permutation.

[0427] The fifth interleaving permutes each bit block in the ninth bit set (0≤i0<42 and 0≤j1<8) to obtain the seventh bit set. As shown in FIG. 21, the seventh bit set is distributed as 42 rows and 8 columns, i.e., 336 bit blocks (0≤i0<42 and 0≤j1<8). Each bit block (0≤i0<42 and 0≤j1<8) has a size of 16 rows and 16 columns of bits (i.e., 16x16=256 bits), as shown in FIG. 9. For simplicity of description, represents a bit in the r2th bit row and the c2th bit column of the bit block in the i2th square row and the j2th square column, where 0≤r2<16 and 0≤c2<16. In some specific applications, the bit block contains 256 bits in total in 16 rows and 16 columns, which are continuous on the third bit stream.

[0428] In some specific applications, the fifth interleaving permutes each bit block in the ninth bit set (0≤i0<42 and 0≤j1<8) to obtain the corresponding bit block in the seventh bit set. The fifth interleaving permutes each bit block in the ninth bit set (0≤i0<42 and 0≤j1<8) to obtain the corresponding bit block

[0429] in the seventh bit set. The fifth interleaving permutes each bit block in the ninth bit set (0≤i0<42 and 0≤j1<8) to obtain the corresponding bit block in the seventh bit set. The fifth interleaving permutes each bit block in the ninth bit set (0≤i0<42 and 0≤j1<8) to obtain the corresponding bit block wherein r2=r0and c2=c0^r0. Here, a^b represents the exclusive or of two positive integers a and b. FIG. 22 is a schematic diagram of an embodiment of the fifth interleaving in the present application. The specific interleaving manner can be understood with reference to FIG. 22.

[0430] The bit block patterns in the seventh bit set 2i and the seventh bit set 2i+1 are introduced below respectively.

[0431] FIG. 21 is a schematic diagram of a seventh bit set in an embodiment of the present application. As shown in FIG. 21, referring to the schematic diagram of 42 rows and 8 columns of bit blocks shown in FIG. 21, the bit block pattern of the seventh bit set 2i on the third bit stream 2i is introduced below. (0≤i0<42 and 0≤j1<8) pattern. FIG. 23(a) is a schematic diagram of a nineteenth bit pattern in an embodiment of the present application; FIG. 23(b) is a schematic diagram of a twentieth bit pattern in an embodiment of the present application; and FIG. 23(c) is a schematic diagram of a twenty-first bit pattern in an embodiment of the present application.

[0432] 1) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks (0≤i0<42 and 0≤j1<8) pattern. FIG. 23(a) is a schematic diagram of a nineteenth bit pattern in an embodiment of the present application; FIG. 23(b) is a schematic diagram of a twentieth bit pattern in an embodiment of the present application; and FIG. 23(c) is a schematic diagram of a twenty-first bit pattern in an embodiment of the present application.

[0433] 2) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8: the corresponding 112 bit blocks The bit pattern of the twentieth bit pattern adopts the twentieth bit pattern. As an example, the twentieth bit pattern is shown in FIG. 23(b), which contains 16 bits marked with the number "0", 16 bits marked with the number "1", 16 bits marked with the number "2", 16 bits marked with the number "3", 32 bits marked with the number "4", 32 bits marked with the number "5", 32 bits marked with the number "6", 32 bits marked with the number "7", 16 bits marked with the number "8", 16 bits marked with the number "9", 16 bits marked with the number "10", and 16 bits marked with the number "11" in a 16-by-16 bit block. That is, it contains 96 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the symbol bits in symbol mapping), and 160 bits from the second bit set with PCS processing (and as the amplitude bits in symbol mapping). Among the 160 bits from the second bit set with PCS processing, 64 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0434] 3) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the 2i+1 bit stream adopts the twenty-first bit pattern. As an example, the twenty-first bit pattern is shown in Fig. 23(c), which contains 16 bits marked with the number "0", 16 bits marked with the number "1", 16 bits marked with the number "2", 16 bits marked with the number "3", 16 bits marked with the number "4", 16 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 32 bits marked with the number "8", 32 bits marked with the number "9", 32 bits marked with the number "10", 32 bits marked with the number "11" in the 16 rows by 16 columns of bit blocks. That is, it contains 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the symbol bits in symbol mapping), and 192 bits from the second bit set with PCS processing (and as the amplitude bits in symbol mapping). Among the 192 bits from the second bit set with PCS processing, 96 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0435] Referring to the 42 rows by 8 columns of bit blocks shown in Fig. 21, the following introduces the bit pattern of the 2i+1 bit set on the 2i+1 bit stream (0≤i0<42 and 0≤j1<8) pattern.

[0436] 1) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, that is, i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the 2i+1 bit stream adopts the twenty-first bit pattern. As an example, the twenty-first bit pattern is shown in Fig. 23(c).

[0437] 2) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, that is, i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the 2i+1 bit stream adopts the nineteenth bit pattern. As an example, the nineteenth bit pattern is shown in Fig. 23(a).

[0438] 3) For 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, that is, i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The bit pattern of the seventh bit set 2i+1 adopts the twentieth bit pattern. As an example, the twentieth bit pattern is shown in Fig. 23(b).

[0439] It should be noted that the bit blocks (squares) of the seventh bit set 2i and the seventh bit set 2i+1 are distributed as shown in Fig. 21, but the specific bit blocks The bit pattern is not exactly the same. More specifically, the distribution pattern of the bit blocks is different, i.e., the distribution positions of the amplitude bits and the sign bits in the bit blocks are different. It should be understood that the fourth bit stream 2i after the fifth interleaving can include a plurality of seventh bit sets 2i, and the fourth bit stream 2i+1 can include a plurality of seventh bit sets 2i+1.

[0440] It should be further noted that for the seventh bit set 2i and the seventh bit set 2i+1, when 0≤i0<42 and 0≤j1<8, the corresponding 336 bit blocks include a total of 57344 bits from the second bit set (as amplitude bits in the symbol mapping) and 28672 bits from the third bit set without PCS processing or from the check bits of the FEC encoding (and as sign bits in the symbol mapping).

[0441] Further, in the 336 bit blocks , each consecutive 3-row bit block, i.e., a total of 3 bit blocks include a total of 512 bits from the second bit set (as amplitude bits in the symbol mapping) and 256 bits from the third bit set without PCS processing or from the check bits of the FEC encoding (and as sign bits in the symbol mapping), where 0≤j1<14. Of the 512 bits from the second bit set with PCS processing, 256 bits are used to generate the first type of amplitude bits, and 256 bits are used to generate the second type of amplitude bits. More specifically, in the above 3 bit blocks, the bits marked with the number "0" (as bits b0in the symbol mapping), the bits marked with the number "1" (as bits b1in the symbol mapping), the bits marked with the number "2" (as bits b2in the symbol mapping), the bits marked with the number "3" (as bits b3in the symbol mapping), the bits marked with the number "4" (as bits b4in the symbol mapping), the bits marked with the number "5" (as bits b5in the symbol mapping), the bits marked with the number "6" (as bits b6in the symbol mapping), the bits marked with the number "7" (as bits b7in the symbol mapping), the bits marked with the number "8" (as bits b8in the symbol mapping), the bits marked with the number "9" (as bits b9in the symbol mapping), the bits marked with the number "10" (as bits b 10), and the bit marked "11" (as bit b in the symbol map). 11 The quantity is 64.

[0442] (4) The third interweaving:

[0443] As shown in Figure 15, the third interleaving can also be called block interleaving. The third interleaving includes intra-block interleaving and inter-block interleaving.

[0444] A set of seventh bits 2i, distributed in 42 rows and 8 columns, from the third bit stream 2i is interleaved within a matrix 2i to obtain a set of ten bits 2i. A set of seventh bits 2i+1, distributed in 42 rows and 8 columns, from the third bit stream 2i+1 is also interleaved within a matrix 2i+1 to obtain a set of ten bits 2i+1. Interleaving between matrices i scrambles the tenth bit set 2i and the tenth bit set 2i+1 to obtain a set of eighth bits i, distributed in 84 rows and 8 columns. It should be noted that in some specific applications, matrix interleaving is also called OFEC interleaving.

[0445] The following sections describe the interweaving within and between squares.

[0446] Figure 24 is a schematic diagram of one implementation of interleaving within a square array in this application. As shown in Figure 24, interleaving within a square array first involves processing the bit blocks of each received seventh bit set. After interleaving within the matrix (0≤i0<42 and 0≤j1<8), the resulting bit block is the tenth bit set of a 42-row, 8-column bit block with a total of 336 bits. (0≤i0<42 and 0≤j1<8). That is, each 16x16 input matrix is ​​interleaved and shuffled according to the interleaving rules shown in Figure 24 to obtain a 16x16 output matrix. In Figure 24, the element in the m-th row and n-th column (0≤m<16 and 0≤n<16) of the 16x16 matrix is ​​(a,b), indicating that the bit in the m-th row and n-th column of the output matrix after interleaving comes from the bit in the a-th row and b-th column of the input matrix. For example, if the element in the 1-th row and 0-th column of Figure 24 is (14,15), then the bit in the 1-th row and 0-th column of the output matrix after interleaving comes from the bit in the 14-th row and 15-th column of the input matrix. More specifically, the bit block after interleaving... The bit in row 1, column 0 comes from the bit block. The bits in the 14th row and 15th column. In some specific applications, square matrices... The bit stream output in the square matrix is continuous, including 16 rows and 16 columns, a total of 256 bits.

[0447] The bit block patterns in the tenth bit set 2i and the tenth bit set 2i+1 are described below. Fig. 25(a) is a schematic diagram of a twenty-second bit pattern in an embodiment of the application; Fig. 25(b) is a schematic diagram of a twenty-third bit pattern in an embodiment of the application; and Fig. 25(c) is a schematic diagram of a twenty-fourth bit pattern in an embodiment of the application.

[0448] The bit block pattern in the tenth bit set 2i is described below. (0≤i0<42 and 0≤j1<8) pattern.

[0449] 1) For 0≤i0<21 and i0%3=0, or 21≤i0<42 and i0%3=2, i.e. i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks is the twenty-second bit pattern. As an example, the twenty-second bit pattern is shown in Fig. 25(a), which includes 16 rows and 16 columns of bit blocks, a total of 32 bits marked with the number "0", 32 bits marked with the number "1", 32 bits marked with the number "2", 32 bits marked with the number "3", 16 bits marked with the number "4", 16 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 16 bits marked with the number "8", 16 bits marked with the number "9", 16 bits marked with the number "10", and 16 bits marked with the number "11". That is, a total of 96 bits from the third bit set without PCS processing or check bits from FEC encoding (and as symbol bits in symbol mapping), and 160 bits from the second bit set with PCS processing (and as amplitude bits in symbol mapping). Of the 160 bits from the second bit set with PCS processing, 96 bits are used to generate the first type of amplitude bits, and 64 bits are used to generate the second type of amplitude bits.

[0450] 2) For 0≤i0<21 and i0%3=1, or 21≤i0<42 and i0%3=0, i.e. i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks The bit pattern of the 23rd bit set is shown in Fig. 25(b). As an example, the 23rd bit pattern is shown in Fig. 25(b), which contains 16 bits marked with the number "0", 16 bits marked with the number "1", 16 bits marked with the number "2", 16 bits marked with the number "3", 32 bits marked with the number "4", 32 bits marked with the number "5", 32 bits marked with the number "6", 32 bits marked with the number "7", 16 bits marked with the number "8", 16 bits marked with the number "9", 16 bits marked with the number "10", 16 bits marked with the number "11" in the 16x16 bit blocks. That is, there are 96 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping), and 160 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping). Among the 160 bits from the second bit set with PCS processing, 64 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0451] 3) for 0≤i0<21 and i0%3=2, or 21≤i0<42 and i0%3=1, i.e. i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the corresponding 112 bit blocks The bit pattern of the 24th bit set is shown in Fig. 25(c). As an example, the 24th bit pattern is shown in Fig. 25(c), which contains 16 bits marked with the number "0", 16 bits marked with the number "1", 16 bits marked with the number "2", 16 bits marked with the number "3", 16 bits marked with the number "4", 16 bits marked with the number "5", 16 bits marked with the number "6", 16 bits marked with the number "7", 32 bits marked with the number "8", 32 bits marked with the number "9", 32 bits marked with the number "10", 32 bits marked with the number "11" in the 16x16 bit blocks. That is, there are 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping), and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping). Among the 192 bits from the second bit set with PCS processing, 96 bits are used to generate the first type of amplitude bits, and 96 bits are used to generate the second type of amplitude bits.

[0452] The bit blocks in the 10th bit set 2i+1 are described as follows pattern.

[0453] 1) For 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks adopts the twenty-fourth bit pattern. As an example, the twenty-fourth bit pattern is shown in FIG. 25(c).

[0454] 2) For 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks adopts the twenty-second bit pattern. As an example, the twenty-second bit pattern is shown in FIG. 25(a).

[0455] 3) For 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks adopts the twenty-third bit pattern. As an example, the twenty-third bit pattern is shown in FIG. 25(b).

[0456] It is noted that the distribution pattern of the bit blocks (square matrices) of the tenth bit set 2i and the tenth bit set 2i+1 are different, i.e., the distribution positions of the amplitude bits and the sign bits in the bit blocks are different.

[0457] It is also noted that for the tenth bit set 2i and the tenth bit set 2i+1, when 0≤i0<42 and 0≤j1<8, the corresponding 336 bit blocks contain a total of 57344 bits from the second bit set (as amplitude bits in the sign mapping) and 28672 bits from the third bit set without PCS processing or from the check bits of the FEC encoding (and as sign bits in the sign mapping). Further, every 3 rows of the 336 bit blocks , i.e., a total of 3 bit blocks The 512 bits from the second set of bits after PCS processing include 256 bits for generating the first type of amplitude bits and 256 bits for generating the second type of amplitude bits. More specifically, the 3 blocks of bits described above include 64 bits labeled with the number "0" (as bits b0in the symbol mapping), 64 bits labeled with the number "1" (as bits b1in the symbol mapping), 64 bits labeled with the number "2" (as bits b2in the symbol mapping), 64 bits labeled with the number "3" (as bits b3in the symbol mapping), 64 bits labeled with the number "4" (as bits b4in the symbol mapping), 64 bits labeled with the number "5" (as bits b5in the symbol mapping), 64 bits labeled with the number "6" (as bits b6in the symbol mapping), and 64 bits labeled with the number "7" (as bits b7in the symbol mapping), 64 bits labeled with the number "8" (as bits b8in the symbol mapping), 64 bits labeled with the number "9" (as bits b9in the symbol mapping), 64 bits labeled with the number "10" (as bits b 10 ), and 64 bits labeled with the number "11" (as bits b 11 ), i.e., a total of 256 bits for generating the first type of amplitude bits.

[0458] The bits after intra-matrix interleaving are interleaved inter-matrix to improve the overall burst performance. The operation of inter-matrix interleaving is described below.

[0459] FIG. 26 is a schematic diagram of an embodiment of inter-matrix interleaving in the present application. As shown in FIG. 26, the inter-matrix interleaving includes an interleaver buffer M of 84 rows and 8 columns, each row including 8 matrices, each matrix including 16 rows and 16 columns, i.e., a total of 256 bits, and the interleaver buffer M includes a total of 84x16=1344 bits in rows and 8x16=128 bits in columns. The interleaver buffer size of the inter-matrix interleaving is 84x8x256=172032 bits, wherein the output packets from the intra-matrix interleaving 2i are located in the even rows of the interleaver buffer M and the output packets from the intra-matrix interleaving 2i+1 are located in the odd rows of the interleaver buffer M.

[0460] FIG. 27 is a schematic diagram of the bit set after inter-matrix interleaving in the present application. As shown in FIG. 27, the 84 rows and 8 columns of bit blocks in the interleaver buffer M include 64 bit blocks labeled with the number "0" (as bits b0in the symbol mapping), 64 bit blocks labeled with the number "1" (as bits b1in the symbol mapping), 64 bit blocks labeled with the number "2" (as bits b2in the symbol mapping), 64 bit blocks labeled with the number "3" (as bits b3in the symbol mapping), 64 bit blocks labeled with the number "4" (as bits b4in the symbol mapping), 64 bit blocks labeled with the number "5" (as bits b5in the symbol mapping), 64 bit blocks labeled with the number "6" (as bits b6in the symbol mapping), and 64 bit blocks labeled with the number "7" (as bits b7in the symbol mapping), 64 bit blocks labeled with the number "8" (as bits b8in the symbol mapping), 64 bit blocks labeled with the number "9" (as bits b9in the symbol mapping), 64 bit blocks labeled with the number "10" (as bits b Figure 25 shows the bit patterns of the twenty-second, twenty-third and twenty-fourth bit patterns.

[0461] 1) For 0≤i1<42 and i1%3=0, or, 42≤i1<84 and i1%3=1, i.e., i1=0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 43, 46, 49, 52, 55, 58, 61, 64, 67, 70, 73, 76, 79, 82, and 0≤j1<8, the bit pattern of the corresponding 224 bit blocks adopts the twenty-second bit pattern. As an example, the twenty-second bit pattern is shown in Figure 25(a).

[0462] 2) For 0≤i1<42 and i1%3=2, or, 42≤i1<84 and i1%3=0, i.e., i1=2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 42, 45, 48, 51, 54, 57, 60, 63, 66, 69, 72, 75, 78, 81, and 0≤j1<8, the bit pattern of the corresponding 224 bit blocks adopts the twenty-third bit pattern. As an example, the twenty-third bit pattern is shown in Figure 25(b).

[0463] 3) For 0≤i1<42 and i1%3=1, or, 42≤i1<84 and i1%3=2, i.e., i1=1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 80, 83, and 0≤j1<8, the bit pattern of the corresponding 224 bit blocks adopts the twenty-fourth bit pattern. As an example, the twenty-fourth bit pattern is shown in Figure 25(c).

[0464] The interleaving buffer M can be divided into four sets as shown in Figure 26. The 0thset contains the 0th, 2nd, 4th, …, 40throws of the square matrices in the interleaving buffer M, which has a total of 21 x 16 x 128 = 43008 bits. The 1stset contains the 1st, 3rd, 5th, …, 41strows of the square matrices in the interleaving buffer M, which has a total of 43008 bits. The 2ndset contains the 42nd, 44th, 46th, …, 82ndrows of the square matrices in the interleaving buffer M, which has a total of 43008 bits. The 3rdset contains the 43rd, 45th, 47th, …, 83rdrows of the square matrices in the interleaving buffer M, which has a total of 43008 bits.

[0465] ​From the interleaving buffer M, 8 bits are polled from each set to read the bits in each column, and after all the bits in each column are read, the bits in the next column are read. First, the first set of 8 bits from the top to the bottom is read from the 0th set, and then the first set of 8 bits from the top to the bottom is read from the 1st set, the 2nd set, and the 3rd set, respectively. In one cycle, 32 bits are read in total. Next, the next set of 8 bits from the top to the bottom is read from the 0th set, the 1st set, the 2nd set, and the 3rd set, respectively, in the next cycle, and 32 bits are read in total. After 42 cycles in total, 1344 bits in the current column are read. For reading the bits in each column from each set, the following operations are performed:

[0466] First, 8 bits (0th-7th bit row in the matrix) are read from the top to the bottom from the 0th row matrix in the interleaving buffer M,

[0467] 8 bits (0th-7th bit row in the matrix) are read from the top to the bottom from the 1st row matrix in the interleaving buffer M,

[0468] 8 bits (0th-7th bit row in the matrix) are read from the top to the bottom from the 42nd row matrix in the interleaving buffer M,

[0469] 8 bits (0th-7th bit row in the matrix) are read from the top to the bottom from the 43rd row matrix in the interleaving buffer M,

[0470] Then, 8 bits (8th-15th bit row in the matrix) are read from the top to the bottom from the 0th row matrix in the interleaving buffer M,

[0471] 8 bits (8th-15th bit row in the matrix) are read from the top to the bottom from the 1st row matrix in the interleaving buffer M,

[0472] 8 bits (8th-15th bit row in the matrix) are read from the top to the bottom from the 42nd row matrix in the interleaving buffer M,

[0473] 8 bits (8th-15th bit row in the matrix) are read from the top to the bottom from the 43rd row matrix in the interleaving buffer M,

[0474] Next, 8 bits (0th-7th bit row in the matrix) are read from the top to the bottom from the 2nd row matrix in the interleaving buffer M,

[0475] …, until all 1344 bits in the current bit column in the interleaving buffer M are completely read.

[0476] Next, likewise, the total of 1344 bits in the next column bit sequence in the interleaving buffer M are read out completely according to the above operation until the total of 1344 bits in the last column bit sequence in the interleaving buffer M are read out completely. At this time, all of the 172032 bits in the interleaving buffer M are read out completely. The 172032 bits read out from the interleaving buffer M are taken as the output of the third interleaving, i.e., the eighth bit set. It should be understood that there are totally 128 column bit sequences in the interleaving buffer M.

[0477] It should be noted that in the first symbol mapping, the bits b2 and b4 are 2 amplitude bits of the I direction component of the DP-64QAM symbol on the X polarization, the bits b8 and b 10 are 2 amplitude bits of the Q direction component of the DP-64QAM symbol on the X polarization, the bits b3 and b5 are 2 amplitude bits of the I direction component of the DP-64QAM symbol on the Y polarization, and the bits b9 and b 11 are 2 amplitude bits of the Q direction component of the DP-64QAM symbol on the Y polarization.

[0478] It should be noted that the bit stream output by the third interleaving (including the intra-square interleaving and the inter-square interleaving) is merged to obtain the fourth bit data, and the fourth bit data is subjected to symbol mapping and polarization division to obtain the dual-polarization symbol. Specifically, the bit streams output by the total of L third interleavings are merged in groups of S=12 bits in a round-robin manner, and then subjected to symbol mapping, i.e., the 12 bits output by the third interleaving 0 are mapped into one dual-polarization modulation symbol, then the 12 bits output by the third interleaving 1 are mapped into one dual-polarization modulation symbol, and then the 12 bits output by the third interleaving L-1 are mapped into one dual-polarization modulation symbol. The interleaving buffer used in the inter-square interleaving in the third interleaving contains 172032 bits, i.e., the interleaving granularity is 172032 bits, and the 172032 bits are mapped into 172032 / 12=14336 DP-64QAM symbols. That is to say, the output of the third interleaving is the eighth bit set, and the total of 172032 bits are mapped into 172032 / 12=14336 DP-64QAM symbols.

[0479] In some application scenarios, for the bit block of the ninth bit set when the first symbol mapping is adopted, the part marked with the number "0" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b0, b1, b6 or b7 bit in the symbol mapping (also referred to as modulation), which is from the third bit set without PCS processing or from the check bit of FEC encoding and is a symbol bit in the symbol mapping (also referred to as modulation). The part marked with the number "1" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b2, b3, b8 or b9 bit in the symbol mapping (also referred to as modulation), which is from the second bit set after PCS processing and is the first type of amplitude bit in the symbol mapping (also referred to as modulation). The part marked with the number "2" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b4, b5, b 10 or b 11 bit, which is from the second bit set after PCS processing and is the second type of amplitude bit in the symbol mapping (also referred to as modulation).

[0480] Considering the above marking manner, the bit block pattern of the ninth bit set 2i and the ninth bit set 2i+1 is introduced respectively. Referring to the 42-row 8-column bit block diagram shown in FIG. 20, the bit block pattern of the ninth bit set 2i on the fifth bit stream 2i is introduced as follows. (0≤i0<42 and 0≤j1<8) pattern. FIG. 28(a) is a schematic diagram of another first bit pattern in an embodiment of the present application. FIG. 28(b) is a schematic diagram of another second bit pattern in an embodiment of the present application. FIG. 28(c) is a schematic diagram of another third bit pattern in an embodiment of the present application.

[0481] 1) for 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, that is, i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks adopts the first bit pattern. As an example, the first bit pattern is shown in FIG. 28(a), which includes 96 bits marked with the number "0", 96 bits marked with the number "1", and 64 bits marked with the number "2" in the 16-row 16-column bit block. That is, a total of 96 bits from the third bit set without PCS processing (and as symbol bits in symbol mapping) and 96 bits for generating the first type of amplitude bit and 64 bits for generating the second type of amplitude bit are included.

[0482] 2) for 0≤i0<21 and i0%3 = 1, or, 21≤i0<42 and i0%3 = 0, i.e., i0 = 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the fifth bit stream 2i+1 (0≤i3<42 and 0≤j3<8) is shown in Fig. 28(b).

[0483] 3) for 0≤i0<21 and i0%3 = 2, or, 21≤i0<42 and i0%3 = 1, i.e., i0 = 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the fifth bit stream 2i+1 (0≤i3<42 and 0≤j3<8) is shown in Fig. 28(c).

[0484] Referring to the 42x8 bit block diagram shown in Fig. 20, the bit pattern of the 112 bit blocks of the 2i+1 bit set on the fifth bit stream 2i+1 (0≤i3<42 and 0≤j3<8) is shown in Fig. 28(b).

[0485] 1) for 0≤i0<21 and i0%3 = 0, or, 21≤i0<42 and i0%3 = 2, i.e., i0 = 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the fifth bit stream 2i+1 (0≤i3<42 and 0≤j3<8) is shown in Fig. 28(b).

[0486] ​2) for 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e. i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8, the bit pattern of the corresponding 112-bit block adopts the first bit pattern. As an example, the first bit pattern is shown in Fig. 28(a).

[0487] 3) for 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e. i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8, the bit pattern of the corresponding 112-bit block adopts the second bit pattern. As an example, the second bit pattern is shown in Fig. 28(b).

[0488] It should be noted that the above introduction of the operations of each of the second data sub-process i (i = 0, 1, …, L-1) is taken as an example of adopting the first symbol mapping scheme. The first bit pattern to the twenty-fourth bit pattern will be introduced respectively when the second symbol mapping scheme, the third symbol mapping scheme and the fourth symbol mapping scheme are adopted.

[0489] 1) when the second symbol mapping is adopted:

[0490] The bit pattern is distributed as r rows and c columns, where the r rows and c columns can be 16 rows and 16 columns, or 16 rows and 15 columns.

[0491] The part marked with the number “0” in the rth row and the cth column of the bit pattern indicates that the bit in the corresponding bit block in the rth row and the cth column is used as the b0 bit in symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from the check bit of FEC encoding, and is used as the symbol bit on X I ;

[0492] The part marked with the number “1” in the rth row and the cth column of the bit pattern indicates that the bit in the corresponding bit block in the rth row and the cth column is used as the b1 bit in symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from the check bit of FEC encoding, and is used as the symbol bit on Y I ;

[0493] The part marked with the number "2" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b2 bit in symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from a check bit of FEC encoding, and is an X bit in symbol mapping (also referred to as modulation) Q on the symbol bit;

[0494] The part marked with the number "3" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b3 bit in symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from a check bit of FEC encoding, and is a Y bit in symbol mapping (also referred to as modulation) Q on the symbol bit;

[0495] The part marked with the number "4" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b4 bit in symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is an X bit in symbol mapping (also referred to as modulation) I on the first type of amplitude bit;

[0496] The part marked with the number "5" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b5 bit in symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is a Y bit in symbol mapping (also referred to as modulation) I on the first type of amplitude bit;

[0497] The part marked with the number "6" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b6 bit in symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is an X bit in symbol mapping (also referred to as modulation) I on the second type of amplitude bit;

[0498] The part marked with the number "7" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b7 bit in symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is a Y bit in symbol mapping (also referred to as modulation) I on the second type of amplitude bit;

[0499] The part marked with the number "8" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is a b8 bit in symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is an X bit in symbol mapping (also referred to as modulation)Q The first type of amplitude bit;

[0500] In the bit pattern, the portion marked with the number "9" at row r and column c indicates that the bit at row r and column c of the corresponding bit block is used as bit b9 in the symbol mapping (also known as modulation); this bit comes from the second bit set processed by PCS and is used as Y in the symbol mapping (also known as modulation). Q The first type of amplitude bit;

[0501] In a bit pattern, the portion marked with the number "10" at row r and column c indicates that the bit at row r and column c in the corresponding bit block is used as 'b' in symbol mapping (also known as modulation). 10 Bit; this bit is from the second set of bits processed by PCS, and serves as X in the symbol mapping (also known as modulation). Q The second type of amplitude bit;

[0502] In a bit pattern, the portion marked with the number "11" at row r and column c indicates that the bit at row r and column c in the corresponding bit block is used as a 'b' in symbol mapping (also known as modulation). 11 Bit; this bit is from the second set of bits processed by PCS, and serves as Y in the symbol mapping (also known as modulation). Q The second type of amplitude bit.

[0503] When the second symbol mapping is used, Figure 29 is a schematic diagram of another fifth bit pattern in an embodiment of this application; Figure 30 is a schematic diagram of another seventh bit pattern, eighth bit pattern and ninth bit pattern in an embodiment of this application; Figure 31 is a schematic diagram of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in an embodiment of this application; Figure 32 is a schematic diagram of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in an embodiment of this application; Figure 33(a) is a schematic diagram of another sixteenth bit pattern in an embodiment of this application; Figure 33(b) is a schematic diagram of another seventeenth bit pattern in an embodiment of this application; and Figure 33(c) is a schematic diagram of another eighteenth bit pattern in an embodiment of this application.

[0504] The first bit pattern adopts the bit distribution pattern shown in Figure 11(a), which contains a 16-row, 16-column bit block containing 128 bits from the third bit set that has not been processed by PCS (and serves as the symbol bits in the symbol map) and 128 bits from the second bit set that has been processed by PCS (and serves as the amplitude bits in the symbol map).

[0505] The second bit pattern employs a bit distribution pattern as shown in Figure 11(b) that includes 64 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0506] The third bit pattern employs a bit distribution pattern as shown in Figure 11(c) that includes 64 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0507] In some embodiments, the fourth bit pattern employs a bit distribution pattern as shown in Figure 12(a) that includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0508] In some embodiments, the fifth bit pattern employs a bit distribution pattern as shown in Figure 29 that includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0509] In some embodiments, the sixth bit pattern employs a bit distribution pattern as shown in Figure 12(c) that includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0510] The seventh bit pattern employs a bit distribution pattern as shown in Figure 30, the eighth bit pattern employs a bit distribution pattern as shown in Figure 30, the ninth bit pattern as shown in Figure 30 that includes 256 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0511] The tenth bit pattern is shown in Figure 31, the eleventh bit pattern is shown in Figure 31, and the twelfth bit pattern is shown in Figure 31, which includes 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 15 column block of bits.

[0512] The thirteenth bit pattern is shown in Figure 32, the fourteenth bit pattern is shown in Figure 32, and the fifteenth bit pattern is shown in Figure 32, which includes 16 FEC-encoded parity bits (and as sign bits in the symbol mapping), and 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0513] The sixteenth bit pattern is shown in Figure 33(a), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0514] The seventeenth bit pattern is shown in Figure 33(b), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0515] The eighteenth bit pattern is shown in Figure 33(c), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0516] The nineteenth bit pattern is shown in Figure 23(a), which includes 128 bits from the third set of non-PCS-processed bits or FEC-encoded parity bits (and as sign bits in the symbol mapping), and 128 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0517] The twentieth bit pattern is shown in Figure 23(b), which includes 64 bits from the third set of non-PCS-processed bits or FEC-encoded parity bits (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0518] The twenty-first bit pattern is shown in Figure 23(c), which includes 64 bits from the third set of non-PCS-processed bits or FEC-encoded parity bits (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0519] The twenty-second bit pattern is shown in Figure 25(a), which includes 128 bits from the third set of bits that are not PCS processed or from the check bits of the FEC encoding (and as the sign bits in the symbol mapping), and 128 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0520] The twenty-third bit pattern is shown in Figure 25(b), which includes 64 bits from the third set of bits that are not PCS processed or from the check bits of the FEC encoding (and as the sign bits in the symbol mapping), and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0521] The twenty-fourth bit pattern is shown in Figure 25(c), which includes 64 bits from the third set of bits that are not PCS processed or from the check bits of the FEC encoding (and as the sign bits in the symbol mapping), and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0522] 2) when the third symbol mapping is employed:

[0523] The bit pattern is distributed as r rows by c columns, where r rows by c columns can be 16 rows by 16 columns, or 16 rows by 15 columns.

[0524] The portion of the bit pattern in the rth row and cth column that is labeled with the numeral "0" indicates that the bit in the rth row and cth column of the corresponding block of bits is a b0 bit in the symbol mapping (also referred to as modulation); this bit is from the second set of bits that are PCS processed, and is a first type of amplitude bit in the X I portion of the symbol mapping;

[0525] The portion of the bit pattern in the rth row and cth column that is labeled with the numeral "1" indicates that the bit in the rth row and cth column of the corresponding block of bits is a b1 bit in the symbol mapping (also referred to as modulation); this bit is from the second set of bits that are PCS processed, and is a first type of amplitude bit in the Y I portion of the symbol mapping;

[0526] The portion of the bit pattern in the rth row and cth column that is labeled with the numeral "2" indicates that the bit in the rth row and cth column of the corresponding block of bits is a b2 bit in the symbol mapping (also referred to as modulation); this bit is from the second set of bits that are PCS processed, and is a first type of amplitude bit in the X Isecond type of amplitude bits on the

[0527] The part of the bit pattern in the rth row and cth column marked with the number "3" indicates that the bit in the rth row and cth column of the corresponding bit block is the b3 bit in the symbol mapping (also called modulation); this bit is from the second set of bits processed by the PCS and is the Y I second type of amplitude bits on the

[0528] The part of the bit pattern in the rth row and cth column marked with the number "4" indicates that the bit in the rth row and cth column of the corresponding bit block is the b4 bit in the symbol mapping (also called modulation); this bit is from the second set of bits processed by the PCS and is the X Q first type of amplitude bits on the

[0529] The part of the bit pattern in the rth row and cth column marked with the number "5" indicates that the bit in the rth row and cth column of the corresponding bit block is the b5 bit in the symbol mapping (also called modulation); this bit is from the second set of bits processed by the PCS and is the Y Q first type of amplitude bits on the

[0530] The part of the bit pattern in the rth row and cth column marked with the number "6" indicates that the bit in the rth row and cth column of the corresponding bit block is the b6 bit in the symbol mapping (also called modulation); this bit is from the second set of bits processed by the PCS and is the X Q second type of amplitude bits on the

[0531] The part of the bit pattern in the rth row and cth column marked with the number "7" indicates that the bit in the rth row and cth column of the corresponding bit block is the b7 bit in the symbol mapping (also called modulation); this bit is from the second set of bits processed by the PCS and is the Y Q second type of amplitude bits on the

[0532] The part of the bit pattern in the rth row and cth column marked with the number "8" indicates that the bit in the rth row and cth column of the corresponding bit block is the b8 bit in the symbol mapping (also called modulation); this bit is from the third set of bits not processed by the PCS or from the check bits of the FEC encoding and is the X I symbol bits on the

[0533] The part marked with the number "9" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b9 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or a check bit from FEC encoding, and is the symbol bit in Y I on the symbol mapping (also referred to as modulation).

[0534] The part marked with the number "10" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 10 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or a check bit from FEC encoding, and is the symbol bit in X Q on the symbol mapping (also referred to as modulation).

[0535] The part marked with the number "11" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 11 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or a check bit from FEC encoding, and is the symbol bit in Y Q on the symbol mapping (also referred to as modulation).

[0536] When the third symbol mapping is used, FIG. 34(a) is a schematic diagram of another fourth bit pattern in the embodiments of the present application, FIG. 34(b) is a schematic diagram of another sixth bit pattern in the embodiments of the present application, FIG. 35 is a schematic diagram of another seventh bit pattern, eighth bit pattern and ninth bit pattern in the embodiments of the present application, FIG. 36 is a schematic diagram of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in the embodiments of the present application, FIG. 37 is a schematic diagram of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in the embodiments of the present application, FIG. 38(a) is a schematic diagram of another sixteenth bit pattern in the embodiments of the present application, FIG. 38(b) is a schematic diagram of another seventeenth bit pattern in the embodiments of the present application, and FIG. 38(c) is a schematic diagram of another eighteenth bit pattern in the embodiments of the present application.

[0537] The first bit pattern adopts the bit distribution pattern shown in FIG. 11(a), which includes 64 bits from the third bit set without PCS processing (and as symbol bits in symbol mapping) and 192 bits from the second bit set with PCS processing (and as amplitude bits in symbol mapping) in the bit block with 16 rows and 16 columns.

[0538] The second bit pattern employs a bit distribution pattern as shown in Figure 11(b) which includes 64 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0539] The third bit pattern employs a bit distribution pattern as shown in Figure 11(c) which includes 128 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 128 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0540] In some embodiments, the fourth bit pattern employs a bit distribution pattern as shown in Figure 34(a) which includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0541] In some embodiments, the fifth bit pattern employs a bit distribution pattern as shown in Figure 30 which includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0542] In some embodiments, the sixth bit pattern employs a bit distribution pattern as shown in Figure 34(b) which includes 104 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping) and 152 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0543] The seventh bit pattern employs a bit distribution pattern as shown in Figure 35, the eighth bit pattern employs a bit distribution pattern as shown in Figure 35, the ninth bit pattern as shown in Figure 35 which includes 256 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0544] The tenth bit pattern is shown in Figure 36, the eleventh bit pattern is shown in Figure 36, and the twelfth bit pattern is shown in Figure 36, which includes 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 15 column block of bits.

[0545] The thirteenth bit pattern is shown in Figure 37, the fourteenth bit pattern is shown in Figure 37, and the fifteenth bit pattern is shown in Figure 37, which includes 16 FEC-encoded parity bits (and as sign bits in the symbol mapping), and 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0546] The sixteenth bit pattern is shown in Figure 38(a), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0547] The seventeenth bit pattern is shown in Figure 38(b), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0548] The eighteenth bit pattern is shown in Figure 38(c), which includes 256 FEC-encoded parity bits (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0549] The nineteenth bit pattern is shown in Figure 23(a), which includes 64 bits from the third set of non-PCS-processed bits or from FEC-encoded parity bits (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0550] The twentieth bit pattern is shown in Figure 23(b), which includes 64 bits from the third set of non-PCS-processed bits or from FEC-encoded parity bits (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0551] The twenty-first bit pattern is shown in Figure 23(c), which includes 128 bits from the third set of non-PCS-processed bits or from FEC-encoded parity bits (and as sign bits in the symbol mapping), and 128 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0552] The twenty-second bit pattern is shown in FIG. 25(a), which includes 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0553] The twenty-third bit pattern is shown in FIG. 25(b), which includes 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0554] The twenty-fourth bit pattern is shown in FIG. 25(c), which includes 128 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 128 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0555] 3) When the fourth symbol mapping is used:

[0556] The bit pattern is distributed as r rows by c columns, where the r rows by c columns can be 16 rows by 16 columns or 16 rows by 15 columns.

[0557] The portion of the bit pattern in the rth row and the cth column marked with the numeral "0" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b0 bit in the symbol mapping (also referred to as modulation); this bit is from the second bit set with PCS processing and is a first type of amplitude bit in X I

[0558] The portion of the bit pattern in the rth row and the cth column marked with the numeral "1" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b1 bit in the symbol mapping (also referred to as modulation); this bit is from the second bit set with PCS processing and is a first type of amplitude bit in Y I

[0559] The portion of the bit pattern in the rth row and the cth column marked with the numeral "2" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b2 bit in the symbol mapping (also referred to as modulation); this bit is from the second bit set with PCS processing and is a first type of amplitude bit in X I ​​second type of amplitude bits on the

[0560] The part marked with the number "3" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b3 bit in the symbol mapping (also called modulation); the bit is from the second bit set processed by the PCS and is Y in the symbol mapping (also called modulation) I second type of amplitude bits on the

[0561] The part marked with the number "4" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b4 bit in the symbol mapping (also called modulation); the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is X in the symbol mapping (also called modulation) I symbol bits on the

[0562] The part marked with the number "5" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b5 bit in the symbol mapping (also called modulation); the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is Y in the symbol mapping (also called modulation) I symbol bits on the

[0563] The part marked with the number "6" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b6 bit in the symbol mapping (also called modulation); the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is X in the symbol mapping (also called modulation) Q symbol bits on the

[0564] The part marked with the number "7" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b7 bit in the symbol mapping (also called modulation); the bit is from the third bit set not processed by the PCS or from the check bit of the FEC encoding and is Y in the symbol mapping (also called modulation) Q symbol bits on the

[0565] The part marked with the number "8" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b8 bit in the symbol mapping (also called modulation); the bit is from the second bit set processed by the PCS and is X in the symbol mapping (also called modulation) Q first type of amplitude bits on the

[0566] The portion marked with the number "9" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b9bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set processed by the PCS, and is the Y Q bit in the symbol mapping (also referred to as modulation).

[0567] The portion marked with the number "10" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 10 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set processed by the PCS, and is the X Q bit in the symbol mapping (also referred to as modulation).

[0568] The portion marked with the number "11" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 11 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set processed by the PCS, and is the Y Q bit in the symbol mapping (also referred to as modulation).

[0569] When the fourth symbol mapping is used, FIG. 39 is a schematic diagram of another fifth bit pattern in an embodiment of the present application, FIG. 40 is a schematic diagram of another seventh bit pattern, eighth bit pattern and ninth bit pattern in an embodiment of the present application, FIG. 41 is a schematic diagram of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in an embodiment of the present application, FIG. 42 is a schematic diagram of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in an embodiment of the present application, FIG. 43(a) is a schematic diagram of another sixteenth bit pattern in an embodiment of the present application, FIG. 43(b) is a schematic diagram of another seventeenth bit pattern in an embodiment of the present application, and FIG. 43(c) is a schematic diagram of another eighteenth bit pattern in an embodiment of the present application.

[0570] The first bit pattern uses the bit distribution pattern shown in FIG. 11(a), which includes 64 bits from the third bit set processed by the PCS (and as symbol bits in the symbol mapping) and 192 bits from the second bit set processed by the PCS (and as amplitude bits in the symbol mapping) in the bit block including 16 rows and 16 columns.

[0571] The second bit pattern employs a bit distribution pattern as shown in Figure 11(b), which includes 128 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping), and 128 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0572] The third bit pattern employs a bit distribution pattern as shown in Figure 11(c), which includes 64 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping), and 192 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0573] In some embodiments, the fourth bit pattern employs a bit distribution pattern as shown in Figure 12(a), which includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping), and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0574] In some embodiments, the fifth bit pattern employs a bit distribution pattern as shown in Figure 39, which includes 104 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping), and 152 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0575] In some embodiments, the sixth bit pattern employs a bit distribution pattern as shown in Figure 12(c), which includes 52 bits from the third set of bits that are not PCS processed (and as the sign bits in the symbol mapping), and 204 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0576] The seventh bit pattern employs a bit distribution pattern as shown in Figure 40, the eighth bit pattern employs a bit distribution pattern as shown in Figure 40, and the ninth bit pattern as shown in Figure 40, which includes 256 bits from the second set of bits that are PCS processed (and as the amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0577] The tenth bit pattern is shown in Figure 41, the eleventh bit pattern is shown in Figure 41, and the twelfth bit pattern is shown in Figure 41, which includes 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 15 column block of bits.

[0578] The thirteenth bit pattern is shown in Figure 42, the fourteenth bit pattern is shown in Figure 42, and the forty-second bit pattern is shown in Figure 37, which includes 16 check bits from the FEC encoding (and as sign bits in the symbol mapping), and 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0579] The sixteenth bit pattern is shown in Figure 43(a), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0580] The seventeenth bit pattern is shown in Figure 43(b), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0581] The eighteenth bit pattern is shown in Figure 43(c), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0582] The nineteenth bit pattern is shown in Figure 23(a), which includes 64 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0583] The twentieth bit pattern is shown in Figure 23(b), which includes 128 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 128 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0584] The twenty-first bit pattern is shown in Figure 23(c), which includes 64 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 192 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0585] The twenty-second bit pattern is shown in FIG. 25(a), which includes 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0586] The twenty-third bit pattern is shown in FIG. 25(b), which includes 128 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 128 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0587] The twenty-fourth bit pattern is shown in FIG. 25(c), which includes 64 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 192 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a 16-row-by-16-column bit block.

[0588] 4) When the fifth symbol mapping is used:

[0589] The bit pattern is distributed as r rows by c columns, where the r rows by c columns can be 16 rows by 16 columns or 16 rows by 15 columns.

[0590] The portion of the bit pattern in the rth row and the cth column marked with the numeral "0" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b0 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from the check bits of FEC encoding and is a sign bit in the X I on the symbol mapping (also referred to as modulation);

[0591] The portion of the bit pattern in the rth row and the cth column marked with the numeral "1" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b1 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing and is a first-type amplitude bit in the X I on the symbol mapping (also referred to as modulation);

[0592] The portion of the bit pattern in the rth row and the cth column marked with the numeral "2" indicates that the bit in the rth row and the cth column of the corresponding bit block is a b2 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing and is a second-type amplitude bit in the XI the second type of amplitude bits on the

[0593] The part marked with the number "3" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b3 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from the check bit of FEC encoding, and is X in the symbol mapping (also referred to as modulation) Q the symbol bit on the

[0594] The part marked with the number "4" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b4 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is X in the symbol mapping (also referred to as modulation) Q the first type of amplitude bits on the

[0595] The part marked with the number "5" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b5 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is X in the symbol mapping (also referred to as modulation) Q the second type of amplitude bits on the

[0596] The part marked with the number "6" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b6 bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or from the check bit of FEC encoding, and is Y in the symbol mapping (also referred to as modulation) I the symbol bit on the

[0597] The part marked with the number "7" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b7 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is Y in the symbol mapping (also referred to as modulation) I the first type of amplitude bits on the

[0598] The part marked with the number "8" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b8 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is Y in the symbol mapping (also referred to as modulation) I the second type of amplitude bits on the

[0599] The part marked with the number "9" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b9bit in the symbol mapping (also referred to as modulation); the bit is from the third bit set without PCS processing or a check bit from FEC encoding, and is the Y Q th amplitude bit in the symbol mapping (also referred to as modulation) on Y

[0600] The part marked with the number "10" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 10 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is the Y Q th first type of amplitude bit in the symbol mapping (also referred to as modulation) on Y

[0601] The part marked with the number "11" in the rth row and the cth column of the bit pattern indicates that the bit in the rth row and the cth column of the corresponding bit block is the b 11 bit in the symbol mapping (also referred to as modulation); the bit is from the second bit set with PCS processing, and is the Y Q th second type of amplitude bit in the symbol mapping (also referred to as modulation).

[0602] When the fifth symbol mapping is used, FIG. 44(a) is a schematic diagram of another fifth bit pattern in the embodiment of the present application, FIG. 44(b) is a schematic diagram of another sixth bit pattern in the embodiment of the present application, FIG. 45 is a schematic diagram of another seventh bit pattern, eighth bit pattern and ninth bit pattern in the embodiment of the present application, FIG. 46 is a schematic diagram of another tenth bit pattern, eleventh bit pattern and twelfth bit pattern in the embodiment of the present application, FIG. 47 is a schematic diagram of another thirteenth bit pattern, fourteenth bit pattern and fifteenth bit pattern in the embodiment of the present application, FIG. 48(a) is a schematic diagram of another sixteenth bit pattern in the embodiment of the present application, FIG. 48(b) is a schematic diagram of another seventeenth bit pattern in the embodiment of the present application, and FIG. 48(c) is a schematic diagram of another eighteenth bit pattern in the embodiment of the present application.

[0603] The first bit pattern adopts the bit distribution pattern shown in FIG. 11(a), which includes 96 bits from the third bit set without PCS processing (and as symbol bits in symbol mapping) and 160 bits from the second bit set with PCS processing (and as amplitude bits in symbol mapping) in the bit block with 16 rows and 16 columns.

[0604] The second bit pattern employs a bit distribution pattern as shown in Figure 11(b) that includes 80 bits from the third set of bits that are not PCS processed (and as sign bits in the symbol mapping) and 176 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0605] The third bit pattern employs a bit distribution pattern as shown in Figure 11(c) that includes 80 bits from the third set of bits that are not PCS processed (and as sign bits in the symbol mapping) and 176 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0606] In some embodiments, the fourth bit pattern employs a bit distribution pattern as shown in Figure 12(a) that includes 82 bits from the third set of bits that are not PCS processed (and as sign bits in the symbol mapping) and 174 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0607] In some embodiments, the fifth bit pattern employs a bit distribution pattern as shown in Figure 44(a) that includes 60 bits from the third set of bits that are not PCS processed (and as sign bits in the symbol mapping) and 196 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0608] In some embodiments, the sixth bit pattern employs a bit distribution pattern as shown in Figure 44(b) that includes 82 bits from the third set of bits that are not PCS processed (and as sign bits in the symbol mapping) and 174 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0609] The seventh bit pattern employs a bit distribution pattern as shown in Figure 45, the eighth bit pattern employs a bit distribution pattern as shown in Figure 45, the ninth bit pattern as shown in Figure 45 that includes 256 bits from the second set of bits that are PCS processed (and as magnitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0610] The tenth bit pattern is shown in Figure 46, the eleventh bit pattern is shown in Figure 46, and the twelfth bit pattern is shown in Figure 46, which includes 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 15 column block of bits.

[0611] The thirteenth bit pattern is shown in Figure 47, the fourteenth bit pattern is shown in Figure 47, and the forty-sixth bit pattern is shown in Figure 37, which includes 16 check bits from the FEC encoding (and as sign bits in the symbol mapping), and 240 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0612] The sixteenth bit pattern is shown in Figure 48(a), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0613] The seventeenth bit pattern is shown in Figure 48(b), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0614] The eighteenth bit pattern is shown in Figure 48(c), which includes 256 check bits from the FEC encoding (and as sign bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0615] The nineteenth bit pattern is shown in Figure 23(a), which includes 96 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 160 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0616] The twentieth bit pattern is shown in Figure 23(b), which includes 80 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 176 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0617] The twenty-first bit pattern is shown in Figure 23(c), which includes 80 bits from the third set of non-PCS-processed bits or check bits from the FEC encoding (and as sign bits in the symbol mapping), and 176 bits from the second set of PCS-processed bits (and as amplitude bits in the symbol mapping) in a 16 row by 16 column block of bits.

[0618] The twenty-second bit pattern is shown in FIG. 25(a), which includes 96 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 160 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a bit block of 16 rows by 16 columns.

[0619] The twenty-third bit pattern is shown in FIG. 25(b), which includes 80 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 176 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a bit block of 16 rows by 16 columns.

[0620] The twenty-fourth bit pattern is shown in FIG. 25(c), which includes 80 bits from the third bit set without PCS processing or from the check bits of FEC encoding (and as the sign bits in the symbol mapping) and 176 bits from the second bit set with PCS processing (and as the amplitude bits in the symbol mapping) in a bit block of 16 rows by 16 columns.

[0621] In some application scenarios, for the bit block of the ninth bit set with the fifth symbol mapping, the portion marked with the numeral "0" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b0, b3, b6 or b9 bit in the symbol mapping (also referred to as modulation), which is from the third bit set without PCS processing or from the check bits of FEC encoding and is a sign bit in the symbol mapping (also referred to as modulation); the portion marked with the numeral "1" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b1, b4, b7 or b 10 In some application scenarios, for the bit block of the ninth bit set with the fifth symbol mapping, the portion marked with the numeral "0" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b0, b3, b6 or b9 bit in the symbol mapping (also referred to as modulation), which is from the third bit set without PCS processing or from the check bits of FEC encoding and is a sign bit in the symbol mapping (also referred to as modulation); the portion marked with the numeral "1" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b1, b4, b7 or b 11 In some application scenarios, for the bit block of the ninth bit set with the fifth symbol mapping, the portion marked with the numeral "0" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b0, b3, b6 or b9 bit in the symbol mapping (also referred to as modulation), which is from the third bit set without PCS processing or from the check bits of FEC encoding and is a sign bit in the symbol mapping (also referred to as modulation); the portion marked with the numeral "1" in the r0th row and the c0th column of the bit pattern indicates that the bit in the r0th row and the c0th column of the corresponding bit block is the b1, b4, b7 or b

[0622] Considering the above labeling manner, the bit block pattern in the ninth bit set 2i and the ninth bit set 2i+1 is introduced respectively. Referring to the 42 rows and 8 columns of bit block diagram shown in FIG. 20, the bit block pattern in the ninth bit set 2i on the fifth bit stream 2i is introduced as follows (0≤i0<42 and 0≤j1<8) pattern. FIG. 49(a) is a schematic diagram of another first bit pattern in an embodiment of the present application. FIG. 49(b) is a schematic diagram of another second bit pattern in an embodiment of the present application. FIG. 49(c) is a schematic diagram of another third bit pattern in an embodiment of the present application.

[0623] 1) For 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks adopts the first bit pattern. As an example, the first bit pattern is shown in FIG. 49(a), which includes 16 rows and 16 columns of bit blocks, and a total of 96 bits labeled with the number "0", 80 bits labeled with the number "1", and 80 bits labeled with the number "2". That is, a total of 80 bits from the third bit set without PCS processing (and as the symbol bit in symbol mapping), 80 bits for generating the first type of amplitude bits, and 64 bits for generating the second type of amplitude bits.

[0624] 2) For 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks adopts the second bit pattern. As an example, the second bit pattern is shown in FIG. 49(b), which includes 16 rows and 16 columns of bit blocks, and a total of 80 bits labeled with the number "0", 96 bits labeled with the number "1", and 80 bits labeled with the number "2". That is, a total of 80 bits from the third bit set without PCS processing (and as the symbol bit in symbol mapping), 96 bits for generating the first type of amplitude bits, and 80 bits for generating the second type of amplitude bits.

[0625] 3) For 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8, the bit pattern of the corresponding 112 bit blocks The bit pattern of the 112 bit blocks of the 2i+1 bit set on the 2i+1 bit stream adopts the third bit pattern. As an example, the third bit pattern is shown in Fig. 49(c), which contains 80 bits marked with the number "0", 80 bits marked with the number "1", and 96 bits marked with the number "2" in the 16 rows by 16 columns of bit blocks. That is, it contains 80 bits from the third bit set which are not processed by the PCS (and are the sign bits in the symbol mapping), and 80 bits for generating the first type of amplitude bits, and 96 bits for generating the second type of amplitude bits.

[0626] Referring to the 42 rows by 8 columns of bit blocks shown in Fig. 20, the bit pattern of the 2i+1 bit set on the 2i+1 bit stream is described below.

[0627] 1) For 0≤i0<21 and i0%3=0, or, 21≤i0<42 and i0%3=2, i.e., i0=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks adopts the third bit pattern. As an example, the third bit pattern is shown in Fig. 49(c).

[0628] 2) For 0≤i0<21 and i0%3=1, or, 21≤i0<42 and i0%3=0, i.e., i0=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks adopts the first bit pattern. As an example, the first bit pattern is shown in Fig. 49(a).

[0629] 3) For 0≤i0<21 and i0%3=2, or, 21≤i0<42 and i0%3=1, i.e., i0=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j1<8: the bit pattern of the corresponding 112 bit blocks adopts the second bit pattern. As an example, the second bit pattern is shown in Fig. 49(b).

[0630] ​From the above introduction of the first data processing and the second data processing, it can be known that for future metropolitan telecommunication transmission and metropolitan DCI interconnection scenarios, DP-64QAM will be adopted in combination with FEC encoding and PCS processing technology to meet longer transmission distance. The introduction of PCS processing requires that when symbol mapping operation is performed, the symbol bits mapped to one modulation symbol are 0 and 1 with equal probability, and the amplitude bits mapped to one modulation symbol are 0 and 1 with unequal probability. More specifically, the probability of the levels corresponding to the amplitude bits mapped to one modulation symbol is not completely the same, which can be 1, 3, 5, and 7. In some specific scenarios, through the design of the specific implementation of PCS processing, 7 levels can not appear, and at this time, it is also called DP-36QAM modulation. Taking OFEC encoding as an example, in order to avoid the influence on the existing OFEC encoding and OFEC interleaver as much as possible, a new interleaver needs to be introduced after OFEC encoding and before symbol mapping operation, so that the 0 and 1 bits obtained through PCS processing can be mapped to the amplitude bits of the modulation symbol, the probability of the constellation point appearing is changed while the position of the constellation point is kept unchanged, the constellation point is non-uniformly distributed, and the overall performance is improved to meet the longer transmission distance requirement in the future.

[0631] The following gives several specific embodiments in combination with the above introduction of the second data processing.

[0632] Embodiment 1:

[0633] FIG. 50 is a schematic diagram of an application scenario of the second data processing in the embodiment of the application. As shown in FIG. 50, considering that the second data processing L=2, it includes two PCS processing and first interleaving, i.e., “PCS processing and first interleaving 0” and “PCS processing and first interleaving 1”, and the PCS processing and first interleaving specifically adopt the manner shown in FIG. 6(c).

[0634] In some application scenarios, the PCS processing, the first interleaving, and the fourth interleaving can be collectively referred to as a probabilistic constellation shaper (Probabilistic Constellation Shaper), as shown in the grid hatched area in FIG. 37. In some application scenarios, the input processing granularity of FEC encoding is K=3552 bits, and the corresponding output granularity is N=4096 bits, and the extended BCH (256, 239) with a coding redundancy of 15.3% is adopted. The FEC encoding and the fifth interleaving can be collectively referred to as OFEC encoding, as shown in the diagonal hatched area in FIG. 50.

[0635] Embodiment 2:

[0636] The first symbol mapping is considered, one of the second bit streams 2i is distributed into the sixth bit set 2i of 42 rows and 8 columns of bit blocks, and is sent into the fourth interleaving 2i to obtain the ninth bit set 2i, one of the second bit streams 2i+1 is distributed into the sixth bit set 2i+1 of 42 rows and 8 columns of bit blocks, and is sent into the fourth interleaving 2i+1 to obtain the ninth bit set 2i+1.

[0637] Fig. 51(a) is a schematic diagram of a bit distribution of the last 69 columns of bits in the sixth bit set 2i according to an embodiment of the present application. Fig. 51(b) is a schematic diagram of another bit distribution of the last 69 columns of bits in the sixth bit set 2i+1 according to an embodiment of the present application. As an example, for 0≤i0<42, the pattern of the last 5 columns of bits in the bit block of the j1=3th column in the i0th row in the sixth bit set 2i is shown in Fig. 51(a), and the pattern of the last 5 columns of bits in the bit block of the j1=3th column in the i0th row in the sixth bit set 2i+1 is shown in Fig. 51(b); the pattern of the bits in the bit blocks of the j1=4, 5, 6 and 7th columns in the i0th row in the sixth bit set 2i is shown in Fig. 51(a), and the pattern of the bits in the bit blocks of the j1=4, 5, 6 and 7th columns in the i0th row in the sixth bit set 2i+1 is shown in Fig. 51(b), i.e. the bits in the bit blocks of the j1=4, 5, 6 and 7th columns in the i0th row in the sixth bit set 2i+1 are all amplitude bits, the bits in the first 15 columns of bits in the bit blocks of the j1=4, 5, 6 and 7th columns in the i0th row in the sixth bit set 2i are all amplitude bits and the bits in the last column of bits in the bit blocks of the j1=4, 5, 6 and 7th columns in the i0th r...

Claims

A data processing method, characterized in that, include: Probabilistic constellation shaping (PCS) is performed on the first set of bits from a plurality of bits to obtain a second set of bits. Half of the bits in the second set of bits are first-type bits, and the other half of the bits in the second set of bits are second-type bits. The second bit set and the third bit set (excluding the first bit set) of the plurality of bits are interleaved in the first interleaving to obtain the fourth bit set 1 and the fourth bit set 2. Forward error correction (FEC) encoding is performed on the two fifth bit sets to obtain two sixth bit sets. The fifth bit set 1 of the two fifth bit sets includes at least one of the fourth bit sets 1, and the fifth bit set 2 of the two fifth bit sets includes at least one of the fourth bit sets 2. The two sets of sixth bits are interleaved a second time to obtain two sets of seventh bits; The two sets of seventh bits are interleaved a third time to obtain a set of eighth bits, wherein 12 consecutive bits in the set of eighth bits are used for mapping to obtain a double polarization symbol, the double polarization symbol including a first polarization symbol and a second polarization symbol; Of the 12 bits, 2 bits used to map to the first polarization symbol come from the first type of bits, 2 bits used to map to the first polarization symbol come from the second type of bits, and 2 bits used to map to the first polarization symbol come from the third bit set or the FEC-encoded check bits; of the 12 bits used to map to the second polarization symbol, 2 bits used to map to the second polarization symbol come from the first type of bits, 2 bits used to map to the second polarization symbol come from the second type of bits, and 2 bits used to map to the second polarization symbol come from the third bit set or the FEC-encoded check bits. The method according to claim 1, characterized in that, The error bit rate of the first type of bit is less than the error bit rate of the second type of bit. The method according to claim 1 or 2, characterized in that, The probability that a bit in the first type of bit is 1 is P. 0；1 The probability that a bit in the first type of bit is 0 is P. 0；0 The probability that a bit in the second type of bit is 1 is P. 1；1 The probability that a bit in the second type of bit is 0 is P. 1；0 P 0；1 -P 0；0 The absolute value is greater than or equal to P 1；1 -P 1；0 The absolute value of. The method according to any one of claims 1 to 3, characterized in that, The first bit set includes L PCS A first subset of bits, subjected to PCS processing to obtain a second set of bits, includes: For each of the first subset of bits, where k pcs_0 The first PCS subprocess is performed on each bit to obtain n. pcs_0 The first bit; For each additional k of the first bit subset pcs_1 Each bit is processed by the second PCS subprocess to obtain n. pcs_1 The first bit; For the n pcs_0 The first bit and the n pcs_1 Perform bit mapping on the first bit to obtain n pcs_0 The second bit and n pcs_1 The second bit; Wherein, n pcs_0 The second bit includes the first type of bit, the n pcs_1 The second bit includes the second type of bit, k pcs_0 and k pcs_1 All are integers greater than or equal to 1, n pcs_0 >k pcs_0 n pcs_1 >k pcs_1 n pcs_0 =n pcs_1 . The method according to claim 4, characterized in that, For the n pcs_0 The first bit and the n pcs_1 Perform bit mapping on the first bit to obtain n pcs_0 The second bit and n pcs_1 The second bit includes: Obtain the n pcs_0 Bit a in the first bit and the n pcs_1 Bit b from the first bit, perform bit mapping on bits a and b to obtain bits a and a∧b, the n pcs_0 The second bit includes bit a, and the n pcs_1 The second bit includes the bit a∧b, where ∧ represents the XOR operation. The method according to claim 4 or 5, characterized in that, The n pcs_0 The probability P that the first bit is 1 cs0； The probability P that 1 is greater than the value of 0. cs0； 0，P cs0； 0+P cs0； 1 = 1; the n pcs_1 The probability P that the first bit is 1 cs1；1 The probability P of a bit being 0 cs1；0 P cs1；0 +P cs1；1 =1. The method according to claim 6, characterized in that, k pcs_0 <k pcs_1 ,P cs0； 1>P cs1；1 ,P cs0； 0 <P cs1；0 Or, k pcs_0 =k pcs_1 P cs0； 1=P cs1；1 ,P cs0；0 =P cs1；0 。 The method according to any one of claims 1 to 7, characterized in that, The two seventh bit sets include seventh bit set 1 and seventh bit set 2. Each of seventh bit set 1 and seventh bit set 2 includes 336 second bit subsets with 42 rows and 8 columns. The second bit subset includes 256 bits with 16 rows and 16 columns. The bit distribution pattern of the second bit subset is used to represent the position of the bit from the first type of bit in the second bit subset, the position of the bit from the second type of bit in the second bit subset, and the position of the bit from the third bit set or the FEC-encoded check bit in the second bit subset. The bit distribution pattern of the second bit subset in rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 of the seventh bit set 1 is the first bit distribution pattern; The bit distribution pattern of the second bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 in the seventh bit set 1 is the second bit distribution pattern; The bit distribution pattern of the second bit subset in rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 of the seventh bit set 1 is the third bit distribution pattern; The bit distribution pattern of the second bit subset in rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 of the seventh bit set 2 is the third bit distribution pattern; The bit distribution pattern of the second bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 in the seventh bit set 2 is the first bit distribution pattern; The bit distribution pattern of the second bit subset in rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 of the seventh bit set 2 is the second bit distribution pattern. The method according to any one of claims 1 to 8, characterized in that, Performing a second interleaving on the two sets of sixth bits to obtain two sets of seventh bits includes: The two sets of sixth bits are interleaved in the fourth way to obtain two sets of ninth bits. The two sets of ninth bits include set 1 and set 2. Each set of ninth bits includes 336 subsets of third bits in 42 rows and 8 columns. Each subset of third bits includes 256 bits in 16 rows and 16 columns. The two sets of ninth bits are subjected to a fifth interleaving to obtain the two sets of seventh bits, wherein the fifth interleaving is used to interleave 16 bits in each row of each of the third bit subsets in the sets of ninth bits. The method according to claim 9, characterized in that, The bit distribution pattern of the third bit subset is used to represent the position of the bit from the first type of bit in the third bit subset, the position of the bit from the second type of bit in the third bit subset, and the position of the bit from the third bit set or the check bit of the FEC encoding in the third bit subset; The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 in the ninth bit set 1 is the fourth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 in the ninth bit set 1 is the fifth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 in the ninth bit set 1 is the sixth bit distribution pattern. The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 in the ninth bit set 2 is the sixth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 in the ninth bit set 2 is the fourth bit distribution pattern. The bit distribution pattern of the third bit subset in rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 of the ninth bit set 2 is the fifth bit distribution pattern. The method according to any one of claims 1 to 10, characterized in that, The two sets of sixth bits include set 1 and set 2. Each set of sixth bits includes 336 subsets of fourth bits in 42 rows and 8 columns, and each subset of fourth bits includes 256 bits in 16 rows and 16 columns. In the 336 fourth bit subsets in the 42 rows and 8 columns, the bits in the fourth bit subsets from column 0 to column 4 come from the second bit set and the third bit set. The bits in the fourth bit subset of column 5 and the bits in the fourth bit subset of column 6 from column 0 to column 14 come from the second bit set. The bits in the fourth bit subset of column 6 and the bits in the fourth bit subset of column 7 are the check bits of the FEC encoding. The method according to claim 11, characterized in that, The bit distribution pattern of the fourth bit subset is used to represent the position of the bit from the first type of bit in the fourth bit subset, the position of the bit from the second type of bit in the fourth bit subset, and the position of the bit from the third bit set or the FEC-encoded check bit in the fourth bit subset. The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 1, namely rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41, is the fourth bit distribution pattern. The bit distribution pattern of the fourth bit subset of columns 0 to 3 in the sixth bit set 1, namely rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39, is the fifth bit distribution pattern; The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 1, namely rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40, is the sixth bit distribution pattern; The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 2, namely rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41, is the sixth bit distribution pattern. The bit distribution pattern of the fourth bit subset of columns 0 to 3 in the sixth bit set 2, namely rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39, is the fourth bit distribution pattern. The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 2, namely rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, and 40, is the fifth bit distribution pattern. The method according to any one of claims 1 to 7, characterized in that, The two seventh bit sets include seventh bit set 1 and seventh bit set 2. Each of seventh bit set 1 and seventh bit set 2 includes 336 second bit subsets with 42 rows and 8 columns. The second bit subset includes 256 bits with 16 rows and 16 columns. The bit distribution pattern of the second bit subset is used to represent the position of the bit from the first type of bit in the second bit subset, the position of the bit from the second type of bit in the second bit subset, and the position of the bit from the third bit set or the FEC-encoded check bit in the second bit subset. The bit distribution pattern of the second bit subset in rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 of the seventh bit set 1 is the first bit distribution pattern; The bit distribution pattern of the second bit subset in rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 of the seventh bit set 1 is the second bit distribution pattern; The bit distribution pattern of the second bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 in the seventh bit set 1 is the third bit distribution pattern; The bit distribution pattern of the second bit subset in rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 of the seventh bit set 2 is the second bit distribution pattern; The bit distribution pattern of the second bit subset in rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 of the seventh bit set 2 is the third bit distribution pattern; The bit distribution pattern of the second bit subset in rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 of the seventh bit set 2 is the first bit distribution pattern. The method according to claim 1, 2, 3, 4, 5, 6, 7 or 13 is characterized in that, Performing a second interleaving on the two sets of sixth bits to obtain two sets of seventh bits includes: The two sets of sixth bits are interleaved in the fourth way to obtain two sets of ninth bits. The two sets of ninth bits include set 1 and set 2. Each set of ninth bits includes 336 subsets of third bits in 42 rows and 8 columns. Each subset of third bits includes 256 bits in 16 rows and 16 columns. The two sets of ninth bits are subjected to a fifth interleaving to obtain the two sets of seventh bits, wherein the fifth interleaving is used to interleave 16 bits in each row of each of the third bit subsets in the sets of ninth bits. The method according to claim 14, characterized in that, The bit distribution pattern of the third bit subset is used to represent the position of the bit from the first type of bit in the third bit subset, the position of the bit from the second type of bit in the third bit subset, and the position of the bit from the third bit set or the check bit of the FEC encoding in the third bit subset; The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 in the ninth bit set 1 is the fourth bit distribution pattern. The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 in the ninth bit set 1 is the fifth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 in the ninth bit set 1 is the sixth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 in the ninth bit set 2 is the fifth bit distribution pattern. The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 in the ninth bit set 2 is the sixth bit distribution pattern. The bit distribution pattern of the third bit subset in rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 of the ninth bit set 2 is the fourth bit distribution pattern. The method according to claim 1, 2, 3, 4, 5, 6, 7, 13, 14 or 15, characterized in that, The two sets of sixth bits include set 1 and set 2. Each set of sixth bits includes 336 subsets of fourth bits in 42 rows and 8 columns, and each subset of fourth bits includes 256 bits in 16 rows and 16 columns. In the 336 fourth bit subsets in the 42 rows and 8 columns, the bits in the fourth bit subsets from column 0 to column 4 come from the second bit set and the third bit set. The bits in the fourth bit subset of column 5 and the bits in the fourth bit subset of column 6 from column 0 to column 14 come from the second bit set. The bits in the fourth bit subset of column 6 and the bits in the fourth bit subset of column 7 are the check bits of the FEC encoding. The method according to claim 16, characterized in that, The bit distribution pattern of the fourth bit subset is used to represent the position of the bit from the first type of bit in the fourth bit subset, the position of the bit from the second type of bit in the fourth bit subset, and the position of the bit from the third bit set or the FEC-encoded check bit in the fourth bit subset. The bit distribution pattern of the fourth bit subset in columns 0 to 40 of the sixth bit set 1 is the fourth bit distribution pattern. The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 1, namely rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41, is the fifth bit distribution pattern; The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 1, namely rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39, is the sixth bit distribution pattern. The bit distribution pattern of the fourth bit subset in columns 0 to 40 of the sixth bit set 2 is the fifth bit distribution pattern. The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 2, namely rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41, is the sixth bit distribution pattern. The bit distribution pattern of the fourth bit subset in columns 0 to 3 of the sixth bit set 2 is the fourth bit distribution pattern. The method according to any one of claims 1 to 17, characterized in that, Bits 0, 2, 4, 6, 8, and 10 of the 12 bits are used to map to the first polarization symbol, and bits 1, 3, 5, 7, 9, and 11 of the 12 bits are used to map to the second polarization symbol. The method according to claim 18, characterized in that, Bits 0, 2, and 4 of the 12 bits are used to map to the first component of the first polarization symbol; bits 6, 8, and 10 of the 12 bits are used to map to the second component of the first polarization symbol; bits 1, 3, and 5 of the 12 bits are used to map to the first component of the second polarization symbol; and bits 7, 9, and 11 of the 12 bits are used to map to the second component of the second polarization symbol. The 2nd, 3rd, 8th, and 9th bits are from the first type of bits, and the 4th, 5th, 10th, and 11th bits are from the second type of bits. The method according to claim 18, characterized in that, Bits 0, 4, and 6 of the 12 bits are used to map to the first component of the first polarization symbol; bits 2, 8, and 10 of the 12 bits are used to map to the second component of the first polarization symbol; bits 1, 5, and 7 of the 12 bits are used to map to the first component of the second polarization symbol; and bits 3, 9, and 11 of the 12 bits are used to map to the second component of the second polarization symbol. The 4th, 5th, 8th, and 9th bits are from the first type of bits, and the 6th, 7th, 10th, and 11th bits are from the second type of bits. The method according to claim 18, characterized in that, The 8th, 0th, and 2nd bits of the 12 bits are used to map to the first component of the first polarization symbol; the 10th, 4th, and 6th bits of the 12 bits are used to map to the second component of the first polarization symbol; the 9th, 1st, and 3rd bits of the 12 bits are used to map to the first component of the second polarization symbol; and the 11th, 5th, and 7th bits of the 12 bits are used to map to the second component of the second polarization symbol. The 0th, 1st, 4th, and 5th bits are from the first type of bits, and the 2nd, 3rd, 6th, and 7th bits are from the second type of bits. The method according to claim 18, characterized in that, The 4th, 0th, and 2nd bits of the 12 bits are used to map to the first component of the first polarization symbol; the 6th, 8th, and 10th bits of the 12 bits are used to map to the second component of the first polarization symbol; the 5th, 1st, and 3rd bits of the 12 bits are used to map to the first component of the second polarization symbol; and the 7th, 9th, and 11th bits of the 12 bits are used to map to the second component of the second polarization symbol. The 0th, 1st, 8th, and 9th bits are from the first type of bits, and the 2nd, 3rd, 10th, and 11th bits are from the second type of bits. The method according to any one of claims 1 to 17, characterized in that, Bits 0, 1, 2, 3, 4, and 5 of the 12 bits are used to map to the first polarization symbol, and bits 6, 7, 8, 9, 10, and 11 of the 12 bits are used to map to the second polarization symbol. The method according to claim 23, characterized in that, Bits 0, 1, and 2 of the 12 bits are used to map to the first component of the first polarization symbol; bits 3, 4, and 5 of the 12 bits are used to map to the second component of the first polarization symbol; bits 6, 7, and 8 of the 12 bits are used to map to the first component of the second polarization symbol; and bits 9, 10, and 11 of the 12 bits are used to map to the second component of the second polarization symbol. The first, fourth, seventh, and tenth bits are from the first type of bits, and the second, fifth, eighth, and eleventh bits are from the second type of bits. The method according to claim 19, 20, 21, 22 or 24 is characterized in that, The polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol; The first component is an I-channel component, and the second component is a Q-channel component; or, the first component is a Q-channel component, and the second component is an I-channel component. The method according to any one of claims 1 to 25, characterized in that, The two sets of seventh bits include set 1 and set 2. The third interleaving of the two sets of seventh bits to obtain the set of eighth bits includes: The seventh bit set 1 is interleaved within a square matrix to obtain the tenth bit set 1, and the seventh bit set 2 is interleaved within a square matrix to obtain the tenth bit set 2. The tenth bit set 1 and the tenth bit set 2 each include 42 rows and 8 columns, totaling 336 fifth bit subsets, and each fifth bit subset includes 16 rows and 16 columns, totaling 256 bits. The tenth bit set 1 and the tenth bit set 2 are interleaved to obtain the eighth bit set, which includes 672 fifth bit subsets in 84 rows and 8 columns. The method according to any one of claims 1 to 26, characterized in that, The first bit set includes a first bit set 1 and a first bit set 2. The second bit set is obtained by performing PCS processing on the first bit set from multiple bits, including: The first bit set 1 is subjected to PCS processing to obtain the second bit set 1, and the first bit set 2 is subjected to PCS processing to obtain the second bit set 2, wherein the second bit set includes the second bit set 1 and the second bit set 2. The method according to claim 27, characterized in that, The third bit set includes the third bit set 1 and the third bit set 2. Performing a first interleaving of the second bit set and the third bit set (excluding the first bit set) among the plurality of bits to obtain the fourth bit set 1 and the fourth bit set 2 includes: The second bit set 1, the second bit set 2, the third bit set 1, and the third bit set 2 are interleaved in the first way to obtain the fourth bit set 1 and the fourth bit set 2. The method according to claim 27, characterized in that, The third bit set includes the third bit set 1 and the third bit set 2. Performing a first interleaving of the second bit set and the third bit set (excluding the first bit set) among the plurality of bits to obtain the fourth bit set 1 and the fourth bit set 2 includes: The second bit set 1 and the third bit set 1 are interleaved in a first manner to obtain the fourth bit set 1, and the second bit set 2 and the third bit set 2 are interleaved in a first manner to obtain the fourth bit set 2. The method according to claim 27, characterized in that, Performing a first interleaving of the second bit set and the third bit set (excluding the first bit set) to obtain the fourth bit set 1 and the fourth bit set 2 includes: The second bit set 1, the second bit set 2, and the third bit set are first interleaved to obtain the fourth bit set 1 and the fourth bit set 2. The method according to any one of claims 1 to 30, characterized in that, The first type of amplitude bits mapped to the dual polarization symbol comes from the first type of bits, the second type of amplitude bits mapped to the dual polarization symbol comes from the second type of bits, and the symbol bits mapped to the dual polarization symbol come from the third bit set or the FEC-encoded check bits. The method according to any one of claims 1 to 31, characterized in that, The data processing method is applicable to scenarios including Ethernet, optical transport networks, and space optical communication. A data processing apparatus, characterized in that, The data processing device includes: a probabilistic constellation shaping (PCS) unit, a first interleaving unit, a forward error correction (FEC) coding unit, a second interleaving unit, and a third interleaving unit; The PCS unit is used to: perform probabilistic constellation shaping (PCS) processing on a first set of bits from a plurality of bits to obtain a second set of bits, wherein half of the bits in the second set of bits are first type bits and the other half of the bits in the second set of bits are second type bits; The first interleaving unit is used to: perform a first interleaving on the second bit set and the third bit set other than the first bit set in the plurality of bits to obtain a fourth bit set 1 and a fourth bit set 2; The FEC coding unit is used to: perform forward error correction FEC coding on the two fifth bit sets respectively to obtain two sixth bit sets, wherein the fifth bit set 1 of the two fifth bit sets includes at least one of the fourth bit sets 1, and the fifth bit set 2 of the two fifth bit sets includes at least one of the fourth bit sets 2; The second interleaving unit is used to: perform a second interleaving on the two sets of sixth bits respectively to obtain two sets of seventh bits; The third interleaving unit is used to: perform a third interleaving on the two sets of seventh bits to obtain an eighth set of bits, wherein 12 consecutive bits in the eighth set of bits are used for mapping to obtain a double polarization symbol, the double polarization symbol including a first polarization symbol and a second polarization symbol; Of the 12 bits, the first group of 2 bits used to map to the first polarization symbol comes from the first type of bits; the second group of 2 bits used to map to the first polarization symbol comes from the second type of bits; and the third group of 2 bits used to map to the first polarization symbol comes from the third bit set or the FEC-encoded check bits. A chip characterized in that, The chip is used to perform the method as described in any one of claims 1 to 32. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being configured to perform the method as described in any one of claims 1 to 32 and to transmit signals through the interface. The optical module according to claim 35 is characterized in that, The processor is used to process the eighth bit set to obtain a superframe, and to send the superframe through the interface. The optical module according to claim 35 is characterized in that, The optical module further includes a modulator. The processor is used to process the eighth bit set to obtain a superframe. The modulator is used to perform electro-optical conversion based on the superframe to obtain an optical signal and to send the optical signal through the interface. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in any one of claims 35 to 37, the optical module being used to generate an optical signal based on data from the host-side device and to transmit the optical signal. A communication system, characterized in that, include: The transmitting device and the receiving device as described in claim 38, wherein the transmitting device is configured to transmit an optical signal to the receiving device.

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