Apparatus, device and system for optically transmitting pcie sideband signal

Abstract

Provided in the present disclosure are a transmission apparatus, transmission device and transmission system for optically transmitting a PCIe sideband signal. The transmission apparatus comprises a first sideband signal processing unit and a first sideband optical transceiving unit, wherein the first sideband signal processing unit is used for acquiring a first initial sideband electrical signal and converting the first initial sideband electrical signal into a first transmission sideband electrical signal; the first sideband optical transceiving unit is used for connecting to a first sideband optical channel that is independent of an in-band optical channel, and converting the first transmission sideband electrical signal into a first transmission sideband optical signal and sending same via the first sideband optical channel, and / or the first sideband optical transceiving unit is used for connecting to the first sideband optical channel that is independent of the in-band optical channel, receiving a second transmission sideband optical signal via the first sideband optical channel, and converting the second transmission sideband optical signal into a second transmission sideband electrical signal; and the first sideband signal processing unit is used for reconverting the received second transmission sideband electrical signal into a second initial sideband electrical signal.

Description

Devices, apparatus and systems for optically transmitting PCIe sideband signals

[0001] This application claims priority to Chinese Patent Application No. 202410552032.6, filed on May 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to the field of optical signal communication, and more specifically to transmission apparatus, transmission devices and transmission systems for optically transmitting PCIe sideband signals. Background Technology

[0003] As the data transmission rate supported by the PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) protocol continues to increase, long-distance transmission via cables becomes difficult. Therefore, optical communication technology has been introduced into the PCIe field, with the aim of replacing electrical transmission with optical transmission.

[0004] According to PCIe, in addition to high-speed data transmission within the band, some sideband signals also need to be transmitted at low speed outside the band (also known as sideband). These sideband signals are used to assist in controlling or managing data transmission within the band, and include, but are not limited to, the reset signal PERST, the presence signal PRSNT, the reference clock signal REFCLK, the SMbus signal, and optional signals such as WAKE, CLKREQ, PWRBRK, PWEREN, general I / O signals, and additional hot-plug signals. However, there are currently various challenges in transmitting these sideband signals, which are originally transmitted on sideband signal lines constructed by cables, over optical channels constructed by optical fibers. Therefore, it is necessary to propose a device capable of transmitting these sideband signals over optical channels. Summary of the Invention

[0005] In view of the above, this disclosure provides a transmission apparatus, transmission device and transmission system for optically transmitting PCIe sideband signals, which enables the transmission of PCIe sideband signals over an optical channel constructed of optical fiber.

[0006] According to a first aspect of this disclosure, a transmission apparatus for optically transmitting PCIe sideband signals is provided, comprising: a first sideband signal processing unit and a first sideband optical transceiver unit; wherein the first sideband signal processing unit is configured to acquire a first initial sideband electrical signal and convert the first initial sideband electrical signal into a first transmission sideband electrical signal, the first sideband optical transceiver unit is configured to connect to a first sideband optical channel independent of an in-band optical channel and convert the first transmission sideband electrical signal into a first transmission sideband optical signal and transmit the first transmission sideband optical signal via the first sideband optical channel, and / or the first sideband signal optical transceiver unit is configured to connect to a first sideband optical channel independent of an in-band optical channel and receive a second transmission sideband optical signal via the first sideband optical channel and convert the second transmission sideband optical signal into a second transmission sideband electrical signal, and the first sideband signal processing unit is configured to restore the received second transmission sideband electrical signal to a second initial sideband electrical signal.

[0007] Optionally, the first transmission sideband signal and the second transmission sideband signal have UART format.

[0008] Optionally, the first initial sideband electrical signal and the second initial sideband electrical signal include an initial presence signal; the first transmission sideband electrical signal and the second transmission sideband electrical signal include a UART-formatted presence signal; the first sideband signal processing unit acquires the initial presence signal when it determines that the transmission device is connected to a PCIe terminal device, and converts the initial presence signal into a UART-formatted presence signal for transmission by the first sideband optical transceiver unit; and the first sideband signal processing unit restores the UART-formatted presence signal received by the first sideband signal optical transceiver unit to the initial presence signal when it determines that the transmission device is connected to a PCIe host device.

[0009] Optionally, the first sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe terminal device by detecting that the level of the plurality of presence signal pins drops to a first predetermined voltage range.

[0010] Optionally, the first sideband signal processing unit further determines that the transmission device is connected to a PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, wherein the highest voltage of the second predetermined voltage range is lower than the lowest voltage of the first predetermined voltage range.

[0011] Optionally, the first sideband signal processing unit controls the first sideband optical transceiver unit to send the first transmission sideband optical signal at a predetermined time interval until an acknowledgment message for the first transmission sideband signal is received, or controls the first sideband optical transceiver unit to send the first transmission sideband optical signal a predetermined number of times.

[0012] Optionally, the first initial sideband electrical signal and the second initial sideband electrical signal further include an initial reset signal; the first transmission sideband electrical signal and the second transmission sideband electrical signal further include a UART format reset signal; wherein, when the first sideband signal processing unit determines that the transmission device is connected to the PCIe host device, it acquires the initial reset signal and converts the initial reset signal into the UART format reset signal for the first sideband optical transceiver unit to perform electro-optical conversion and then transmit; and when the first sideband signal processing unit determines that the transmission device is connected to the PCIe terminal device, it restores the UART format reset signal received and photoelectrically converted by the first sideband signal optical transceiver unit into the initial reset signal.

[0013] Optionally, the first initial sideband electrical signal and the second initial sideband electrical signal further include an initial Internet packet explorer Ping message; the first transmission sideband electrical signal and the second transmission sideband electrical signal further include a Ping message in UART format, wherein the first sideband signal processing unit generates the initial Ping message in response to power-on, and converts the initial Ping message into a Ping message in UART format for the first sideband optical transceiver unit to perform electro-optical conversion and then transmit.

[0014] Thus, the transmission apparatus according to the first aspect of this disclosure realizes the optical transmission of PCIe sideband signals, and utilizes a first low-speed sideband optical channel independent of the high-speed in-band optical channel to transmit the PCIe sideband signals, resulting in low power consumption and high reliability.

[0015] Optionally, the transmission device further includes: an in-band optical transceiver unit for connecting to each optical channel in the in-band optical channel; and a receiver detection circuit for performing receiver detection for each optical channel in the in-band optical channel to generate an initial receiver result electrical signal indicating whether the receiver detection of the optical channel is successful or unsuccessful for each optical channel, wherein the first sideband signal processing unit also converts the initial receiver result electrical signal of each optical channel into a receiver detection result electrical signal in UART format, and the first sideband optical transceiver unit also converts the UART format receiver detection result electrical signal into a receiver detection result optical signal in UART format and transmits it via the first sideband optical channel.

[0016] Optionally, the receiver detection circuit includes: a plurality of receiver detection sub-circuits, each of the plurality of receiver detection sub-circuits being used to perform receiver detection for a corresponding optical channel among the plurality of optical channels, wherein each receiver detection sub-circuit includes an RC circuit, and generates an initial receiver detection result electrical signal indicating successful receiver detection of the corresponding optical channel based on the time constant of the RC circuit responding to a common-mode voltage step being greater than a predetermined duration threshold, or generates an initial receiver detection result electrical signal indicating failed receiver detection of the corresponding optical channel based on the time constant being less than the predetermined duration threshold.

[0017] Optionally, each detection sub-circuit further includes: a first differential cable pair, a second differential cable pair, a detection unit, and two second resistors, wherein the first differential cable pair is used to connect to the electro-optic converter in the in-band optical transceiver unit; the second differential cable pair is used to connect to the photoelectric converter in the in-band optical transceiver unit; the RC circuit includes two identical sub-RC circuits respectively coupled to the two cables of the first differential cable pair, each sub-RC circuit including a first capacitor and a first resistor; the detection unit is used to drive the common-mode voltage step on the first differential cable pair, determine the time constant of the two sub-RC circuits responding to the common-mode voltage step, and generate a receiver detection result electrical signal indicating successful receiver detection of the corresponding optical channel based on the time constant being greater than the predetermined duration threshold, or generate a receiver detection result electrical signal indicating failed receiver detection of the corresponding optical channel based on the time constant being less than the predetermined duration threshold; and the two second resistors are respectively coupled to the two cables of the second differential cable pair.

[0018] Optionally, the first detection unit includes: a common-mode voltage driving subunit, configured to drive a common-mode low voltage on the first differential cable pair to pull the voltage of the first capacitor down to a predetermined low voltage value, and, after determining that the voltage across the first capacitor has been pulled down to the predetermined low voltage value, drive a common-mode high voltage on the first differential cable pair; a recording subunit, configured to record the time elapsed from the moment the common-mode voltage driving subunit drives the common-mode high voltage until the voltage across the first capacitor reaches the predetermined high voltage value, as the time constant; and a determination unit, configured to generate an initial receiver detection result electrical signal indicating successful detection of the receiver in the corresponding optical channel based on the time constant being greater than the predetermined time threshold, or to generate an initial receiver detection result electrical signal indicating failed detection of the receiver in the corresponding optical channel based on the time constant being less than the predetermined time threshold.

[0019] Optionally, the first sideband signal processing unit further multiplexes and encodes the corresponding two or more initial reception detection result electrical signals of two or more optical channels among the plurality of optical channels of the in-band optical channel into multiplexed reception detection result electrical signals in UART format; the first sideband optical transceiver unit further transmits the multiplexed reception detection result electrical signals in UART format via the first sideband optical channel.

[0020] Optionally, the detection unit is integrated into the first sideband signal processing unit.

[0021] Optionally, the detection unit is implemented by a PCIe ReDriver chip.

[0022] Thus, the transmission apparatus according to the first aspect of this disclosure also provides an optical solution for receiver detection, and transmits the receiver detection result signal by utilizing a first sideband optical channel independent of the in-band optical channel, resulting in low power consumption and high reliability.

[0023] According to a second aspect of this disclosure, a transmission apparatus for optically transmitting a reference clock electrical signal is provided, comprising: a second sideband signal processing unit, a clock multiplexing unit, and a second sideband optical transceiver unit, wherein the clock multiplexing unit includes a first branch and a second branch, wherein the second sideband signal processing unit enables the first branch and disables the second branch when it determines that the transmission apparatus is connected to a PCIe host device, such that the clock multiplexing unit receives the reference clock electrical signal from the PCIe host device and transmits the reference clock electrical signal to the second sideband optical transceiver unit via the first branch, and then the second sideband optical transceiver unit converts the reference clock electrical signal into a reference clock optical signal and transmits it; or the second sideband signal processing unit enables the second branch and disables the first branch when it determines that the transmission apparatus is connected to a PCIe terminal device, such that the second sideband optical transceiver unit receives the reference clock optical signal and converts the reference clock optical signal into a reference clock electrical signal, and then the clock multiplexing unit transmits the reference clock electrical signal to the PCIe terminal device via the second branch.

[0024] Optionally, the clock multiplexing unit includes a clock selection unit, a first switch, and a second switch. The clock selection unit includes a first input / output terminal, an input terminal, and an output terminal. The first switch is connected between the output terminal and the second sideband optical transceiver unit, and together with the first input / output terminal and the output terminal, forms the first branch. The second switch is connected between the output terminal and the first input / output terminal, and together with the input terminal, the output terminal, and the first input / output terminal, forms the second branch. The second sideband signal processing unit, upon determining that the transmission device is connected to a PCIe host device, turns on the first switch and turns off the second switch to enable the first branch and disable the second branch, thereby enabling the first branch. The input / output terminal receives the reference clock electrical signal from the PCIe host device, and the reference clock electrical signal is transmitted sequentially through the output terminal and the first switch to the second sideband optical transceiver unit, where it is converted into a reference clock optical signal and transmitted. Alternatively, the second sideband signal processing unit, upon determining that the transmission device is connected to the PCIe terminal device, turns on the second switch and turns off the first switch to enable the second branch and disable the first branch, so that the reference clock electrical signal obtained after the second sideband optical transceiver unit converts the received reference clock optical signal is transmitted sequentially through the input terminal, the output terminal, the second switch, and the first input / output terminal to the PCIe terminal device.

[0025] Optionally, the output is also connected to a retimer for the in-band optical channel to transmit the reference clock signal to the retimer.

[0026] Optionally, the second sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to the PCIe terminal device by detecting that the level of at least one of the plurality of presence signal pins drops to a first predetermined voltage range.

[0027] Optionally, the second sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, wherein the highest voltage of the second predetermined voltage range is lower than the lowest voltage of the first predetermined voltage range.

[0028] Thus, the transmission device according to the second aspect of this disclosure realizes an optical solution for the reference clock signal by using a second sideband optical channel independent of the in-band optical channel to transmit the reference clock signal, enabling optical PCIe systems to also use the reference clock signal as a clock reference.

[0029] According to a third aspect of this disclosure, a transmission apparatus is provided for optically transmitting SMbus electrical signals, the SMbus electrical signals including a serial clock signal and a serial data signal. The transmission apparatus includes a third sideband signal processing unit and a third sideband optical transceiver unit. The third sideband signal processing unit, upon determining that the transmission apparatus is connected to a PCIe host device, acquires the serial clock signal from the PCIe host device. The third sideband optical transceiver unit is configured to connect to a third sideband optical channel independent of the in-band optical channel, and converts the serial clock signal into a serial clock optical signal and transmits it via the third sideband optical channel. Alternatively, upon determining that the transmission apparatus is connected to a PCIe host device, the third sideband signal processing unit acquires the serial clock signal from the PCIe host device. In the case of a PCIe terminal device, the third sideband optical transceiver unit receives a serial clock optical signal via the third sideband optical channel and converts the serial clock optical signal into a serial clock electrical signal. The third sideband signal processing unit sends the serial clock electrical signal to the PCIe terminal device. When the third sideband signal processing unit determines that the transmission device is connected to the PCIe host device, the third sideband signal processing unit is further configured to maintain the level of the serial clock electrical signal at a low voltage for a first delay period when the serial clock electrical signal reaches its rising edge. The first delay period ensures that when the rising edge of the serial clock electrical signal arrives, the data in the serial data electrical signal has been established for a predetermined duration.

[0030] Optionally, the side of the third sideband signal processing unit connected to the third sideband optical transceiver unit is configured with four terminals. These four terminals are respectively used to receive the serial clock signal from the third sideband optical transceiver unit, to send the serial clock signal to the third sideband optical transceiver unit, to receive the serial data signal from the third sideband optical transceiver unit, and to send the serial data signal to the third sideband optical transceiver unit. The other side of the third sideband signal processing unit, opposite to the first side, is configured with two additional terminals. These two additional terminals are respectively used to obtain the serial clock signal from the PCIe host device or to send the serial clock signal to the PCIe terminal device, to receive or send the serial data signal from the PCIe host device or from the PCIe terminal device, and the third sideband signal processing unit controls the reception and transmission of the four terminals and the two additional terminals.

[0031] Optionally, the third sideband signal processing unit includes a first processing unit for processing the serial clock signal and a second processing unit for processing the serial data signal. The first processing unit includes a second input / output terminal, a first Schmitt trigger, a first diode, a third resistor, a third switch, and a delay unit, wherein: the second input / output terminal is used to connect to a PCIe host device or a PCIe terminal device, and when connected to a PCIe host device, it is used to receive the serial clock signal from the PCIe host device, and when connected to a PCIe terminal device, it is used to output the serial clock signal to the PCIe terminal device; the input terminal of the first Schmitt trigger is connected to the second input / output terminal, and its output terminal is connected to the third sideband optical transceiver unit; the cathode of the first diode is connected to the third sideband optical transceiver unit, and its anode is connected to the first terminal of the third resistor and the input terminal of the first Schmitt trigger; the second terminal of the third resistor is connected to the power supply voltage; the third switch includes a first terminal, a second terminal, and a control terminal, and its first terminal is connected to the second input / output terminal. The second terminal of the delay device is grounded, and its control terminal is connected to the first terminal of the delay device. The second terminal of the delay device is connected to the output terminal of the first Schmitt trigger. When the delay device senses that the first Schmitt trigger has stopped triggering and has no output, it controls the third switch to turn on so that the voltage of the first input / output terminal remains low for a first delay period. The threshold voltage of the first Schmitt trigger is greater than the low-level voltage of the serial clock signal and less than the forward voltage of the first diode. The forward voltage of the first diode is lower than the logic low-level threshold of the PCIe terminal device. The second input / output terminal is one of the other two terminals used to obtain the serial clock signal from the PCIe host device or send the serial clock signal to the PCIe terminal device. The output terminal of the first Schmitt trigger is one of the four terminals used to send the serial clock signal to the third sideband optical transceiver unit. The cathode of the first diode is one of the four terminals used to receive the serial clock signal from the third sideband optical transceiver unit.

[0032] Optionally, the second processing unit includes a third input / output terminal, a second Schmitt trigger, a second diode, and a fourth resistor, wherein: the third input / output terminal receives or outputs a serial data signal; the input terminal of the second Schmitt trigger is connected to the third input / output terminal, and its output terminal is connected to the third sideband optical transceiver unit; the cathode of the second diode is connected to the third sideband optical transceiver unit, and its anode is connected to the first terminal of the fourth resistor and the input terminal of the second Schmitt trigger; the second terminal of the fourth resistor is connected to a power supply voltage; wherein the threshold voltage of the second Schmitt trigger is greater than the low-level voltage of the serial data signal and less than the forward voltage of the second diode; wherein the third input / output terminal serves as one of the other two terminals for receiving or transmitting the serial data signal from the PCIe host device or from the PCIe terminal device; the output terminal of the second Schmitt trigger serves as one of the four terminals for transmitting the serial data signal to the third sideband optical transceiver unit; and the cathode of the second diode serves as one of the four terminals for receiving the serial data signal from the third sideband optical transceiver unit.

[0033] Optionally, the third sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe terminal device by detecting that the level of the plurality of presence signal pins is low but higher than the ground level.

[0034] Optionally, the third sideband signal processing unit further includes a plurality of presence signal pins, and determines that the transmission device is connected to the PCIe host device by detecting that the level of at least one of the plurality of presence signal pins goes low to ground.

[0035] Optionally, the delay unit is integrated into the third sideband signal processing unit.

[0036] Thus, the transmission apparatus according to the third aspect of this disclosure provides a solution for the optical transmission of SMbus electrical signals, and also avoids the problem that the transmission time of the serial data electrical signal SDA may exceed the clock cycle of the serial clock electrical signal SCL due to the length of the optical cable by delaying the rising edge of the serial clock electrical signal SCL.

[0037] According to a fourth aspect of this disclosure, a transmission device is provided, comprising: a fourth transmission means for connecting to an in-band optical channel and transmitting in-band signals via the in-band transmission channel; and one or more of a first transmission means as the transmission means of the aforementioned first aspect, a second transmission means as the transmission means of the aforementioned second aspect, and a third transmission means as the transmission means of the aforementioned third aspect.

[0038] Thus, the transmission device according to the fourth aspect of this disclosure can realize the transmission of PCIe sideband signals, including reference clock signals and SMbus signals, on the sideband optical channel.

[0039] According to a fifth aspect of this disclosure, a transmission system for optically transmitting sideband signals is provided, comprising: a first transmission device, which is the transmission device as described in the fourth aspect above; a second transmission device, which is the transmission device as described in the fourth aspect above; and a set of in-band optical cables connected between the first transmission device and the second transmission device to form an in-band optical channel, wherein, when both the first transmission device and the second transmission device include the first transmission device, the transmission system further includes a first set of sideband optical cables for connecting the first transmission device and the first transmission device of the second transmission device; when both the first transmission device and the second transmission device include the second transmission device, the transmission system further includes a second set of sideband optical cables for connecting the second transmission device of the first transmission device and the second transmission device of the second transmission device; and when both the first transmission device and the second transmission device include the third transmission device, the transmission system further includes a third set of sideband optical cables for connecting the third transmission device of the first transmission device and the third transmission device of the second transmission device, wherein the first transmission device is used to connect to a PCIe host device, and the second transmission device is used to connect to a PCIe terminal device.

[0040] Thus, the transmission system according to the fifth aspect of this disclosure can realize the transmission of in-band signals on the in-band optical channel and the transmission of PCIe sideband signals, including reference clock electrical signals and SMbus electrical signals, on the sideband optical channel independent of the in-band optical channel, providing a comprehensive optical solution for PCIe systems. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some exemplary embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0042] Figure 1 shows a schematic structure of a transmission system according to an embodiment of the present disclosure;

[0043] Figure 2 shows a schematic structure of a first transmission device according to an embodiment of the present disclosure;

[0044] Figure 3 illustrates an example frame format of a first transmission sideband signal according to an embodiment of the present disclosure;

[0045] Figure 4 shows a schematic structure of a first transmission device according to another embodiment of the present disclosure;

[0046] Figure 5 illustrates the principle of receiver detection according to an embodiment of the present disclosure;

[0047] Figure 6 shows a schematic structure of a second transmission device according to an embodiment of the present disclosure;

[0048] Figure 7 shows a schematic structure of a clock multiplexing unit according to an embodiment of the present disclosure;

[0049] Figure 8 shows a schematic structure of a clock multiplexing unit according to another embodiment of the present disclosure;

[0050] Figure 9 illustrates a schematic structure of a third transmission device according to an embodiment of the present disclosure; and

[0051] Figure 10 shows the effect of delaying the rising edge of the serial clock signal SCL by a delayer according to an embodiment of the present disclosure. Detailed Implementation

[0052] The present disclosure will now be described in detail with reference to exemplary embodiments thereof. However, the present disclosure is not limited to the embodiments described herein, which may be implemented in many different forms. The described embodiments are provided only to make the present disclosure thorough and complete, and to fully convey the concept of the present disclosure to those skilled in the art. Features of the various embodiments described may be combined with or substituted for each other, unless expressly excluded or should be excluded based on the context.

[0053] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0054] The PCIe end devices mentioned in this disclosure include any device such as a graphics card, network card, solid-state drive, etc., that is connected to the PCIe bus for operation. The PCIe host devices mentioned in this disclosure include any device that is connected to the PCIe bus to communicate with the PCIe end devices and to control and manage the operation of the PCIe end devices.

[0055] As mentioned earlier, there are still various challenges in transmitting PCIe sideband signals, which are originally transmitted on sideband signal lines constructed by cables, over optical channels constructed by optical fibers. For ease of explanation, some possible transmission methods of PCIe sideband signals in electrical solutions and current optical solutions are briefly described below.

[0056] In electrical solutions, when a PCIe terminal device is inserted into a PCIe slot, it sends a presence signal (PRSNT) to the PCIe host device to indicate its presence and readiness for communication. Upon receiving the presence signal and confirming the correct connection, the PCIe host device configures and manages the terminal device accordingly, including allocating resources, initializing the device, and starting relevant drivers. Current optical solutions attempt to determine the insertion of a PCIe terminal device into the corresponding PCIe slot by detecting the presence of optical signals in the in-band optical path. However, this method is unreliable because optical signals in the in-band optical path can be lost not only when the PCIe terminal device is removed from the PCIe slot but also due to other factors.

[0057] In electrical solutions, PCIe host devices sometimes need to send a reset signal PERST to PCIe end devices to restore them to their initial state. Upon receiving the reset signal, the PCIe end device performs a reset operation, including initialization and restoration to default settings. The PERST reset signal plays a crucial role in system startup, fault recovery, and software control; triggering the re-initialization of the PCIe end device ensures system stability and reliability. In optical solutions, attempts are made to transmit the PERST reset signal via the in-band optical channel, or to infer the need for a reset operation based on the absence of optical signals in the in-band optical channel without transmitting the PERST reset signal. However, both methods either interfere with data transmission in the in-band optical channel or may cause the PCIe end device reset to be out of sync with the physical layer reset.

[0058] In electrical solutions, PCIe host devices need to transmit a reference clock signal, REFCLK, generated by a crystal oscillator on the motherboard, to PCIe end devices as their clock reference. Differential cable pairs are used to transmit REFCLK to reduce crosstalk and noise. In optical solutions, the transmission of the REFCLK reference clock signal is not currently implemented, and attempts are being made to use independent clock modes (i.e., SRIS mode and SRNS mode) as alternatives. However, SRIS mode suffers from bandwidth loss, and SRNS mode lacks a spread spectrum clock. Therefore, a REFCLK reference clock signal that supports a spread spectrum clock without bandwidth loss remains ideal. Furthermore, since the transmission of the REFCLK reference clock signal requires very low jitter, it is desirable to transmit REFCLK via a low-speed sideband optical channel.

[0059] In electrical solutions, SMbus electrical signals need to be transmitted between PCIe host devices and PCIe end devices, and differential cable pairs can be used for this transmission to reduce signal crosstalk and noise. The SMbus electrical signal is typically used to connect devices such as temperature sensors, fan controllers, and power management chips to manage and control these devices, and it includes a serial data signal (SDA) and a serial clock signal (SCL). In optical solutions, SMbus signal transmission is not currently implemented.

[0060] Furthermore, in electrical solutions, link training is required between the PCIe host device and the PCIe end device, including receiver detection (Rx Detect) to determine whether each channel in the in-band has formed a path. This is achieved by emitting a common-mode voltage pulse at one end of the channel and sensing the current attenuation feedback of the pulse. In optical solutions, since current attenuation feedback cannot be sensed on the optical fiber, there is currently no implementation of receiver detection.

[0061] Furthermore, in electrical solutions, cable transmission is bidirectional. In contrast, in optical solutions, the optical channel constructed by the optical cable and optical transceiver unit is unidirectional. Therefore, when considering solutions for optically transmitting PCIe sideband signals, it is also necessary to consider how to determine the directionality of the optical channel.

[0062] In summary, there is currently no optical solution capable of transmitting PCIe sideband signals such as presence signals, reset signals, reference clock signals, and SMbus signals using low-speed sideband optical channels, nor is there an optical solution that supports receiver detection for in-band optical channels. Furthermore, existing optical solutions attempt to avoid transmitting these PCIe sideband signals altogether.

[0063] In view of this, the present disclosure provides a transmission apparatus, transmission device, and transmission system capable of realizing the sideband optical transmission of the aforementioned PCIe sideband signals. Furthermore, the transmission apparatus, transmission device, and transmission system according to embodiments of the present disclosure are suitable for various versions of the PCIe protocol and other related protocols such as protocols derived from these protocols, protocols incorporating these protocols, new protocols formed by reusing these protocols, such as the CXL (Compute Express Link) protocol.

[0064] The embodiments of this disclosure are described below.

[0065] Figure 1 shows a schematic structure of a transmission system according to an embodiment of the present disclosure.

[0066] Referring to FIG1, the transmission system 1 according to an embodiment of the present disclosure includes a transmission device 100 and a transmission device 100', and an optical cable (shown as a thick solid line in the figure) connecting the two transmission devices 100 and 100'. When a user uses the transmission system 1, the optical cable is connected between the transmission device 100 and the transmission device 100', and either the transmission device 100 or the transmission device 100' is connected to a PCIe host device, while the other is connected to a PCIe terminal device.

[0067] Depending on the functions to be implemented, transmission device 100 may include one or more of the first transmission device 10, the second transmission device 20, and the third transmission device 30, as well as a fourth transmission device 40. Transmission device 100' may include one or more of the first transmission device 10', the second transmission device 20', and the third transmission device 30', as well as the fourth transmission device 40'. For ease of illustration, in FIG1, transmission device 100 is shown as including all of the first transmission device 10, the second transmission device 20, and the third transmission device 30, as well as the fourth transmission device 40, and transmission device 100' is also shown as including all of the first transmission device 10', the second transmission device 20', and the third transmission device 30', as well as the fourth transmission device 40'.

[0068] The first transmission device 10 functions to perform optical transmission of PCIe sideband signals, including presence and reset signals, and optionally also to perform receiver detection for in-band optical channels. The second transmission device 20 functions to perform optical transmission of a reference clock electrical signal. The third transmission device 30 functions to perform optical transmission of an SMbus electrical signal. The fourth transmission device functions to perform optical transmission of in-band signals (i.e., PCIe data). The first transmission device 10', second transmission device 20', third transmission device 30', and fourth transmission device 40' in transmission device 100' have similar structures to the first transmission device 10, second transmission device 20, third transmission device 30, and fourth transmission device 40 in transmission device 10.

[0069] Accordingly, the optical cable connecting transmission device 100 and transmission device 100' may include a set of in-band optical cables MB1 connecting the fourth transmission device 40 and the fourth transmission device 40' to form an in-band optical channel. When transmission device 100 includes a first transmission device 10, transmission system 1 correspondingly includes a first set of sideband optical cables SB1 for connecting the first transmission device 10 and the first transmission device 10'. When transmission device 100 includes a second transmission device 20, transmission system 1 correspondingly includes a second set of sideband optical cables SB2 for connecting the second transmission device 20 and the second transmission device 20'. When transmission device 100 includes a first transmission device 30, transmission system 1 further includes a third set of sideband optical cables SB3 for connecting the third transmission device 30 and the third transmission device 30'. The first to fourth transmission devices 10 to 40 and the first to fourth transmission devices 10' to 40' all include optical transceiver units to connect the corresponding optical cables.

[0070] For simplicity, Figure 1 shows each group of optical cables as consisting of only two cables to represent the cables used in the two transmission directions. For example, the first group of sideband cables SB1 is shown as including sideband cable SB1-1 for the first transmission direction and sideband cable SB1-2 for the second transmission direction. However, it should be understood that the number of optical cables included in each group is not limited to this. Furthermore, when transmission device 100 is connected to a PCIe host device and transmission device 100' is connected to a PCIe terminal device, the first transmission direction refers to the downstream direction from the PCIe host device to the PCIe terminal device, and the second transmission direction refers to the upstream direction from the PCIe terminal device to the PCIe host device.

[0071] The first transmission device 10 to the third transmission device 30 are described below. Since the first transmission device 10' to the third transmission device 30' have the same structure as the first transmission device 10 to the third transmission device 30, for the sake of simplicity, some descriptions of them are omitted below.

[0072] It should be noted that while the first sideband signal processing unit 120, the second sideband signal processing unit 220, and the third sideband signal processing unit 320 are shown as separate in Figure 1, this does not mean that they are physically separated from each other. Rather, it is for functional distinction and ease of description. It should be understood that any two or all of the first sideband signal processing unit 120, the second sideband signal processing unit 220, and the third sideband signal processing unit 320 can physically belong to the same processing unit.

[0073] First transmission device 10

[0074] Figure 2 shows a schematic structure of a first transmission device according to an embodiment of the present disclosure.

[0075] Specifically, Figure 2 shows a first transmission device 10 and a first transmission device 10', and a first set of sideband optical cables SB1 connected between them.

[0076] Referring to Figure 2, the first transmission device 10 includes a first sideband optical transceiver unit 110 and a first sideband signal processing unit 120. The first sideband optical transceiver unit 110 includes an electro-optic converter 110-1 for electro-optic conversion and an opto-optic converter 110-2 for opto-optic conversion. To avoid complexity and as this is easily understood by those skilled in the art, these two will be collectively referred to as the first sideband optical transceiver unit 110 in the following text.

[0077] The first sideband signal processing unit 120 is used to acquire a first initial sideband electrical signal and convert the first initial sideband electrical signal into a first transmission sideband electrical signal. The first sideband optical transceiver unit 110 is used to connect to a first sideband optical channel independent of the in-band optical channel and convert the first transmission sideband electrical signal into a first sideband transmission optical signal, and transmit the first transmission sideband optical signal via the first sideband optical channel. And / or, the first sideband signal optical transceiver unit 110 is used to connect to a first sideband optical channel independent of the in-band optical channel and receive a second transmission sideband optical signal via the first sideband optical channel and convert the second transmission sideband optical signal into a second transmission sideband electrical signal. The first sideband signal processing unit is used to restore the received second transmission sideband electrical signal into a second initial sideband electrical signal.

[0078] For example, when the first transmission device 10 is connected to a PCIe terminal device, the first sideband signal processing unit 120 can be used to acquire the initial presence signal generated by the PCIe terminal device and convert the initial presence signal into a presence signal with a specific format that can be transmitted via the first sideband optical channel after electro-optical conversion by the first sideband optical transceiver unit 110. The first sideband signal processing unit 120 can also be used to restore the reset signal with a specific format received by the first sideband optical transceiver unit 110 from the PCIe host device and photoelectrically converted back to the initial reset signal. The first sideband signal processing unit 120 can also be used to acquire the Internet probe PING message generated by the PCIe terminal device and convert it into a PING message with a specific format that can be transmitted via the first sideband optical channel after electro-optical conversion by the first sideband optical transceiver unit 110, and can also be used to restore the PING message with a specific format received by the first sideband optical transceiver unit 110 from the PCIe host device and photoelectrically converted back to the initial PING message.

[0079] For example, when the first transmission device 10 is connected to the PCIe host device, the first sideband signal processing unit 120 can be used to acquire the initial reset signal generated by the PCIe host device and convert the initial reset signal into a reset signal with a specific format that can be transmitted via the first sideband optical channel after electro-optical conversion by the first sideband optical transceiver unit 110. The first sideband signal processing unit 120 can also be used to restore the presence signal with a specific format that has been received by the first sideband optical transceiver unit 110 from the PCIe terminal device and photoelectrically converted back to the initial presence signal. The first sideband signal processing unit 120 can also be used to acquire the Internet detector PING message generated by the PCIe host device and convert it into a PING message with a specific format that can be transmitted via the first sideband optical channel after electro-optical conversion by the first sideband optical transceiver unit 110, and can also be used to restore the PING message with a specific format that has been received by the first sideband optical transceiver unit 110 from the PCIe terminal device and photoelectrically converted back to the initial PING message.

[0080] In other words, for bidirectional PCIe sideband signals transmitted between PCIe host devices and PCIe terminal devices, the first transmission device 10 uses both a transmitting channel (the channel formed by the first sideband signal processing unit 120 and the electro-optical converter 110-1 in Figure 1) and a receiving channel (the channel formed by the first sideband signal processing unit 120 and the photoelectric converter 110-2 in Figure 1). For PCIe sideband signals that can only be transmitted from the PCIe host device to the PCIe terminal device, the first transmission device 10 uses the transmitting channel when connected to the PCIe host device and the receiving channel when connected to the PCIe terminal device. Similarly, for PCIe sideband signals that can only be transmitted from the PCIe terminal device to the PCIe host device, the first transmission device 10 uses the transmitting channel when connected to the PCIe terminal device and the receiving channel when connected to the PCIe host device.

[0081] Furthermore, the first sideband signal processing unit 120 can control the first sideband optical transceiver unit 110 to send the first transmission sideband signal at predetermined time intervals until an acknowledgment message for the first transmission sideband signal is received, or to send the first transmission sideband signal a predetermined number of times. For example, for an presence signal, the first transmission device 10 can send it once per second until an acknowledgment message for the presence signal is received, or send the presence signal three times without using an acknowledgment message.

[0082] Thus, the first transmission device 10 according to the embodiments of this disclosure realizes the optical transmission of PCIe sideband signals, and uses a first low-speed sideband optical channel independent of the high-speed in-band optical channel to transmit the PCIe sideband signals, resulting in low power consumption and high reliability.

[0083] Figure 3 illustrates an example frame format of a first transmission sideband signal and a second transmission sideband signal according to an embodiment of the present disclosure.

[0084] In one example, the conversion of the first initial sideband signal into a first transmission sideband signal by the first sideband signal processing unit 120 or the first sideband signal processing unit 120' can be performed based on the Universal Asynchronous Receiver / Transmitter (UART) protocol. The first initial sideband electrical signal is converted into a UART format, and the converted signal can serve as the first transmission sideband electrical signal. This first transmission sideband electrical signal is then converted by the first optical sideband transceiver unit into a first transmission sideband optical signal in UART format, in the form of an optical signal. However, this disclosure is not limited thereto. It should be understood that in other examples, the conversion can also be performed based on other protocols, as long as the converted optical signal is suitable for transmission on the first sideband optical channel SB1.

[0085] Referring to Figure 3, the example frame format is UART format, which includes start bit, data bits, parity bit, and stop bit. The data bits include optical bits 0 to 7, OP[0] to OP[7], which can be 0 or 1 respectively, depending on the encoding of the PCIe sideband signal to be transmitted. During the reception of the UART frame, the receiver removes the start bit and stop bit from the message frame, performs parity checking, and converts the data bytes from serial to parallel.

[0086] Table 1 shows some exemplary encodings of the first transmission sideband optical signals. For example, the presence signal PRSNT in optical signal form is encoded such that only the 0th to 3rd optical bits are filled with 0010 while the 4th to 7th optical bits are not used, and the acknowledgment signal PRSNT_ack in optical signal form for the presence signal is encoded such that the 0th to 3rd optical bits are filled with 0000 and the 4th to 7th optical bits are filled with 0011.

[0087] Table 1

[0088] Referring back to Figure 2, for ease of explanation, Figure 2 shows an example where the first transmission device 10 is connected to a PCIe host device and the first transmission device 10' is connected to a PCIe terminal device.

[0089] As previously described, after a PCIe terminal device is inserted into a PCIe slot, it sends an presence signal to the PCIe host device to indicate its presence and readiness to communicate with the PCIe host device. Referring to Figure 2, after the PCIe terminal device is inserted into the PCIe slot, the first sideband signal processing unit 120' can determine that the first transmission device 10' is connected to the PCIe terminal device. In this case, the first sideband signal processing unit 120' obtains the initial presence signal generated by the PCIe terminal device and converts it into a presence signal in, for example, UART format. The first sideband optical transceiver unit 110'-1 converts this UART format presence signal into a UART format presence signal in optical signal form, and sends this optical UART format presence signal to the first sideband optical transceiver unit 110-2 of the first transmission device 10 via the first sideband optical channel SB1-2. The first sideband optical transceiver unit 110-2 converts the received UART format presence signal in the form of an optical signal into a UART format presence signal in the form of an electrical signal. The first sideband signal processing unit 120 restores the UART format presence signal in the form of an electrical signal back to the initial presence signal, and then sends the restored initial presence signal to the PCIe host device.

[0090] As mentioned earlier, PCIe host devices sometimes need to send a reset signal PERST to PCIe terminal devices to reset the PCIe terminal devices. Referring to Figure 2, after the first transmission device 10 is connected to the PCIe host device, the first sideband signal processing unit 120 can determine that the first transmission device 10 is connected to the PCIe host device. In this case, the first sideband signal processing unit 120 obtains the initial reset signal generated by the PCIe host device and converts the initial reset signal into a reset signal in, for example, UART format. The first sideband optical transceiver unit 110-1 performs electro-optical conversion on the UART format reset signal and sends it to the first sideband optical transceiver unit 110'-2 of the first transmission device 10' via the first sideband optical channel SB1-1. The first sideband optical transceiver unit 110'-2 performs photoelectric conversion on the received UART format reset signal in the form of an optical signal to obtain a UART format reset signal in the form of an electrical signal. The first sideband signal processing unit 120' restores the UART format reset signal in the form of an electrical signal to the initial reset signal, and then sends the restored initial reset signal to the PCIe terminal device.

[0091] Thus, the transmission system 1 according to this disclosure, by using a transmission device including the first transmission device 10, enables the transmission of PCIe sideband signals, including presence signals and reset signals, between a PCIe host device and a PCIe terminal device via a low-speed sideband optical channel. As mentioned above, the first transmission device 10 needs to determine whether it is connected to a PCIe host device or a PCIe terminal device before determining whether it is a sender or receiver of presence signals, reset signals, etc. Referring to FIG2, the first sideband signal processing unit 120 may include a plurality of presence signal pins, and determines whether it is connected to a PCIe host device or a PCIe terminal device through these plurality of presence signal pins. FIG2 uses two presence signal pins, PRSNT#1 and PRSNT#2, as an example. The first sideband signal processing unit 120 can determine that the first transmission device 10 is connected to a PCIe terminal device by detecting that the level of the plurality of presence signal pins drops to a first predetermined voltage range. Alternatively, the first sideband signal processing unit 120 can determine that the first transmission device 10 is connected to a PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, where the highest voltage of the second predetermined voltage range is lower than the lowest voltage of the first predetermined voltage range. In one example, the first sideband signal processing unit 120 can determine that the first transmission device 10 is connected to a PCIe terminal device by detecting that the level of the plurality of presence signal pins drops to a level higher than ground, or by detecting that the level of the plurality of presence signal pins drops to a level ground. The principle of this detection method is as follows.

[0092] As shown in Figure 2, when the first transmission device 10' is not yet connected to the PCIe terminal device, the presence signal pins PRSNT#1' and PRSNT#2' of the first sideband signal processing unit 120' are left floating. When the first transmission device 10' is connected to the PCIe terminal device, the PCIe terminal device shorts both presence signal pins PRSNT#1 and PRSNT#2, causing the voltage levels of the presence signal pins PRSNT#1' and PRSNT#2' to decrease to a first predetermined voltage range relative to when they are floating (e.g., decrease but remain above ground). Therefore, the first sideband signal processing unit 120' can determine that the first transmission device 10' is connected to the PCIe terminal device based on the fact that both presence signal pins PRSNT#1 and PRSNT#2' have decreased to the first predetermined voltage range.

[0093] When the first transmission device 10 is not yet connected to the PCIe host device, the presence signal pins PRSNT#1 and PRSNT#2 of the first sideband signal processing unit 120 are left floating. When the first transmission device 10 is connected to the PCIe host device, the presence signal pin PRSNT#1 is grounded, causing its level to drop to a second predetermined voltage range, the highest voltage of which is lower than the lowest voltage of the first predetermined voltage range (e.g., dropping to ground), while the presence signal pin PRSNT#2 is connected to a high level. This can be achieved by configuring appropriate circuitry within the first sideband signal processing unit 120, which is not limited in this disclosure. Therefore, the first sideband signal processing unit 120 determines that the first transmission device 10 is connected to the PCIe host device based on sensing that the level of the presence signal pin PRSNT#2 has dropped to the second predetermined voltage range.

[0094] Therefore, the first transmission device 10 according to the embodiments of this disclosure can also determine the directionality of the optical channel, so that when the user uses the transmission system 1, the first transmission device 10 and the first transmission device 10' used upstream and downstream can have the same structure, which can reduce the design complexity of the first transmission device, and there is no need to worry about reversing the connection when connecting the first transmission device 10 and the first transmission device 10', making it convenient to use.

[0095] Furthermore, the first sideband signal processing unit 120 and the first sideband signal processing unit 120' can generate Ping messages after the first transmission device 10 and the first transmission device 10' are powered on, respectively, and control the first sideband optical transceiver unit 110 and the first sideband optical transceiver unit 110' to perform electro-optical conversion on the Ping messages and then send the Ping messages through the first sideband optical channels SB1-1 and SB1-2. The Ping message can be used to detect whether the corresponding first sideband optical channels SB1-1 and SB1-2 are connected. The rule for sending Ping messages can be to send them continuously at predetermined time intervals or to send them in response to a certain triggering event (power-on, reset).

[0096] Variation of the first transmission device 10

[0097] Figure 4 shows a schematic structure of a first transmission device 10 according to another embodiment of the present disclosure.

[0098] Referring to Figure 4, the first transmission device 10 may further include an in-band optical transceiver unit 130 and a receiver detection circuit 140. The in-band optical transceiver unit 130 is used to connect to each of the in-band optical channels MB1-1 and MB1-2. The receiver detection circuit 140 is used to perform receiver detection for each of the in-band optical channels MB to generate an initial receiver result electrical signal indicating whether the receiver detection for that optical channel was successful or failed.

[0099] The first sideband signal processing unit 120 also converts the initial receiver result electrical signal for each optical channel into a UART format receiver result electrical signal. The first sideband optical transceiver unit 110 also converts the UART format receiver result electrical signal into a UART format receiver result optical signal and transmits the UART format receiver result optical signal via the first sideband optical channel SB1.

[0100] In one example, the in-band signal channel may include multiple optical channels MB1 to MBN (N being an integer greater than or equal to 2) and corresponding multiple electrical channels. The receiver detection circuit 140 may include first to Nth receiver detection sub-circuits. Each of the first to Nth receiver detection sub-circuits is used to perform receiver detection for a corresponding optical channel among the multiple optical channels MB1 to MBN. Furthermore, each receiver detection sub-circuit includes an RC circuit, and generates a receiver detection result signal indicating successful receiver detection for its corresponding optical channel based on the time constant of the RC circuit responding to a common-mode voltage step being greater than a predetermined duration threshold, or generates a receiver detection result electrical signal indicating failed receiver detection for its corresponding optical channel based on the time constant being less than the predetermined duration threshold.

[0101] Therefore, the first transmission device 10 according to the embodiments of the present disclosure can realize receiver detection of each optical channel in the in-band optical channel and transmit the receiver detection result via the first sideband optical channel.

[0102] For simplicity, Figure 4 shows the in-band optical channel as including only one optical channel MB1, and correspondingly, the in-band optical transceiver unit 130 is shown as including only an electro-optical converter 130-1 and an opto-electric converter 130-2 for connecting the optical channel MB1, and the receiver detection circuit 140 is shown as including only a first receiver detection sub-circuit for receiver detection of the optical channel MB1. However, it should be understood that the in-band optical transceiver unit 130 may also include electro-optical converters and opto-electric converters for connecting one or more other optical channels within the in-band optical channel, and the receiver detection circuit 140 may also include corresponding one or more receiver detection sub-circuits for performing receiver detection on one or more other optical channels within the in-band optical channel. Furthermore, to avoid complexity and for ease of understanding by those skilled in the art, the electro-optical converter 130-1 or opto-electric converter 130-2 will be referred to as the in-band optical transceiver unit 130 below.

[0103] As shown in Figure 4, the first optical channel MB1 in the in-band optical channel includes a first in-band optical cable MB1-1 for the first transmission direction and a second in-band optical cable MB1-2 for the second transmission direction.

[0104] The first receiving and detection sub-circuit includes a first differential cable pair 141 connected to the electro-optical converter 130-1 in the in-band optical transceiver unit 130, a second differential cable pair 142 connected to the photoelectric converter 130-2 in the in-band optical transceiver unit 130, two RC circuits coupled to the two cables of the first differential cable pair 141, two second resistors R2 coupled to the two cables of the second differential cable pair 142, and a detection unit 143. Each of the two RC circuits includes a first capacitor C1 and a first resistor R1.

[0105] The detection unit 143 is used to drive a common-mode voltage step on the first differential cable pair 141, determine the time constant of the two RC circuits responding to the common-mode voltage step, and generate an initial receiver detection result electrical signal indicating that the receiver detection of the corresponding optical channel is successful based on the time constant being greater than a predetermined duration threshold, or generate an initial receiver detection result electrical signal indicating that the receiver detection of the corresponding optical channel is unsuccessful based on the time constant being less than the predetermined duration threshold.

[0106] Specifically, the detection unit 143 may include a common-mode voltage driving subunit 1431, a recording subunit 1432, and a determination unit 1433 (not further subdivided in the figure for simplicity), and performs receiver detection for the first optical channel MB1 through the following process. First, the common-mode voltage driving subunit 1431 drives a common-mode low voltage on the first differential cable pair 141 to pull down the voltage on the first capacitor C1 in the two sub-RC circuits to a predetermined low voltage value V. L And it is determined that the voltage across the first capacitor C1 has been pulled down to the predetermined low voltage value V. L Subsequently, the common-mode voltage driving subunit 1431 continues to drive a common-mode high voltage on the first differential cable pair 141. Then, the recording subunit 1432 records the period from the moment the common-mode voltage driving subunit 1431 drives the common-mode high voltage until the voltage on the first capacitor C1 in the two sub-RC circuits reaches the predetermined high voltage value V. H The elapsed time Δt is the time constant. Subsequently, the determination unit 1433 determines that the receiver detection of the first optical channel MB1-1 is successful based on the time Δt being greater than the predetermined time threshold T, or determines that the receiver detection of the first optical channel MB1-1 is unsuccessful based on the time Δt being less than the predetermined time threshold T.

[0107] The detection unit 143 may be designed to trigger receiver detection for the first in-band optical channel MB1, for example, autonomously periodically or in response to receiving a command from an external source (e.g., from the first sideband signal processing unit 120) to perform receiver detection on the first optical channel MB1.

[0108] The principle of receiver detection implemented by the first transmission device 10 will be explained below with reference to Figures 4 and 5.

[0109] Figure 5 illustrates the principle of receiver detection according to an embodiment of the present disclosure.

[0110] Referring to Figure 5, at time t0, the voltage on the first capacitor C1 is pulled down to a predetermined low voltage value V due to the common-mode low voltage driven by the detection unit 143 on the first differential cable pair 141. L At time t1, the detection unit 143 drives a common-mode high voltage on the first differential cable pair 151. If at time t1, the second resistor R in the first transmission device 10'... 2’ If no path is formed with the in-band cable MB1-1, the first capacitor C1 is rapidly charged, causing it to reach the predetermined high voltage value V at time t2. H (The charging trajectory is shown as the solid line in the figure). Conversely, if at time t1, the second resistor R in the transmission device 10'... 2’ Since a circuit has been formed with the in-band cable MB1-1, the first capacitor C1 is slowly charged until time t3 before reaching the predetermined high voltage value V. H (The charging trajectory is shown by the dashed line in the figure). Based on this principle, the predetermined duration T can be set, for example, T = t2 - t1. As an example, assume that the first capacitor C1 reaches the predetermined high voltage value V at time tr. H The time constant recorded by the recording subunit 1432 is Δt = tr - t1. Then, the determination unit 1433 generates an initial receiver detection result electrical signal RXDET_ based on Δt > T, indicating successful receiver detection of the in-band cable MB1-1. MB1-1 .

[0111] Similarly, the detection unit 143' in the first transmission device 10' also performs a similar operation to the detection unit 143 to determine whether the receiver detection of the in-band optical cable MB1-2 is successful or unsuccessful, and generates an initial receiver detection result electrical signal RXDET_ indicating whether the receiver detection of the in-band optical cable MB1-2 is successful or unsuccessful. MB1-2 .

[0112] Thus, the first transmission device 10 according to the present disclosure can realize PCIe receiver detection by measuring the time constant of the RC circuit arranged on the differential cable pair in response to the common-mode voltage step, providing support for the link training of the in-band optical channel of the PCIe optical system.

[0113] In the example shown in Figure 4, detection unit 143 and detection unit 143' are components independent of first sideband signal processing unit 120 and first sideband signal processing unit 120', respectively. In this example, detection unit 143 processes the generated initial receiver detection result electrical signal RXDET_ MB1-1 The signal is sent to the first sideband signal processing unit 120, and the detection unit 143' generates the initial receiver detection result electrical signal RXDET_. MB1-2 The signal is sent to the first sideband signal processing unit 120'. Furthermore, in this example, the initial receiver detection result electrical signal RXDET_ MB1-1 The optical signal, converted into a receiver detection result optical signal by the first sideband optical transceiver unit 110, is transmitted to the first sideband optical transceiver unit 110' via the sideband optical cable SB1-1, and then sent to the PCIe terminal device by the first sideband signal processing unit 120'. The initial receiver detection result electrical signal is RXDET_. MB1-2 The optical signal, converted into a receiver detection result optical signal by the first sideband optical transceiver unit 110', is transmitted to the first sideband optical transceiver unit 110 via the sideband optical cable SB1-2, and then sent to the PCIe host device by the first sideband signal processing unit 120. In this example, the detection unit 143 and the detection unit 143' can be implemented using a PCIe ReDriver chip.

[0114] In another example, detection unit 143 and detection unit 143' can be integrated into the first sideband signal processing unit 120 and the first sideband signal processing unit 120', respectively. In this example, the initial receiver detection result electrical signal RXDET_ MB1-1 The signal is generated by the first sideband signal processing unit 120, then transmitted by the first sideband optical transceiver unit 110' via the sideband optical cable SB1-1, and subsequently transmitted by the first sideband signal processing unit 120' to the PCIe terminal device. The initial receiver detection result electrical signal RXDET_ MB1-2 The signal is generated by the first sideband signal processing unit 120', then transmitted by the first sideband optical transceiver unit 110' via the sideband optical cable SB1-2, and then transmitted by the first sideband signal processing unit 120 to the PCIe host device.

[0115] Thus, the first receiving device 10 according to the embodiments of this disclosure further transmits the receiver detection results through a low-speed sideband optical channel, providing communication assurance for the receiver detection process.

[0116] In most cases, the number of sideband optical cables in the first sideband optical channel SB1 may be less than the number of in-band optical cables in the in-band optical channel. The first sideband signal processing unit 120 can transmit multiple initial receiver detection result electrical signals for all optical channels in the in-band optical channel in groups or individually. For example, in one example, assuming that the in-band optical channel includes a total of 16 optical channels, the first sideband signal processing unit 120 will receive or generate 16 initial receiver result electrical signals. The first sideband signal processing unit 120 can multiplex and encode every four receiver detection result electrical signals into a composite receiver detection result electrical signal with UART format according to the UART frame format shown in FIG3 for transmission. For example, the first sideband signal processing unit 120 can transmit the initial receiver detection result electrical signals RXDET_ for the four in-band optical cables in the first to fourth optical channels for the first transmission direction. MB1-1 To RXDET_ MB4-1 The receiver detection result electrical signal RXDETa, multiplexed and encoded into a first multiplexed UART format, is transmitted through the first sideband optical channel SB1-1 after electro-optical conversion by the first sideband optical transceiver unit. As shown in Table 1 above, if RXDETa is coded as 0100, the PCIe terminal device receiving RXDETa will interpret it as a receiver detection result of failure, success, failure, failure for the four in-band optical cables in the first to fourth optical channels for the first transmission direction. Similarly, exemplarily, the initial receiver detection result electrical signals corresponding to the four in-band optical cables in the first transmission direction in the 5th to 8th optical channels are multiplexed, encoded, and converted into RXDETb in Table 1; the receiver detection result electrical signals corresponding to the four in-band optical cables in the first transmission direction in the 9th to 12th optical channels are multiplexed, encoded, and converted into RXDETc in Table 1; and the receiver detection result electrical signals corresponding to the four in-band optical cables in the first transmission direction in the 13th to 16th optical channels are multiplexed, encoded, and converted into RXDETd in Table 1.

[0117] Thus, even if the number of optical cables in the first sideband optical channel is less than the number of optical cables in the in-band optical channel, the first transmission device 10 can still promptly transmit the detection results to the receiver of the in-band optical channel.

[0118] Second transmission device 20

[0119] Figure 6 shows a schematic structure of a second transmission device according to an embodiment of the present disclosure.

[0120] Specifically, Figure 6 shows a second transmission device 20 and a second transmission device 20' with the same structure, and a second set of sideband optical cables SB2 connected between them. Referring to Figure 6, the second transmission device 20 includes a clock multiplexing unit 210, a second sideband signal processing unit 220, and a second sideband optical transceiver unit 230. The second sideband optical transceiver unit 230 includes an electro-optic converter 230-1 and a photoelectric converter 230-2. To avoid complexity and for ease of understanding by those skilled in the art, the electro-optic converter 230-1 or the photoelectric converter 230-2 will be referred to as the in-band optical transceiver unit 230 below. The second transmission device 20' has a similar structure to the second transmission device 20; only the second transmission device 20 will be described in detail below.

[0121] The clock multiplexing unit 210 includes a first branch BR1 and a second branch BR2. When the second sideband signal processing unit 210 determines that the second transmission device 20 is connected to the PCIe host device, it enables the first branch BR1 and disables the second branch BR2. This allows the clock multiplexing unit 210 to receive a reference clock electrical signal REFCLK from the PCIe host device and transmit the REFCLK via the first branch BR1 to the second sideband optical transceiver unit 220. The second sideband optical transceiver unit 220 then converts the REFCLK into a reference clock optical signal and transmits it. Alternatively, when the second transmission device 20 is connected to the PCIe terminal device, the second sideband signal processing unit 210 enables the second branch BR2 and disables the first branch BR1. This allows the second sideband optical transceiver unit 210 to receive the reference clock optical signal and convert it into a reference clock electrical signal REFCLK. The clock multiplexing unit 210 then transmits the REFCLK via the second branch BR2 to the PCIe terminal device.

[0122] For ease of explanation, Figure 6 uses the example of the second transmission device 20 being connected to the PCIe host device and the second transmission device 20' being connected to the PCIe terminal device.

[0123] As shown in Figure 6, when the second transmission device 20 is connected to the PCIe host device, the second sideband signal processing unit 220 enables the first tributary BR1 and disables the second tributary BR2. The clock multiplexing unit 210 receives the reference clock electrical signal REFCLK from the PCIe host device and transmits it to the second sideband optical transceiver unit 230 via the first tributary BR1. The second optical transceiver unit 230 performs electro-optical conversion on the reference clock electrical signal REFCLK and transmits the reference clock optical signal to the second sideband optical transceiver unit 230' of the second transmission device 20' via the sideband optical cable SB2-1 for the first transmission direction of the second sideband optical channel.

[0124] The clock multiplexing unit 210' of the second transmission device 20' also includes a first branch BR1' and a second branch BR2'. When the second transmission device 20' is connected to the PCIe terminal device, the second sideband signal processing unit 220' enables the second branch BR2' and disables the first branch BR1'. The second sideband optical transceiver unit 230' receives the reference clock optical signal and converts it into a reference clock electrical signal REFCLK. The second sideband signal processing unit 220' sends the reference clock electrical signal REFCLK to the PCIe terminal device via the second branch BR2'.

[0125] Figure 7 shows a schematic structure of a clock multiplexing unit according to an embodiment of the present disclosure.

[0126] Specifically, Figure 7 shows clock multiplexing unit 220 and clock multiplexing unit 220' with the same structure.

[0127] Referring to Figure 7, the clock multiplexing unit 210 includes a clock selection unit 211, a first switch S1, and a second switch S2. The clock selection unit 211 includes a first input / output terminal I / O1, an input terminal IN, and an output terminal OUT. The first input / output terminal I / O1 is used for input when connected to a PCIe host device and for output when connected to a PCIe terminal device. The input terminal IN is used only for input, and the output terminal OUT is used only for output. The first switch S1 is connected between the output terminal OUT of the clock selection unit 211 and the second sideband optical transceiver unit 230, and together with the first input / output terminal I / O1 and the output terminal OUT, forms a first branch BR1. The second switch S2 is connected between the output terminal OUT of the clock selection unit 211 and the first input / output terminal I / O1, and together with the input terminal IN, the output terminal OUT, and the first input / output terminal I / O1, forms a second branch BR2.

[0128] Referring to Figures 6 and 7, when the second transmission device 20 is connected to the PCIe host device, the second sideband signal processing unit 220 turns on the first switch S1 and turns off the second switch S2, enabling the first branch BR1 and disabling the second branch BR2. The clock selection unit 211 receives the reference clock signal REFCLK from the first input / output terminal I / O1 and then outputs the reference clock signal REFCLK from its output terminal OUT. Since the first switch S1 is on and the second switch S2 is off, the reference clock signal REFCLK is transmitted to the second sideband optical transceiver unit 230. The second sideband optical transceiver unit 230 converts the reference clock signal REFCLK into a reference clock optical signal and transmits the reference clock optical signal to the second sideband optical transceiver unit 230' of the second transmission device 20' via the sideband optical cable SB2-1 in the second sideband optical channel.

[0129] When the second transmission device 20' is connected to the PCIe terminal device, the second sideband signal processing unit 220' turns on the second switch S2' and turns off the first switch S1', enabling the second branch BR2' and disabling the first branch BR1'. The reference clock electrical signal REFCLK, obtained by the second sideband optical transceiver unit 230' after photoelectric conversion of the received reference clock optical signal, is input from the input terminal IN' of the clock selection unit 211' and then output from the output terminal OUT' of the clock selection unit 211'. Since the first switch S1' is off and the second switch S2' is on, the reference clock electrical signal REFCLK is output to the PCIe terminal device via the first input / output terminal I / O1' of the clock selection unit 211'.

[0130] Thus, the second transmission device 20 realizes the optical solution for the reference clock signal REFCLK by using a second sideband optical channel independent of the in-band optical channel to transmit the reference clock signal REFCLK, enabling all devices within the PCIe system optics to use the reference clock signal REFCLK as a clock reference.

[0131] Furthermore, referring back to Figure 6, similar to the aforementioned first sideband signal processing unit 120, the second sideband signal processing unit 220 may also include multiple presence signal pins (Figure 6 shows two presence signal pins, PRSNT#1 and PRSNT#2, as an example). The second sideband signal processing unit 220 may also determine that the second transmission device 20 is connected to the PCIe host device by detecting that the level of at least one of the multiple presence signal pins is low to a second predetermined voltage range, or by detecting that the level of the multiple presence signal pins is low to a first voltage range. To avoid repetition, the principle of the second sideband signal processing unit 220 performing this detection will not be described here.

[0132] It should be understood that when the transmission device 1 includes both the first transmission device 10 and the second transmission device 30, the second sideband signal processing unit 220 may not have an presence signal pin. This is because it can obtain a message from the first sideband signal processing unit 120 indicating whether the first transmission device 10 is connected to a PCIe host device or a PCIe terminal device, thereby determining whether it itself is connected to a PCIe host device or a PCIe terminal device in the same way as the first sideband signal processing unit 120. Furthermore, as mentioned above, the second sideband signal processing unit 220 may belong to the same unit as the first sideband signal processing unit 120, thus eliminating the need for an additional presence signal pin.

[0133] Figure 8 shows a schematic structure of a clock multiplexing unit according to another embodiment of the present disclosure.

[0134] Generally, in a PCIe system, multiple first-level timers RT1 are typically arranged between the PCIe host device and the in-band optical channel, and multiple second-level timers RT2 are typically arranged between the in-band optical channel and the PCIe terminal device. For simplicity, only one first-level timer RT1 and one second-level timer RT2 are shown in Figure 8. The function of these timers is to recover jittered signals, regenerate new signals, and retransmit them to solve the signal attenuation problem.

[0135] Compared to Figure 7, the output terminal OUT of the clock selection unit 211 in Figure 8 is additionally connected to at least one of the plurality of first timers RT1 and the plurality of second timers RT2. This is beneficial for the device associated with the at least one timer in the PCIe system to receive an accurate reference clock signal REFCLK, thereby improving the clock synchronization accuracy of the entire example PCIe system.

[0136] Third transmission device 30

[0137] Figure 9 shows a schematic structure of a third transmission device according to an embodiment of the present disclosure.

[0138] As mentioned earlier, in electrical solutions, serial data signal lines and serial clock signal lines are used to transmit the serial clock signal SCL and the serial data signal SDA, respectively. However, in optical solutions, due to the unidirectional nature of optical fiber transmission, four optical fibers are required to transmit both the serial data signal SDA and the serial clock signal SCL.

[0139] Specifically, Figure 9 shows a third transmission device 30 and a third transmission device 30' having the same structure, and a third set of sideband optical cables SB3 connected between them. The third set of sideband optical cables SB3 includes sideband optical cable SB3-1 for transmitting the serial clock signal SCL from the third transmission device 30 to the third transmission device 30' and sideband optical cable SB3-2 for transmitting the serial clock signal SCL from the third transmission device 30' to the third transmission device 30, and sideband optical cable SB3-3 for transmitting the serial data signal SDA from the third transmission device 30 to the third transmission device 30' and sideband optical cable SB3-4 for transmitting the serial data signal SDA from the third transmission device 30' to the third transmission device 30.

[0140] The third transmission device 30 includes a third sideband optical transceiver unit 310 and a third sideband optical processing unit 320. The third sideband optical transceiver unit 310 includes electro-optical converters 310-1 and 310-3 and photoelectric converters 310-2 and 310-4. To avoid complexity and for ease of understanding by those skilled in the art, the electro-optical converters 310-1 and 310-3 or the photoelectric converters 310-2 and 310-4 will be referred to hereafter as the in-band optical transceiver unit 310.

[0141] When the third transmission device 30 is connected to the PCIe host device, the third sideband signal processing unit 320 can determine that the third transmission device 30 is connected to the PCIe host device. In this case, the third sideband signal processing unit 320 obtains the serial clock electrical signal SCL from the PCIe host device. The third sideband optical transceiver unit 310 is used to connect to a third sideband optical channel SB3, which is independent of the in-band optical channel, and converts the serial clock electrical signal SCL into a serial clock optical signal and transmits the serial clock optical signal via the third sideband optical channel SB3.

[0142] Alternatively, when the third transmission device 30 is connected to the PCIe terminal device, the third sideband signal processing unit 320 can determine that the third transmission device 30 is connected to the PCIe terminal device. In this case, the third sideband signal processing unit 320 controls the third sideband optical transceiver unit 310 to receive the serial clock optical signal via the third sideband optical channel SB3 and convert it into a serial clock electrical signal SCL. Then, the third sideband signal processing unit 320 sends the received serial clock electrical signal SCL to the PCIe terminal device.

[0143] Furthermore, when the third transmission device 30 is connected to the PCIe host device, the third sideband signal processing unit 320 can receive the serial data electrical signal SDA generated by the PCIe host device and control the third sideband optical transceiver unit 310 to convert it into a serial data optical signal and transmit the serial data optical signal. The third sideband optical transceiver unit 310 can also receive the serial data optical signal from the PCIe terminal device and convert it into a serial data electrical signal SDA, which is then transmitted to the PCIe host device by the third sideband signal processing unit 320. When the third transmission device 30 is connected to the PCIe terminal device, the third sideband signal processing unit 320 can receive the serial data electrical signal SDA generated by the PCIe terminal device and control the third sideband optical transceiver unit 310 to convert it into a serial data optical signal and transmit the serial data optical signal. Furthermore, the third sideband optical transceiver unit 310 can also receive serial data optical signals from the PCIe host device and convert them into serial data electrical signals SDA, which are then sent to the PCIe terminal device by the third sideband signal processing unit 320.

[0144] According to the SMbus standard, the serial data signal SDA must remain stable while the serial clock signal SCL is high, and high-low level changes are only permitted during the period when the serial clock signal SCL is low. In other words, the data transmitted in the serial data signal SDA needs to be ready before the rising edge of the serial clock signal SCL arrives. For example, in one example, it is required that the setup time of the serial data signal SDA be at least 50 ns before the rising edge of the serial clock signal SCL. However, in the optical scheme described above, if the sideband optical cable SB3-3 and / or sideband optical cable SB-4 used to transmit the serial data signal SDA is too long, it may cause the data transmission time in the serial data signal SDA to exceed the clock cycle in the serial clock signal SCL.

[0145] Therefore, when the third sideband signal processing unit 320 determines that the third transmission device 30 is connected to the PCIe host device, the third sideband signal processing unit 320 is further configured to keep the serial clock signal SCL low for a predetermined delay time T when the serial clock signal SCL reaches the rising edge. delay The scheduled delay period T delay It can be determined through theoretical calculations or experiments that the data in the serial data signal SDA has been established for a predetermined duration T when the rising edge of the serial clock signal SCL arrives. SDA (e.g., 50ns).

[0146] Therefore, the third transmission device 30 according to the embodiments of this disclosure can realize the transmission of SMbus electrical signals on a low-speed sideband optical channel. Furthermore, the third transmission device 30 also includes a delay unit to prevent the transmission time of data in the serial data signal SDA from exceeding the clock period in the serial clock signal SCL due to the excessive length of the sideband optical cable used to transmit the serial digital signal SDA.

[0147] Figure 9 shows an example where the third transmission device 30 is connected to the PCIe host device and the third transmission device 30' is connected to the PCIe terminal device.

[0148] When the third transmission device 30 is connected to the PCIe host device, the third sideband signal processing unit 320 can determine that the third transmission device 30 is connected to the PCIe host device. Therefore, the third sideband signal processing unit 320 can obtain the serial clock signal SCL from the PCIe host device and transmit this serial clock signal SCL to the third sideband optical transceiver unit 310. The third sideband optical transceiver unit 310 converts this serial clock signal SCL into a serial clock optical signal and then transmits the serial clock optical signal to the third sideband optical transceiver unit 310' of the third transmission device 30' via the sideband optical cable SB3-1 in the third sideband optical channel SB3.

[0149] When the third transmission device 30' is connected to the PCIe terminal device, the third sideband signal processing unit 310' can determine that the third transmission device 30' is connected to the PCIe terminal device. Then, the third sideband optical transceiver unit 310' receives the serial clock optical signal and converts it into a serial clock electrical signal SCL, and the third sideband signal processing unit 310' sends the serial clock electrical signal SCL to the PCIe terminal device.

[0150] For example, after the PCIe terminal device receives the serial clock signal SCL, it generates a serial data signal SDA. The third sideband signal processing unit 310' receives this serial data signal SDA from the PCIe terminal device and transmits it to the third sideband optical transceiver unit 310'. The third sideband optical transceiver unit 310' converts this serial data signal SDA into a serial data optical signal and transmits it to the third sideband optical transceiver unit 310 of the third transmission device 30 via the sideband optical cable SB3-4 in the third sideband optical channel SB3.

[0151] The third sideband optical transceiver unit 310 converts the received serial data optical signal into a serial data electrical signal SDA. The third sideband signal processing unit 320 then sends the serial data electrical signal SDA to the PCIe host device.

[0152] Furthermore, in the above process, the third sideband signal processing unit 320 is further configured to: hold the serial clock signal SCL at a low level for a predetermined delay time T when the serial clock signal SCL reaches its rising edge. delay This ensures that when the rising edge of the serial clock signal SCL arrives, the data in the serial data signal SDA has been established for a predetermined duration T. SDA .

[0153] Therefore, the third transmission device 30 according to this embodiment uses four optical cables SB3-1 to SB3-4 to transmit the SMbus communication function implemented by the serial clock line and serial data line in the electrical solution. Furthermore, by delaying the serial clock signal SCL, the problem of inaccurate acquisition of data in the serial data signal SDA due to the transmission time of data in the serial data signal SDA exceeding the clock cycle in the serial clock signal SCL is avoided.

[0154] In one embodiment, to facilitate the conversion between the two wires used for the serial clock signal SCL and the serial data signal SDA, respectively, and the four optical cables SB3-1 to SB3-4, the side of the third sideband signal processing unit 320 connected to the third sideband optical transceiver unit 310 is configured with four terminals, and the other side of the third sideband signal processing unit (i.e., the side opposite to the side connected to the third sideband optical transceiver unit 310) is configured with two additional terminals. These four terminals are respectively used to receive the serial clock signal SCL from the third sideband optical transceiver unit, to transmit the serial clock signal SCL to the third sideband optical transceiver unit, to receive the serial data signal SDA from the third sideband optical transceiver unit, and to transmit the serial data signal SDA to the third sideband optical transceiver unit. The additional two terminals are respectively used to obtain the serial clock signal SCL from the PCIe host device or to transmit the serial clock signal SCL to the PCIe terminal device, and to receive or transmit the serial data signal SDA from the PCIe host device or from the PCIe terminal device. The third sideband signal processing unit controls the reception and transmission of the four terminals and the other two terminals.

[0155] Further, as shown in FIG9, the third sideband signal processing unit 320 may include a first processing unit 321 for processing the serial clock signal SCL and a second processing unit 322 for processing the serial data signal SDA.

[0156] The first processing unit 321 includes a second input / output terminal I / O2, a first Schmitt trigger ST1, a first diode D1, a third resistor R3, a third switch S3, and a delay unit 3211.

[0157] The second input / output terminal I / O2 is used to connect to a PCIe host device or a PCIe terminal device, and when connected to a PCIe host device, it is used to receive the serial clock signal SCL from the PCIe host device, and when connected to a PCIe terminal device, it is used to output the serial clock signal SCL to the PCIe terminal device. The input IN1 of the first Schmitt trigger ST1 is connected to the second input / output terminal I / O2, and its output OUT1 is connected to the third sideband optical transceiver unit 310. The cathode of the first diode D1 is connected to the third sideband optical transceiver unit 310. The anode of the first diode D1 is connected to the first terminal of the third resistor R3 and the input IN1 of the first Schmitt trigger ST1. The second terminal of the third resistor R3 is connected to the power supply voltage Vcc. The third switch S3 includes a first terminal, a second terminal, and a control terminal. Its first terminal is connected to the second input / output terminal I / O1, its second terminal is grounded, and its control terminal is connected to the first terminal of the delay unit 3211. The second terminal of the delay unit 3211 is connected to the output OUT1 of the first Schmitt trigger ST1. The threshold voltage of the first Schmitt trigger ST1 is greater than the low-level voltage of the serial clock signal SCL and less than the forward voltage of the first diode D1. Furthermore, when the delay unit 3211 senses that the first Schmitt trigger ST1 has stopped triggering and has no output, it controls the third switch S3 to turn on, so that the voltage at the second input / output terminal I / O2 remains low for a first delay time period T. delay .

[0158] As shown in Figure 9, the output terminal OUT1 of the first Schmitt trigger ST1 is the terminal among the four terminals of the third sideband signal processing unit 320 connected to the third sideband optical transceiver unit 310 used to send the serial clock signal SCL to the third sideband optical transceiver unit 310. The cathode of the first diode D1 is the terminal among the four terminals used to receive the serial clock signal SCL from the third sideband optical transceiver unit 310. The second input / output terminal I / O2 is the terminal among the other two terminals on the opposite side of the third sideband signal processing unit 320 connected to the third sideband optical transceiver unit 310 used to obtain the serial clock signal from the PCIe host device or send the serial clock signal to the PCIe terminal device.

[0159] The second processing unit 322 includes a third input / output terminal I / O3, a second Schmitt trigger ST2, a second diode D2, and a fourth resistor R4. The third input / output terminal I / O3 is used to connect to a PCIe host device or a PCIe terminal device, and when connected to a PCIe host device, it outputs a serial data signal SDA to the PCIe host device and receives a serial clock signal SDA from the PCIe terminal device when connected to the PCIe terminal device. The input IN2 of the second Schmitt trigger ST2 is connected to the third input / output terminal I / O3, and its output OUT2 is connected to the third sideband optical transceiver unit 310. The cathode of the second diode D2 is connected to the third sideband optical transceiver unit 310. The anode of the second diode D1 is connected to the first terminal of the fourth resistor R4 and the second input IN2 of the Schmitt trigger ST2. The second terminal of the fourth resistor R4 is connected to the power supply voltage Vcc. The power supply voltage Vcc can be a power supply disposed inside the third sideband signal processing unit 320. The threshold voltage of the second Schmitt trigger ST2 is greater than the low-level voltage of the serial data signal SDA and less than the forward voltage of the second diode D2.

[0160] As shown in Figure 9, the output terminal OUT2 of the second Schmitt trigger ST2 is the terminal among the four terminals of the third sideband signal processing unit 320 connected to the third sideband optical transceiver unit 310, used to transmit the serial data signal SDA to the third sideband optical transceiver unit 310. The cathode of the second diode D2 is the terminal among the four terminals used to receive the serial data signal SDA from the third sideband optical transceiver unit 310. The third input / output terminal I / O3 is the terminal among the other two terminals on the opposite side of the third sideband signal processing unit 320 connected to the third sideband optical transceiver unit 310, used to receive or transmit the serial data signal SDA from the PCIe host device or from the PCIe terminal device.

[0161] The working principle of the third transmission device 30 is described below with reference to Figure 9. In Figure 9, the third transmission device 30 is connected to the PCIe host device, and the third sideband signal processor unit 320' is connected to the PCIe terminal device, taking this as an example. Specifically, the second input / output terminal I / O2 and the third input / output terminal I / O3 of the third sideband signal processor unit 320 are connected to the PCIe host device, and the second input / output terminal I / O2' and the third input / output terminal I / O3' of the third sideband signal processor unit 320' are connected to the PCIe terminal device.

[0162] When the PCIe host device pulls the serial clock signal SCL low to a low level voltage (e.g., 0.4V), the second input / output terminal I / O2 receives this low level voltage (e.g., 0.4V). The input IN1 of the first Schmitt trigger ST1, connected to the second input / output terminal I / O2, receives this low level voltage (e.g., 0.4V). Since this low level voltage (e.g., 0.4V) is less than the threshold voltage of the first Schmitt trigger ST1 (e.g., 0.55V), the output OUT1 of the first Schmitt trigger ST1 outputs its low level voltage (e.g., 0.55V). This low level voltage (e.g., 0.55V) is converted from electro-optical signal by the third sideband transceiver unit 310-1 and transmitted via optical fiber SB3-1 to the third sideband transceiver unit 310'-2 in the third transmission device 30'. It is then photoelectrically converted by the third sideband transceiver unit 310'-2 and transmitted to the cathode of the first diode D1'. Because this low-level voltage (e.g., 0.55V) is lower than the turn-on voltage of the first diode D1' (e.g., 0.75V), the first diode D1' is turned on, causing the voltage at the second input / output terminal I / O2' and the voltage at the input terminal IN1' of the first Schmitt trigger ST1' to both be equal to the turn-on voltage of the first diode D1' (e.g., 0.75V). Since the logic low-level threshold of the PCIe terminal device (e.g., 0.8V) is higher than the turn-on voltage of the first diode D1' (e.g., 0.75V), the PCIe terminal device interprets the voltage at the second input / output terminal I / O2' (e.g., 0.75V) as a logic low level. Thus, the serial clock signal SCL from the PCIe host device side is transmitted to the PCIe terminal device.

[0163] Furthermore, since the threshold voltage of the first Schmitt trigger ST1' (e.g., 0.55V) is less than the forward voltage of the first diode D1' (e.g., 0.75V), the first Schmitt trigger ST1' is not triggered and there is no output, thus preventing the creation of a feedback loop on the optical cable SB3-2 and preventing latch-up.

[0164] It is worth noting that during the transmission of the aforementioned serial clock signal SCL, it is possible that the voltage at the input terminal IN1' of the first Schmitt trigger ST1' may also be pulled down below its threshold voltage (e.g., 0.55V) by the PCIe termination device. In this case, the first Schmitt trigger ST1' outputs its low-level voltage (e.g., 0.55V) from its output terminal OUT1'. This low-level voltage (e.g., 0.55V) is transmitted to the cathode of the first diode D1 via the third sideband optical transceiver unit 310'-1, the sideband optical cable SB3-2, and the third sideband optical transceiver unit 310-2. Since the forward voltage of the first diode D1 (e.g., 0.75V) is greater than this low-level voltage (e.g., 0.55V), the first diode D1 conducts. However, since the voltage input from the second input / output terminal 1 / O2 to the input terminal IN1 of the first Schmitt trigger ST1 is the low-level voltage of the serial clock signal SCL (e.g., 0.4V), which is lower than the forward voltage of the first diode D1 (e.g., 0.75V), the first Schmitt trigger ST1 will continue to trigger and output its low-level voltage (e.g., 0.55V) until the PCIe host device stops pulling the serial clock signal SCL low. Only then will the voltage at the input terminal IN1 of the first Schmitt trigger ST1 be equal to the forward voltage of the first diode D1 (e.g., 0.75V), thereby causing the first Schmitt trigger ST1 to stop triggering and have no output.

[0165] Thus, the third transmission device 30 can utilize the low-speed third sideband optical channel to transmit the serial clock signal SCL in a low-power, stable, and reliable manner.

[0166] Referring again to Figure 9, as previously described, when the PCIe host device stops pulling the serial clock signal SCL low, the voltage at the input terminal IN1 of the first Schmitt trigger ST1 is equal to the forward voltage of the first diode D1, causing the first Schmitt trigger ST1 to stop triggering and not output. The second terminal of the delay unit 3211 is connected to the output terminal OUT1 of the first Schmitt trigger ST1, enabling the delay unit 3211 to sense that the first Schmitt trigger ST1 has stopped triggering and has no output. This allows the delay unit 3211 to control the third switch S3 to turn on, keeping the voltage at the second input / output terminal I / O2 low (e.g., 0.4V) for the first delay time period T. delay .

[0167] The principle of transmitting the serial clock signal SDA from the second processing unit 322' to the second processing unit 322 is the same as the principle of transmitting the serial clock signal SCL from the first processing unit 321 to the second processing unit 321', and will not be repeated here for the sake of simplicity.

[0168] Therefore, the third transmission device 30 according to the present disclosure further delays the rising edge of the serial clock signal SCL by using a delayer to avoid the problem that the transmission time of the serial data signal SDA may exceed the clock period of the serial clock signal SCL due to the length of the optical cable, thus ensuring that the data in the serial data signal SDA is correctly received.

[0169] Figure 10 shows the effect of delaying the rising edge of the serial clock signal SCL by a delayer according to an embodiment of the present disclosure.

[0170] Referring to Figure 10, before time t0, both the serial clock signal SCL and the serial data signal SDA are at a high level, indicating an idle state. While the serial clock signal SCL is high, at time t0, the serial data signal SDA transitions from high to low, indicating the start of communication. From time t0 to time tk, the first byte of data is transmitted. Then, from time tm to tn, the second byte of data is transmitted. This process continues until all data transmission is complete. Finally, at time th, while the serial clock signal SCL is high, the serial data signal SDA transitions from low to high, indicating the end of communication.

[0171] The thick solid line in Figure 10 represents the predetermined delay period T. delay1 For example, the time period between time t1 and time t2. For instance, if the low level of the serial clock signal SCL is not delayed, the serial clock signal SCL will have a rising edge at time t1, but data transmission in the serial data signal SDA has not yet been established at this time. If the low level of the serial clock signal SCL is delayed to after time t2, the serial clock signal SCL will have a rising edge at time t2, at which point data in the serial data signal SDA has been established for a predetermined duration (e.g., 50 ns).

[0172] Furthermore, as shown in FIG9, similar to the aforementioned first sideband signal processing unit 120, the third sideband signal processing unit 320 may also include a plurality of presence signal pins (FIG. 9 shows two presence signal pins, PRSNT#1 and PRSNT#2, as an example). The third transmission device 30 is connected to the PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, or by detecting that the level of the plurality of presence signal pins drops below a first predetermined voltage range. Since the principle of this detection performed by the first sideband signal processing unit 120 has already been described in conjunction with FIG. 2, for simplicity, the principle of this detection performed by the third sideband signal processing units 320 and 320' will not be described here.

[0173] It should be understood that when the transmission device 1 includes both the first transmission device 10 and the third transmission device 30, the third sideband signal processing unit 320 may not have an presence signal pin. This is because it can obtain a message from the first sideband signal processing unit 120 indicating whether the first transmission device 10 is connected to a PCIe host device or a PCIe terminal device, thereby determining whether it is also connected to a PCIe host device or a PCIe terminal device in the same way as the first sideband signal processing unit 120. Furthermore, as mentioned above, the third sideband signal processing unit 320 may belong to the same unit as the first sideband signal processing unit 120, thus eliminating the need for an additional presence signal pin.

[0174] Thus, the transmission system 1 constructed using the transmission device 100 including the first to third transmission devices 10 to 30 according to embodiments of the present disclosure can realize the transmission of PCIe sideband signals, including presence signals, reset signals, reference clock signals, and SMbus signals, on sideband optical channels independent of in-band optical channels, and realize the detection of receivers in in-band optical channels, comprehensively solving the problems that the current PCIe optical solutions described above urgently need to solve.

[0175] Those skilled in the art should understand that the specific embodiments described above are merely examples and not limitations. Various modifications, combinations, partial combinations, and substitutions can be made to the embodiments of this disclosure according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents, and thus fall within the scope of the rights to be protected by this disclosure.

Claims

1. A transmission device for optically transmitting PCIe sideband signals, comprising: First sideband signal processing unit and first sideband optical transceiver unit; Wherein, the first sideband signal processing unit is used to acquire a first initial sideband electrical signal and convert the first initial sideband electrical signal into a first transmission sideband electrical signal; the first sideband optical transceiver unit is used to connect to a first sideband optical channel independent of the in-band optical channel and convert the first transmission sideband electrical signal into a first transmission sideband optical signal and transmit the first transmission sideband optical signal via the first sideband optical channel, and / or The first sideband optical transceiver unit is used to connect to a first sideband optical channel independent of the in-band optical channel and receive a second transmission sideband optical signal via the first sideband optical channel and convert the second transmission sideband optical signal into a second transmission sideband electrical signal. The first sideband signal processing unit is used to restore the received second transmission sideband electrical signal into a second initial sideband electrical signal.

2. The transmission device according to claim 1, wherein, The first transmission sideband signal and the second transmission sideband signal are in UART format.

3. The transmission device according to claim 2, wherein, The first initial sideband signal and the second initial sideband signal include an initial presence signal; The first transmission sideband signal and the second transmission sideband signal include a UART format presence signal; The first sideband signal processing unit, upon determining that the transmission device is connected to the PCIe terminal device, acquires the initial presence signal and converts the initial presence signal into a UART format presence signal for transmission by the first sideband optical transceiver unit; and When the first sideband signal processing unit determines that the transmission device is connected to the PCIe host device, it restores the UART format presence signal received by the first sideband signal optical transceiver unit to the initial presence signal.

4. The transmission device according to claim 3, wherein, The first sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe terminal device by detecting that the level of the plurality of presence signal pins drops to a first predetermined voltage range.

5. The transmission device according to claim 4, wherein, The first sideband signal processing unit further determines that the transmission device is connected to a PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, wherein the highest voltage of the second predetermined voltage range is lower than the lowest voltage of the first predetermined voltage range.

6. The transmission device according to claim 1, wherein, The first sideband signal processing unit controls the first sideband optical transceiver unit to send the first transmission sideband optical signal at a predetermined time interval until an acknowledgment message for the first transmission sideband optical signal is received, or controls the first sideband optical transceiver unit to send the first transmission sideband optical signal a predetermined number of times.

7. The transmission device according to claim 1, wherein, The first initial sideband signal and the second initial sideband signal also include an initial reset signal; The first transmission sideband signal and the second transmission sideband signal also include a reset signal in UART format; Specifically, the first sideband signal processing unit acquires the initial reset signal upon determining that the transmission device is connected to the PCIe host device, and converts the initial reset signal into a UART format reset signal for the first sideband optical transceiver unit to perform electro-optical conversion before transmission; and When the first sideband signal processing unit determines that the transmission device is connected to the PCIe terminal device, it restores the UART format reset signal, which has been received and photoelectrically converted by the first sideband signal optical transceiver unit, into the initial reset signal.

8. The transmission device according to any one of claims 1-7, wherein, The first initial sideband signal and the second initial sideband signal also include the initial Internet Packet Explorer Ping message; The first and second transmission sideband signals also include Ping messages in UART format. The first sideband signal processing unit generates the initial Ping message in response to power-on, and converts the initial Ping message into a Ping message in UART format for the first sideband optical transceiver unit to perform electro-optical conversion and then transmit.

9. The transmission device according to claim 1, further comprising: An in-band optical transceiver unit is used to connect each optical channel in the in-band optical channel; as well as A receiver detection circuit is configured to perform receiver detection for each of the in-band optical channels to generate an initial receiver result electrical signal for each optical channel indicating whether the receiver detection for that optical channel was successful or failed. The first sideband signal processing unit also converts the initial receiver result electrical signal of each optical channel into a receiver detection result electrical signal in UART format. The first sideband optical transceiver unit also converts the UART format receiver detection result electrical signal into a UART format receiver detection result optical signal and transmits it via the first sideband optical channel.

10. The transmission device according to claim 9, wherein, The receiver detection circuit includes: Multiple receiver detection sub-circuits, each of which is configured to perform receiver detection for a corresponding optical channel in the in-band optical channels, and Each receiver detection sub-circuit includes an RC circuit, and generates an initial receiver detection result electrical signal indicating successful receiver detection for the corresponding optical channel based on the time constant of the RC circuit responding to a common-mode voltage step being greater than a predetermined duration threshold, or generates an initial receiver detection result electrical signal indicating failed receiver detection for the corresponding optical channel based on the time constant being less than the predetermined duration threshold.

11. The transmission device according to claim 10, wherein, Each detection sub-circuit also includes: The system consists of a first differential cable pair, a second differential cable pair, a detection unit, and two second resistors. The first differential cable pair is used to connect to the electro-optic converter in the in-band optical transceiver unit; The second differential cable pair is used to connect to the photoelectric converter in the in-band optical transceiver unit; The RC circuit includes two identical sub-RC circuits respectively coupled to the two cables of the first differential cable pair, each sub-RC circuit including a first capacitor and a first resistor. The detection unit is used to drive the common-mode voltage step on the first differential cable pair, determine the time constant of the two sub-RC circuits responding to the common-mode voltage step, and generate a receiver detection result electrical signal indicating successful receiver detection for the corresponding optical channel based on the time constant being greater than the predetermined duration threshold, or generate a receiver detection result electrical signal indicating failed receiver detection for the corresponding optical channel based on the time constant being less than the predetermined duration threshold; and The two second resistors are respectively coupled to the two cables of the second differential cable pair.

12. The transmission device according to claim 11, wherein, The detection unit includes: A common-mode voltage driving subunit is configured to drive a common-mode low voltage on the first differential cable pair to pull the voltage of the first capacitor down to a predetermined low voltage value, and after determining that the voltage across the first capacitor has been pulled down to the predetermined low voltage value, drive a common-mode high voltage on the first differential cable pair. A recording subunit records the time elapsed from the moment the common-mode voltage driving subunit drives the common-mode high voltage until the voltage across the first capacitor reaches a predetermined high voltage value, using this time constant as the time constant; and The determination unit generates an initial receiver detection result electrical signal indicating successful detection of the receiver in the corresponding optical channel based on the time constant being greater than the predetermined duration threshold, or generates an initial receiver detection result electrical signal indicating failed detection of the receiver in the corresponding optical channel based on the time constant being less than the predetermined duration threshold.

13. The transmission device according to claim 10, wherein, The first sideband signal processing unit also multiplexes and encodes the corresponding two or more initial reception detection result electrical signals of two or more optical channels among the multiple optical channels of the in-band optical channel into multiplexed reception detection result electrical signals in UART format. The first sideband optical transceiver unit also transmits the UART format multiplexed reception detection result electrical signal via the first sideband optical channel.

14. The transmission device according to claim 11, wherein, The detection unit is integrated into the first sideband signal processing unit.

15. The transmission device according to claim 11, wherein, The detection unit is implemented by a PCIe ReDriver chip.

16. A transmission device for optically transmitting a reference clock electrical signal, comprising: Second sideband signal processing unit, clock multiplexing unit, and second sideband optical transceiver unit The clock multiplexing unit includes a first branch and a second branch. Wherein, the second sideband signal processing unit enables the first tributary and disables the second tributary when it determines that the transmission device is connected to the PCIe host device, so that the clock multiplexing unit receives the reference clock electrical signal from the PCIe host device and sends the reference clock electrical signal to the second sideband optical transceiver unit via the first tributary. The second sideband optical transceiver unit then converts the reference clock electrical signal into a reference clock optical signal and transmits it. When the second sideband signal processing unit determines that the transmission device is connected to the PCIe terminal device, it enables the second branch and disables the first branch, so that the second sideband optical transceiver unit receives the reference clock optical signal and converts the reference clock optical signal into a reference clock electrical signal, and then the clock multiplexing unit sends the reference clock electrical signal to the PCIe terminal device via the second branch.

17. The transmission device according to claim 16, wherein, The clock multiplexing unit includes a clock selection unit, a first switch, and a second switch. The clock selection unit includes a first input / output terminal, an input terminal, and an output terminal; The first switch is connected between the output terminal and the second sideband optical transceiver unit, and together with the first input / output terminal and the output terminal, forms the first branch; The second switch is connected between the output terminal and the first input / output terminal, and together with the input terminal, the output terminal, and the first input / output terminal, forms the second branch. The second sideband signal processing unit, upon determining that the transmission device is connected to the PCIe host device, turns on the first switch and turns off the second switch to enable the first branch and disable the second branch. This allows the first input / output terminal to receive the reference clock electrical signal from the PCIe host device, and the reference clock electrical signal is transmitted sequentially via the output terminal and the first switch to the second sideband optical transceiver unit, where it is converted into a reference clock optical signal and transmitted. When the second sideband signal processing unit determines that the transmission device is connected to the PCIe terminal device, it turns on the second switch and turns off the first switch to enable the second branch and disable the first branch, so that the reference clock electrical signal obtained by the second sideband optical transceiver unit after converting the received reference clock optical signal is sent to the PCIe terminal device in sequence via the input terminal, the output terminal, the second switch and the first input / output terminal.

18. The transmission device according to claim 17, wherein, The output is also connected to a retimer for the in-band optical channel to transmit the reference clock signal to the retimer.

19. The transmission device according to claim 16, wherein, The second sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe terminal device by detecting that the level of at least one of the plurality of presence signal pins drops to a first predetermined voltage range.

20. The transmission device according to claim 19, wherein, The second sideband signal processing unit includes a plurality of presence signal pins, and determines that the transmission device is connected to a PCIe host device by detecting that the level of at least one of the plurality of presence signal pins drops to a second predetermined voltage range, wherein the highest voltage of the second predetermined voltage range is lower than the lowest voltage of the first predetermined voltage range.

21. A transmission apparatus for optically transmitting SMbus electrical signals, the SMbus electrical signals including serial clock signals and serial data signals, the transmission apparatus comprising: Third sideband signal processing unit and third sideband optical transceiver unit Specifically, when the third sideband signal processing unit determines that the transmission device is connected to the PCIe host device, it obtains the serial clock electrical signal from the PCIe host device. The third sideband optical transceiver unit is used to connect to a third sideband optical channel independent of the in-band optical channel, and converts the serial clock electrical signal into a serial clock optical signal and transmits it via the third sideband optical channel. Alternatively, When the third sideband signal processing unit determines that the transmission device is connected to the PCIe terminal device, the third sideband optical transceiver unit receives the serial clock optical signal via the third sideband optical channel and converts the serial clock optical signal into a serial clock electrical signal. The third sideband signal processing unit then transmits the serial clock electrical signal to the PCIe terminal device. Wherein, when the third sideband signal processing unit determines that the transmission device is connected to the PCIe host device, the third sideband signal processing unit is further configured to maintain the level of the serial clock signal at a low level voltage for a first delay period when the serial clock signal reaches the rising edge, and the first delay period ensures that when the rising edge of the serial clock signal arrives, the data in the serial data signal has been established for a predetermined duration.

22. The transmission device according to claim 21, wherein, The third sideband signal processing unit, connected to the third sideband optical transceiver unit, has four terminals on one side. These four terminals are respectively used to receive the serial clock signal from the third sideband optical transceiver unit, to transmit the serial clock signal to the third sideband optical transceiver unit, to receive the serial data signal from the third sideband optical transceiver unit, and to transmit the serial data signal to the third sideband optical transceiver unit. The other side of the third sideband signal processing unit, opposite to the first side, has two additional terminals. These two additional terminals are respectively used to obtain the serial clock signal from the PCIe host device or to transmit the serial clock signal to the PCIe terminal device, and to receive or transmit the serial data signal from the PCIe host device or from the PCIe terminal device. The third sideband signal processing unit controls the reception and transmission of the four terminals and the other two terminals.

23. The transmission device according to claim 22, wherein, The third sideband signal processing unit includes a first processing unit for processing the serial clock signal and a second processing unit for processing the serial data signal. The first processing unit includes a second input / output terminal, a first Schmitt trigger, a first diode, a third resistor, a third switch, and a delay unit, wherein: The second input / output terminal is used to connect to a PCIe host device or a PCIe terminal device, and when it is connected to a PCIe host device, it is used to receive a serial clock signal from the PCIe host device, and when it is connected to a PCIe terminal device, it is used to output a serial clock signal to the PCIe terminal device. The input of the first Schmitt trigger is connected to the second input / output terminal, and its output is connected to the third sideband optical transceiver unit; The cathode of the first diode is connected to the third sideband optical transceiver unit, and its anode is connected to the first terminal of the third resistor and the input terminal of the first Schmitt trigger. The second terminal of the third resistor is connected to the power supply voltage; The third switch includes a first terminal, a second terminal, and a control terminal, with its first terminal connected to the second input / output terminal, its second terminal grounded, and its control terminal connected to the first terminal of the delay unit. The second terminal of the delay unit is connected to the output terminal of the first Schmitt trigger, and when the delay unit senses that there is no output at the output terminal of the first Schmitt trigger, it controls the third switch to be turned on so that the voltage at the first input and output terminals remains low for a first delay period. Specifically, the threshold voltage of the first Schmitt trigger is greater than the low-level voltage of the serial clock signal and less than the forward voltage of the first diode, and the forward voltage of the first diode is lower than the logic low-level threshold of the PCIe terminal device. Wherein, the second input / output terminal serves as one of the other two terminals for obtaining the serial clock signal from the PCIe host device or sending the serial clock signal to the PCIe terminal device; the output terminal of the first Schmitt trigger serves as one of the four terminals for sending the serial clock signal to the third sideband optical transceiver unit; and the cathode of the first diode serves as one of the four terminals for receiving the serial clock signal from the third sideband optical transceiver unit.

24. The transmission device according to claim 23, wherein, The second processing unit includes a third input / output terminal, a second Schmitt trigger, a second diode, and a fourth resistor, wherein: The third input / output terminal receives or outputs serial data electrical signals; The input of the second Schmitt trigger is connected to the third input / output terminal, and its output is connected to the third sideband optical transceiver unit; The cathode of the second diode is connected to the third sideband optical transceiver unit, and its anode is connected to the first terminal of the fourth resistor and the input terminal of the second Schmitt trigger. The second terminal of the fourth resistor is connected to the power supply voltage; Wherein, the threshold voltage of the second Schmitt trigger is greater than the low-level voltage of the serial data signal and less than the forward voltage of the second diode. Wherein, the third input / output terminal serves as one of the other two terminals for receiving or sending the serial data signal from the PCIe host device or from the PCIe terminal device; the output terminal of the second Schmitt trigger serves as one of the four terminals for sending the serial data signal to the third sideband optical transceiver unit; and the cathode of the second diode serves as one of the four terminals for receiving the serial data signal from the third sideband optical transceiver unit.

25. The transmission device according to claim 24, wherein, The third sideband signal processing unit includes multiple presence signal pins, and determines that the transmission device is connected to a PCIe terminal device by detecting that the level of the multiple presence signal pins is low but higher than the ground level.

26. The transmission device according to claim 24, wherein, The third sideband signal processing unit also includes a plurality of presence signal pins, and determines that the transmission device is connected to the PCIe host device by detecting that the level of at least one of the plurality of presence signal pins goes low to ground.

27. The transmission device according to claim 23, wherein, The delay unit is integrated into the third sideband signal processing unit.

28. A transmission device, comprising: A fourth transmission device for connecting to and transmitting in-band signals via an in-band optical channel; as well as One or more of the first transmission device, the second transmission device, and the third transmission device Wherein, the first transmission device is the transmission device as described in any one of claims 1 to 15. The second transmission device is the transmission device as described in any one of claims 16 to 20. The third transmission device is the transmission device as described in any one of claims 21 to 27.

29. A transmission system for optically transmitting sideband signals, comprising: The first transmission device is the transmission device as described in claim 28; The second transmission device is the transmission device as described in claim 28; as well as A set of in-band optical cables connected between the fourth transmission device of the first transmission device and the fourth transmission device of the second transmission device to form an in-band optical channel. Where both the first transmission device and the second transmission device include the first transmission unit, the transmission system further includes a first set of sideband optical cables for connecting the first transmission units of the first transmission device and the second transmission device. When both the first transmission device and the second transmission device include the second transmission unit, the transmission system further includes a second set of sideband optical cables for connecting the second transmission units of the first transmission device and the second transmission device. When both the first transmission device and the second transmission device include the third transmission unit, the transmission system further includes a third set of sideband optical cables for connecting the third transmission units of the first transmission device and the second transmission device. The first transmission device is used to connect to a PCIe host device, and the second transmission device is used to connect to a PCIe terminal device.

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