A load driving arrangement

Abstract

A load driving arrangement having a buffer circuit of a capacitance network connected to an input of a switched mode power factor correction circuit of the load driving arrangement. A tuning circuit is configured to tune an capacitance of the capacitance network responsive to an amplitude of an AC input signal powering the load driving arrangement by responsive to the amplitude of the AC input power reaching or falling below a first threshold value, controlling the capacitance of the capacitance network to a first capacitance at which first capacitance the voltage on the capacitance network is lower than the amplitude of the AC input power thereby conducting current flows of the AC input power.

Description

[0001] A load driving arrangement

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to the field of load driving arrangements, particularly those that employ a switched-mode power supply.

[0004] BACKGROUND OF THE INVENTION

[0005] In modem electrical circuits, there is usually a need to provide accurate and reliable driving of a load. Thus, there is a need for an accurate and reliable load driving arrangement. One use case scenario for a load driving arrangement is in artificial lighting, e.g., to drive a semiconductor light emitting element load such as an LED and / or laser diode that functions as the main load.

[0006] In general, a load driving arrangement will receive an input signal and generate an output signal suitable for driving a (desired) load. It is desirable for a load driving arrangement to be able to provide the output signal with a low noise, whilst the load driving arrangement achieves a good power factor. One approach to ensuring a good power factor is to make use of a switched mode power factor correction circuit to produce the output signal.

[0007] There is an ongoing desire to improve the performance of a load driving arrangement e.g., to reduce a noise in the output signal and improve a power factor of the load driving arrangement.

[0008] CN 113348614 A discloses an active EMI filter with an adjustable capacitor (Figure 4) which is used for compensating temperature or compensating for different working conditions, such as when selecting a different frequency band or switching frequency.

[0009] US2023253878A1 discloses an active electromagnetic interference cancellation circuit and method, used for DC power application.

[0010] WO2024056577A1 discloses a PFC circuitry with predictive active EMI filter, used for AC mains application.

[0011] W02022095080A1 discloses an active filter for electromagnetic interference with an adjustable capacitor, similar as CN113348614A. SUMMARY OF THE INVENTION

[0012] A load driving arrangement would benefit from a switched mode power factor correction circuit especially for driving a high electrical load, i.e., a load that demands a high power. It is thus advantageous to also provide an active EMI filter together with the switched mode power factor correction circuit by using a buffer circuit that is controlled to perform compensation of a high frequency switching ripple of an AC input signal (e.g., a significant contributor to differential noise in the circuit). However, the inventor has recognized that such a buffer circuit for example a capacitance network can result, for low amplitudes of an AC input signal, deadtime in the signal provided to the switched mode power factor correction circuit. This deadtime disadvantageous^ increases a total harmonic distortion and reduces a power factor of the load driving arrangement. More particularly, this deadtime effectively prevents the load driving arrangement from being able to operate for certain amplitudes of the AC input power. Thus, the active EMI filter conflicts with the switched mode power factor correction circuit.

[0013] It is herein proposed to modify an electrical parameter of the buffer circuit responsive to the amplitude of the AC input signal to facilitate a reduction and / or avoidance of deadtime in converting the AC power by the load driving arrangement.

[0014] The present disclosure thereby provides a load driving arrangement with active EMI noise compensation method. The proposed load driving arrangement includes a novel main switching frequency current ripple cancellation technique with high PF and low THD for high efficiency and size reduction. In particular, the load driving arrangement includes a buffer circuit configured to attenuate a current ripple in a provided AC power. Most importantly, an electrical parameter of the buffer circuit is tuned responsive to the amplitude of the AC power, to reduce or avoid deadtime in the converted AC power. Since the frequency of the switched mode power factor correction circuit also varies as the amplitude of the AC power varies, appropriate tuning of the electrical parameter of the buffer circuit is able to (e.g., just) satisfy the frequency of the switched mode power factor correction circuit so as to provide compensation signal with a matching frequency. Double function / double technical effect is thereby achieved.

[0015] The invention is defined by the claims.

[0016] According to examples in accordance with an aspect of the invention, there is provided a load driving arrangement comprising: an input interface adapted to connect to an AC input power; an output interface for connection to a load; a switched mode power factor correction (SMPFC) circuit, connected between the input interface and the output interface, wherein the switching mode power factor correction circuit is configured to produce a switched signal by switchably connecting, at a switching frequency, the AC input power to the output interface and performing power factor correction on the AC input power, wherein said switching frequency is variable responsive to an amplitude of the AC input power; a buffer circuit connected to the input interface, wherein the buffer circuit comprises a capacitor network (445) having a capacitance as a buffering capability configured to buffer the AC input power and be operable at a selectable frequency corresponding to the switching frequency; a switch circuit configured to switch, corresponding to the switching frequency, the buffer circuit to thereby control the buffer circuit at the selectable frequency corresponding to the switching frequency to generate a compensation signal for compensating the switched signal; and a tuning circuit adapted to tune the buffering capability of the buffer circuit, namely the capacitance of the capacitor network, responsive to an amplitude of the AC input power.

[0017] In this way, the tuning circuit is able to, for a first amplitude of the AC input power, both generate the compensation signal at the selected frequency corresponding to the switching frequency at this first amplitude of the AC input power and prevent the load driving arrangement from being unable to operate at the first amplitude of the AC input power, by responsive to the amplitude of the AC input power reaching or falling below a first threshold value, controlling the capacitance of the capacitance network to a first capacitance at which first capacitance the voltage on the capacitance network is lower than the amplitude of the AC input power thereby conducting current flows of the AC input power.

[0018] The input interface may comprise a rectifier arrangement configured to perform rectification on the AC input power and the capacitance network is cascaded after the rectifier arrangement,. In particular examples at the first amplitude of the AC input power, the rectifier arrangement is unable to conduct because the voltage on the capacitance network higher than the amplitude of the AC input power thereby making the load driving arrangement unable to operate were the electrical parameter of the buffer circuit not tuned. It should also be understood that there may be other causes that make the load driving arrangement unable to operate and the parameter of the buffer circuit can also be tuned to solve such causes.

[0019] The proposed approach thereby facilitates the conduction of the rectifier arrangement even for low amplitudes of the AC input signal which would otherwise not be conducted (i.e. , would create deadtime). Thus, a deadtime where no current flows is reduced and THD can be reduced and power factor can be increased. The tuned selected frequency resulted from the tuned parameter still matches the switching frequency at this amplitude of the AC input signal thus active EMI filter is also still able to operate. It has been identified that the capacitance of the buffer circuit will significantly affect the length of the deadtime of the conduction of the rectifier bridge and the signal at the input to the SMPFC circuit. This is because the rectifier bridge does not conduct when the input voltage is lower than the voltage on the buffer circuit after the rectifier bridge. The higher the capacitance on the buffer circuit, the higher the voltage it will store / keep and thus the longer the deadtime. By controlling or tuning the capacitance, the deadtime can therefore be controlled or reduced.

[0020] The buffer circuit may further comprise an inductor connected in series with the capacitor network, such that the buffer circuit comprises an LC circuit comprising the capacitor network and the inductor. The use of an LC circuit provides a filtering mechanism, e.g., for filtering any ripples at the switching frequency.

[0021] The capacitance network may comprise: a first capacitor; and a second capacitor arrangement connected in parallel with the first capacitor, wherein the second capacitor arrangement comprises a second capacitor and a switch connected in series, wherein the tuning circuit is configured to control a conductivity of the switch of the second capacitor arrangement to thereby tune the electrical parameter of the buffer circuit. This approach provides a robust and reliable mechanism for controlling or tuning the capacitance of the buffer circuit. It should be noted that other ways of tuning the capacitance are also possible, such as using a voltage- controlled capacitor.

[0022] The tuning circuit may be configured to: responsive to the amplitude of the AC input power reaching or rising above below a second threshold value, controlling the capacitance of the capacitance network to a second capacitance, wherein the first capacitance is less than the second capacitance. This approach provides a reliable and modifiable mechanism for tuning the capacitance of the capacitance network so as to keep the rectifier bridge conducting throughout the AC mains cycles as long as possible.

[0023] The rectifier arrangement may be unable to conduct if the capacitance of the capacitance network is the second capacitance when the amplitude of the AC input power reaches or falls below the first threshold value.

[0024] The switched mode power factor correction circuit may be configured to responsive to the amplitude of the AC input power reaching or falling below the first threshold value, controlling the switching frequency to a first switching frequency; and responsive to the amplitude of the AC input power reaching or rising above the second threshold value, controlling the switching frequency to a second switching frequency, wherein the first switching frequency is greater than the second switching frequency. In this way, the change in the switching frequency by the SMPFC correction may be synchronous with a change in the capacitance of the buffer circuit. This allows the capacitance of the buffer circuit to be changed to align with the switching frequency, e.g., to ensure filtering or attenuating of any ripple caused by the switching frequency is achieved.

[0025] In some examples, the buffer circuit with the first capacitance is adapted to generate the compensation signal corresponding to the switched signal at the first switching frequency, and the buffer circuit with the second capacitance is adapted to generate the compensation signal corresponding to the switched signal at the second switching frequency.

[0026] More specifically, at low amplitude of AC mains, the switching frequency is high, and a low capacitance can be sufficient to provide a matching frequency meanwhile making the rectifier bridge conduct at the low amplitude of AC mains; at high amplitude, the switching frequency goes low, and a large(r) capacitance is needed to provide the matching frequency, However, at this high amplitude there is no concern about the conduction of the rectifier bridge, thus it is acceptable to use such a large capacitance for normally buffering AC mains ripple.

[0027] The switch circuit may be configured to alternately connect, at the selectable frequency, the buffer circuit to a first reference voltage and a second reference voltage, wherein the second reference voltage is less than the first reference voltage. This provides a mechanism for producing a compensation circuit that tracks or follows a high frequency switching ripple in the AC input signal, which is the differential mode noise, resulted by the high frequency switching of the switched mode power factor corrector.

[0028] The switch circuit may comprise: a high-side switch for selectively connecting the buffer circuit to the first reference voltage synchronously with one switching state of the switched mode power factor correction circuit; and a low-side switch for selectively connecting the buffer circuit to the second reference voltage synchronously with the other switching state of the switched mode power factor correction circuit, wherein the switch circuit is configured to only connect one of the first reference voltage and the second reference voltage to the buffer circuit at a time. This does not need a separate control signal for the active EMI filter but reuses the switching control signal of the switch mode power factor correction circuit, and provides a simple but reliable and robust open loop mechanism for selectively connecting the buffer circuit to the first and second reference voltage in synchronization with the switching of the switch mode power factor correction circuit. Thus, the differential switching signal of the switch mode power factor correction circuit automatically triggers an inverted version of signal by the buffer circuit thus those two signals would inherently be complementary with each other and is able to perform appropriate compensation.

[0029] Alternatively, the switch circuit may also be implemented by a detector to detect the HF switching ripple on the AC mains and provide a supplementary signal accordingly. This is a closed loop for active EMI filtering and its advantage is accuracy, at a cost of complexity. The prevent invention is applicable to both the open loop and the closed loop active EMI filtering as above.

[0030] The switched mode power factor correction circuit may comprise a boost converter, such as a synchronous boost converter. Such converters provide an accurate and precise mechanism for performing power factor correction conversion on an AC input power to produce a desired output power.

[0031] The buffer circuit and the switch circuit may be configured to together function as an active EMI filter for filtering differential mode noise in the switched signal.

[0032] Some examples further comprise an output capacitance arrangement connected to the output interface, where the output capacitance arrangement is configured to receive and buffer the switched signal produced by the switched mode power factor correction circuit. The output capacitance arrangement functions to smooth the switched signal to produce a smoother (e.g., with attenuation ripple) DC output signal for any load connected to the output interface.

[0033] There is also proposed a lighting arrangement comprising any herein proposed load driving arrangement; and a semiconductor light emitting element arrangement connected to the output interface.

[0034] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS

[0036] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0037] Fig. 1 illustrates an existing load driving arrangement;

[0038] Fig. 2 is a waveform depicting an input to a switched mode power factor correction circuit of the existing load driving arrangement for an AC input power;

[0039] Fig. 3 illustrates waveforms in an existing load driving arrangement for an AC input power in different scenarios;

[0040] Fig. 4 illustrates a proposed load driving arrangement; Fig. 5 illustrates a switched mode power factor correction circuit for use in proposed embodiments; and

[0041] Fig. 6 illustrates waveforms during operation of the proposed load driving arrangement.

[0042] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The invention will be described with reference to the Figures.

[0044] It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims, and accompanying drawings. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

[0045] The invention provides a load driving arrangement. A buffer circuit is connected to an input of a switched mode power factor correction circuit of the load driving arrangement. The buffer circuit is able to provide a signal with a selected frequency to compensate a switching signal from the switched mode power factor correction circuit. A tuning circuit is configured to tune an electrical parameter of the buffer circuit responsive to an amplitude of an AC input signal powering the load driving arrangement in such a way that both the selected frequency matches the frequency of the switched mode power factor correction circuit and the load driving arrangement is prevented from becoming non-operational due to conflict between the AC input signal and an untuned electrical parameter of the buffer circuit.

[0046] In the context of the present disclosure, the terms amplitude and magnitude are considered to be interchangeable, and refer to the absolute value or modulus of a signal.

[0047] Figure 1 illustrates an existing load driving arrangement 100. The load driving arrangement comprises an input interface 110, an output interface 120, a switched mode power factor correction circuit 130, a buffer circuit 140 and a switch circuit 150.

[0048] The input interface 110 is adapted to connect to an DC input power SDC.

[0049] The output interface 120 is configured for connection to a load 190. Thus, the output interface 120 may comprise one or more connecting elements for connecting to a load.

[0050] The output interface 120 may, for instance, comprise an output capacitor COUT or buffer for smoothing a signal provided to the output interface. The switched mode power supply circuit 130 is connected between the input interface and the output interface. The switched mode power supply circuit 130 produces a switched signal Ssw by switchably connecting the DC input power to the output interface. The switched mode power supply circuit 130 thereby operates at a switching frequency.

[0051] The output capacitor COUT may thereby smooth the switched signal Ssw to provide a DC voltage for driving a load 190 coupled to the output interface 120.

[0052] The buffer circuit 140 is also connected to the input interface 110. The buffer circuit has a buffering capability configured to buffer the DC input power. The buffer circuit is operable at a selectable frequency. The switch circuit 150 is configured to control the selectable frequency to correspond to the switching frequency, thereby causing the buffer circuit to generate a compensation signal for compensating the switched signal.

[0053] In particular, the illustrated buffer circuit 140 comprises a capacitor CB and inductor IB connected to an intermediate node NINT. The intermediate node may be controllably connected to a first reference voltage VRI and a second reference voltage VR2 by the switch circuit 150 (at the selectable frequency), e.g., using a controller 151 and a single-pole doublethrow switch SC. The selectable frequency may be controlled to be the same as the switching frequency for performing the compensation. The buffer capacitor is switched such that when the current into the switched mode power supply circuit 130 increases, the buffer capacitor draws a decreasing current from the DC input power SDC or even supplies the switched mode power supply circuit 130; and when current into the switched mode power supply circuit 130 decreases, the buffer capacitor draws an increasing current from the DC input power SDC, thus the total current from the DC input power SDC is smooth. The energy in and out of the buffer capacitor is usually in a lossless or near-lossless manner thus the efficiency is also high.

[0054] In this way, the buffer circuit 140 and the switch circuit 150 effectively function as an active EMI filter that generates an opposite high frequency ripple current to compensate the high frequency switching ripple current introduced by the switched mode power supply circuit. Compared to traditional passive EMI filters, active EMI filters can help to reduce the EIM filter size and increase efficiency. The EMI filter formed from the buffer circuit 140 and switch circuit 150 is particularly advantageous for performing differential mode noise cancellation.

[0055] The present disclosure recognizes the existing load driving arrangement is designed for a DC input power. However, there are a number of use-case scenarios (such as lighting applications) in which only an AC input power (e.g., a mains supply) is available. There is therefore a challenge of how to adapt the load driving arrangement 100 for an AC input power.

[0056] More particularly, it has been recognized that the buffering capability, e.g., the capacitance, of the buffer circuit 140 will significantly deteriorate the power factor (PF) and / or total harmonic distortion (THD) of the load driving arrangement.

[0057] Figure 2 illustrates atypical input current waveform 210 to the circuit 130 when the input interface is supplied with an AC input power, i.e., at a node lying between the input interface and the circuit 130, wherein the circuit 130 is implemented into a switched mode power factor correction (SMPFC) circuit.

[0058] One or more deadtimes 220, 230, are clearly visible in the waveform, during which the value of the current waveform does not change. The deadtimes 220, 230 occur at low voltage magnitudes of the AC input power. Deadtime 220, 230 in the current waveform 210 significantly influences the power factor (PF) and / or total harmonic distortion (THD). This is because when adapting the load driving arrangement for use with an AC input power, there is a rectifier bridge before the active EMI filter 140. The rectifier bridge would become unconductive if the AC input power voltage is less than the voltage on the buffer capacitor CB. The larger the capacitance of the buffer capacitor CB, the higher voltage it will build thus the worse the THD / power factor. On the other hand, in order to provide a selected frequency corresponding to the switching frequency of the switched mode power factor correction circuit 130, a most convenient way is to provide a large capacitor to form a frequency pass band starting from low frequency such that the switched signal can pass regardless of the chosen switching frequency (e.g., within a predetermined range of known candidate switching frequencies). An active EMI filter thereby require a relatively large capacitance, but increasing capacitance make THD / PF worse, thus conflict is caused.

[0059] The present disclosure recognizes that the (length of the) deadtime is responsive to the buffering capability, e.g., the capacitance, of the buffer circuit 140. The larger the buffering capability (e.g., the larger the capacitance), the larger the deadtime. An increase to the buffering capability and deadtime disadvantageous^ causes the phase shift angle of the load driving arrangement to increase, as well as a reduction in the power factor and an increase in the total harmonic distortion.

[0060] Figure 3 shows waveforms 310, 320, 330 of a simple equivalent simulation model for the load driving arrangement 100 for the sake of improved understanding.

[0061] A first waveform 310 illustrates the input voltage to the switched mode power supply circuit in both a first and second scenario. A second waveform 320 illustrates the input current to the switched mode power supply circuit in a first scenario. A third waveform 330 illustrates the input current to the switched mode power supply circuit in a second scenario.

[0062] In the first scenario, the capacitance of the buffer circuit has a first value. In the second scenario, the capacitance of the buffer circuit has a second value, less than the first value. As illustrated, the deadtime of the input current increases for an increased value of the capacitance, causing the power factor to decrease and the total harmonic distortion to increase (for increasing capacitance(s)).

[0063] Nonetheless, it is noted that a capacitance or buffering capacity that is too low will cause the buffer circuit 140 and switch circuit 150 to be less capable of functioning as an active EMI filter. It has therefore been historically accepted to have a relatively large capacitance or buffering capacity, to achieve EMI filtering, at the expense of reduced power factor and increased total harmonic distortion.

[0064] The present disclosure proposes to provide a tuning circuit adapted to tune an electrical parameter of the buffer circuit to tune the buffering capability of the buffer circuit. This allows the buffering capability of the buffer circuit to be adapted for different amplitudes of the AC input signal, thereby facilitating control over and / or a reduction in the deadtime of the current input (which occurs at low voltages) to the SMPFC whilst providing sufficient buffering capability for performing EMI filtering at respective voltages.

[0065] Figure 4 illustrates a proposed load driving arrangement 400.

[0066] The load driving arrangement 400 comprises an input interface 410, an output interface 420, a switched mode power factor correction (SMPFC) circuit 430, a buffer circuit 440, a switch circuit 450 and a tuning circuit 460.

[0067] The input interface 410 is adapted to connect to an AC input power SAC.

[0068] The input interface may, for instance, comprise a rectifier arrangement 415 configured to perform rectification on the AC input power SAC to produce a rectified version of the AC input power SACR. Examples of suitable rectifier arrangements 415 are well known, including half-wave rectifiers, full-wave rectifiers, bridge rectifiers, active or synchronous rectifiers and so on.

[0069] During any deadtime (outlined above), more specifically, when the AC input power SAC is less than the voltage on the buffer circuit 440, the rectifier arrangement will effectively fail to conduct any power.

[0070] The output interface 420 is configured for connection to a load 490. Thus, the output interface 420 may comprise one or more connecting elements for connecting to a load. One suitable example of a load 490 is a light emitting arrangement, such as a semiconductor light emitting element arrangement.

[0071] The load driving arrangement 400 may, for instance, further comprise an output capacitance arrangement 425 connected to the output interface. The output capacitance arrangement is configured to receive and buffer the switched signal produced by the switched mode power factor correction circuit. Here, the output capacitance arrangement 425 is configured as a single capacitor, but may instead comprise a plurality or array of capacitors.

[0072] The switched mode power factor correction (SMPFC) circuit 430 is connected between the input interface and the output interface. The SMPFC circuit produces a switched signal Ssw by switchably connecting the (rectified) AC input power SACR to the output interface, and thereby operates at a switching frequency.

[0073] In particular, the switched mode power factor correction circuit 430 is configured to vary the switching frequency responsive to an amplitude or magnitude (e.g., voltage magnitude) of the AC input power SAC.

[0074] More particularly, the SMPFC circuit 430 may operate in a boundary current mode (particularly suited for driving a semiconductor light emitting element arrangement) in which the switching frequency is varied with the voltage magnitude of the AC input power SAC. Generally, the greater the voltage magnitude of the AC input power SAC, the lower the switching frequency. Thus, the switching frequency may vary between a maximum switching frequency fsmax and a minimum switching frequency fsmin. The switching frequency may move from the maximum switching frequency (for low voltage magnitudes of the AC input power SAC) to the minimum switching frequency (for high voltage magnitudes of the AC input power). The maximum switching frequency is thereby defined by the control scheme of the SMPFC circuit 430.

[0075] In a simple example, the switched mode power factor correction circuit is configured to, responsive to the amplitude of the AC input power reaching or falling below the first threshold value, control the switching frequency to a first switching frequency. Similarly, the switched mode power factor correction circuit may be configured to, responsive to the amplitude of the AC input power reaching or rising above the second threshold value, control the switching frequency to a second switching frequency, wherein the first switching frequency is greater than the second switching frequency.

[0076] The first and second threshold values may be the same.

[0077] In this way, the switching frequency of the SMPFC circuit is effectively able to switch between (at least) two different switching frequencies. Of course, the skilled person would readily understand how the SMPFC circuit may be operable to provide more than two different switching frequencies. For instance, there may be a plurality of different thresholds (including at least the first threshold and the second threshold) defining a plurality of threshold ranges for the AC input power. Each range may be associated with a different switching frequency, such that the switching frequency is responsive to into which threshold range the amplitude of the AC input power falls.

[0078] Preferably, the switched mode power factor correction circuit 430 comprises a boost converter, such as a synchronous boost converter.

[0079] Figure 5 illustrates an example of a suitable switched mode power factor correction circuit 430 for the sake of improved understanding, which is embodied as a synchronous boost converter.

[0080] The SMPFC circuit 430 comprises a switched-mode inductor ISM and a first switched mode switch SSMI connected in series. A second switched mode switch SSM2 connects between a ground / reference voltage and a first node N 1 positioned between the switched-mode inductor ISM and a first switched mode switch SSMI. The switched mode inductor receives the (rectified) AC input power SACR and the first switched mode switch SSMI provides the switched signal Ssw. This SMPFC circuit is a boost converter. Other types of converters are also applicable.

[0081] Control circuitry 435 synchronously controls the operation of the first and second switched mode switches at the switching frequency. In particular, the control circuity may operate in accordance with the boundary current mode operation previously disclosed.

[0082] Turning back to Figure 4, and similarly to the buffer circuit of the existing load driving arrangement, the buffer circuit 440 is connected to the input interface 410. The buffer circuit has a buffering capability configured to buffer the rectified AC input power. The buffer circuit is also operable at a selectable frequency.

[0083] The switch circuit 450 is configured to control the selectable frequency to correspond to the switching frequency, thereby causing the buffer circuit to generate a compensation signal for compensating the switched signal.

[0084] Figure 6 illustrates the rectified AC input power SACR and the current II through the buffer circuit. The buffer circuit is controlled at the switching frequency, which (as previously explained) may switch between a first frequency (when the amplitude of the AC input power SACR falls below a first threshold AT) and a second frequency (when the amplitude of the AC input power SACR rises above a second threshold AT - which is here the same as the first threshold). In this way, a compensation signal is generated for compensating a ripple induced in the SMPFC circuit 430 as a result of the switching signal.

[0085] Turning back to Figure 4, the buffer circuit 440 comprises a capacitor network 445 and / or an inductor network IB connected to an intermediate node NINT. The intermediate node may be controllably connected to a first reference voltage VRI and a second reference voltage VR2 by the switch circuit 150 (at the selectable frequency). The selectable frequency may be controlled to be the same as the switching frequency for performing the compensation.

[0086] More particularly, in the illustrated examples, the buffer circuit comprises an inductor IB (forming the inductor network) connected in series with the capacitor network. In this way, the buffer circuit 440 comprises an LC circuit comprising the capacitor network and the inductor.

[0087] The illustrated switch circuit 450 comprises a high-side switch Sn for selectively connecting the buffer circuit to the first reference voltage VRI synchronously with one switching state of the switched mode power factor correction circuit; and a low-side switch SL for selectively connecting the buffer circuit to the second reference voltage VR2 synchronously with the other switching state of the switched mode power factor correction circuit. The switch circuit is configured to only connect one of the first reference voltage and the second reference voltage to the buffer circuit at a time.

[0088] The high-side and low-side switches may each be embodied as any suitable transistor, such as a MOSFET or GaN HEMT. Other examples will be apparent to the appropriately skilled person.

[0089] More detail on the design of the buffer circuit 440 is hereafter provided for the sake of improved contextual understanding.

[0090] The buffer circuit has a buffering capability of both buffering the AC input power and has a selectable frequency in order to facilitate compensation of the PFC current ripple. More particularly, the capacitor network 445 is used to block DC voltage and as a part of LC filter, together with the inductor network IB, to pass (i.e., filter out) the switching frequency component to / from the SACR signal. This helps make sure that the current in the inductor network takes the form of a triangular waveform to perform compensation of the inductor current in the SMPFC circuit 130.

[0091] More specifically, the switched current of the SMPFC circuit 130 will have a ramp up / ramp down waveform. Thus, the inductor network IB is mainly used for generating a corresponding ramp up / ramp down current for (ripple) compensation. Of course, the inductor network also forms part of an LC filter to pass the switching frequency component for suitable compensation. Thus, the capacitance (of the capacitance network) and the inductance (of the inductor network) C should be large enough to pass (i.e., filter out) the switching frequency component. Failure to do so may result in resonance worsening the ripple cancellation.

[0092] The capacitance C of the capacitance network and the inductance L of the inductor network preferably meet the criteria defined by the following equations:

[0093] 1

[0094] - < 10 f (1)

[0095] 2ny U!smax= VR2

[0096] (2) LoL where fsmax is the (maximum) switching frequency, Vo is the output voltage, Lois the inductance of the SMPFC circuit 130 and VR2 is the second reference voltage .

[0097] Equation (1) is designed for passing / filtering out of the switching frequency fs. Equation (2) is designed for performing appropriate ripple cancellation.

[0098] For ripple cancellation, the value of L may therefore be determined by equation (2) and is fixed for a certain converter design. Accordingly, the capacitance C can be appropriately designed to meet the criterion of equation (1). A most convenient design is providing a large capacitance C.

[0099] More particularly, the capacitance network and the inductor network together function as a high pass LC filter. The larger the capacitance of the capacitance network, the lower the cut off frequency. If the LC filter is designed to be capable of passing fsat the peak of AC (e.g., at the maximum frequency), then it is naturally also able to pass the switching frequency at the zero crossing of AC.

[0100] However, as previously explained, large values for the capacitance C will worsen the PF / THD for an AC input power since, such a large capacitance will increase the deadtime of input current as well as the phase-shift.

[0101] The present disclosure proposes a variation to the buffer circuit 440, together with the addition of a tuning circuit 460.

[0102] The buffer circuit 440 is adapted to have a tunable or configurable electrical parameter (and therefore buffering capability). The tuning circuit 460 is configured to tune an electrical parameter of the buffer circuit so as to tune the buffering capability of the buffer circuit responsive to an amplitude of the AC input power.

[0103] In the illustrated example, the capacitance network of the buffer circuit is configured to have a tunable capacitance. The tuning circuit is correspondingly configured to tune the capacitance of the capacitor network to thereby tune the electrical parameter of the buffer circuit.

[0104] More particularly, the tuning circuit may be configured to reduce a capacitance of the capacitor network responsive to the amplitude of the AC input power reducing. The advantageously recognizes that a large capacitance makes the PF / THD significantly worse at low voltage magnitudes of the AC input power (e.g., close to the zero crossing). This smaller capacitor achieves a double function / effect: capable of passing the high frequency requirement of the switched signal at the zero crossing to realize active EMI filtering, and keep the appliance / rectifier bridge's operation thereby allowing high PF / low THD.

[0105] As mentioned above, the SMPFC circuit is configured to increase the switched frequency as the amplitude of the AC input power reduces. Thus, a smaller capacitance C is sufficient to pass this increasing switching frequency whilst still adhering, for instance, to equation (1). Conversely, the switching frequency decreases as the amplitude of the AC input near peak increases, thus benefitting from a larger capacitor C to pass the switching frequency.

[0106] By using the tuning circuit to tune the capacitance value depending on the amplitude of the AC input power, it is possible to perform good active EMI filtering / compensation and also providing good PF and THD for changing switching frequencies.

[0107] In some examples, the tuning network may be configured to responsive to the amplitude of the AC input power reaching or falling below a first threshold value, controlling the capacitance of the capacitance network to a first capacitance; and responsive to the amplitude of the AC input power reaching or rising above below a second threshold value, controlling the capacitance of the capacitance network to a second capacitance, wherein the first capacitance is less than the second capacitance.

[0108] The first threshold value may be the same as the second threshold value, but this is not essential (e.g., if performing hysteresis style control).

[0109] The first and second threshold values effectively control for how long (in each period of the AC input power) the capacitance of the capacitance network has the first and second capacitance. Changing the first and / or second threshold value will therefore impact at least the EMI performance and the power factor of the load driving arrangement. More particularly, EMI performance will improve and power factor will reduce as the first and / or second threshold value increase (and the proportion of each period of the AC input power for which the capacitance of the capacitance network is at the second capacitance).

[0110] In the illustrated example, the capacitance network comprises: a first capacitor Cl; and a second capacitor arrangement 445 connected in parallel with the first capacitor. The second capacitor arrangement 445 comprises a second capacitor C2 and a switch SI connected in series. The tuning circuit 460 is configured to control a conductivity of the switch of the second capacitor arrangement to thereby tune the electrical parameter of the buffer circuit.

[0111] In this approach, the tuning circuit 460 may close the switch SI when the switching frequency is high (e.g., when the amplitude of the AC input power reaches or falls below a first threshold value) and open the switch SI when the switching frequency is low (e.g., when the amplitude of the AC input power reaches or falls below a second threshold value, which may be the same as the first threshold value).

[0112] In this way, the capacitance can increase (e.g., to the sum of the capacitance of the first and second capacitors) when the amplitude of the AC input power reaches or falls below a first threshold value. This summed capacitance is preferably large enough to meet the criterion of equation (1). During this period, as the current is large, the large capacitance of the capacitance network will not significantly influence the waveform of input current.

[0113] Similarly, the capacitance may decrease (e.g., to the capacitance of the first capacitor only) when the amplitude of the AC input power reaches or falls below a second threshold value. Since the switching frequency will be relatively high, a smaller capacitance can be used is needed to filter switching frequency whilst also helping to reduce deadtime and (thereby) improve PF and THD.

[0114] The summed capacitance of the first and second capacitor may be selected using equation (1), where the value of fsmax is instead replaced with the value of the switching frequency when the amplitude of the AC input power is at the first threshold. The capacitance of the first value may be similarly selected using equation (1).

[0115] Other example approaches for providing a buffer circuit with a tunable electrical parameter will be apparent to the skilled person and can be employed to a similar effect.

[0116] For instance, the second capacitor arrangement 445 may instead comprise a second capacitor and a switch connected in series, and the tuning circuit may be correspondingly configured to control a conductivity of the switch of the second capacitor arrangement to thereby tune the electrical parameter of the buffer circuit. As another example, the capacitance network may comprise two or more capacitors connected in series. A bypass switch may be connected to controllably bypass one or more (but not all) of the capacitors connected in series. The tuning circuit may control the operation of the bypass switch to thereby control the capacitance, and therefore buffering capability, of the buffer circuit.

[0117] The capacitance network may also be implemented by a single voltage controlled capacitor.

[0118] The buffer circuit is advantageously able to, for a first amplitude of the AC input power, both generate the compensation signal at the selected frequency corresponding to the switching frequency at this first certain amplitude of the AC input power and prevent the loading driving circuit from being unable to operate at the certain first amplitude of the AC input power.

[0119] In some examples, the tuning circuit is configured to monitor a power factor and / or EMI performance of the load driving arrangement. The tuning circuit may be configured to modify or adjust the value of the first and / or second threshold values responsive to the monitored power factor and / or EMI performance.

[0120] As previously explained, EMI performance will improve and power factor will reduce as the first and / or second threshold value increase (and the proportion of each period of the AC input power for which the capacitance of the capacitance network is at the second capacitance). Thus, it is possible to calibrate the first and / or second threshold values to achieve a desired EMI performance and / or power factor (e.g., to prioritize one or strike a balance between the two).

[0121] The proposed load driving arrangement is particularly advantageous when used to control a lighting load, such as a semiconductor light emitting element arrangement. Accordingly, there is also proposed a lighting arrangement comprising: any herein disclosed load driving arrangement; and a semiconductor light emitting element arrangement connected to the output interface.

[0122] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality.

[0123] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. If the term "adapted to" is used in the claims or description, it is noted the term "adapted to" is intended to be equivalent to the term "configured to". If the term "arrangement" is used in the claims or description, it is noted the term "arrangement" is intended to be equivalent to the term "system", and vice versa. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A load driving arrangement (400) comprising an input interface (410) adapted to connect to an AC input power (SAC); an output interface (420) for connection to a load; a switched mode power factor correction circuit (430), connected between the input interface and the output interface, wherein the switching mode power factor correction circuit is configured to produce a switched signal (Ssw) by switchably connecting, at a switching frequency, the AC input power to the output interface and performing power factor correction on the AC input power, wherein said switching frequency is variable responsive to an amplitude of the AC input power; a buffer circuit (440) connected to the input interface, wherein the buffer circuit comprises a capacitor network (445) having a capacitance as a buffering capability configured to buffer the AC input power and be operable at a selectable frequency corresponding to the switching frequency; a switch circuit (450) configured to switch, corresponding to the switching frequency, the buffer circuit to thereby control the buffer circuit at the selectable frequency corresponding to the switching frequency to generate a compensation signal for compensating the switched signal; and a tuning circuit (460) adapted to tune an electrical parameter of the buffer circuit so as to tune the capacitance of the capacitor network responsive to an amplitude of the AC input power so as to, for a first amplitude of the AC input power, both generate the compensation signal at the selectable frequency corresponding to the switching frequency at this first amplitude of the AC input power and prevent the load driving arrangement from being unable to operate at the first amplitude of the AC input power, by responsive to the amplitude of the AC input power reaching or falling below a first threshold value, controlling the capacitance of the capacitance network to a first capacitance at which first capacitance the voltage on the capacitance network is lower than the amplitude of the AC input power thereby conducting current flows of the AC input power.

2. The load driving arrangement of claim 1, wherein the input interface comprises a rectifier arrangement configured to perform rectification on the AC input power and the capacitance network is cascaded after the rectifier arrangement.

3. The load driving arrangement of claim 2, wherein, at the first amplitude of the AC input power, the rectifier arrangement is unable to conduct because the voltage on the capacitance network higher than the amplitude of the AC input power thereby making the load driving arrangement unable to operate, were the electrical parameter of the buffer circuit not tuned.

4. The load driving arrangement of any one of claims 1 to 3, wherein the buffer circuit further comprises an inductor (IB) connected in series with the capacitor network, such that the buffer circuit comprises an LC circuit comprising the capacitor network and the inductor.

5. The load driving arrangement of any one of claims 1 to 3, wherein the capacitance network comprises: a first capacitor (Cl); and a second capacitor arrangement connected in parallel with the first capacitor, wherein the second capacitor arrangement comprises a second capacitor (C2) and a switch (SI) connected in series, wherein the tuning circuit (460) is configured to control a conductivity of the switch of the second capacitor arrangement to thereby tune the electrical parameter of the buffer circuit.

6. The load driving arrangement of any of claims 1 to 4, wherein the tuning circuit is configured to: responsive to the amplitude of the AC input power reaching or rising above below a second threshold value, controlling the capacitance of the capacitance network to a second capacitance, wherein the first capacitance is less than the second capacitance, and wherein the rectifier arrangement is unable to conduct if the capacitance of the capacitance network is the second capacitance when the amplitude of the AC input power reaches or falls below the first threshold value.

7. The load driving arrangement of claim 6, wherein the switched mode power factor correction circuit is configured to: responsive to the amplitude of the AC input power reaching or falling below the first threshold value, control the switching frequency to a first switching frequency; and responsive to the amplitude of the AC input power reaching or rising above the second threshold value, control the switching frequency to a second switching frequency, wherein the first switching frequency is greater than the second switching frequency.

8. The load driving arrangement of claim 7, wherein the buffer circuit with the first capacitance is adapted to generate the compensation signal corresponding to the switched signal at the first switching frequency, and the buffer circuit with the second capacitance is adapted to generate the compensation signal corresponding to the switched signal at the second switching frequency.

9. The load driving arrangement of any of claims 1 to 8, wherein the switch circuit is configured to alternately connect, at the selectable frequency, the buffer circuit to a first reference voltage and a second reference voltage, wherein the second reference voltage is less than the first reference voltage.

10. The load driving arrangement of claim 9, wherein the switch circuit comprises: a high-side switch (Sn) for selectively connecting the buffer circuit to the first reference voltage synchronously with one switching state of the switched mode power factor correction circuit; and a low-side switch (SL) for selectively connecting the buffer circuit to the second reference voltage synchronously with the other switching state of the switched mode power factor correction circuit, wherein the switch circuit is configured to only connect one of the first reference voltage and the second reference voltage to the buffer circuit at a time.

11. The load driving arrangement of any of claims 1 to 10, wherein the switched mode power factor correction circuit comprises a boost converter.

12. The load driving arrangement of any of claims 1 to 11, wherein the boost converter is a synchronous boost converter.

13. The load driving arrangement of any of claims 1 to 12, wherein the buffer circuit and the switch circuit are configured to together function as an active EMI filter for filtering differential mode noise in the switched signal.

14. The load driving arrangement of any one of claims 1 to 13, further comprising an output capacitance arrangement (425) connected to the output interface, where the output capacitance arrangement is configured to receive and buffer the switched signal produced by the switched mode power factor correction circuit.

15. A lighting arrangement comprising: the load driving arrangement (400) of any of claims 1 to 14; and a semiconductor light emitting element arrangement (490) connected to the output interface.

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