Doherty power amplifier compression compensation circuit

Abstract

A Doherty power amplifier compression compensation circuit is disclosed. A power amplifier chain may include a Doherty amplifier having a main power amplifier path and a peaking power amplifier path, where both paths have a driver stage and an output stage. One or more compression detection circuits may be associated with an output of the main output stage. Responsive to detecting compression at this output, an adjustment is made to one or more knobs in the power amplifier chain. In a first aspect, a variable gain control circuit may adjust the gain of an earlier amplifier (e.g., the driver stage) for either (or both) of the main path or the peaking path. In further aspects, one or more bias circuits may have bias signals adjusted. Both amplitude and phase compression may be addressed by aspects of the present disclosure.

Description

Ref. No. P241491-WO-UTLDOHERTY POWER AMPLIFIER COMPRESSION COMPENSATION CIRCUITPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 645,623, filed on May 10, 2024, and entitled “DOHERTY POWER AMPLIFIER COMPRESSION COMPENSATION CIRCUIT,” the contents of which are incorporated herein by reference in its entirety.RELATED APPLICATION

[0002] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 641,687 filed on May 2, 2024, and entitled “POWER AMPLIFIER COMPRESSION COMPENSATION CIRCUIT,” the contents of which are incorporated herein by reference in its entirety.BACKGROUNDI. Field of the Disclosure

[0003] The technology of the disclosure relates generally to power amplifiers and, more particularly, to circuits that compensate for compression in Doherty power amplifiers at high power.II. Background

[0004] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to reduce power consumption. For wireless communication devices, one of the primary power uses is in the transceiver, and particularly, in the power amplifier of the transceiver. Making these power amplifiers more efficient provides room for innovation.Ref. No. P241491-WO-UTLSUMMARY

[0005] Aspects disclosed in the detailed description include a Doherty power amplifier compression compensation circuit. In particular, a power amplifier chain may include a Doherty amplifier having a main power amplifier path and a peaking power amplifier path, where both paths have a driver stage and an output stage. One or more compression detection circuits may be associated with an output of the main output stage. Responsive to detecting compression at this output, an adjustment is made to one or more knobs in the power amplifier chain. In a first aspect, a variable gain control circuit may adjust the gain of an earlier amplifier (e.g., the driver stage) for either (or both) of the main path or the peaking path. In further aspects, one or more bias circuits may have bias signals adjusted. Both amplitude and phase compression may be addressed by aspects of the present disclosure.

[0006] In this regard, in one aspect, a Doherty amplifier chain is disclosed. The Doherty amplifier chain includes a main path comprising a main driver stage and a main output stage. The Doherty amplifier chain also includes a peaking path comprising a peaking driver stage and a peaking output stage. The Doherty amplifier chain further includes a compression detector coupled to the main output stage and configured to detect when an output signal crosses a threshold indicating compression is occurring; and a gain control circuit coupled to the compression detector and the peaking driver stage, the gain control circuit configured to adjust a gain of the driver stage responsive to detection that compression is occurring.

[0007] In another aspect, a communication device is disclosed. The communication device includes transmit circuitry comprising a baseband processor and a Doherty amplifier chain communicatively coupled to the baseband processor. The Doherty amplifier chain comprising a main path comprising a main driver stage and a main output stage. The Doherty amplifier stage also comprising a peaking path comprising a peaking driver stage and a peaking output stage. The communication device further includes a compression detector coupled to the main output stage and configured to detect when an output signal crosses a threshold indicating compression is occurring and a gain control circuit coupled to the compression detector and the peaking driver stage, the gain control circuit configured to adjust a gain of the driver stage responsive to detection that compression is occurring.Ref. No. P241491-WO-UTL

[0008] In another aspect, a method of controlling an amplifier chain is disclosed. The method includes detecting compression at a main output stage of a Doherty amplifier chain and responsive to detecting compression, adjusting a gain of a peaking driver stage in the Doherty amplifier chain.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a conventional amplifier with a bias circuit that is used to compensate for non-linearities in the operation of the amplifier;

[0010] Figure 2A is a block diagram of a multi-stage amplifier chain with a compression compensation circuit working with a driver stage to assist in the linear operation of the amplifier chain;

[0011] Figure 2B is a block diagram of a three-stage amplifier chain with a compression compensation circuit working with an intermediate stage to assist in the linear operation of the amplifier chain;

[0012] Figure 3 is a block diagram of a multi-stage amplifier chain with a compression compensation circuit that adjusts both the amplitude and phase of an earlier amplifier stage to assist in the linear operation of the amplifier chain;

[0013] Figure 4 is a block diagram of a multi-stage amplifier chain with a compression compensation circuit having two compression detectors that adjust both amplitude and phase of an earlier amplifier stage to assist in the linear operation of the amplifier chain;

[0014] Figure 5A is a block diagram of a multi-stage amplifier chain with a compression compensation circuit that works with a single-ended amplifier in the amplifier chain;

[0015] Figure 5B is a block diagram of a multi-stage amplifier chain with a compression compensation circuit that works with a differential-ended amplifier in the amplifier chain;

[0016] Figures 6A-6C are circuit diagrams of possible amplifier stages reliant on field effect transistors that are amenable to compression compensation according to aspects of the present disclosure;

[0017] Figure 7 is a hybrid circuit-block diagram of a multi-stage amplifier chain with a compression compensation circuit that adjusts both the amplitude and phase of an earlier amplifier stage to assist in the linear operation of the amplifier chain;Ref. No. P241491-WO-UTL

[0018] Figure 8 is a flowchart illustrating an exemplary process for compensating for compression in an amplifier stage according to aspects of the present disclosure;

[0019] Figure 9 is a block diagram of an amplifier chain using a Doherty amplifier structure with compression compensation circuits working with driver stages to assist in linear operation of the amplifier chain;

[0020] Figure 10 is a block diagram of an amplifier chain using a Doherty amplifier structure with compression compensation circuits working with driver stages and bias circuits to assist in linear operation of the amplifier chain;

[0021] Figure 11 is a block diagram of an amplifier chain using a Doherty amplifier structure with mixed single-ended and differential-ended amplifiers in the chain and compression compensation circuits according to aspects of the present disclosure;

[0022] Figure 12 is a hybrid circuit and block diagram of an amplifier chain showing a hybrid complementary metal oxide semiconductor (CMOS) and bipolar structure and compression compensation circuits according to aspects of the present disclosure;

[0023] Figure 13 is a circuit diagram highlighting the gain adjustment for a differential-ended driver stage similar to those introduced in Figures 6A-6C;

[0024] Figure 14 is a flowchart illustrating an exemplary process for compensating for compression in an amplifier stage according to aspects of the present disclosure; and

[0025] Figure 15 is a block diagram of a communication device, which may include the power amplifier chains with compression compensation circuits of Figures 9-13B according to the present disclosure.DETAILED DESCRIPTION

[0026] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0027] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a firstRef. No. P241491-WO-UTL element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0029] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill inRef. No. P241491-WO-UTL the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0032] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0033] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0034] Aspects disclosed in the detailed description include a Doherty power amplifier compression compensation circuit. In particular, a power amplifier chain may include a Doherty amplifier having a main power amplifier path and a peaking power amplifier path, where both paths have a driver stage and an output stage. One or more compression detection circuits may be associated with an output of the main output stage. Responsive to detecting compression at this output, an adjustment is made to one or more knobs in the power amplifier chain. In a first aspect, a variable gain control circuit may adjust the gain of an earlier amplifier (e.g., the driver stage) for either (or both) of the main path or the peaking path. In further aspects, one or more bias circuits may have bias signals adjusted. Both amplitude and phase compression may be addressed by aspects of the present disclosure.

[0035] Before addressing aspects of the present disclosure, a brief overview of a power amplifier circuit and bias compensation for non-linearities is provided with reference to Figure 1. A discussion of compression compensation as it applies to a single path amplifier chain begins below with reference to Figure 2A. A discussion ofRef. No. P241491-WO-UTL compression compensation as it applies to Doherty amplifier chains according to aspects of the present disclosure begins below with reference to Figure 9.

[0036] In this regard, Figure 1 illustrates an amplifier chain 100 with an input node 102 and an output node 104. A blocking capacitor 106 may be coupled to the input node 102 and an input of a power amplifier 108. A bias circuit 110 may also be coupled to the input of the power amplifier 108. The bias circuit 110 may raise or set a voltage level at the input of the power amplifier 108 through a ballast resistor 112 and rectifying capacitor 114.

[0037] In general, communication device designers want the amplifier chain 100 to operate linearly over a wide range of input power levels. Most amplifier chains will be linear over low and moderate power levels but will experience some sort of non-linearity at higher levels. This non-linearity may be compression or sometimes may be a small expansion followed by compression. The compression may begin as a soft compression and then may experience hard clipping at sufficiently high levels. To get more linearity at the higher levels, the bias circuit 110 with the ballast resistor 112 and the rectifying capacitor 114 may be added. Such a design may allow radio frequency (RF) signals to leak into the bias circuit 110. This leakage may create memories or otherwise negatively impact performance. Further, the bias circuit 110 is not able to react to complicated gain non-linearities of the power amplifier 108.

[0038] Other amplifier chains (not shown) may employ a saturation detector and feedback loop which allows some dynamic adjustment of the bias circuit. However, any such bias circuit adjustments to the output stage of an amplifier chain necessarily rely on increased current to offset the compression. As more current is used, there is a decrease in efficiency. As the wireless standards continue to evolve, there is pressure to minimize the efficiency compromises required to secure desired linear performance.

[0039] The present disclosure is primarily focused on adding a compression detection circuit to a Doherty amplifier to assist in providing linear operation of a Doherty amplifier. However, before addressing the Doherty amplifier aspects, a discussion of adding a compression detection circuit that detects a compression threshold being exceeded at an output stage of an amplifier chain is explored. A gain control loop circuit, responsive to the threshold being exceeded, adjusts a gain of an earlier stage of a multistage amplifier chain to compensate for amplitude compression at the output stage. This preliminary discussion focuses on adjusting a gain of a preceding amplifier stage (e.g., aRef. No. P241491-WO-UTL driver stage) and notes that using the gain of such a preceding amplifier provides a positive improvement in performance without needing to use a bias circuit adjustment. While avoiding a bias circuit adjustment avoids an efficiency penalty, there may be occasions where the use of a bias circuit adjustment further improves linearity and may be warranted. Thus, Figures 2A-8 discuss avoiding the use of a bias circuit, but beginning in Figure 10, the use of a bias circuit adjustment is reintroduced.

[0040] In this regard, Figure 2A illustrates a multi-stage amplifier chain 200 that includes an input node 202 and an output node 204. A first driver stage 206 may be coupled to the input node 202. An output stage 208 may be coupled to the output node 204. Optionally, one or more additional stages may be present, as indicated by the box 210. For example, for some millimeter-wave applications, the box 210 may have two intermediate amplifier stages. Likewise, for some 2G applications, the box 210 may have one intermediate amplifier stage. Other applications may have no intermediate stages. An inter-stage match circuit 212 may be positioned between the first driver stage 206 and the output stage 208.

[0041] Aspects of the present disclosure add a compression detection circuit 214 that detects (generally at 214A) a voltage level at the output node 204 or in the output stage 208. This detected voltage is compared to a threshold by a comparator 214B. When the threshold is exceeded, a detection circuit 214C generates an output signal 216, which is received by a variable slope control circuit 218 as part of a gain control loop 220. The gain control loop 220 then changes the gain of the first driver stage 206. The threshold for the comparator 214B and the slope for the slope control circuit 218 may be provided from a memory element 222 associated with a control circuit 224. The values for the threshold and slope may be stored in a lookup table (LUT) or the like. The control circuit 224 may further include a bus interface 226, which allows communication with other circuits, such as a baseband processor (not shown). In an exemplary aspect, the bus interface 226 may be compliant with MIPI’s radio frequency front end (RFFE) standard and may be considered a digital input / output (I / O) interface. The control circuit 224 may receive information about a mode of operation including, but not limited to a band / frequency range, a power level, and a modulation scheme through the bus interface 226. This information may be used to select an appropriate threshold and / or slope from the memory element 222.Ref. No. P241491-WO-UTL

[0042] A compression detector such as detection circuit 214 is chosen because it may be more sensitive than a saturation detector and may detect an inception of non-linear behavior and provide correction through a driver stage in the amplifier chain. By adjusting gain directly, instead of adjusting gain indirectly through changes to a bias circuit, the efficiency of the gain change is improved. Further, the adjustments at the driver stage may be a few milliamps of current adjustment rather than multiple amps at an output stage.

[0043] Note that adjusting a gain of a first driver stage 206 may change an input impedance of the amplifier chain 200. Accordingly, it may be more efficient to change an intermediate stage as better shown in amplifier chain 250 of Figure 2B. Much of the amplifier chain 250 is identical to the amplifier chain 200, so discussion of repeated elements is omitted. The amplifier chain 250 includes a first driver stage 252 and an intermediate driver stage 254. The control loop 220 adjusts the gain of the intermediate driver stage 254. This avoids changing the input impedance excessively and allows smoother operation.

[0044] Note further that while the compression is a function of the supply voltage, the load voltage standing wave ratio (VSWR), process variations, temperature variations and potentially other variables, the compression compensation of the present disclosure is self-aligning in that, regardless of the source of the compression, once the compression detection circuit 214 detects compression, compensation begins, thereby subsuming all the other variables.

[0045] With that introduction, various permutations are now presented. In this regard, Figure 3 illustrates an amplifier chain 300 that has both amplitude compression compensation and phase modulation compensation. As a note of nomenclature, amplitude modulation-amplitude modulation (AM-AM) compensation is based on compensating the gain (amplitude) based on an amplitude of the output. Similarly, AM- phase modulation (AM-PM) is based on compensating the phase based on the amplitude of the output.

[0046] With continued reference to Figure 3, the amplifier chain 300 has an input node 302 and an output node 304. An adjustable driver stage 306 is serially positioned before an output stage 308. Optionally, additional stages may be present before the adjustable driver stage 306 at position 310A or between the adjustable driver stage 306 and the output stage 308 at position 310B. An inter-stage match circuit 312 may beRef. No. P241491-WO-UTL positioned between the adjustable driver stage 306 and the output stage 308. A compression detection circuit 314 detects the voltage level (generally at 314A). This detected voltage is compared to a threshold by a comparator 314B. When the threshold is exceeded, a detection circuit 314C generates an output signal 316, which is received by a variable common slope control circuit 318. The threshold and slope are controlled by a control circuit (not shown) analogous to the control circuit 224.

[0047] The amplifier chain 300 has two feedback loops. In this regard, an AM-AM control loop 320 is substantially similar to the gain control loop 220. However, the variable common slope control circuit 318 also provides a signal to the AM- PM control loop 322. The AM-PM control loop 322 controls an AM-PM correction circuit 324. In an exemplary aspect, the AM-PM correction circuit 324 uses varactors to provide the phase adjustment. More details are provided below with reference to Figure 7.

[0048] It should be appreciated that most times when the gain is changed at an amplifier stage, the impedance changes, which in turn may be associated with a capacitance change. Such a capacitance change may create a phase compression. The AM-PM control loop 322 helps offset this induced phase compression. Note that because the phase compression (and subsequent correction) is a function of the AM compression correction, the phase compression compensation is also self-aligned.

[0049] Figure 4 illustrates an amplifier chain 400 that is similar to amplifier chain 300 but has two compression detector circuits 402, 404. The compression detector circuit 402 uses a first threshold from the control circuit (not shown) to initiate compensation of amplitude compression with the AM-AM control loop 320, and the compression detector circuit 404 uses a second threshold from the control circuit to initiate compensation of phase compression with the AM-PM control loop 322. Note that this may also result in splitting the common slope control circuit 318 into an AM-AM slop control circuit 406 and an AM-PM slope control circuit 408.

[0050] Instead of controlling gain and phase with the two compression detectors, it may instead be possible to change the gain function based on different thresholds detected by the two compression detectors. That is, where the compression function is, for example, non-mono tonic, it may be able to detect the first threshold using the first compression detector and use a first gain function but turn that gain function off when the second threshold is detected at the second compression detector. Still, other multi-Ref. No. P241491-WO-UTL compression detector arrangements are possible (multiple threshold detectors and gain / phase detectors).

[0051] The above discussion has been silent on the nature of the amplifier stages in terms of single-ended versus differential-ended. In many cases, the inputs and outputs are single-ended, but there are advantages to having the internal stages of an amplifier chain be differential-ended. The present disclosure is readily suited for use in either situation, as illustrated in Figures 5A & 5B. That is, an amplifier chain 500A illustrated in Figure 5A may have a single-ended input node 502 and a single-ended output node 504. An input match circuit 506 may couple a driver stage 508 to the input node 502. The driver stage 508 may be single-ended as well and may have its gain controlled by an AM- AM control loop 510. Optionally, there may be an AM-PM control loop as well. A first balun or transformer 512 converts an output of the driver stage 508 to a differential signal for an output stage 514. A compression detection circuit 518 may detect compression for triggering the AM- AM control loop 510. A second balun or transformer 520 converts the signal back to a single-ended signal for the output node 504.

[0052] Note that the compression detection circuit 518 may measure signals on both parts of the differential output stage 514. Note also that there may be other intermediate driver stages (not shown), or the driver stage 508 may be an intermediate driver stage (analogous to the driver stage 254).

[0053] In contrast, Figure 5B illustrates an amplifier chain 500B that places a balun 530 in front of a differential adjustable driver stage 508’ and moves the matching circuit to an inter-stage matching circuit 532. Additionally, the AM-AM control loop 534 (and optional AM-PM control loop) provides a differentia] signal to adjust the gain of the differential adjustable driver stage 508’.

[0054] Figures 6A-6C provide some exemplary ways to implement the gain adjustment for the driver stage. These are not meant to be exhaustive but reflect the flexibility of the present disclosure. In this regard, Figure 6A illustrates a driver stage 600 that may be used for driver stage 206, 254, 306, 508, or the like. Specifically, the driver stage 600 includes a transconductance transistor 602 coupled to an input 601 with cascoded transistors 604(1 )-604(N). A degenerative resistive transistor 606 is coupled to the gain control loop circuit 608, and adjustments at a gate 606G of the degenerative resistive transistor 606 adjust the overall gain generated at output 610. The transistorsRef. No. P241491-WO-UTL602, 604(l)-604(N), and 606 are all field effect transistors (FETs) and, more specifically, n-type FETs (NFETs).

[0055] In contrast, a driver amplifier 620 in Figure 6B may include inputs 622A, 622B, and an output 624. The input 622A is associated with a first NFET transconductance FET 626 and one or more cascode NFETs 628 (only one shown). A first degenerative resistive NFET 630 coupled the first NFET transconductance FET 626 to ground and is responsive to the gain control loop circuit 632. The gain control loop circuit 632 also controls a second degenerative resistive p-type FET 634 associated with the input 622B. The input 622B is associated with a second PFET transconductance FET 636 and one or more cascode PFETs 638 (only one shown). Thus, the driver amplifier 620 may be considered a complementary stack.

[0056] Another illustrated option is the differential driver amplifier 650 in Figure 6C. The differential driver amplifier 650 may include inputs 652+ and 652- as well as outputs 654+, 654-. The input 652+ is associated with transconductance NFET 656+, while the input 652- is associated with transconductance NFET 656-. Each transconductance NFET 656+, 656- is associated with cascode NFETs 658+, 658-, respectively, and degenerative resistive NFETs 660+, 660-, respectively. A gain control circuit 662 controls the degenerative resistive NFETs 660+, 660-.

[0057] Note that it is possible to have a complementary differential driver, a bipolar technology-based driver, a differential bipolar driver, a hybrid bipolar- FET driver, or the like (none illustrated) without departing from the present disclosure.

[0058] Figure 7 inserts the structure of the driver amplifier 600 into an amplifier chain 700 as well as provides additional details about the phase (AM-PM) correction circuit 324. In this regard, the amplifier chain 700 has an input node 702 and an output node 704. The driver amplifier 600 acts as a driver stage and may be coupled to the input node 702 through a blocking capacitor 706. A bias circuit 708 may bias the input 601 of the driver amplifier 600. Further, the AM-PM correction circuit 324 may be coupled to the input 601. The AM-PM correction circuit 324 may include a varactor 710 having a bias resistor 712 and a filter capacitor 714 that blocks RF signals. An AM-PM slope control circuit 716 couples to the bias resistor 712. The slope control circuit 608 couples to the degenerative resistive NFET 606 to control the gain of the driver amplifier 600. As illustrated, the output stage 718 may be a bipolar junction transistor (BJTs) 720 makingRef. No. P241491-WO-UTL the amplifier chain 700 a hybrid device (i.e., FETs and BJTs). Compression detectors 722, 724 couple to the control circuits 608, 716, respectively.

[0059] Relevantly, neither a bias (not shown) for the output stage 718, nor the bias 708 for the driver amplifier 600 is modified responsive to detection of the compression.

[0060] A process 800 for compensating for compression in an amplifier chain is set forth with reference to Figure 8. In this regard, the process 800 begins by setting the threshold(s) (block 802). These thresholds may be set from information stored in a memory and based on information received by a control circuit through a bus interface. One or more compression detectors detect compression at an output stage of the amplifier chain using the threshold(s) (block 804). This detection may be done using a comparator. Responsive to threshold detection, a gain at a driver stage of the amplifier chain is changed (block 806). Optionally, a phase at the driver stage is also changed as a function of the change in the gain (block 808).

[0061] As mentioned above, the discussion of Figures 2A-8 contemplates a singlepath amplifier chain and avoids the use of a bias circuit to improve the linearity of the output stage. However, the present disclosure also contemplates using compression detection with a Doherty amplifier, and, in part, because of the dual path nature of the Doherty amplif ier, there are aspects where the use of a bias circuit adjustment may further improve the linearity of the amplifier chain. Specifically, many Doherty amplifiers use a soft activation of a peaking path through a bias circuit to prevent a large non-linearity when the peaking path is activated. While gradual activation may avert non-linearities, the gradual activation is not efficient. Additionally, the peaking path has no information about supply voltages or load conditions, and performance may be negatively impacted by variations in supply voltages or load conditions.

[0062] In this regard, Figure 9 illustrates a Doherty amplifier chain 900 that has a main path 902 and a peaking path 904 between an input node 906 and an output node 908. The Doherty amplifier chain 900 may be implemented in a front-end module (FEM) 910 or the like. The main path 902 has, for the purposes of the current discussion, a main driver amplifier 912, a main output amplifier 914, a main bias circuit 916, and a phase shifter impedance 918. It should be appreciated that other elements, not shown, may be present in the main path without departing from the present disclosure. For example, a second driver amplifier (between the main driver amplifier 912 and the main output amplifier 914) may be present. The phase shifter impedance 918 may shift the phase ofRef. No. P241491-WO-UTL an amplified signal by ninety degrees to phase align with the peaking path at the output node 908 as is well understood.

[0063] With continued reference to Figure 9, the peaking path 904 includes a peaking phase shifter impedance 920 that shifts the signal on the peaking path by 90 degrees. The peaking path 904 also includes a peaking driver amplifier 922, a peaking output amplifier 924, and a peaking bias circuit 926. The output of the peaking output amplifier 924 couples to the output node 908. Again, there may be other elements, not shown, such as an intermediate driver amplifier.

[0064] As is customary with Doherty amplifiers, the Doherty amplifier chain 900 initially operates using just the main path 902, but once a desired output signal exceeds a certain threshold, the peaking path 904 is turned on, and its amplification is added to the amplification of the main path 902 at the output node 908. Supply voltages for the output amplifiers 914, 924 may be generated and supplied by a power management integrated circuit (PMIC) 926 based on information received from a remote source (e.g., a baseband processor (BBP) through a bus such as a radio frequency front end (RFFE) bus).

[0065] As noted above, at certain points, output amplifiers such as main output amplifier 914 will experience some compression as power levels increase. This compression means that the amplifier chain will operate non-linearly, which is undesirable. The discussion above provides insight into how this non-linearity may be addressed, however, that discussion did not have the complications of the two paths.

[0066] Accordingly, aspects of the present disclosure provide a way to offset compression in a Doherty amplifier. In this regard, a first detector 928 and a second detector 930 may be provided at node 932 at the output of the main output amplifier 914 (and before the phase shifter impedance 918). The first detector 928, may be a saturation detector or a compression detector, as previously described, and may provide a feedback signal that causes an adjustment in the gain of the peaking driver amplifier 922. In an exemplary aspect, the peaking path 904 activation tracks the point at which compression starts in the main path 902. In essence, the compression is offset by the activated peaking path 904.

[0067] The second detector 930, may be a saturation detector or compression detector, and may provide a feedback signal that causes an adjustment in the gain of the main driver amplifier 912. As explained above, changing the gain of the driver amplifier is a more efficient mechanism (compared to changing a bias) to change an input to theRef. No. P241491-WO-UTL output amplifier to offset compression. In an exemplary aspect, it is appropriate for the main path 902 to contribute more power after the compression of the main path 902 begins. Thus, the main driver amplifier 912 is adjusted to increase gain based on the second threshold, albeit with a higher slope such that the main output amplifier 914 is “pushed” harder with a larger RF signal after the initial compression.

[0068] Activating the peaking output amplifier 924 using a boosted peaking driver amplifier 922 is more efficient than boosting the bias of the peaking output amplifier 924. Further, the peaking output amplifier 924 has a much lower gain control dynamic range when compared to a relatively lower power peaking driver amplifier 922. Thus, when the first detector 928 detects compression or saturation above a first threshold, a seep peaking path activation is applied to the peaking driver amplifier 922. At a second threshold, the main driver amplifier 912 may be adjusted to adjust an input to the main output amplifier 914. This adjustment allows the main output amplifier 914 to be more efficient, helping overall efficiency. In specifically contemplated aspects, the second threshold is greater than the first threshold such that changes to the main path occur after activation of the peaking path. However, the slope control applied to the main driver amplifier 912 may have a higher slope of control. This will keep the main path 902 pushing more output power after a “soft” compression point, where “soft” as used herein is a less than 20% compression.

[0069] Further, aspects of the present disclosure may omit the second detector 930 and the adjustment to the main driver amplifier 912. However, this omission results in an overall less efficient system.

[0070] To help mitigate non-linearities caused by the steep activation, the second feedback path adjusting the gain of the main driver amplifier 912 is used. In particular, the gain is adjusted to mitigate the ripple at the peaking path 904 activation. Using both feedback loops allows the overall linearity of the Doherty amplifier chain 900 to meet current cellular standards without need for digital predistortion in the BBP. Accordingly, costs may be reduced.

[0071] It should further be appreciated that to achieve high efficiency, the peaking path 904 may initially be biased deep in class-C at low power levels. Having the peaking path 904 completely off may create undesirable performance since the capacitive basecollector (CBC) Miller effect on the peaking output amplifier 924 will result in a large impedance change and thus a large loading change, which will negatively affect linearity.Ref. No. P241491-WO-UTLAccordingly, a small RF signal may be maintained in the peaking path 904 to balance the RF current needed to avoid the Miller effect. Then, when the path is activated, the steep slope makes the amplifiers 922, 912 to move to class-B or class- AB quickly.

[0072] While not shown, the thresholds and slopes of the gain control can be set based on signals from a control circuit. Further, these settings may be adjusted based on band of operation, supply voltages, process variations, temperature variations, or the like as described above. Note that if DPD is available, the need for precise calibration of thresholds and gain control slopes may be relaxed, but that is a design choice.

[0073] Unlike the discussion for Figures 2A-8, aspects of the present disclosure may also use the bias circuits 916 and 926 to assist in supporting linear operation. Thus, Figure 10 illustrates a Doherty amplifier chain 1000 that is similar to Doherty amplifier chain 900, but the detector 928 may also provide control signals to bias circuits 916, 926 causing the bias circuits 916, 926 to adjust bias signals provided to the respective output amplifiers 914, 924. This sort of bias-kicking will extend the saturation / compression of both the main output amplifier 914 and the peaking output amplifier 924. Note also that this biaskicking (for both bias circuits 916, 926) is aligned with the first compression threshold by virtue of the first detector 928 having that threshold.

[0074] The above discussion of Doherty amplifier chains has ignored the distinctions between single-ended and differential-ended elements within the chains. However, as with Figures 5 A and 5B, there may be instances where having one or more elements be differential-ended helps designers. Accordingly, aspects of the present disclosure are applicable to the aforedescribed monolithic single-ended structures, a single-ended main path 902 and a different! al -ended peaking path 904, or having both paths be differential- ended. It is also possible to have some stages in a given path be single-ended and others of that same path be differential-ended with an inter-stage balun for conversion.

[0075] One exemplary structure including a differential-ended element is Doherty amplifier chain 1100 illustrated in Figure 11 where the peaking path is differential-ended. In this regard, the Doherty amplifier chain 1100 has a main path 1102 and a peaking path 1104 between an input node 1106 and an output node 1108. The main path 1102 has, for the purposes of the current discussion, a main driver amplifier 1112, a main output amplifier 1114, a main bias circuit 1116, and a phase shifter impedance 1118.

[0076] A splitter and phase shifter 1110 may be positioned between the input node 1106 and the main path 1102 and peaking path 1104. The splitter and phase shifter 1110Ref. No. P241491-WO-UTL provides a single-ended signal that is not shifted to the main path 1102 and a split and phase shifted differential signal to the peaking path 1104.

[0077] With continued reference to Figure 11, the peaking path 1104 includes a two peaking driver amplifiers 1122A, 1122B, two peaking output amplifiers 1124A, 1124B, and a peaking bias circuit 1126. The output of the peaking output amplifiers 1124A, 1124B couples to a balun 1120 the output node 1108. The output node 1108 combines the two single-ended signals. In this way, the main path 1102 only goes through the phase shifter impedance 1118 and avoids a double insertion loss penalty of a balun in the main path 1102. The balun 1120 may impose a substantial delay and the input lines are swapped at 1 140 to provide an additional delay to ensure an overall 360 degree phase shift from the input to the output so that the phases are properly aligned.

[0078] Detectors 1128, 1130 are on the single-ended node 1132 and function substantially similar to the detectors 1128, 1130, but do control the gains of both peaking driver amplifiers 1122 A, 1122B.

[0079] Figures 9-11 all contemplate bipolar junction transistors (BJTs) as at least the output amplifiers. However, the present disclosure is not limited to BJT technology and metal oxide semiconductor (MOS) or more specifically complementary MOS technology may be used. Likewise, a hybrid BJT-CMOS amplifier chain may be formed. One exemplary hybrid is an output stage (i.e., output amplifiers 914, 924) being formed in gallium arsenide (GaAs) or other bipolar process and the front-side (i.e., driver amplifiers 912, 922) being implemented in CMOS. When the structure is this sort of hybrid technology, the feedback loops from the detectors 928, 930 will have to leave the bipolar die and travel to an input of the CMOS die so that all needed digital adjustments for the threshold and slopes may be done in the CMOS die. When a monolithic technology is used (e.g., all bipolar or all CMOS), the control voltages for the driver amplifiers will be inside the FEM 910 without need for out-of-die routing. Some bipolar processes (e.g., SiGe BiCMOS or GaAs BiFET) allow for integration of digital control. However, other bipolar processes do not digital circuitry support and cannot easily implement tunability and adjustability control.

[0080] The Doherty amplifier chain 1100 is expanded in Figure 12 showing how part of the Doherty amplifier chain 1100 may be CMOS 1200 and part bipolar 1202. Further, the output amplifiers 1114, 1124A, 1124B are implemented as two stage amplifiers withRef. No. P241491-WO-UTL emitter followers to minimize the Cbc Miller effect when the peaking path 1104 gets activated.

[0081] In addition to the gain control techniques illustrated in Figures 6A-6C, the present disclosure also contemplates a differential-ended driver stage that uses subtraction of the opposite polarity signal as better illustrated in Figure 13. More particularly, a driver amplifier 1300 has differential inputs 1302A, 1302B and differential outputs 1304A, 1304B. Each side has cascoded FETs 1306A, 1306B controlled by a bias circuit 1308. The bias circuit 1308 also biases transconductance FETs 1310A, 1310B. However, instead of degenerative resistive transistor 606, mirrored FETs 1312A, 1312B pull signals from the other side to change the gain of the corresponding FETs 1310A, 1310B.

[0082] A process 1400 for controlling a Doherty amplifier chain is set forth with reference to Figure 14. The process begins by setting the first threshold (block 1402) and the second threshold (block 1404) corresponding to the compression points to be detected by the detectors 928, 930 respectively. The first detector 928 detects the first threshold (block 1406). Responsive to the detecting of the first threshold, the peaking path 904 is activated by changing the gain at the peaking driver amplifier 922 (block 1408). Optionally, this detection may also activate the bias-kick (block 1410). On detection of the second threshold, the gain on the main driver amplifier 912 is adjusted (block 1412).

[0083] The power amplifier compression compensation circuit, according to aspects disclosed herein, may be provided in or integrated into any processor-based device that includes a power amplifier chain, such as may occur in a communication circuit. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0084] Figure 15 is a schematic diagram of an exemplary communication device 1500 wherein the power amplifier compression compensation circuit can be provided. Herein,Ref. No. P241491-WO-UTL the communication device 1500 can be any type of communication devices, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0085] More particularly, the communication device 1500 will generally include a control system 1502, a baseband processor 1504, transmit circuitry 1506, receive circuitry 1508, antenna switching circuitry 1510, multiple antennas 1512, and user interface circuitry 1514. In a non-limiting example, the control system 1502 can be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1502 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1508 receives radio frequency signals via the antennas 1512 and through the antenna switching circuitry 1510 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1508 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0086] The baseband processor 1504 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1504 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0087] For transmission, the baseband processor 1504 receives digitized data, which may represent voice, data, or control information, from the control system 1502, which it encodes for transmission. The encoded data is output to the transmit circuitry 1506, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier, which may be a power amplifier chain with a compression compensation circuit as described above, will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1512 through the antenna switching circuitry 1510 to theRef. No. P241491-WO-UTL antennas 1512. The multiple antennas 1512 and the replicated transmit and receive circuitries 1506, 1508 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0088] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0089] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 25 Jul 2025(25.07.2025)What is claimed is:

1. (Previously Presented) A Doherty amplifier chain comprising: a main path comprising: a main driver stage; and a main output stage; a peaking path comprising: a peaking driver stage; and a peaking output stage; a compression detector coupled to the main output stage and configured to detect when an output signal crosses a threshold indicating compression is occurring; and a gain control circuit coupled to the compression detector and the peaking driver stage, the gain control circuit configured to adjust a gain of the peaking driver stage responsive to detection that compression is occurring; and a first bias circuit coupled to the main output stage, wherein the first bias circuit is configured to adjust a bias for the main output stage responsive to the compression occurring.

2. (Original) The Doherty amplifier chain of claim 1, further comprising a second compression detector coupled to the main output stage and configured to detect when the output signal crosses a second threshold; and a main gain control circuit coupled to the second compression detector and the main driver stage.

3. Canceled4. (Previously Presented) The Doherty amplifier chain of claim [[3]] j_, further comprising: a second bias circuit coupled to the peaking output stage, wherein the second bias circuit is configured to adjust a second bias for the peaking output stage responsive to the compression occurring.AMENDED SHEET (ARTICLE 19)5. (Original) The Doherty amplifier chain of claim 1, further comprising a control circuit coupled to the compression detector, wherein the control circuit is configured to set the threshold for the compression detector based at least in part on information received through a bus interface.

6. (Original) The Doherty amplifier chain of claim 5, wherein the control circuit is further configured to provide a slope control value for the gain control circuit.

7. (Original) The Doherty amplifier chain of claim 1, wherein the main driver stage comprises a plurality of field effect transistors (FETs), and the main output stage comprises a bipolar junction transistor (BJT).

8. (Original) The Doherty amplifier chain of claim 1, wherein the peaking output stage comprises a differential amplifier.

9. (Original) The Doherty amplifier chain of claim 7, wherein the peaking driver stage comprises a differential driver amplifier.

10. (Original) The Doherty amplifier chain of claim 1, further comprising a phase control loop circuit coupled to the compression detector, wherein the phase control loop circuit is configured to adjust a phase of the peaking driver stage responsive to the compression occurring.

11. (Previously Presented) A communication device comprising: transmit circuitry comprising: a baseband processor; a Doherty amplifier chain communicatively coupled to the baseband processor, the Doherty amplifier chain comprising the Doherty amplifier chain of claim 1.: a main path comprising: a main driver stage; andAMENDED SHEET (ARTICLE 19)a main output stage; a peaking path comprising: a peaking driver stage; and a peaking output stage; a compression detector coupled to the main output stage and configured to detect when an output signal crosses a threshold indicating compression is occurring; and a gain control circuit coupled to the compression detector and the peaking driver stage, the gain control circuit configured to adjust a gain of the peaking driver stage responsive to detection that compression is occurring.

12. (Original) The communication device of claim 11, further comprising a second compression detector coupled to the main output stage and configured to detect when the output signal crosses a second threshold; and a main gain control circuit coupled to the second compression detector and the main driver stage.

13. Canceled14. (Previously Presented) The communication device of claim [[13]] 11, further comprising: a second bias circuit coupled to the peaking output stage, wherein the second bias circuit is configured to adjust a second bias for the peaking output stage responsive to the compression occurring.

15. (Original) The communication device of claim 11 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer;AMENDED SHEET (ARTICLE 19)a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

16. (Previously Presented) A method of controlling an amplifier chain, comprising: detecting compression at a main output stage of a Doherty amplifier chain; and responsive to detecting compression, adjusting a gain of a peaking driver stage in the Doherty amplifier chain detecting a second compression at the main output stage; and responsive to detecting the second compression, adjusting a gain of a main peaking driver stage in the Doherty amplifier chain.

17. Canceled18. (Original) The method of claim 16, further comprising, responsive to detecting compression, adjusting a bias-kick for a main output stage.

19. (Previously Presented) The method of claim [[17]] 16, further comprising adjusting a phase of the peaking driver stage responsive to detecting compression.

20. (Previously Presented) The method of claim [[17]] 16, further comprising setting a threshold indicative of compression based on information received through a bus interface.STATEMENT UNDER ARTICLE 19(1)Applicant herein amends claim 1 to include claim 3. Support for this can be found in claim 3.Applicant amends claim 11 to depend from claim 1 responsive to Item VIII.Claim 13 is canceled as redundant.Claim 16 is amended to include claim 17. Support for this can be found in claim 17.Claims 4, 14, and 19-20 are amended to correct dependencies in light of the cancellation of claims 3, 13, and 17.If you have any questions, please do not hesitate to contact me.

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