Display substrate and driving method therefor, and display device

Abstract

A display substrate and a driving method therefor, and a display device. The display substrate comprises a plurality of circuit units. Each circuit unit at least comprises a pixel driving circuit. The pixel driving circuit at least comprises a first capacitor (C1), a second capacitor (C2), a first transistor (T1), a third transistor (T3), an eighth transistor (T8), and a ninth transistor (T9). A second electrode of the first transistor (T1) is separately connected to a gate electrode of the third transistor (T3) and a first end of the first capacitor (C1). A first electrode of the ninth transistor (T9) is separately connected to a second end of the first capacitor (C1) and a second end of the second capacitor (C2). A second electrode of the ninth transistor (T9) is separately connected to a first electrode of the third transistor (T3) and a second electrode of the eighth transistor (T8).

Description

Display substrate, driving method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a driving method thereof and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and signal control by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, a second electrode of the first transistor being connected to a gate electrode of the third transistor and a first end of the first capacitor respectively, a first electrode of the ninth transistor being connected to a second end of the first capacitor and a second end of the second capacitor respectively, a second electrode of the ninth transistor being connected to a first electrode of the third transistor and a second electrode of the eighth transistor respectively, a first electrode of the fourth transistor being connected to a data signal line.

[0006] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor being connected to the second electrode of the first transistor, the gate electrode of the third transistor and the first end of the first capacitor respectively, and a second electrode of the second transistor being connected to the second electrode of the third transistor.

[0007] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor being connected to a second initial signal line, and a second electrode of the second transistor being connected to the second electrode of the third transistor.

[0008] In an exemplary embodiment, the first transistor and the second transistor are connected to the same scan signal line.

[0009] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate comprises at least a first gate metal layer disposed on a base, a second gate metal layer disposed on a side of the first gate metal layer away from the base, and a first source-drain metal layer disposed on a side of the second gate metal layer away from the base, the gate electrode of the first transistor and the gate electrode of the second transistor are disposed in the first gate metal layer, and the scan signal line is disposed in the first source-drain metal layer.

[0010] In an exemplary embodiment, the gate electrode of the first transistor and the gate electrode of the second transistor are an integrated structure connected to each other.

[0011] In an exemplary embodiment, the first transistor and the second transistor are double-gate structures, the gate electrode of the first transistor comprises a first sub-gate electrode and a third sub-gate electrode, the gate electrode of the second transistor comprises a second sub-gate electrode and a third sub-gate electrode, and the first transistor and the second transistor share the third sub-gate electrode.

[0012] In an exemplary embodiment, the first sub-gate electrode and the second sub-gate electrode are in the shape of a strip extending along a first direction, the third sub-gate electrode is in the shape of a strip extending along a second direction, the first direction and the second direction intersect, the first sub-gate electrode and the second sub-gate electrode are disposed on one side of the third sub-gate electrode in the first direction, the first sub-gate electrode is disposed on one side of the third sub-gate electrode in the opposite direction of the second direction, and the second sub-gate electrode is disposed on one side of the third sub-gate electrode in the second direction, forming a “C” shape.

[0013] In an exemplary embodiment, the second electrode of the fourth transistor is connected to the first electrode of the ninth transistor, or the second electrode of the fourth transistor is connected to the second electrode of the ninth transistor.

[0014] In an exemplary embodiment, the first electrode of the first transistor is connected to a first initial signal line, the pixel driving circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, the second electrode of the seventh transistor is connected to the light emitting device, and the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the unit row are connected to the first scan signal line in the unit row.

[0015] In an exemplary embodiment, the first electrode of the first transistor is connected with a first initial signal line, and the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with a second initial signal line and a first electrode of the first transistor respectively, and a second electrode of the seventh transistor is connected with the light emitting device; a gate electrode of the seventh transistor of the circuit unit in the present unit row is connected with a first scan signal line in the next unit row, and a gate electrode of the eighth transistor of the circuit unit in the present unit row is connected with the first scan signal line in the present unit row.

[0016] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with a second initial signal line and a first electrode of the first transistor respectively, and a second electrode of the seventh transistor is connected with the light emitting device; a gate electrode of the seventh transistor and a gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row.

[0017] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with a second initial signal line and a first electrode of the first transistor respectively, and a second electrode of the seventh transistor is connected with the light emitting device; a gate electrode of the seventh transistor of the circuit unit in the present unit row is connected with a first scan signal line in the next unit row, and a gate electrode of the eighth transistor of the circuit unit in the present unit row is connected with the first scan signal line in the present unit row.

[0018] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0019] In yet another aspect, the present disclosure also provides a driving method of a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, a second electrode of the first transistor being connected with a gate electrode of the third transistor and a first terminal of the first capacitor respectively, a first electrode of the ninth transistor being connected with a second terminal of the first capacitor and a second terminal of the second capacitor respectively, a second electrode of the ninth transistor being connected with a first electrode of the third transistor and a second electrode of the eighth transistor respectively, and a first electrode of the fourth transistor being connected with a data signal line; the display substrate being configured to display a corresponding display content, the display content comprising a plurality of display frames, at least one display frame comprising a refresh frame, the refresh frame comprising at least a compensation phase and a data writing phase in sequence, and the compensation phase being performed by a threshold voltage sampling in a capacitor self-discharge manner.

[0020] In an exemplary embodiment, the refresh frame comprises at least an initialization stage, a compensation stage and a data writing stage.

[0021] In the initialization stage, the eighth transistor and the ninth transistor are turned on, a third initial signal of a third initial signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor, and the second capacitor is charged.

[0022] In the compensation stage, the first transistor is turned on, the gate electrode of the third transistor is initialized, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor and the turned-on third transistor, so that the voltage difference across the first capacitor is |Vth|, and Vth is the threshold voltage of the third transistor.

[0023] In the data writing stage, the fourth transistor is turned on, and a data signal of the data signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor.

[0024] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected with the second electrode of the first transistor, the gate electrode of the third transistor and the first terminal of the first capacitor respectively, and a second electrode of the second transistor is connected with the second electrode of the third transistor; in the compensation stage, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor and the turned-on second transistor.

[0025] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected with a second initial signal line, and a second electrode of the second transistor is connected with the second electrode of the third transistor; in the compensation stage, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor and the turned-on second transistor.

[0026] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with a second initial signal line, and a second electrode of the seventh transistor is connected with the light emitting device; in the initialization stage, the seventh transistor is turned on, and a second initial signal of the second initial signal line initializes the light emitting device, or, in the compensation stage, the seventh transistor is turned on, and a second initial signal of the second initial signal line initializes the light emitting device.

[0027] In an exemplary embodiment, the at least one display frame further comprises a holding frame, and the holding frame comprises at least an adjustment stage.

[0028] In the adjusting stage, the eighth transistor is turned on, and a third initial signal of the third initial signal line is written to the first electrode of the third transistor to adjust the bias state of the third transistor.

[0029] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected with a second initial signal line, and a second electrode of the seventh transistor being connected with the light emitting device; in the adjusting stage, the seventh transistor is turned on, and a second initial signal of the second initial signal line is used to initialize the light emitting device.

[0030] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and are not intended to limit the present disclosure.

[0032] FIG. 1 is a structural schematic diagram of a display device;

[0033] FIG. 2 is a plan structural schematic diagram of a display substrate;

[0034] FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0035] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0036] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4;

[0037] FIG. 6 is a plan structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0038] FIG. 7 is a structural schematic diagram of a first transistor and a second transistor according to an exemplary embodiment of the present disclosure;

[0039] FIG. 8 is a schematic diagram of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0040] FIG. 9A and FIG. 9B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0041] FIG. 10A and FIG. 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0042] FIG. 11 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0043] FIG. 12A and FIG. 12B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0044] FIG. 13 is a schematic view of a display substrate after forming a first planarization layer pattern according to the present disclosure;

[0045] FIGS. 14A and 14B are schematic views of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0046] FIG. 15 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0047] FIG. 16 is a schematic view of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG. 17 is a schematic view of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0049] FIGS. 18A and 18B are schematic views of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0050] FIGS. 19A and 19B are schematic views of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0051] FIG. 20 is a schematic view of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0052] FIGS. 21A and 21B are schematic views of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0053] FIG. 22 is a schematic view of a display substrate after forming a first planarization layer pattern according to the present disclosure;

[0054] FIGS. 23A and 23B are schematic views of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0055] FIG. 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0056] FIG. 25 is a schematic view of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0057] FIG. 26 is a schematic view of a display substrate after forming a semiconductor layer pattern according to the present disclosure;

[0058] FIGS. 27A and 27B are schematic views of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0059] FIGS. 28A and 28B are schematic views of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0060] FIG. 29 is a schematic view of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0061] FIGS. 30A and 30B are schematic views of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0062] FIG. 31 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0063] FIG. 32 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0064] FIG. 33 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0065] FIG. 34 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0066] FIG. 35 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0067] FIG. 36 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0068] Explanation of reference signs: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 19-ninth active layer; 21-first gate electrode; 22-second gate electrode; 24-fourth gate electrode; 27-seventh gate electrode; 28-eighth gate electrode; 29-ninth gate electrode; 30-gate connecting line; 31-first scan signal line; 32-second scan signal line; 33-third scan signal line; 34-fourth scan signal line; 35-emitting signal line; 36-power supply connecting line; 41-first connecting electrode; 42-second connecting electrode; 43-third connecting electrode; 44-fourth connecting electrode; 45-fifth connecting electrode; 51-first power line; 52-data signal line; 53-anode connecting electrode; 71-first pole plate; 72-second pole plate; 73-third pole plate; 74-fourth pole plate; 75-first opening; 76-second opening; 81-first initial signal line; 82-second initial signal line; 83-third initial signal line; 84-first initial connecting line; 85-second initial connecting line; 86-third initial connecting line; 101-substrate; 102-driving circuit layer; 103-emitting structure layer; 104-encapsulation structure layer. DETAILED DESCRIPTION

[0069] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0070] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0071] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limited in terms of numbers.

[0072] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0073] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0074] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0075] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0076] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0077] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0078] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0079] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, and can have some small deformation due to a tolerance, a rounded corner, a rounded side, or the like.

[0080] In this specification, "about" means not strictly limited to the limit, and a value within a range of process and measurement error is allowed.

[0081] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, an emission driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the emission driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the emission driver is connected with a plurality of emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and an emission unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the emission signal line, and the data signal line respectively, and the emission unit can include an emission device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the emission driver to the emission driver. The data driver can generate a data voltage to be provided to the data signal lines DATA1, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines DATA1 to Dn in a unit of a pixel row. n can be a natural number. The scan driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The emission driver can generate an emission signal to be provided to the emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the emission driver can sequentially provide the emission signal having an off-level pulse to the emission signal lines E1 to Eo. For example, the emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0082] FIG. 2 is a schematic diagram of a planar structure of a display substrate. In an example embodiment, the display substrate can include a display area and a frame area located at a periphery of the display area. As shown in FIG. 2, the display area of the display substrate can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel can include a circuit unit and a light emitting unit, and the circuit unit can include at least a pixel driving circuit, the pixel driving circuit being connected with a scan signal line, a data signal line and a light emitting signal line respectively, and the pixel driving circuit being configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to a light emitting device. The light emitting unit can include at least a light emitting device, the light emitting device being connected with the pixel driving circuit of the sub-pixel where the light emitting device is located, and the light emitting device being configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light emitting device is located.

[0083] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0084] In an example embodiment, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0085] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display area of the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0086] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, which can at least include a pixel driving circuit, and the pixel driving circuit can include a plurality of transistors and a capacitor. The light emitting structure layer 103 can include a plurality of light emitting units, which can at least include a light emitting device, and the light emitting device can include an anode, an organic light emitting layer, and a cathode, the anode is connected with the pixel driving circuit, the organic light emitting layer is connected with the anode, and the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer can adopt inorganic materials, the second encapsulation layer can adopt an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.

[0087] An example embodiment of the present disclosure provides a display substrate, which includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit configured to output a driving current to a connected light emitting device; the pixel driving circuit at least including a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, a second electrode of the first transistor being connected with a gate electrode of the third transistor and a first end of the first capacitor respectively, a first electrode of the ninth transistor being connected with a second end of the first capacitor and a second end of the second capacitor respectively, a second electrode of the ninth transistor being connected with a first electrode of the third transistor and a second electrode of the eighth transistor respectively, and a first electrode of the fourth transistor being connected with a data signal line.

[0088] In an example embodiment, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected with a second electrode of the first transistor, a gate electrode of the third transistor, and the first end of the first capacitor respectively, and a second electrode of the second transistor being connected with a second electrode of the third transistor.

[0089] In another example embodiment, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected with a second initial signal line, and a second electrode of the second transistor being connected with a second electrode of the third transistor.

[0090] In an example embodiment, the first transistor and the second transistor are connected with the same scan signal line.

[0091] In an exemplary embodiment, the gate electrode of the first transistor and the gate electrode of the second transistor are an integrated structure connected to each other.

[0092] In an exemplary embodiment, the first transistor and the second transistor are double-gate structures, the gate electrode of the first transistor includes a first sub-gate electrode and a third sub-gate electrode, the gate electrode of the second transistor includes a second sub-gate electrode and the third sub-gate electrode, and the first transistor and the second transistor share the third sub-gate electrode.

[0093] In an exemplary embodiment, the second electrode of the fourth transistor is connected to the first electrode of the ninth transistor, or the second electrode of the fourth transistor is connected to the second electrode of the ninth transistor.

[0094] The display substrate of the present disclosure is illustrated below through some exemplary embodiments.

[0095] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 4, the pixel driving circuit according to an exemplary embodiment of the present disclosure can be a 9T2C structure, can include 9 transistors (first transistor T1 to ninth transistor T9) and 2 capacitors (first capacitor C1 and second capacitor C2), and is connected to 11 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0096] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 is connected to the second electrode of the fourth transistor T4, the first electrode of the ninth transistor T9, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2, respectively.

[0097] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the fifth node N5, a first end of the second capacitor C2 is connected to the first power supply line VDD, and a second end of the second capacitor C2 is connected to the fifth node N5.

[0098] In an exemplary embodiment, the first transistor T1 can be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor is connected to the first node N1.

[0099] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the third scan signal line S3, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3.

[0100] In an exemplary embodiment, the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 of the present disclosure are connected to the same third scan signal line S3, and the first transistor T1 and the second transistor T2 are simultaneously turned on and simultaneously turned off.

[0101] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0102] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor, a gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0103] In an exemplary embodiment, the fifth transistor T5 can be referred to as a first light emitting control transistor, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0104] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second light emitting control transistor, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0105] In an exemplary embodiment, the seventh transistor T7 can be referred to as a second initialization transistor, the gate electrode of the seventh transistor T7 is connected with the fifth scan signal line S5, the first electrode of the seventh transistor T7 is connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected with the fourth node N4. In an exemplary embodiment, the fifth scan signal line S5 in one unit row can be the first scan signal line S1 in the next unit row, or the first scan signal line S1 in one unit row can be the fifth scan signal line S5 in the previous unit row.

[0106] In an exemplary embodiment, the eighth transistor T8 can be referred to as a third initialization transistor, the gate electrode of the eighth transistor T8 is connected with the first scan signal line S1, the first electrode of the eighth transistor T8 is connected with the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected with the second node N2.

[0107] In an exemplary embodiment, the ninth transistor T9 can be referred to as a charge-discharge transistor, the gate electrode of the ninth transistor T9 is connected with the second scan signal line S2, the first electrode of the ninth transistor T9 is connected with the fifth node N5, and the second electrode of the ninth transistor T9 is connected with the second node N2.

[0108] In an exemplary embodiment, the light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked. The first electrode of the light emitting device EL is connected with the fourth node N4, and the second electrode of the light emitting device EL is connected with the second power supply line VSS.

[0109] In an exemplary embodiment, the signal of the first power supply line VDD is a high-level signal continuously provided, and the signal of the second power supply line VSS is a low-level signal continuously provided.

[0110] In an exemplary embodiment, the first transistor T1 to the second transistor T2 and the fourth transistor T4 to the ninth transistor T9 are switch transistors.

[0111] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be low-temperature polysilicon transistors (P-type transistors). Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0112] FIG. 5 is a driving timing diagram of the pixel driving circuit shown in FIG. 4. As shown in FIG. 5, taking the first transistor T1 to the ninth transistor T9 as P-type transistors as an example, the working process of the pixel driving circuit can include:

[0113] The first stage A can be called an initialization stage. In this stage, the signals of the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5 and the emitting signal line EM are high level signals, the signals of the first scan signal line S1 and the second scan signal line S2 are low level signals, the eighth transistor T8 and the ninth transistor T9 are turned on, and the other switch transistors are turned off.

[0114] The eighth transistor T8 is turned on to write the third initial signal of the third initial signal line INIT3 to the second node N2, and the ninth transistor T9 is turned on to write the signal of the second node N2 to the fifth node N5, so as to charge the second capacitor C2. Since the eighth transistor T8 and the ninth transistor T9 are completely turned on in the charging path, the charging is completed quickly. When the stage is completed, the potentials of the second node N2 and the fifth node N5 are the voltage Vint3 of the third initial signal.

[0115] The second stage B can be called a compensation stage. In this stage, the signals of the first scan signal line S1, the fourth scan signal line S4 and the emitting signal line EM are high level signals, the signals of the second scan signal line S2, the third scan signal line S3 and the fifth scan signal line S5 are low level signals, the first transistor T1, the second transistor T2, the seventh transistor T7 and the ninth transistor T9 are turned on, and the other switch transistors are turned off.

[0116] The seventh transistor T7 is turned on to write the second initial signal of the second initial signal line INIT2 to the fourth node N4, so as to initialize the fourth node N4 (the emitting device). The first transistor T1 is turned on to write the first initial signal of the first initial signal line INIT1 to the first node N1, so as to initialize the first node N1 (the gate electrode of the third transistor T3 and the first end of the first capacitor C1), and the potential of the first node N1 is the voltage Vint1 of the first initial signal. Since the voltage Vint1 of the first initial signal is low, the third transistor T3 is turned on. The second transistor T2 and the ninth transistor T9 are turned on to discharge the first capacitor C1 and the second capacitor C2 through the turned-on ninth transistor T9, the turned-on third transistor T3 and the turned-on second transistor T2, so that the potential of the fifth node N5 gradually decreases until the third transistor T3 is turned off. When the stage is completed, the voltage difference between the two ends of the first capacitor C1 is |Vth|, the potential of the fifth node N5 is Vint1+|Vth|, and Vth is the threshold voltage of the third transistor T3.

[0117] The third stage C can be called a data writing stage. In this stage, the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fifth scan signal line S5 and the emitting signal line EM are high level signals, the signal of the fourth scan signal line S4 is a low level signal, the fourth transistor T4 is turned on, and the other switch transistors are turned off.

[0118] The fourth transistor T4 is turned on to write the data signal of the data signal line to the fifth node N5. Since the fourth transistor T4 is fully turned on, the data signal is written to the fifth node N5 quickly. When this stage is completed, the voltage difference across the first capacitor C1 is |Vth|, the voltage difference across the second capacitor C2 is VDD-Vdata, and the voltage difference Vsg across the gate electrode and the first electrode of the third transistor T3 is the sum of the voltage differences across the first capacitor C1 and the second capacitor C2, i.e., Vsg=Vdd-Vdata+|Vth|, where Vdata is the voltage of the data signal, and Vdd is the voltage of the first power signal of the first power line VDD.

[0119] The fourth stage D can be referred to as a light emitting stage. In this stage, the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are high level signals, the signal of the light emitting signal line EM is a low level signal, and the fifth transistor T5 and the sixth transistor T6 are turned on, while the other switch transistors are turned off.

[0120] The fifth transistor T5 and the sixth transistor T6 are turned on to enable the first power signal of the first power line VDD to provide a driving current to the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, so as to drive the light emitting device EL to emit light. The driving current is: EL =K(Vsg-|Vth|) 2 =K(Vdd-Vdata+|Vth|-|Vth|) 2 =K(Vdd-Vdata) 2 ;

[0121] where K is a constant related to the process and design.

[0122] The fifth stage E can be referred to as an adjusting stage. In this stage, the signals of the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the light emitting signal line EM are high level signals, the signals of the first scan signal line S1 and the fifth scan signal line S5 are low level signals, and the seventh transistor T7 and the eighth transistor T8 are turned on, while the other switch transistors are turned off.

[0123] The seventh transistor T7 is turned on to write the second initial signal of the second initial signal line INIT2 to the fourth node N4, and the fourth node N4 (the light emitting device) is initialized again. The eighth transistor T8 is turned on to write the third initial signal of the third initial signal line INIT3 to the second node N2 (the first electrode of the third transistor T3), so as to adjust the bias state of the third transistor T3. Since the third transistor T3 (that is, the driving transistor) is in a state for a long time, electrons are trapped in the trap, causing hysteresis. In this stage, by applying a direct current signal to the first electrode of the third transistor T3 and changing the potential of the second node N2, the hysteresis of the driving transistor can be effectively improved, which is beneficial to the improvement of residual image and the support of low-frequency display, and is beneficial to the improvement of display effect.

[0124] In the exemplary embodiment, in this stage, the first scan signal line S1 can change from a high level signal to a low level signal at the first time, and change from a low level signal to a high level signal at the second time, that is, the eighth transistor T8 is turned on at the first time, and is turned off at the second time. The fifth scan signal line S5 can change from a high level signal to a low level signal at the second time, and change from a low level signal to a high level signal at the third time, that is, the seventh transistor T7 is turned on at the second time, and is turned off at the third time. That is, in this stage, the light emitting device is first initialized, and then the bias state of the third transistor T3 is adjusted.

[0125] The sixth stage F can be referred to as the light emitting stage again. In this stage, the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4 and the fifth scan signal line S5 are high level signals, the light emitting signal line EM is a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the other switch transistors are turned off.

[0126] The turned-on fifth transistor T5 and the turned-on sixth transistor T6 enable the first power supply signal of the first power supply line VDD to provide a driving current to the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the turned-on sixth transistor T6, so as to drive the light emitting device EL to emit light again.

[0127] In the exemplary embodiment, the first stage A, the second stage B, the third stage C and the fourth stage D can constitute a refresh frame, which can be used for driving of high frequency display (such as 90Hz and 120Hz), that is, the high frequency display needs the first stage A to the fourth stage D for a total of four stages. The fifth stage E and the sixth stage F can constitute a holding frame, and the refresh frame and the holding frame together can be used for driving of low frequency display (such as 60Hz), that is, the low frequency display needs the first stage A to the sixth stage F for a total of six stages.

[0128] The driving method of the pixel driving circuit provided by the example embodiment of the present disclosure can realize the writing of the data signal more quickly by separating the compensation stage and the data writing stage, thereby supporting a higher frame frequency display. The present disclosure improves the compensation effect by sampling the threshold voltage in the compensation stage using the self-discharge mode of the capacitor and storing the threshold voltage in the capacitor. The present disclosure can effectively improve the hysteresis of the third transistor by applying a direct current signal to the first electrode of the third transistor, which is conducive to improving the residual image and supporting low-frequency display, and improving the display effect.

[0129] FIG. 6 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure. In the example embodiment, the display substrate can include a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. The driving circuit layer can include at least a plurality of circuit units, and the light-emitting structure layer can include at least a plurality of light-emitting units. At least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device. The light-emitting device is connected to the pixel driving circuit in the corresponding circuit unit, and the pixel driving circuit is configured to output a driving current to the connected light-emitting device.

[0130] In the example embodiment, the circuit unit in the present disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit in the present disclosure refers to a region divided according to the light-emitting device. In the example embodiment, the position of the light-emitting unit orthogonally projected on the base can correspond to the position of the circuit unit orthogonally projected on the base, or the position of the light-emitting unit orthogonally projected on the base can not correspond to the position of the circuit unit orthogonally projected on the base.

[0131] In the example embodiment, the plurality of circuit units arranged in sequence along the first direction X can be referred to as a unit row, and the plurality of circuit units arranged in sequence along the second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns form an array of circuit units arranged in an array. The first direction X and the second direction Y intersect.

[0132] As shown in FIG. 6, the pixel driving circuit in at least one circuit unit can be connected to the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light-emitting signal line 35, the first power supply line 51, the data signal line 52, the first initial signal line 81, the second initial signal line 82, and the third initial signal line 83. The plurality of signal lines connected to the pixel driving circuit can be located within the corresponding circuit unit.

[0133] In the example embodiment, the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light emission signal line 35, the first initial signal line 81, the second initial signal line 82, and the third initial signal line 83 can have a shape of a straight line or a broken line in which a main portion extends along the first direction X. The first power supply line 51 and the data signal line 52 can have a shape of a straight line or a broken line in which a main portion extends along the second direction Y.

[0134] In the present disclosure, A extending along B means that A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the B direction, and the length of the main portion extending along the B direction is greater than the length of the secondary portion extending along other directions. In the following description, A extending along B means that the main portion of A extends along B.

[0135] In the example embodiment, the at least one pixel driving circuit can include a first capacitor, a second capacitor, and a plurality of transistors, the plurality of transistors can include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a third initialization transistor, and a ninth transistor T9 as a charge-discharge transistor. The first transistor T1 to the ninth transistor T9 can be low-temperature polysilicon transistors. The first capacitor can include a first electrode plate and a third electrode plate stacked, and the second capacitor can include a second electrode plate and a fourth electrode plate stacked.

[0136] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 33, the first electrode of the first transistor T1 is connected to the first initial signal line 81, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 and the first electrode plate of the first capacitor. The gate electrode of the second transistor T2 is connected to the third scan signal line 33, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the third transistor T3 can serve as the first electrode plate of the first capacitor, and the first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 34, the first electrode of the fourth transistor T4 is connected to the data signal line 52, and the second electrode of the fourth transistor T4 is connected to the first electrode of the ninth transistor T9, the third electrode plate of the first capacitor, and the second electrode plate of the second capacitor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line 35, and the first electrode of the fifth transistor T5 is connected to the first power supply line 51. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line 35, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scan signal line 31, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scan signal line 31, the first electrode of the eighth transistor T8 is connected to the third initial signal line 83, and the gate electrode of the ninth transistor T9 is connected to the second scan signal line 32.

[0137] In the exemplary embodiment, the connection of the gate electrode of the seventh transistor T7 to the first scan signal line 31 and the connection of the gate electrode of the eighth transistor T8 to the first scan signal line 31 mean that the gate electrode of the seventh transistor T7 of the circuit unit in the present unit row is connected to the first scan signal line 31 in the next unit row, and the gate electrode of the eighth transistor T8 of the circuit unit in the present unit row is connected to the first scan signal line 31 in the present unit row.

[0138] In the exemplary embodiment, the first transistor T1 and the second transistor T2 are connected to the same scan signal line, i.e., the same third scan signal line 33.

[0139] In the exemplary embodiment, at least one circuit unit can further include a power supply connection line 36. The power supply connection line 36 can have a shape of a straight line or a broken line extending along the first direction X, and the power supply connection line 36 extending along the first direction X and the first power supply line 51 extending along the second direction Y are connected to each other to form a meshed communication structure for transmitting the first power supply signal.

[0140] In the exemplary embodiment, the at least one circuit unit can further include a first initial connection line 84. The first initial connection line 84 can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y, and a first initial signal line 81 extending in the first direction X and the first initial connection line 84 extending in the second direction Y are connected to each other, thereby forming a meshed communication structure for transmitting a first initial signal.

[0141] In the exemplary embodiment, the at least one circuit unit can further include a second initial connection line 85. The second initial connection line 85 can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y, and a second initial signal line 82 extending in the first direction X and the second initial connection line 85 extending in the second direction Y are connected to each other, thereby forming a meshed communication structure for transmitting a second initial signal.

[0142] In the exemplary embodiment, the at least one circuit unit can further include a third initial connection line 86. The third initial connection line 86 can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y, and a third initial signal line 83 extending in the first direction X and the third initial connection line 86 extending in the second direction Y are connected to each other, thereby forming a meshed communication structure for transmitting a third initial signal.

[0143] FIG. 7 is a structural schematic view of a first transistor and a second transistor according to an exemplary embodiment of the present disclosure. As shown in FIGS. 6 and 7, the first transistor T1 can include at least a first active layer 11, a first gate electrode 21, a first source electrode (a first electrode of the first transistor T1), and a first drain electrode (a second electrode of the first transistor T1), and the second transistor T2 can include at least a second active layer 12, a second gate electrode 22, a second source electrode (a first electrode of the second transistor T2), and a second drain electrode (a second electrode of the second transistor T2), and the first drain electrode and the second source electrode are connected.

[0144] In the exemplary embodiment, the first transistor T1 and the second transistor T2 can each have a double-gate structure and can each include two sub-active layers and two sub-gate electrodes.

[0145] In the exemplary embodiment, the first active layer 11 can include a first sub-active layer 10-1 and a third sub-active layer 10-3, the first sub-active layer 10-1 can have a shape of a bar extending in the second direction Y, and the third sub-active layer 10-3 can have a shape of a bar extending in the first direction X. In the first direction X, the first sub-active layer 10-1 can be disposed on one side of the third sub-active layer 10-3 in the first direction X, and in the second direction Y, the first sub-active layer 10-1 can be disposed on one side of the third sub-active layer 10-3 in the opposite direction of the second direction Y, and the first sub-active layer 10-1 and the third sub-active layer 10-3 are connected to each other at the ends thereof close to each other, thereby forming a meshed communication structure for transmitting a first initial signal. Shape.

[0146] In an example embodiment, the second active layer 12 can include a second sub-active layer 10-2 and a third sub-active layer 10-3, the second sub-active layer 10-2 can have a shape of a strip extending along the second direction Y. In the first direction X, the second sub-active layer 10-2 can be disposed at one side of the third sub-active layer 10-3 in the first direction X, in the second direction Y, the second sub-active layer 10-2 can be disposed at one side of the third sub-active layer 10-3 in the second direction Y, and the ends of the second sub-active layer 10-2 and the third sub-active layer 10-3 close to each other are connected to each other, forming a first sub-active layer 10-1. Shape.

[0147] In an example embodiment, since the first sub-active layer 10-1 and the second sub-active layer 10-2 are both connected to the third sub-active layer 10-3, the first active layer 11 and the second active layer 12 together constitute a first active layer 11. Shape.

[0148] In an example embodiment, the third sub-active layer 10-3 serves as a sub-active layer of the first active layer 11 and a sub-active layer of the second active layer 12, that is, the first active layer 11 and the second active layer 12 share the same third sub-active layer 10-3.

[0149] In an example embodiment, the first active layer 11 and the second active layer 12 can be an integrated structure connected to each other.

[0150] In an example embodiment, the first gate electrode 21 can include a first sub-gate electrode 20-1 and a third sub-gate electrode 20-3, the first sub-gate electrode 20-1 can have a shape of a strip extending along the first direction X, the orthographic projection of the first sub-gate electrode 20-1 on the substrate at least partially overlaps the orthographic projection of the first sub-active layer 10-1 on the substrate, the third sub-gate electrode 20-3 can have a shape of a strip extending along the second direction Y, the orthographic projection of the third sub-gate electrode 20-3 on the substrate at least partially overlaps the orthographic projection of the third sub-active layer 10-3 on the substrate. In the first direction X, the first sub-gate electrode 20-1 can be disposed at one side of the third sub-gate electrode 20-3 in the first direction X, in the second direction Y, the first sub-gate electrode 20-1 can be disposed at one side of the third sub-gate electrode 20-3 in the opposite direction of the second direction Y, and the ends of the first sub-gate electrode 20-1 and the third sub-gate electrode 20-3 close to each other are connected to each other, forming a second gate electrode 22. Shape.

[0151] In an example embodiment, the second gate electrode 22 can include a second sub-gate electrode 20-2 and a third sub-gate electrode 20-3, the shape of the second gate electrode 22 can be a strip shape extending along the first direction X, and the orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps the orthographic projection of the second sub-active layer 10-2 on the substrate. In the first direction X, the second sub-gate electrode 20-2 can be disposed on one side of the third sub-gate electrode 20-3 in the first direction X, in the second direction Y, the second sub-gate electrode 20-2 can be disposed on one side of the third sub-gate electrode 20-3 in the second direction Y, and the ends of the second sub-gate electrode 20-2 and the third sub-gate electrode 20-3 close to each other are connected to each other, forming a "C" shape. Shape.

[0152] In an example embodiment, since the first sub-gate electrode 20-1 and the second sub-gate electrode 20-2 are both connected to the third sub-gate electrode 20-3, the first gate electrode 21 and the second gate electrode 22 together form a "C" shape.

[0153] In an example embodiment, the third sub-gate electrode 20-3 serves as a sub-gate electrode of the first gate electrode 21 and a sub-gate electrode of the second gate electrode 22, that is, the first gate electrode 21 and the second gate electrode 22 share the same third sub-gate electrode 20-3.

[0154] In an example embodiment, the first gate electrode 21 and the second gate electrode 22 can be an integrated structure connected to each other.

[0155] In an example embodiment, in a plane perpendicular to the display substrate, the display substrate can include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed in sequence on the substrate. The first active layer 11 and the second active layer 12 can be disposed in the semiconductor layer, the first gate electrode 21 and the second gate electrode 22 can be disposed in the first gate metal layer, the third scan signal line 33 can be disposed in the first source-drain metal layer, and the third scan signal line 33 is connected to the first gate electrode 21 and the second gate electrode 22 of the integrated structure through a via.

[0156] In an example embodiment, the first initial signal line 81 can be disposed in the second gate metal, the second initial signal line 82 and the third initial signal line 83 can be disposed in the first source-drain metal layer, and the first initial connection line 84, the second initial connection line 85, and the third initial connection line 86 can be disposed in the second source-drain metal layer.

[0157] In an example embodiment, the power supply connection line 36 can be disposed in the first source-drain metal layer, and the first power supply line 51 can be disposed in the second source-drain metal layer.

[0158] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the whole preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the whole preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0159] In the exemplary embodiments, taking three circuit units in the Mth unit row as an example, the preparation process of the display substrate can include the following operations.

[0160] (11) Forming a semiconductor layer pattern. In the exemplary embodiments, forming a semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a semiconductor thin film on the substrate, patterning the semiconductor thin film by a patterning process, forming a first insulating layer covering the substrate, and a semiconductor layer arranged on the first insulating layer, as shown in FIG. 8.

[0161] In the exemplary embodiments, the semiconductor layer of each circuit unit in the display substrate can at least include: a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first active layer 11 to the ninth active layer 19 can be an integrated structure connected with each other.

[0162] In the exemplary embodiment, in the first direction X, the first active layer 11, the second active layer 12, the sixth active layer 16, and the seventh active layer 17 can be located on one side of the third active layer 13 in the first direction X, and the fifth active layer 15 and the eighth active layer 18 can be located on the opposite side of the third active layer 13 in the first direction X. In the second direction Y, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 can be located on one side of the third active layer 13 in the second direction Y, and the first active layer 11, the second active layer 12, the fourth active layer 14, the eighth active layer 18, and the ninth active layer 19 can be located on the opposite side of the third active layer 13 in the second direction Y.

[0163] In the exemplary embodiment, the shape of the third active layer 13 can be an inverted "Ω" shape, the shape of the first active layer 11 and the second active layer 12 can be an "L" shape, the shape of the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can be an "I" shape, and the shape of the ninth active layer 19 can be a "one" shape.

[0164] In the exemplary embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be connected to each other, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer, and the second region 19-2 of the ninth active layer can be connected to each other, and the first region 13-1 of the third active layer can simultaneously serve as the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer, and the second region 19-2 of the ninth active layer, constituting a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can simultaneously serve as the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, constituting a third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the first region 19-1 of the ninth active layer can be connected to each other, and the second region 14-2 of the fourth active layer can serve as the first region 19-1 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, constituting a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, and the first region 18-1 of the eighth active layer can be separately provided.

[0165] In an exemplary embodiment, the first transistor T1 has a dual-gate structure, including two sub-active layers. The second transistor T2 has a dual-gate structure, including two sub-active layers.

[0166] In an exemplary embodiment, the first active layer 11 may include a first sub-active layer 10-1 and a third sub-active layer 10-3. The first sub-active layer 10-1 may be a strip extending along the second direction Y, and the third sub-active layer 10-3 may be a strip extending along the first direction X. In the first direction X, the first sub-active layer 10-1 may be disposed on one side of the third sub-active layer 10-3 in the first direction X. In the second direction Y, the first sub-active layer 10-1 may be disposed on the opposite side of the third sub-active layer 10-3 in the second direction Y, and the ends of the first sub-active layer 10-1 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.

[0167] In an exemplary embodiment, the second active layer 12 may include a second sub-active layer 10-2 and a third sub-active layer 10-3. The second sub-active layer 10-2 may be a strip extending along the second direction Y. In the first direction X, the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the first direction X. In the second direction Y, the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the second direction Y. The ends of the second sub-active layer 10-2 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.

[0168] In an exemplary embodiment, since both the first sub-active layer 10-1 and the second sub-active layer 10-2 are connected to the third sub-active layer 10-3, the first active layer 11 and the second active layer 12 together constitute... shape.

[0169] In an exemplary embodiment, the third sub-active layer 10-3 serves as both a sub-active layer of the first active layer 11 and a sub-active layer of the second active layer 12, meaning that the first active layer 11 and the second active layer 12 share the same third sub-active layer 10-3.

[0170] In the example embodiment, the first semiconductor layer can adopt polycrystalline silicon (p-Si), i.e., the first transistor T1 to the ninth transistor T9 are LTPS transistors. In the example embodiment, the patterning of the first semiconductor thin film by the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing a dehydrogenation treatment on the amorphous silicon thin film, performing a crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment, and forming a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the first semiconductor layer pattern.

[0171] (12) Forming the first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the first conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 9A and 9B, FIG. 9B being a schematic view of the first conductive layer in FIG. 9A. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0172] In the example embodiment, the first conductive layer pattern of each circuit unit in the display substrate at least includes: the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, the seventh gate electrode 27, the eighth gate electrode 28, the ninth gate electrode 29, the gate connection line 30, the light-emitting signal line 35, the first plate 71 of the first capacitor, and the second plate 72 of the second capacitor.

[0173] In the example embodiment, the first plate 71 of the first capacitor can have a rectangular shape, and the corners of the rectangular shape can be provided with chamfers or grooves. The orthographic projection of the first plate 71 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first plate 71 can simultaneously serve as the lower plate of the first capacitor and the gate electrode of the third transistor T3.

[0174] In the example embodiment, the second plate 72 of the second capacitor can have a rectangular shape, and the corners of the rectangular shape can be provided with chamfers or grooves. The second plate 72 can be located on one side of the first plate 71 in the second direction Y. The orthographic projection of the second plate 72 on the substrate does not overlap the orthographic projection of the semiconductor layer on the substrate. In the example embodiment, the second plate 72 can serve as the lower plate of the second capacitor.

[0175] In the example embodiment, the first gate electrode 21 can be located on the side of the first plate 71 away from the second plate 72. The area where the first gate electrode 21 overlaps the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0176] In the example embodiment, the second gate electrode 22 can be located between the first gate electrode 21 and the first plate 71, and the region of the second gate electrode 22 overlapping the second active layer can serve as a gate electrode of the second transistor T2 of the dual-gate structure.

[0177] In the example embodiment, the first gate electrode 21 and the second gate electrode 22 can be connected to each other to form a "C" shape, and the first transistor T1 of the dual-gate structure and the second transistor T2 of the dual-gate structure share one of the sub-gate electrodes.

[0178] In the example embodiment, the first gate electrode 21 can include a first sub-gate electrode 20-1 and a third sub-gate electrode 20-3, the first sub-gate electrode 20-1 can have a shape of a strip extending along the first direction X, and a projection of the first sub-gate electrode 20-1 on the substrate at least partially overlaps a projection of the first sub-active layer 10-1 on the substrate, the third sub-gate electrode 20-3 can have a shape of a strip extending along the second direction Y, and a projection of the third sub-gate electrode 20-3 on the substrate at least partially overlaps a projection of the third sub-active layer 10-3 on the substrate. In the first direction X, the first sub-gate electrode 20-1 can be disposed on one side of the third sub-gate electrode 20-3 in the first direction X, in the second direction Y, the first sub-gate electrode 20-1 can be disposed on one side of the third sub-gate electrode 20-3 in the second direction Y, and the first sub-gate electrode 20-1 and the third sub-gate electrode 20-3 are connected to each other at the ends close to each other to form a "C" shape.

[0179] In the example embodiment, the second gate electrode 22 can include a second sub-gate electrode 20-2 and a third sub-gate electrode 20-3, the second gate electrode 22 can have a shape of a strip extending along the first direction X, and a projection of the second gate electrode 22 on the substrate at least partially overlaps a projection of the second sub-active layer 10-2 on the substrate. In the first direction X, the second sub-gate electrode 20-2 can be disposed on one side of the third sub-gate electrode 20-3 in the first direction X, in the second direction Y, the second sub-gate electrode 20-2 can be disposed on one side of the third sub-gate electrode 20-3 in the second direction Y, and the second sub-gate electrode 20-2 and the third sub-gate electrode 20-3 are connected to each other at the ends close to each other to form a "C" shape.

[0180] In the example embodiment, since the first sub-gate electrode 20-1 and the second sub-gate electrode 20-2 are both connected to the third sub-gate electrode 20-3, the first gate electrode 21 and the second gate electrode 22 together form a "C" shape.

[0181] ​​In the exemplary embodiment, the third sub-gate electrode 20-3 serves as one of the sub-gate electrodes of the first gate electrode 21 and one of the sub-gate electrodes of the second gate electrode 22, i.e., the first gate electrode 21 and the second gate electrode 22 share the same third sub-gate electrode 20-3.

[0182] In the exemplary embodiment, the first gate electrode 21 and the second gate electrode 22 can be an integrated structure connected to each other.

[0183] In the exemplary embodiment, the fourth gate electrode 24 can have a "C" shape, can be located on the side of the first plate 71 away from the second plate 72, and the region where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4 of the double-gate structure.

[0184] In the exemplary embodiment, the seventh gate electrode 27 can have a strip shape extending along the first direction X, can be located on the side of the first plate 71 in the second direction Y, and the region where the seventh gate electrode 27 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0185] In the exemplary embodiment, the eighth gate electrode 28 can have a strip shape extending along the first direction X, can be located on the side of the fourth gate electrode 24 away from the first plate 71, and the region where the eighth gate electrode 28 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0186] In the exemplary embodiment, the ninth gate electrode 29 can have a "U" shape, can be located between the fourth gate electrode 24 and the first plate 71, and the region where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the double-gate structure.

[0187] In the exemplary embodiment, the gate connection line 30 can have a strip shape extending along the second direction Y, can be located on the side of the seventh gate electrode 27 away from the first plate 71. The first end of the gate connection line 30 is connected to the seventh gate electrode 27 of the circuit unit in the current unit row, and the second end of the gate connection line 30 is connected to the eighth gate electrode 28 of the circuit unit in the next unit row after extending along the second direction Y, so that the seventh transistor T7 in the current unit row and the eighth transistor T8 in the next unit row are turned on or turned off at the same time. Alternatively, the first end of the gate connection line 30 is connected to the seventh gate electrode 27 of the circuit unit in the previous unit row, and the second end of the gate connection line 30 is connected to the eighth gate electrode 28 of the circuit unit in the current unit row after extending along the second direction Y, so that the seventh transistor T7 in the previous unit row and the eighth transistor T8 in the current unit row are turned on or turned off at the same time.

[0188] In the example embodiment, the seventh gate electrode 27 of the circuit unit in the present unit row, the eighth gate electrode 28 of the circuit unit in the next unit row, and the gate connecting line 30 can be an integrated structure connected with each other. Alternatively, the seventh gate electrode 27 of the circuit unit in the previous unit row, the eighth gate electrode 28 of the circuit unit in the present unit row, and the gate connecting line 30 can be an integrated structure connected with each other.

[0189] In the example embodiment, the light emitting signal line 35 can be in a straight line shape or a broken line shape with a main body portion extending along the first direction X, can be located between the first plate 71 and the second plate 72, and an area where the light emitting signal line 35 overlaps with the fifth active layer can serve as a gate electrode of the fifth transistor T5, and an area where the light emitting signal line 35 overlaps with the sixth active layer can serve as a gate electrode of the sixth transistor T6.

[0190] In the example embodiment, after the first conductive layer pattern is formed, the semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the ninth active layer are conductorized.

[0191] (13) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the second conductive thin film by using a patterning process, forming a third insulating layer covering the first conductive layer, and forming the second conductive layer pattern on the third insulating layer, as shown in FIG. 10A and FIG. 10B, FIG. 10B is a schematic view of the second conductive layer in FIG. 10A. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0192] In the example embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: the third plate 73 of the first capacitor, the fourth plate 74 of the second capacitor, and the first initial signal line 81.

[0193] In the example embodiment, the third plate 73 of the first capacitor can have a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer or a groove, and the orthographic projection of the third plate 73 on the substrate at least partially overlaps with the orthographic projection of the first plate 71 on the substrate, and the third plate 73 can serve as the upper plate of the first capacitor, and the first plate 71 and the third plate 73 constitute the first capacitor of the pixel driving circuit.

[0194] In the example embodiment, the fourth plate 74 of the second capacitor can be rectangular, and the corners of the rectangular shape can be chamfered or recessed. The fourth plate 74 can be an upper plate of the second capacitor, and the second plate 72 and the fourth plate 74 can form the second capacitor of the pixel driving circuit.

[0195] In the example embodiment, the third plate 73 of each circuit unit can be provided with a first opening 75, which can be block-shaped (e.g., rectangular) and located in a middle region of the third plate 73, so that the third plate 73 forms a ring structure. The first opening 75 exposes the third insulating layer covering the first plate 71, and the first plate 71 has a projection on the substrate that contains the projection of the first opening 75 on the substrate. In the example embodiment, the first opening 75 is configured to accommodate a tenth via to be formed later, which is located in the first opening 75 and exposes the first plate 71, so that a first connecting electrode to be formed later is connected to the first plate 71.

[0196] In the example embodiment, the fourth plate 74 of each circuit unit can be provided with a second opening 76, which can be block-shaped (e.g., rectangular) and located on a side of the fourth plate 74 close to the third plate 73. The second opening 76 exposes the third insulating layer covering the second plate 72, and the second plate 72 has a projection on the substrate that contains the projection of the second opening 76 on the substrate. In the example embodiment, the second opening 76 is configured to accommodate an eleventh via to be formed later, which is located in the second opening 76 and exposes the second plate 72, so that a second connecting electrode to be formed later is connected to the second plate 72.

[0197] In the example embodiment, the first initial signal line 81 can be linear or zigzag-shaped with a main body extending along the first direction X, and can be located between the fourth gate electrode 24 and the eighth gate electrode 28. In the example embodiment, the first initial signal line 81 can be provided with a first initial connecting block 81-1, which can be provided in each circuit unit and connected to the first initial signal line 81. The first initial connecting block 81-1 is configured to be connected to the first region of the first active layer through a fifth connecting electrode to be formed later.

[0198] In the example embodiment, the first initial signal line 81 and the plurality of first initial connecting blocks 81-1 can be an integral structure connected to each other.

[0199] (14) forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film using a patterning process, forming the fourth insulating layer covering the second conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 11.

[0200] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0201] In an exemplary embodiment, the first via V1 has a normal projection on the substrate within a range of a normal projection on the substrate of the first region of the first active layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away, exposing a surface of the first region of the first active layer, and the first via V1 is configured to allow a fifth connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0202] In an exemplary embodiment, the second via V2 has a normal projection on the substrate within a range of a normal projection on the substrate of the second region of the first active layer (also the first region of the second active layer), the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing a surface of the second region of the first active layer (also the first region of the second active layer), and the second via V2 is configured to allow a first connection electrode formed subsequently to connect with the second region of the first active layer (also the first region of the second active layer) through the via.

[0203] In an exemplary embodiment, the third via V3 has a normal projection on the substrate within a range of a normal projection on the substrate of the first region of the fourth active layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing a surface of the first region of the fourth active layer, and the third via V3 is configured to allow a third connection electrode formed subsequently to connect with the first region of the fourth active layer through the via.

[0204] In an example embodiment, the fourth via V4 is configured such that a second connection electrode formed subsequently is connected to the second region of the fourth active layer (also the first region of the ninth active layer) through the fourth via V4.

[0205] In an example embodiment, the fifth via V5 is configured such that a power connection line formed subsequently is connected to the first region of the fifth active layer through the fifth via V5.

[0206] In an example embodiment, the sixth via V6 is configured such that a fourth connection electrode formed subsequently is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via V6.

[0207] In an example embodiment, the seventh via V7 is configured such that a second initial signal line formed subsequently is connected to the first region of the seventh active layer through the seventh via V7.

[0208] In an example embodiment, the eighth via V8 is configured such that a third initial signal line formed subsequently is connected to the first region of the eighth active layer through the eighth via V8.

[0209] In the example embodiment, the normal projection of the ninth via V9 on the substrate is located within the range of the normal projection of the first initial connection block 81-1 of the first initial signal line 81 on the substrate, the fourth insulating layer in the ninth via V9 is etched away to expose the surface of the first initial connection block 81-1, and the ninth via V9 is configured to enable the fifth connection electrode formed subsequently to connect with the first initial connection block 81-1 through the via.

[0210] In the example embodiment, the normal projection of the tenth via V10 on the substrate is located within the range of the normal projection of the first opening 75 of the third plate 73 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via V10 are etched away to expose the surface of the first plate 71, and the tenth via V10 is configured to enable the first connection electrode formed subsequently to connect with the first plate 71 through the via.

[0211] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is located within the range of the normal projection of the second opening 76 of the fourth plate 74 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via V11 are etched away to expose the surface of the second plate 72, and the eleventh via V11 is configured to enable the second connection electrode formed subsequently to connect with the second plate 72 through the via.

[0212] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the range of the normal projection of the third plate 73 on the substrate, the fourth insulating layer in the twelfth via V12 is etched away to expose the surface of the third plate 73, and the twelfth via V12 is configured to enable the second connection electrode formed subsequently to connect with the third plate 73 through the via.

[0213] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is located within the range of the normal projection of the fourth plate 74 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose the surface of the fourth plate 74, and the thirteenth via V13 is configured to enable the power connection line formed subsequently to connect with the fourth plate 74 through the via.

[0214] In the example embodiment, the normal projection of the fourteenth via V14 on the substrate is located within the range of the normal projection of the first gate electrode 21 and the second gate electrode 22 of the integrated structure on the substrate, the fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the first gate electrode 21 and the second gate electrode 22, and the fourteenth via V14 is configured to enable the third scan signal line formed subsequently to connect with the first gate electrode 21 and the second gate electrode 22 through the via.

[0215] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the fifteenth via V15 are etched away, exposing the surface of the fourth gate electrode 24, and the fifteenth via V15 is configured to allow the fourth scan signal line formed subsequently to connect with the fourth gate electrode 24 through the via.

[0216] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the sixteenth via V16 are etched away, exposing the surface of the eighth gate electrode 28, and the sixteenth via V16 is configured to allow the first scan signal line formed subsequently to connect with the eighth gate electrode 28 through the via.

[0217] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the seventeenth via V17 are etched away, exposing the surface of the ninth gate electrode 29, and the seventeenth via V17 is configured to allow the second scan signal line formed subsequently to connect with the ninth gate electrode 29 through the via.

[0218] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a third conductive thin film, and patterning the third conductive thin film by using a patterning process, to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG. 12A and FIG. 12B, which is a schematic diagram of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0219] In an exemplary embodiment, the third conductive layer pattern of each of the plurality of circuit units in the display substrate can include: the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the power connection line 36, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the fourth connection electrode 44, the fifth connection electrode 45, the second initial signal line 82, and the third initial signal line 83.

[0220] In the example embodiment, the first scan signal line 31 can be in a straight line shape or a broken line shape with a main body extending along the first direction X, and can be located on the side of the first initial signal line 81 away from the third plate 73. The first scan signal line 31 is connected to the eighth gate electrode 28 in each circuit unit through the sixteenth via V16, so that the first scan signal line 31 is connected to the gate electrode of the eighth transistor T8 in each circuit unit, and the first scan signal line 31 can control the on and off of the eighth transistor T8.

[0221] In the example embodiment, since the seventh gate electrode 27 of the circuit unit in the present unit row is connected to the eighth gate electrode 28 of the circuit unit in the next unit row through the gate connection line 30, or the eighth gate electrode 28 of the circuit unit in the present unit row is connected to the seventh gate electrode 27 of the circuit unit in the previous unit row through the gate connection line 30, the first scan signal line 31 in the present unit row is also connected to the gate electrode of the seventh transistor T7 of each circuit unit in the previous unit row, and the first scan signal line 31 in the present unit row can simultaneously control the on and off of the seventh transistor T7 of each circuit unit in the previous unit row.

[0222] In the example embodiment, the first scan signal line 31 for controlling the eighth transistor T8 in the present unit row can also be the fifth scan signal line for controlling the seventh transistor T7 in the previous unit row, or the fifth scan signal line for controlling the seventh transistor T7 in the present unit row is realized by the first scan signal line 31 for controlling the eighth transistor T8 in the next unit row.

[0223] In the example embodiment, the second scan signal line 32 can be in a straight line shape or a broken line shape with a main body extending along the first direction X, and can be located on the side of the third plate 73 away from the fourth plate 74. The second scan signal line 32 is connected to the ninth gate electrode 29 in each circuit unit through the seventeenth via V17, so that the second scan signal line 32 is connected to the gate electrode of the ninth transistor T9 in each circuit unit, and the second scan signal line 32 can control the on and off of the ninth transistor T9.

[0224] In the example embodiment, the second scan signal line 32 can be provided with a scan connection strip 32-1, and the scan connection strip 32-1 can be arranged in each circuit unit. The scan connection strip 32-1 can be in a strip shape extending along the second direction Y, the first end of the scan connection strip 32-1 is connected to the second scan signal line 32, and the second end of the scan connection strip 32-1 extends towards the third plate 73, and is connected to the ninth gate electrode 29 through the seventeenth via V17.

[0225] In the example embodiment, the second scan signal line 32 and the plurality of scan connection strips 32-1 can be an integral structure connected to each other.

[0226] In the example embodiment, the third scan signal line 33 can be in a linear or zigzag shape with a main body extending along the first direction X, and can be located on the side of the second scan signal line 32 away from the third plate 73. The third scan signal line 33 is connected to the first gate electrode 21 and the second gate electrode 22 of the integral structure in each circuit unit through the fourteenth via V14, so that the third scan signal line 33 is connected to the gate electrodes of the first transistor T1 and the second transistor T2 in each circuit unit, and can control the simultaneous conduction and the simultaneous disconnection of the first transistor T1 and the second transistor T2.

[0227] In the example embodiment, the fourth scan signal line 34 can be in a linear or zigzag shape with a main body extending along the first direction X, and can be located between the third scan signal line 33 and the first initial signal line 81. The fourth scan signal line 34 is connected to the fourth gate electrode 24 in each circuit unit through the fifteenth via V15, so that the fourth scan signal line 34 is connected to the gate electrode of the fourth transistor T4 in each circuit unit, and can control the conduction and the disconnection of the fourth transistor T4.

[0228] In the example embodiment, the power connection line 36 can be in a linear or zigzag shape with a main body extending along the first direction X, and can be located on the side of the light-emitting signal line 35 away from the third plate 73. The power connection line 36 is connected to the fourth plate 74 in each circuit unit through the thirteenth via V13, and is connected to the first region of the fifth active layer in each circuit unit through the fifth via V5. Since the power connection line 36 is configured to be connected to the first power line formed later, the first power line can write the first power signal to the first electrode of the fifth transistor T5 and the fourth plate 74 in each circuit unit. In the example embodiment, the power connection line 36 is also configured to form a mesh communication structure with the first power line formed later.

[0229] In the example embodiment, the orthogonal projection of the power connection line 36 on the substrate at least partially overlaps the orthogonal projection of the fourth plate 74 on the substrate.

[0230] In the example embodiment, the power connection line 36 can be provided with a power connection block 36-1. The power connection block 36-1 can be in a block shape (such as a rectangular shape) and connected to the power connection line 36. The power connection block 36-1 is configured to be connected to the fourth plate 74 through the thirteenth via V13, and is configured to be connected to the first power line formed later.

[0231] In an example embodiment, the power connection line 36 can be provided with a power connection strip 36-2, which can be provided in each circuit unit. The power connection strip 36-2 can have a shape of a strip extending along the second direction Y, a first end of the power connection strip 36-2 being connected to the power connection line 36, and a second end of the power connection strip 36-2 extending towards the first region of the fifth active layer via the fifth via V5.

[0232] In an example embodiment, the power connection line 36, the power connection block 36-1, and the power connection strip 36-2 can be an integrated structure connected to each other.

[0233] In an example embodiment, the second initial signal line 82 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and can be located on a side of the power connection line 36 away from the third plate 73. The second initial signal line 82 can be connected to the first region of the seventh active layer in each circuit unit via the seventh via V7, so as to realize that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first electrode of the seventh transistor T7.

[0234] In an example embodiment, the second initial signal line 82 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and can be located on a side of the power connection line 36 away from the third plate 73. The second initial signal line 82 can be connected to the first region of the seventh active layer in each circuit unit via the seventh via V7, so as to realize that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first electrode of the seventh transistor T7.

[0235] In an example embodiment, the second initial signal line 82 can be provided with a second initial connection block 82-1. The second initial connection block 82-1 can have a shape of a block (e.g., a rectangle) connected to the second initial signal line 82, and configured to be connected to a second initial connection line formed subsequently.

[0236] In an example embodiment, the second initial connection block 82-1 can be provided in the circuit unit of the (N+2)th unit column.

[0237] In an example embodiment, the third initial signal line 83 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and can be located on a side of the first scan signal line 31 away from the third plate 73. The third initial signal line 83 can be connected to the first region of the eighth active layer in each circuit unit via the eighth via V8, so as to realize that the third initial signal line 83 is connected to the first electrode of the eighth transistor T8, and the third initial signal line 83 can write the third initial signal to the first electrode of the eighth transistor T8.

[0238] In the exemplary embodiment, a third initial connection block 83-1 is provided on the third initial signal line 83. The third initial connection block 83-1 can have a block shape (e.g., a rectangular shape), and is connected to the third initial signal line 83. The third initial connection block 83-1 is configured to be connected to a third initial connection line to be formed later.

[0239] In the exemplary embodiment, the third initial signal line 83 can be provided in the circuit unit of the (N+1)th unit column.

[0240] In the exemplary embodiment, the first connection electrode 41 can have a bar shape in which a main body portion extends along the second direction Y, and can be provided between the second scan signal line 32 and the emission signal line 35. The first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via V2, and the second end of the first connection electrode 41 is connected to the first plate 71 through the tenth via V10. Since the first plate 71 serves as the gate electrode of the third transistor T3, the first connection electrode 41 achieves the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 71 of the first capacitor, and the first connection electrode 41 can serve as the first node N1 of the pixel driving circuit.

[0241] In the exemplary embodiment, the second connection electrode 42 can have a bar shape in which a main body portion extends along the second direction Y, and can be provided between the second scan signal line 32 and the power connection line 36. The first end of the second connection electrode 42 is connected to the second region of the fourth active layer (also the first region of the ninth active layer) through the fourth via V4, and the second end of the second connection electrode 42 is connected to the second plate 72 through the eleventh via V11. The position between the first end and the second end of the second connection electrode 42 is connected to the third plate 73 through the twelfth via V12. The second connection electrode 42 achieves the interconnection between the second electrode of the fourth transistor T4, the first electrode of the ninth transistor T9, the third plate 73 of the first capacitor, and the second plate 72 of the second capacitor, and the second connection electrode 42 can serve as the fifth node N5 of the pixel driving circuit.

[0242] In the exemplary embodiment, the third connection electrode 43 can have a block shape (e.g., a rectangular shape or the like), and can be located between the fourth scan signal line 34 and the first initial signal line 81. The third connection electrode 43 is connected to the first region of the fourth active layer through the third via V3, and is configured to be connected to a data signal line to be formed later.

[0243] In the example embodiment, the fourth connection electrode 44 can be in a block shape (such as a rectangular shape, etc.), can be located between the light-emitting signal line 35 and the power supply connection line 36, the fourth connection electrode 44 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via hole V6, and the fourth connection electrode 44 is configured to be connected with the anode connection electrode formed subsequently.

[0244] In the example embodiment, the fifth connection electrode 45 can be in a block shape (such as a rectangular shape, etc.), can be located between the first scan signal line 31 and the fourth scan signal line 34, the first end of the fifth connection electrode 45 is connected with the first region of the first active layer through the first via hole V1, and the second end of the fifth connection electrode 45 is connected with the first initial connection block 81-1 through the ninth via hole V9. Since the first initial connection block 81-1 is connected with the first initial signal line 81, the first initial signal line 81 is connected with the first electrode of the first transistor T1, and the first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1. In the example embodiment, the fifth connection electrode 45 in at least one circuit unit is further configured to be connected with the first initial connection line formed subsequently.

[0245] In the example embodiment, since the first plate 71 has the potential of the first node N1 of the pixel driving circuit, and the third plate 73 has the potential of the fifth node N5 of the pixel driving circuit, the first plate 71 (the first end of the first capacitor) having the potential of the first node N1 and the third plate 73 (the second end of the first capacitor) having the potential of the fifth node N5 form the first capacitor of the pixel driving circuit.

[0246] In the example embodiment, since the second plate 72 has the potential of the fifth node N5 of the pixel driving circuit, the fourth plate 74 is connected with the power supply connection line 36, the power supply connection line 36 is configured to be connected with the first power supply line formed subsequently, and the fourth plate 74 has the potential of the first power supply line, the fourth plate 74 (the first end of the second capacitor) having the potential of the first power supply line and the second plate 72 (the second end of the second capacitor) having the potential of the fifth node N5 form the second capacitor of the pixel driving circuit.

[0247] (16) Forming a first planar layer pattern. In the example embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a first planar film, patterning the first planar film by using a patterning process, and forming a first planar layer covering the third conductive layer, and the first planar layer in each circuit unit is provided with a plurality of via holes, as shown in FIG. 13.

[0248] In the example embodiment, the plurality of via holes of each circuit unit in the display substrate at least includes: a thirty-first via hole V31, a thirty-second via hole V32, and a thirty-third via hole V33.

[0249] In the example embodiment, the thirty-first via hole V31 has a projection on the substrate within a projection of a power connection block 36-1 of the power connection line 36 on the substrate, the first planar layer in the thirty-first via hole V31 is removed to expose a surface of the power connection block 36-1, and the thirty-first via hole V31 is configured to allow a first power line formed subsequently to pass through the via hole and connect with the power connection block 36-1.

[0250] In the example embodiment, the thirty-second via hole V32 has a projection on the substrate within a projection of the third connection electrode 43 on the substrate, the first planar layer in the thirty-second via hole V32 is removed to expose a surface of the third connection electrode 43, and the thirty-second via hole V32 is configured to allow a data signal line formed subsequently to pass through the via hole and connect with the third connection electrode 43.

[0251] In the example embodiment, the thirty-third via hole V33 has a projection on the substrate within a projection of the fourth connection electrode 44 on the substrate, the first planar layer in the thirty-third via hole V33 is removed to expose a surface of the fourth connection electrode 44, and the thirty-third via hole V33 is configured to allow an anode connection electrode formed subsequently to pass through the via hole and connect with the fourth connection electrode 44.

[0252] In the example embodiment, the at least one circuit unit can further include a thirty-fourth via hole V34. The thirty-fourth via hole V34 has a projection on the substrate within a projection of the fifth connection electrode 45 on the substrate, the first planar layer in the thirty-fourth via hole V34 is removed to expose a surface of the fifth connection electrode 45, and the thirty-fourth via hole V34 is configured to allow a first initial connection line formed subsequently to pass through the via hole and connect with the fifth connection electrode 45.

[0253] In the example embodiment, the thirty-fourth via hole V34 can be provided in the circuit unit of the Nth unit column.

[0254] In the example embodiment, the at least one circuit unit can further include a thirty-fifth via hole V35. The thirty-fifth via hole V35 has a projection on the substrate within a projection of a second initial connection block 82-1 of a second initial signal line 82 on the substrate, the first planar layer in the thirty-fifth via hole V35 is removed to expose a surface of the second initial connection block 82-1, and the thirty-fifth via hole V35 is configured to allow a second initial connection line formed subsequently to pass through the via hole and connect with the second initial connection block 82-1.

[0255] In an example embodiment, the thirty-fifth via V35 can be disposed in the circuit unit of the N+2th unit column.

[0256] In an example embodiment, the at least one circuit unit can further include a thirty-sixth via V36. A projection of the thirty-sixth via V36 on the substrate is located within a projection of the third initial connection block 83-1 of the third initial signal line 83 on the substrate, a first planar layer within the thirty-sixth via V36 is removed to expose a surface of the third initial connection block 83-1, and the thirty-sixth via V36 is configured to enable a subsequently formed third initial connection line to connect to the third initial connection block 83-1 through the via.

[0257] In an example embodiment, the thirty-sixth via V36 can be disposed in the circuit unit of the N+1th unit column.

[0258] (17) Forming a fourth conductive layer pattern. In an example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film to form a fourth conductive layer disposed on the first planar layer, as shown in FIGS. 14A and 14B, which is a schematic view of the fourth conductive layer in FIG. 14A. In an example embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0259] In an example embodiment, the fourth conductive layer pattern of each of the plurality of circuit units in the display substrate can include a first power supply line 51, a data signal line 52, and an anode connection electrode 53.

[0260] In an example embodiment, the first power supply line 51 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the first power supply line 51 can be connected to the power supply connection block 36-1 through the thirty-first via V31. Since the power supply connection block 36-1 is connected to the power supply connection line 36, the power supply connection line 36, which extends along the first direction X, and the first power supply line 51, which extends along the second direction Y, are connected to each other, and the first power supply line 51 and the power supply connection line 36 form a mesh-like communication structure for transmitting the first power supply signal on the display substrate, which not only effectively reduces the resistance of the first power supply line and the voltage drop of the first power supply signal, but also effectively improves the uniformity of the first power supply signal in the display substrate and the display uniformity, thereby improving the display quality and the display performance.

[0261] In an example embodiment, the power supply connection line 36 of the third conductive layer can be disposed in each unit row, and the first power supply line 51 of the fourth conductive layer can be disposed in each unit column, and a plurality of first power supply lines 51 are respectively connected to a plurality of power supply connection lines 36 to form a mesh-like communication structure for transmitting the first power supply signal.

[0262] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 41 on the substrate. Since the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the first power line 51 with constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, avoiding the influence of other signals (such as data voltage jump) on the potential of the first node N1 in the pixel driving circuit, and improving the display effect.

[0263] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Since the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the first power line 51 with constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, avoiding the influence of other signals on the potential of the fifth node N5 in the pixel driving circuit, and improving the display effect.

[0264] In an exemplary embodiment, the first power line 51 can be designed with non-equal width. The first power line 51 designed with non-equal width not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0265] In an exemplary embodiment, the shape of the data signal line 52 can be a straight line or a broken line shape with the main part extending along the second direction Y. The data signal line 52 is connected to the third connection electrode 43 through the thirty-second via V32. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via, the data signal line 52 realizes writing data signals to the first electrode of the fourth transistor T4.

[0266] In an exemplary embodiment, the shape of the anode connection electrode 53 can be a block shape (such as a rectangular shape, etc.). The anode connection electrode 53 is connected to the fourth connection electrode 44 through the thirty-third via V33. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via, the anode connection electrode 53 realizes connection with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 53 is configured to connect with the subsequently formed anode, so as to realize driving of the light emitting device by the pixel driving circuit.

[0267] In the example embodiment, the first initial connection line 84 can also be included in the at least one circuit unit. The first initial connection line 84 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the first initial connection line 84 is connected to the fifth connection electrode 45 through the thirty-fourth via hole V34. Since the fifth connection electrode 45 is connected to the first initial signal line 81, the first initial signal line 81 with the main body extending along the first direction X and the first initial connection line 84 with the main body extending along the second direction Y are connected to each other, and the first initial signal line 81 and the first initial connection line 84 form a meshed communication structure for transmitting the first initial signal on the display substrate, which can effectively reduce the resistance of the first initial connection line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0268] In the example embodiment, the first initial signal line 81 of the second conductive layer can be arranged in each unit row, and the first initial connection line 84 of the fourth conductive layer can be arranged in every two unit columns, and the plurality of first initial connection lines 84 are respectively connected to the plurality of first initial signal lines 81 to form a meshed communication structure for transmitting the first initial signal.

[0269] In the example embodiment, the first initial connection line 84 can be arranged in the circuit unit of the Nth unit column.

[0270] In the example embodiment, the second initial connection line 85 can also be included in the at least one circuit unit. The second initial connection line 85 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the second initial connection line 85 is connected to the second initial connection block 82-1 through the thirty-fifth via hole V35. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the second initial signal line 82 with the main body extending along the first direction X and the second initial connection line 85 with the main body extending along the second direction Y are connected to each other, and the second initial signal line 82 and the second initial connection line 85 form a meshed communication structure for transmitting the second initial signal on the display substrate, which can effectively reduce the resistance of the second initial connection line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0271] In the example embodiment, the second initial signal line 82 of the third conductive layer can be arranged in each unit row, and the second initial connection line 85 of the fourth conductive layer can be arranged in every two unit columns, and the plurality of second initial signal lines 82 are respectively connected to the plurality of second initial connection lines 85 to form a meshed communication structure for transmitting the second initial signal.

[0272] In an example embodiment, the second initial connection line 85 can be disposed in the circuit units of the N+2th unit column.

[0273] In an example embodiment, the third initial connection line 86 can also be included in at least one circuit unit. The third initial connection line 86 can be in a straight line shape or a broken line shape with a main body portion extending along the second direction Y, and the third initial connection line 86 is connected to the third initial connection block 83-1 through the third thirty-sixth via hole V36. Since the third initial connection block 83-1 is connected to the third initial signal line 83, the third initial signal line 83 with the main body portion extending along the first direction X and the third initial connection line 86 with the main body portion extending along the second direction Y are connected to each other, and the third initial signal line 83 and the third initial connection line 86 form a meshed communication structure for transmitting the third initial signal on the display substrate, which not only effectively reduces the resistance of the third initial connection line and reduces the voltage drop of the third initial signal, but also effectively improves the uniformity of the third initial signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0274] In an example embodiment, the third initial signal line 83 of the third conductive layer can be disposed in each unit row, and the third initial connection line 86 of the fourth conductive layer can be disposed every 2 unit columns. The plurality of third initial signal lines 83 are respectively connected to the plurality of third initial connection lines 86, and form a meshed communication structure for transmitting the third initial signal.

[0275] In an example embodiment, the third initial connection line 86 can be disposed in the circuit units of the N+1th unit column.

[0276] The subsequent preparation process can include forming a second planar layer pattern, the second planar layer being provided with a plurality of anode via holes, the orthographic projection of the anode via hole on the substrate being within the range of the orthographic projection of the anode connection electrode on the substrate, the second planar layer in the anode via hole being removed to expose the surface of the anode connection electrode, and the anode via hole being configured to allow the subsequently formed anode to be connected to the anode connection electrode through the via hole.

[0277] So far, the driving circuit layer has been prepared on the substrate. In an example embodiment, after the driving circuit layer is prepared, the light-emitting structure layer and the encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be described here.

[0278] In an example embodiment, in a plane parallel to the display substrate, the driving circuit layer can include a plurality of circuit units, at least one circuit unit can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a fifth scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer can include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer stacked in order on the base.

[0279] In an example embodiment, the semiconductor layer can include at least a first active layer to a ninth active layer, the first conductive layer can include at least a first gate electrode, a second gate electrode, a fourth gate electrode, a seventh gate electrode, an eighth gate electrode, a ninth gate electrode, a gate connection line, a light-emitting signal line, a first plate, and a second plate, the second conductive layer can include at least a third plate, a fourth plate, and a first initial signal line, the third conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a second initial signal line, a third initial signal line, and a plurality of connection electrodes, and the fourth conductive layer can include at least a first power supply line, a data signal line, and an anode connection electrode.

[0280] In an example embodiment, the base can be a flexible base or can be a rigid base. The rigid base can be, but is not limited to, one or more of glass, quartz, and the flexible base can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible base can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked in order, the material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the base, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0281] In the example embodiments, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer. The first planar layer and the second planar layer can adopt an organic material, such as resin, etc. The active layer can adopt a material such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathienyl or polythienyl, etc., i.e., the present disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.

[0282] The example embodiments of the present disclosure provide a display substrate, which is composed of a pixel driving circuit of nine transistors and two capacitors, can not only realize separation of the compensation stage and the data writing stage, can quickly realize writing of the data signal, effectively ensure the charge amount of the writing capacitor, effectively avoid display unevenness and other quality problems under high-frequency display and low gray-scale display, and through the capacitor self-discharge method for sampling of the threshold voltage in the compensation stage, effectively avoid problems such as insufficient threshold compensation of the driving transistor, improve the compensation effect, and can support higher frame frequency display.

[0283] In the pixel driving circuit of the example embodiments of the present disclosure, the first transistor T1 and the second transistor T2 are connected to the same scan signal line, and the first transistor T1 and the second transistor T2 share one sub-gate electrode, through flexible design of the transistor layout, the layout space can be optimized, the occupied area of the pixel driving circuit is reduced, and high resolution can be realized.

[0284] In the display substrate of the example embodiments of the present disclosure, the power supply connection line extending along the first direction X and the first power supply line extending along the second direction Y are arranged in the main body part, and the first power supply line and the first power supply connection line are connected to each other to form a mesh communication structure on the display substrate, which can not only effectively reduce the resistance of the first power supply line and reduce the voltage drop of the first power supply signal, but also effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0285] The display substrate of the embodiment of the present disclosure forms a mesh communication structure on the display substrate by arranging the first initial signal line extending along the first direction X and the first initial connection line extending along the second direction Y, and the first initial signal line and the first initial connection line are connected to each other, which not only can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, but also can effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0286] The display substrate of the embodiment of the present disclosure forms a mesh communication structure on the display substrate by arranging the second initial signal line extending along the first direction X and the second initial connection line extending along the second direction Y, and the second initial signal line and the second initial connection line are connected to each other, which not only can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, but also can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0287] The display substrate of the embodiment of the present disclosure forms a mesh communication structure on the display substrate by arranging the third initial signal line extending along the first direction X and the third initial connection line extending along the second direction Y, and the third initial signal line and the third initial connection line are connected to each other, which not only can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, but also can effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0288] The preparation process of the present disclosure can be well compatible with the existing preparation process, and has the advantages of simple process implementation, easy implementation, high production efficiency, low production cost, and high yield.

[0289] FIG. 15 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 15, the pixel driving circuit of the present embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in FIG. 4, except that the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are connected to each other, and both are connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0290] In the example embodiment, the pixel driving circuit is connected with 10 signal lines, which are first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, emitting signal line EM, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power supply line VDD respectively. Different from the embodiment shown in FIG. 4, the first initial signal line is removed in the example embodiment, or the two initial signal lines are combined into one initial signal line.

[0291] In the example embodiment, the driving timing of the pixel driving circuit is basically the same as that shown in FIG. 5, and the driving current is basically the same as well. The difference is that the potential of the fifth node N5 is Vint2+|Vth| when the second stage B is completed, and Vint2 is the voltage of the second initial signal of the second initial signal line INIT2.

[0292] FIG. 16 is a schematic diagram of the planar structure of another display substrate according to an example embodiment of the present disclosure. As shown in FIG. 16, the main structure of the display substrate is basically the same as that shown in FIG. 6. In the example embodiment, the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected with the same third scan signal line S3. The gate electrode of the seventh transistor T7 of the circuit unit in the current unit row is connected with the first scan signal line S1 in the next unit row, and the gate electrode of the eighth transistor T8 of the circuit unit in the current unit row is connected with the first scan signal line S1 in the current unit row. The difference is that the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are connected with each other and connected with the second initial signal line 82 in the example embodiment. That is, the first initial signal line is not provided in the second conductive layer, and the first initial connection line is not provided in the fourth conductive layer.

[0293] In the example embodiment, the preparation process of the display substrate can include the following operations.

[0294] (21) Forming a semiconductor layer pattern. In the example embodiment, the process of forming the semiconductor layer pattern and the formed semiconductor layer pattern are basically the same as those shown in FIG. 6. The difference is that, in the example embodiment, the first region 11-1 of the first active layer of the circuit unit in the current unit row is arranged in the circuit unit of the previous unit row and connected with the first region 17-1 of the seventh active layer of the circuit unit in the previous unit row, or the first region 11-1 of the first active layer of the circuit unit in the next unit row is arranged in the circuit unit of the current unit row, and the first region 17-1 of the seventh active layer of the circuit unit in the current unit row is connected with each other, as shown in FIG. 17.

[0295] In the example embodiment, the first region 11-1 of the first active layer can be configured as the first region 17-1 of the seventh active layer to be connected with the second initial signal line formed subsequently.

[0296] (22) Forming a first conductive layer pattern. In the example embodiment, the process of forming the first conductive layer pattern and the formed first conductive layer pattern are substantially the same as the scheme shown in FIG. 6, as shown in FIGS. 18A and 18B, which are schematic diagrams of the first conductive layer in FIG. 18A.

[0297] (23) Forming a second conductive layer pattern. In the example embodiment, the process of forming the second conductive layer pattern and the formed second conductive layer pattern are substantially the same as the scheme shown in FIG. 6, except that the second conductive layer is not provided with the first initial signal line, as shown in FIGS. 19A and 19B, which are schematic diagrams of the second conductive layer in FIG. 19A.

[0298] (24) Forming a fourth insulating layer pattern. In the example embodiment, the process of forming the fourth insulating layer pattern and the formed vias are substantially the same as the scheme shown in FIG. 6, except that the vias of each circuit unit at least include the second via V2 to the eighth via V8, the tenth via V10 to the seventeenth via V17, as shown in FIG. 20.

[0299] In the example embodiment, since the first region of the seventh active layer of the circuit unit in the present unit row can be configured as the first region of the first active layer of the circuit unit in the next unit row, the seventh via V7 of the circuit unit in the present unit row can be configured as the first via of the circuit unit in the next unit row. Since the second conductive layer is not provided with the first initial signal line, the ninth via is not provided in the present embodiment.

[0300] (25) Forming a third conductive layer pattern. In the example embodiment, the process of forming the third conductive layer pattern and the formed third conductive layer pattern are substantially the same as the scheme shown in FIG. 6, except that the third conductive layer is not provided with the fifth connection electrode, as shown in FIGS. 21A and 21B, which are schematic diagrams of the third conductive layer in FIG. 21A.

[0301] In the example embodiment, the second initial signal line 82 can have a shape of a straight line or a broken line extending along the first direction X, and the second initial signal line 82 is connected with the first region of the seventh active layer (also the first region of the first active layer) in each circuit unit through the seventh via V7, so that the second initial signal line 82 can write the second initial signal to the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7.

[0302] In the example embodiment, the second initial signal line 82 is provided with a second initial connection block 82-1, which can be arranged in the circuit units of the Nth unit column and the N+2th unit column.

[0303] In the example embodiment, the third initial signal line 83 can be in the shape of a straight line or a broken line extending along the first direction X, and the third initial signal line 83 is connected to the first region of the eighth active layer in each circuit unit through the eighth via V8, so that the third initial signal line 83 can write the third initial signal to the first electrode of the eighth transistor T8.

[0304] In the example embodiment, the third initial signal line 83 is provided with a third initial connection block 83-1, which can be arranged in the circuit units of the N+1th unit column.

[0305] (26) Forming a first planar layer pattern. In the example embodiment, the process of forming the first planar layer pattern and the formed plurality of vias are basically the same as those shown in FIG. 6, except that the first planar layer is not provided with a thirty-fourth via, as shown in FIG. 22.

[0306] In the example embodiment, the thirty-fifth via V35 exposes the surface of the second initial connection block 82-1, and the thirty-fifth via V35 can be arranged in the circuit units of the Nth unit column and the N+2th unit column.

[0307] In the example embodiment, the thirty-sixth via V36 exposes the surface of the third initial connection block 83-1, and the thirty-sixth via V36 can be arranged in the circuit units of the N+1th unit column.

[0308] (27) Forming a fourth conductive layer pattern. In the example embodiment, the process of forming the fourth conductive layer pattern and the formed fourth conductive layer pattern are basically the same as those shown in FIG. 6, except that the fourth conductive layer is not provided with a first initial connection line, as shown in FIGS. 23A and 23B, which is a schematic view of the fourth conductive layer in FIG. 23A.

[0309] In the example embodiment, the second initial connection line 85 is connected to the second initial connection block 82-1 through the thirty-fifth via V35, so that the second initial signal line 82 and the second initial connection line 85 form a mesh-like communication structure for transmitting the second initial signal on the display substrate.

[0310] In the example embodiment, the second initial signal line 82 of the third conductive layer can be arranged in each unit row, and the second initial connection line 85 of the fourth conductive layer can be arranged every 1 unit column.

[0311] In an exemplary embodiment, the second initial connection line 85 can be arranged in the circuit units of the Nth unit column and the N+2th unit column.

[0312] In an exemplary embodiment, the third initial connection line 86 is connected with the third initial connection block 83-1 through the thirty-sixth via V36, so that the third initial signal line 83 and the third initial connection line 86 form a meshed transmission structure for transmitting the third initial signal on the display substrate.

[0313] In an exemplary embodiment, the third initial signal line 83 of the third conductive layer can be arranged in each unit row, and the third initial connection line 86 of the fourth conductive layer can be arranged every 1 unit column.

[0314] In an exemplary embodiment, the third initial connection line 86 can be arranged in the circuit units of the N+1th unit column.

[0315] The subsequent preparation process can include forming a second planar layer pattern, and sequentially preparing a light-emitting structure layer and an encapsulation structure layer, and the forming process and the pattern are basically the same as the scheme shown in FIG. 6, which will not be described here.

[0316] The exemplary embodiments of the present disclosure provide a display substrate, which not only has the technical effects of the scheme shown in FIG. 6, but also can optimize the layout space, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by reducing one initial signal line.

[0317] FIG. 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 24, the pixel driving circuit of the present embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in FIG. 15, except that the second electrode of the fourth transistor T4 is connected with the second node N2.

[0318] In an exemplary embodiment, the connection structure of the first node N1, the third node N3 and the fourth node N4 of the present embodiment is basically the same as that of the embodiments shown in FIG. 4 and FIG. 15, except that the second node N2 is connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, the second electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9, respectively, and the fifth node N5 is connected with the first electrode of the ninth transistor T9, the second end of the first capacitor C1 and the second end of the second capacitor C2, respectively.

[0319] In the example embodiment, the driving timing of the pixel driving circuit of the embodiment is basically the same as the driving timing shown in FIG. 5, and the driving current is basically the same, except that, in the data writing stage, the second scan signal line S2 and the fourth scan signal line S4 are low-level signals, the fourth transistor T4 and the ninth transistor T9 are synchronously turned on, and the data signal line writes the data signal to the fifth node N5. Therefore, the low-level signal pulse width of the second scan signal line S2 of the embodiment is widened accordingly.

[0320] FIG. 25 is a schematic diagram of a planar structure of a display substrate according to another example embodiment of the present disclosure. As shown in FIG. 25, the main structure of the display substrate of the embodiment is basically the same as the embodiment shown in FIG. 16, the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 of the embodiment are connected to the same third scan signal line 33, the gate electrode of the seventh transistor T7 of the circuit unit in the current unit row is connected to the first scan signal line 31 in the next unit row, the gate electrode of the eighth transistor T8 of the circuit unit in the current unit row is connected to the first scan signal line 31 in the current unit row, the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are connected to each other and connected to the second initial signal line 82. The difference is that the connection relationship of the fourth transistor T4 and the ninth transistor T9 of the embodiment is different.

[0321] In the example embodiment, the preparation process of the display substrate of the embodiment can include the following operations.

[0322] (31) Forming a semiconductor layer pattern. In the example embodiment, the process of forming the semiconductor layer pattern and the formed semiconductor layer pattern are basically the same as the scheme shown in FIG. 16, except that the first region 19-1 of the ninth active layer in the embodiment can be separately provided, the first region 13-1 of the third active layer can simultaneously serve as the second region 14-2 of the fourth active layer, the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer, and the second region 19-2 of the ninth active layer, constituting the second node N2 of the pixel driving circuit, as shown in FIG. 26.

[0323] (22) Forming a first conductive layer pattern. In the example embodiment, the process of forming the first conductive layer pattern and the formed first conductive layer pattern are basically the same as the scheme shown in FIG. 16, except that the fourth gate electrode 24 can have a strip shape extending along the first direction X, the area where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, the ninth gate electrode 29 can have an "L" shape, and the area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the double-gate structure, as shown in FIGS. 27A and 27B, where FIG. 27B is a schematic diagram of the first conductive layer in FIG. 27A.

[0324] (33) Forming a second conductive layer pattern. In an exemplary embodiment, the process of forming the second conductive layer pattern and the formed second conductive layer pattern are substantially the same as the scheme shown in FIG. 16, as shown in FIGS. 28A and 28B, FIG. 28B being a schematic view of the second conductive layer in FIG. 28A.

[0325] (34) Forming a fourth insulating layer pattern. In an exemplary embodiment, the process of forming the fourth insulating layer pattern and the formed plurality of vias are substantially the same as the scheme shown in FIG. 16, except that the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, and the fourth via V4 is configured to enable the second connection electrode formed subsequently to connect with the first region of the ninth active layer through the via, as shown in FIG. 29.

[0326] (35) Forming a third conductive layer pattern. In an exemplary embodiment, the process of forming the third conductive layer pattern and the formed third conductive layer pattern are substantially the same as the scheme shown in FIG. 16, except that the first end of the second connection electrode 42 is connected with the first region of the ninth active layer through the fourth via V4, the second end of the second connection electrode 42 is connected with the second plate 72 through the eleventh via V11, and the position between the first end and the second end of the second connection electrode 42 is connected with the third plate 73 through the twelfth via V12, realizing the interconnection between the first electrode of the ninth transistor T9, the third plate 73 of the first capacitor, and the second plate 72 of the second capacitor, forming a fifth node N5 of the pixel driving circuit, as shown in FIGS. 30A and 30B, FIG. 30B being a schematic view of the third conductive layer in FIG. 30A.

[0327] The subsequent preparation process can include forming a first planar layer, a fourth conductive layer, and a second planar layer pattern, and sequentially preparing a light-emitting structure layer and an encapsulation structure layer, the forming process and the pattern being substantially the same as the scheme shown in FIG. 16, which will not be described here.

[0328] FIG. 31 is an equivalent circuit diagram of yet another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 31, the pixel driving circuit of the present embodiment can be of a 9T2C structure, and the main structure is substantially the same as that of the embodiment shown in FIG. 4, except that the gate electrode of the seventh transistor T7 of the circuit unit in the present unit row is connected with the first scan signal line 31 in the present unit row, i.e., the seventh transistor T7 and the eighth transistor T8 of the circuit unit in the present unit row are connected with the same scan signal line, i.e., the same first scan signal line 31.

[0329] In the exemplary embodiment, the driving timing of the pixel driving circuit of the present embodiment is basically the same as the driving timing shown in FIG. 5, and the driving current is also basically the same, except that the first stage A further includes that the seventh transistor T7 is turned on, and the second initial signal of the second initial signal line INIT2 is written to the fourth node N4, and the fourth node N4 (the light emitting device) is initialized. In addition, in the fifth stage E, the seventh transistor T7 and the eighth transistor T8 are turned on at the same time, and are turned off at the same time.

[0330] FIG. 32 is an equivalent circuit diagram of still another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 32, the pixel driving circuit of the present embodiment can be a 9T2C structure, and the main structure is basically the same as the embodiment shown in FIG. 15, except that the gate electrode of the seventh transistor T7 of the circuit unit in the present unit row is connected with the first scanning signal line 31 in the present unit row, that is, the seventh transistor T7 and the eighth transistor T8 of the circuit unit in the present unit row are connected with the same scanning signal line, that is, the same first scanning signal line 31.

[0331] In the exemplary embodiment, the driving timing of the pixel driving circuit of the present embodiment is basically the same as the driving timing shown in FIG. 5, and the driving current is also basically the same, except that the first stage A further includes that the seventh transistor T7 is turned on, and the second initial signal of the second initial signal line INIT2 is written to the fourth node N4, and the fourth node N4 (the light emitting device) is initialized. In addition, in the fifth stage E, the seventh transistor T7 and the eighth transistor T8 are turned on at the same time, and are turned off at the same time.

[0332] FIG. 33 is an equivalent circuit diagram of still another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 33, the pixel driving circuit of the present embodiment can be a 9T2C structure, and the main structure is basically the same as the embodiment shown in FIG. 4, except that the gate electrode of the second transistor T2 in the present embodiment is connected with the third scanning signal line S3, the first electrode of the second transistor T2 is connected with the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected with the third node N3.

[0333] In the exemplary embodiment, the first node N1 of the present embodiment is connected with the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively, and the structures of the other nodes are basically the same as the embodiment shown in FIG. 4.

[0334] In the exemplary embodiment, the driving timing of the pixel driving circuit of the present embodiment is basically the same as the driving timing shown in FIG. 5, and the driving current is also basically the same, which will not be described herein again.

[0335] Fig. 34 is an equivalent circuit diagram of another pixel driving circuit according to an example embodiment of the present disclosure. As shown in Fig. 34, the pixel driving circuit according to the present embodiment can be of a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Fig. 33, except that the gate electrode of the seventh transistor T7 of the circuit unit in the present unit row is connected with the first scan signal line 31 in the present unit row, i.e., the seventh transistor T7 and the eighth transistor T8 of the circuit unit in the present unit row are connected with the same scan signal line, i.e., the same first scan signal line 31.

[0336] In the example implementation, the driving timing of the pixel driving circuit according to the present embodiment is basically the same as that shown in Fig. 5, and the driving current is basically the same, except that the first stage A further includes that the seventh transistor T7 is turned on, and the second initial signal of the second initial signal line INIT2 is written to the fourth node N4 to initialize the fourth node N4 (the light emitting device). In addition, in the fifth stage E, the seventh transistor T7 and the eighth transistor T8 are turned on at the same time and are turned off at the same time.

[0337] Fig. 35 is an equivalent circuit diagram of another pixel driving circuit according to an example embodiment of the present disclosure. As shown in Fig. 35, the pixel driving circuit according to the present embodiment can be of a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Fig. 4, except that the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 can be oxide transistors, and the other transistors are low-temperature polysilicon transistors.

[0338] In the example implementation, the low-temperature polysilicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. By integrating the low-temperature polysilicon transistor and the oxide transistor on one display substrate to form an LTPS+Oxide (LTPO for short) display substrate, the advantages of both can be utilized, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0339] In the example implementation, the driving timing of the pixel driving circuit according to the present embodiment is basically the same as that shown in Fig. 5, and the corresponding driving signals are inverted, and the driving current is basically the same. Details are not repeated here.

[0340] Fig. 36 is an equivalent circuit diagram of another pixel driving circuit according to an example embodiment of the present disclosure. As shown in Fig. 36, the pixel driving circuit according to the present embodiment can be of a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Fig. 24, except that the first transistor T1, the second transistor T2 and the ninth transistor T9 can be oxide transistors, and the other transistors are low-temperature polysilicon transistors.

[0341] In the exemplary embodiment, the driving timing of the pixel driving circuit is basically the same as that shown in FIG. 5, the corresponding driving signals are inverted, and the driving current is basically the same. Details are not repeated here.

[0342] In some possible embodiments, the embodiments shown in FIG. 15, FIG. 31, FIG. 32, FIG. 33, and FIG. 34 can also adopt the LTPO structure, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 or multiple transistors are oxide transistors, and the other transistors are low-temperature polysilicon transistors. The present disclosure is not limited here.

[0343] In some possible embodiments, the embodiment shown in FIG. 24 can also adopt the structure that the gate electrode of the seventh transistor T7 of the circuit unit in the unit row is connected with the first scan signal line 31 in the unit row, and the first electrode of the second transistor T2 is connected with the second initial signal line INIT2, and the present disclosure is not limited here.

[0344] In the exemplary embodiments, the embodiments and the features in the embodiments in the present disclosure can be combined with each other arbitrarily without conflict.

[0345] The foregoing structures and their preparation processes of the present disclosure are only exemplary descriptions. In the exemplary embodiments, the corresponding structures can be changed, and the patterning processes can be increased or reduced according to actual needs. The present disclosure is not limited here.

[0346] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc. The present disclosure is not limited here.

[0347] The display substrate provided by the present disclosure can be driven by a driving method of a display substrate. In an exemplary embodiment, the display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, the second electrode of the first transistor being connected to the gate electrode of the third transistor and the first end of the first capacitor respectively, the first electrode of the ninth transistor being connected to the second end of the first capacitor and the second end of the second capacitor respectively, the second electrode of the ninth transistor being connected to the first electrode of the third transistor and the second electrode of the eighth transistor respectively, and the first electrode of the fourth transistor being connected to a data signal line; the display substrate is configured to display corresponding display content, the display content comprising a plurality of display frames, at least one display frame comprising a refresh frame, the refresh frame comprising at least a compensation phase and a data writing phase performed in sequence, and the compensation phase being performed by sampling the threshold voltage in a capacitor self-discharge manner.

[0348] In an exemplary embodiment, the refresh frame comprises at least an initialization phase, a compensation phase, and a data writing phase.

[0349] In the initialization phase, the eighth transistor and the ninth transistor are turned on, a third initial signal of a third initial signal line is written to the second end of the first capacitor and the second end of the second capacitor, and the second capacitor is charged.

[0350] In the compensation phase, the first transistor is turned on, the gate electrode of the third transistor is initialized, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor and the turned-on third transistor, so that the voltage difference across the first capacitor is |Vth|, and Vth is the threshold voltage of the third transistor.

[0351] In the data writing phase, the fourth transistor is turned on, and a data signal of the data signal line is written to the second end of the first capacitor and the second end of the second capacitor.

[0352] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, the first electrode of the second transistor being connected to the second electrode of the first transistor, the gate electrode of the third transistor, and the first end of the first capacitor respectively, and the second electrode of the second transistor being connected to the second electrode of the third transistor; in the compensation phase, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor, and the turned-on second transistor.

[0353] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor, a first electrode of the second transistor being connected with the second initial signal line, a second electrode of the second transistor being connected with the second electrode of the third transistor; in the compensation stage, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor and the turned-on second transistor.

[0354] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected with the second initial signal line, a second electrode of the seventh transistor being connected with the light emitting device; in the initialization stage, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light emitting device, or, in the compensation stage, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light emitting device.

[0355] In an exemplary embodiment, the at least one display frame further comprises a holding frame, the holding frame comprising at least an adjustment stage.

[0356] In the adjustment stage, the eighth transistor is turned on, and the third initial signal of the third initial signal line is written to the first electrode of the third transistor to adjust the bias state of the third transistor.

[0357] In an exemplary embodiment, the pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor being connected with the second initial signal line, a second electrode of the seventh transistor being connected with the light emitting device; in the adjustment stage, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light emitting device.

[0358] The driving method of the display substrate provided by the present disclosure not only separates the compensation stage and the data writing stage, but also uses the self-discharge mode of the capacitor to sample the threshold voltage in the compensation stage, which can quickly write the data signal, support higher frame frequency display, and improve the compensation effect.

[0359] The driving method of the display substrate provided by the present disclosure can effectively improve the hysteresis of the third transistor by applying a direct current signal to the first electrode of the third transistor, which is conducive to improving the residual image and supporting low-frequency display, and improving the display effect.

[0360] The present disclosure also provides a display device comprising the display substrate described above. The display device can be any product or component with display function, such as mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigation devices, etc., and the embodiments of the present disclosure are not limited thereto.

[0361] While the embodiments disclosed in the present disclosure are as described above, it should be noted that the above-described embodiments are merely exemplary, and are not intended to be limiting. Accordingly, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made without departing from the scope of the present disclosure.

Claims

A display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one of the circuit units including a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, a second electrode of the first transistor being connected to a gate electrode of the third transistor and a first terminal of the first capacitor, respectively, a first electrode of the ninth transistor being connected to a second terminal of the first capacitor and a second terminal of the second capacitor, respectively, a second electrode of the ninth transistor being connected to a first electrode of the third transistor and a second electrode of the eighth transistor, respectively, and a first electrode of the fourth transistor being connected to a data signal line. The display substrate according to claim 1, wherein The pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the second electrode of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor, respectively, and a second electrode of the second transistor being connected to the second electrode of the third transistor. The display substrate according to claim 1, wherein The pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to a second initial signal line, and a second electrode of the second transistor being connected to the second electrode of the third transistor. The display substrate according to claim 2 or 3, wherein The first transistor and the second transistor are connected to the same scan signal line. The display substrate according to claim 4, wherein In a direction perpendicular to the display substrate, the display substrate includes at least a first gate metal layer disposed on a base, a second gate metal layer disposed on a side of the first gate metal layer away from the base, and a first source-drain metal layer disposed on a side of the second gate metal layer away from the base, a gate electrode of the first transistor and a gate electrode of the second transistor being disposed in the first gate metal layer, and the scan signal line being disposed in the first source-drain metal layer. The display substrate according to claim 5, wherein The gate electrode of the first transistor and the gate electrode of the second transistor are an integrated structure connected to each other. The display substrate according to claim 6, wherein The first transistor and the second transistor are double-gate structures, the gate electrode of the first transistor includes a first sub-gate electrode and a third sub-gate electrode, the gate electrode of the second transistor includes a second sub-gate electrode and the third sub-gate electrode, and the first transistor and the second transistor share the third sub-gate electrode. The display substrate according to claim 7, wherein The first sub-gate electrode and the second sub-gate electrode are in the shape of a strip extending along a first direction, the third sub-gate electrode is in the shape of a strip extending along a second direction, the first direction and the second direction intersect, the first sub-gate electrode and the second sub-gate electrode are disposed on one side of the third sub-gate electrode in the first direction, the first sub-gate electrode is disposed on one side of the third sub-gate electrode in the opposite direction of the second direction, and the second sub-gate electrode is disposed on one side of the third sub-gate electrode in the second direction, forming a "C" shape. The display substrate according to claim 1, wherein The second electrode of the fourth transistor is connected to the first electrode of the ninth transistor, or the second electrode of the fourth transistor is connected to the second electrode of the ninth transistor. The display substrate according to claim 1, wherein The first electrode of the first transistor is connected with a first initial signal line, and the pixel drive circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected with a second initial signal line, and the second electrode of the seventh transistor is connected with the light emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row. The display substrate according to claim 1, wherein The first electrode of the first transistor is connected with a first initial signal line, and the pixel drive circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected with a second initial signal line, and the second electrode of the seventh transistor is connected with the light emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row. The first electrode of the first transistor is connected with a first initial signal line, and the pixel drive circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected with a second initial signal line, and the second electrode of the seventh transistor is connected with the light emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row. The display substrate according to claim 1, wherein The first electrode of the first transistor is connected with a first initial signal line, and the pixel drive circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected with a second initial signal line, and the second electrode of the seventh transistor is connected with the light emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row. The display substrate according to claim 1, wherein The first electrode of the first transistor is connected with a first initial signal line, and the pixel drive circuit further comprises a seventh transistor, the first electrode of the seventh transistor is connected with a second initial signal line, and the second electrode of the seventh transistor is connected with the light emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in the present unit row are connected with a first scan signal line in the present unit row. A display device comprises the display substrate as claimed in any one of claims 1 to 13. A driving method of a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel drive circuit, the pixel drive circuit comprising at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a drive transistor, the second electrode of the first transistor being connected with the gate electrode of the third transistor and the first end of the first capacitor respectively, the first electrode of the ninth transistor being connected with the second end of the first capacitor and the second end of the second capacitor respectively, the second electrode of the ninth transistor being connected with the first electrode of the third transistor and the second electrode of the eighth transistor respectively, the first electrode of the fourth transistor being connected with a data signal line; the display substrate is configured to display corresponding display content, the display content comprising a plurality of display frames, at least one display frame comprising a refresh frame, the refresh frame comprising at least a compensation stage and a data writing stage carried out in sequence, and the compensation stage being carried out by capacitor self-discharge to sample threshold voltage. The driving method according to claim 15, wherein The refresh frame comprises at least an initialization stage, a compensation stage and a data writing stage; In the initialization stage, the eighth transistor and the ninth transistor are turned on, a third initial signal of a third initial signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor, and the second capacitor is charged; In the compensation stage, the first transistor is turned on, the gate electrode of the third transistor is initialized, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor and the turned-on third transistor, so that the voltage difference across the first capacitor is |Vth|, and Vth is the threshold voltage of the third transistor; In the data writing stage, the fourth transistor is turned on, and a data signal of the data signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor. The driving method according to claim 16, wherein The pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected with the second electrode of the first transistor, the gate electrode of the third transistor and the first terminal of the first capacitor respectively, and a second electrode of the second transistor is connected with the second electrode of the third transistor; In the compensation stage, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor and the turned-on second transistor. The driving method according to claim 16, wherein The pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected with the second initial signal line, and a second electrode of the second transistor is connected with the second electrode of the third transistor; In the compensation stage, the second transistor is turned on, and the first capacitor and the second capacitor are discharged through the turned-on ninth transistor, the turned-on third transistor and the turned-on second transistor. The driving method according to claim 16, wherein The pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with the light emitting device; In the initialization stage, the seventh transistor is turned on, and a second initial signal of the second initial signal line initializes the light emitting device, or in the compensation stage, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light emitting device. At least one display frame further comprises a holding frame, and the holding frame at least comprises an adjustment stage; The driving method according to claim 15, wherein In the adjustment stage, the eighth transistor is turned on, a third initial signal of a third initial signal line is written to the first electrode of the third transistor, and the bias state of the third transistor is adjusted. The pixel driving circuit further comprises a seventh transistor, a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with the light emitting device; in the adjustment stage, the seventh transistor is turned on, and a second initial signal of the second initial signal line initializes the light emitting device. The driving method according to claim 20, wherein ​

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