Pixel driving circuit and driving method therefor, and display panel and display apparatus

Abstract

Provided is a pixel driving circuit, comprising a driving sub-circuit, a reset sub-circuit, a write sub-circuit, a coupling sub-circuit, and a modulation sub-circuit, wherein the reset sub-circuit is coupled to a reference signal line, an initialization signal line, a first node and a second node; the write sub-circuit is coupled to a data signal line and the first node; the driving sub-circuit is coupled to a first power signal line, the first node and the second node, the second node being coupled to an element to be driven; the coupling sub-circuit is coupled to the first node and the second node; and the modulation sub-circuit is coupled to a modulation signal line and is further coupled to the first node or the second node, and the modulation sub-circuit is configured to couple a voltage variation of a modulation signal transmitted by the modulation signal line to the second node or the first node, such that the driving sub-circuit is disconnected under the control of the voltage of the first node and the voltage of the second node.

Description

Pixel driving circuit, driving method thereof, display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof, a display panel and a display device. BACKGROUND

[0002] Display panels, such as OLED (Organic Light-Emitting Diode) display panels or QLED (Quantum Dot Light Emitting Diodes) display panels, have been increasingly applied in various display devices, such as mobile phones, tablets, computers and televisions, due to their self-luminous characteristics.

[0003] The PPI (Pixels per inch) of a display panel represents the number of pixels per inch, and the higher the PPI value, the higher the density of the display panel in displaying a picture, the higher the picture fidelity and the richer the picture details. At present, high PPI has become an important direction for the development of display panels, such as OLED display panels.

[0004] At present, the number of transistors in the pixel driving circuit of a display panel is relatively large, which is one of the important factors affecting the improvement of PPI. Therefore, reducing the number of transistors in the pixel driving circuit is the key to improving PPI.

[0005] SUMMARY

[0006] In one aspect, a pixel driving circuit is provided, comprising a driving sub-circuit, a reset sub-circuit, a writing sub-circuit, a coupling sub-circuit, and a modulation sub-circuit. The reset sub-circuit is coupled to a reference signal line, an initialization signal line, a first node, and a second node. The reset sub-circuit is configured to transmit a reference signal received at the reference signal line to the first node and transmit an initialization signal received at the initialization signal line to the second node. The writing sub-circuit is coupled to a data signal line and the first node. The writing sub-circuit is configured to transmit a data signal received at the data signal line to the first node. The driving sub-circuit is coupled to a first power signal line, the first node, and the second node. The second node is coupled to a to-be-driven element. The driving sub-circuit is configured to be turned on under the control of a first power signal transmitted by the first power signal line, a voltage of the first node, and a voltage of the second node, to generate a driving signal to drive the to-be-driven element. The coupling sub-circuit is coupled to the first node and the second node. The coupling sub-circuit is configured to couple a voltage variation of the first node to the second node. The modulation sub-circuit is coupled to a modulation signal line and the first node. The modulation sub-circuit is configured to couple a voltage variation of a modulation signal transmitted by the modulation signal line to the first node, so that the driving sub-circuit is turned off under the control of the voltage of the first node and the voltage of the second node. Alternatively, the modulation sub-circuit is coupled to the modulation signal line and the second node. The modulation sub-circuit is configured to couple the voltage variation of the modulation signal transmitted by the modulation signal line to the second node, so that the driving sub-circuit is turned off under the control of the voltage of the first node and the voltage of the second node.

[0007] In some embodiments, the modulation sub-circuit comprises a modulation capacitor. A first plate of the modulation capacitor is coupled to the modulation signal line. A second plate of the modulation capacitor is coupled to the first node or the second node.

[0008] In some embodiments, the driving sub-circuit comprises a third transistor. A first gate of the third transistor is coupled to the first node. A first electrode of the third transistor is coupled to the first power signal line. A second electrode of the third transistor is coupled to the second node.

[0009] In some embodiments, the third transistor further comprises a second gate. The second gate of the third transistor is coupled to the second node.

[0010] In some embodiments, the reset sub-circuit comprises a first transistor and a fourth transistor. A first gate of the first transistor is coupled to a reset signal line. A first electrode of the first transistor is coupled to the initialization signal line. A second electrode of the first transistor is coupled to the second node. A gate of the fourth transistor is coupled to a first gate signal line. A first electrode of the fourth transistor is coupled to the reference signal line. A second electrode of the fourth transistor is coupled to the first node.

[0011] In some embodiments, the first transistor further comprises a second gate. The first gate of the first transistor is coupled to the second gate of the first transistor.

[0012] In some embodiments, the writing sub-circuit comprises a second transistor, a gate of the second transistor is coupled with the second gate signal line, a first pole of the second transistor is coupled with the data signal line, and a second pole of the second transistor is coupled with the first node.

[0013] In some embodiments, the coupling sub-circuit comprises a coupling capacitor, a first plate of the coupling capacitor is coupled with the first node, and a second plate of the coupling capacitor is coupled with the second node.

[0014] In some embodiments, the second transistor and the fourth transistor are first-type transistors, and the first-type transistors are P-type low-temperature polysilicon transistors; the first transistor and the third transistor are second-type transistors, and the second-type transistors are N-type oxide transistors.

[0015] In some embodiments, the pixel driving circuit further comprises a direct-current sub-circuit; in the case that the modulation sub-circuit is coupled with the first node, the direct-current sub-circuit is coupled with the direct-current signal line and the second node, and the direct-current sub-circuit is configured to stabilize the voltage of the second node under the action of the direct-current signal transmitted by the direct-current signal line; in the case that the modulation sub-circuit is coupled with the second node, the direct-current sub-circuit is coupled with the direct-current signal line and the first node, and the direct-current sub-circuit is configured to stabilize the voltage of the first node under the action of the direct-current signal transmitted by the direct-current signal line.

[0016] In some embodiments, the direct-current sub-circuit comprises a direct-current capacitor, a first plate of the direct-current capacitor is coupled with the direct-current signal line, and a second plate of the direct-current capacitor is coupled with the second node or the first node.

[0017] In still another aspect, a pixel driving method is provided, which is applied to the pixel driving circuit described above, and includes: a frame period including a reset phase, a compensation phase, a writing phase, a light emitting phase and a modulation phase; in the reset phase, the reset sub-circuit transmits a reference signal received at a reference signal line to the first node, and resets the voltage of the first node to the voltage of the reference signal; the reset sub-circuit transmits an initialization signal received at an initialization signal line to the second node, and resets the voltage of the second node to the voltage of the initialization signal; in the compensation phase, the reset sub-circuit continues to transmit the reference signal received at the reference signal line to the first node; the driving sub-circuit is turned on under the control of the voltage of the first node until the threshold voltage of the driving sub-circuit is stored in the second node, and the driving sub-circuit is turned off; in the writing phase, the writing sub-circuit transmits a data signal received at a data signal line to the first node; the coupling sub-circuit couples the voltage variation of the first node to the second node; the driving sub-circuit is turned on under the control of the first power signal transmitted by the first power signal line, the voltage of the first node and the voltage of the second node; in the light emitting phase, the driving sub-circuit is turned on and outputs a driving current; in the modulation phase, the modulation sub-circuit couples the voltage variation of the modulation signal transmitted by the modulation signal line to the first node; the coupling sub-circuit couples the voltage variation of the first node to the second node; the driving sub-circuit is turned off under the control of the first power signal transmitted by the first power signal line, the voltage of the first node and the voltage of the second node; or, the modulation sub-circuit couples the voltage variation of the modulation signal transmitted by the modulation signal line to the second node; the coupling sub-circuit couples the voltage variation of the second node to the first node; the driving sub-circuit is turned off under the control of the first power signal transmitted by the first power signal line, the voltage of the first node and the voltage of the second node.

[0018] In still another aspect, a display panel is provided, which includes: a substrate, a driving circuit layer arranged on one side of the substrate, and a driving element layer arranged on a side of the driving circuit layer away from the substrate; the driving circuit layer is provided with a plurality of pixel driving circuits described above; the driving element layer includes a plurality of to-be-driven elements, and the to-be-driven elements are coupled with the pixel driving circuits.

[0019] In some embodiments, the pixel driving circuit includes a coupling capacitor; the driving circuit layer includes a bottom metal layer arranged on one side of the substrate, at least one active layer arranged on a side of the bottom metal layer away from the substrate, and a top metal layer arranged on a side of the at least one active layer away from the substrate, the bottom metal layer includes a data signal line pattern; and the top metal layer includes a pattern of the pole plate of the coupling capacitor.

[0020] In some embodiments, the pixel driving circuit includes a second transistor and a fourth transistor; a gate of the second transistor is coupled with a second gate signal line, and a gate of the fourth transistor is coupled with a first gate signal line; the driving circuit layer includes a first active layer disposed on a far side of a bottom metal layer from a substrate, a first gate metal layer disposed on a far side of the first active layer from the substrate, and a first source-drain metal layer disposed on a far side of the first gate metal layer from the substrate; the first active layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor, and the active layer pattern of the second transistor and the active layer pattern of the fourth transistor are connected; the first gate metal layer includes a second gate signal line pattern and a first gate signal line pattern, the second gate signal line pattern overlaps the active layer pattern of the second transistor, and a portion of the second gate signal line pattern overlapping the active layer pattern of the second transistor is a gate pattern of the second transistor; the first gate signal line pattern overlaps the active layer pattern of the fourth transistor, and a portion of the first gate signal line pattern overlapping the active layer pattern of the fourth transistor is a gate pattern of the fourth transistor; the first source-drain metal layer includes a first electrode pattern and a second electrode pattern of the second transistor and a first electrode pattern and a second electrode pattern of the fourth transistor; the second electrode pattern of the second transistor and the second electrode pattern of the fourth transistor are connected; the first electrode pattern and the second electrode pattern of the second transistor are connected through a via hole with the active layer pattern of the second transistor; and the first electrode pattern and the second electrode pattern of the fourth transistor are connected through a via hole with the active layer pattern of the fourth transistor.

[0021] In some embodiments, the bottom metal layer further includes a reference signal line pattern; the first electrode pattern of the fourth transistor is connected through a via hole with the reference signal line pattern; and the first electrode pattern of the second transistor is connected through a via hole with a data signal line pattern.

[0022] In some embodiments, the pixel driving circuit includes a first transistor and a third transistor; a first gate of the first transistor is coupled with a reset signal line, and a second gate of the first transistor is coupled with the reset signal line; the reset signal line includes a first sub-reset signal line and a second sub-reset signal line; the driving circuit layer further includes a third gate metal layer disposed on a side of the first source-drain metal layer away from the substrate, a second active layer disposed on a side of the third gate metal layer away from the substrate, a fourth gate metal layer disposed on a side of the second active layer away from the substrate, and a second source-drain metal layer disposed on a side of the fourth gate metal layer away from the substrate; the third gate metal layer includes a first sub-reset signal line pattern and a second gate pattern of the third transistor; the second active layer includes an active layer pattern of the first transistor and an active layer pattern of the third transistor, and the active layer pattern of the first transistor is connected with the active layer pattern of the third transistor; the first sub-reset signal line pattern overlaps with the active layer pattern of the first transistor, and a portion of the first sub-reset signal line pattern overlapping with the active layer pattern of the first transistor serves as the second gate pattern of the first transistor; the fourth gate metal layer includes a second sub-reset signal line pattern and a first gate pattern of the third transistor; the second sub-reset signal line pattern overlaps with the active layer pattern of the first transistor, and a portion of the second sub-reset signal line pattern overlapping with the active layer pattern of the first transistor serves as the first gate pattern of the first transistor; the second source-drain metal layer includes a first electrode pattern, a second electrode pattern of the first transistor, and a first electrode pattern, a second electrode pattern of the third transistor; the second electrode pattern of the first transistor is connected with the second electrode pattern of the third transistor; the first electrode pattern, the second electrode pattern of the first transistor, and the active layer pattern of the first transistor are connected through a via; the first electrode pattern, the second electrode pattern of the third transistor, and the active layer pattern of the third transistor are connected through a via; and the first sub-reset signal line pattern and the second sub-reset signal line pattern are connected.

[0023] In some embodiments, the display panel includes a display area and a peripheral area, and the first sub-reset signal line pattern and the second sub-reset signal line pattern are connected in the peripheral area.

[0024] In some embodiments, the driving circuit layer further includes a second gate metal layer disposed between the first source-drain metal layer and the third gate metal layer, the second gate metal layer includes a first power signal line pattern and an initialization signal line pattern; the first power signal line pattern and the initialization signal line pattern are arranged alternately; in two adjacent rows of pixel driving circuits, an active layer pattern of the third transistor of one of the rows is connected with the first power signal line pattern, and an active layer pattern of the first transistor of the one of the rows is connected with the initialization signal line pattern; first electrode patterns of the third transistors in the same column are connected in sequence, and first electrode patterns of the first transistors in the same column are connected in sequence.

[0025] In some embodiments, the pixel driving circuit further comprises a coupling capacitor, the coupling capacitor comprises a first sub-coupling capacitor, a second sub-coupling capacitor and a third sub-coupling capacitor; the second gate metal layer further comprises a first plate pattern of the first sub-coupling capacitor; a second gate pattern of the third transistor of the third gate metal layer serves as a second plate pattern of the first sub-coupling capacitor; an active layer pattern of the third transistor of the second active layer serves as a first plate pattern of the second sub-coupling capacitor; a first gate pattern of the third transistor of the fourth gate metal layer serves as a second plate pattern of the second sub-coupling capacitor; the second plate pattern of the second sub-coupling capacitor is connected with the first plate pattern of the first sub-coupling capacitor through a via; the first gate pattern of the third transistor of the fourth gate metal layer further serves as a first plate pattern of the third sub-coupling capacitor; a second plate pattern of the third transistor of the second source-drain metal layer serves as a second plate pattern of the third sub-coupling capacitor.

[0026] In some embodiments, the pixel driving circuit further comprises a modulation capacitor; a first gate pattern of the third transistor of the fourth gate metal layer serves as a first plate pattern of the modulation capacitor; the driving circuit layer further comprises a fifth gate metal layer disposed between the fourth gate metal layer and the second source-drain metal layer, the fifth gate metal layer comprises a modulation signal line pattern, the modulation signal line pattern overlaps with the first plate pattern of the modulation capacitor, and a portion of the modulation signal line pattern overlapping with the first plate pattern of the modulation capacitor serves as a second plate pattern of the modulation capacitor.

[0027] In some embodiments, the driving circuit layer further comprises a planar layer, the planar layer comprises a plurality of planar vias; the driving element layer comprises an anode extension layer disposed on a side of the planar layer away from the substrate and an anode layer disposed on a side of the anode extension layer away from the substrate; the anode extension layer comprises a plurality of anode extension patterns, each anode extension pattern comprises an anode corresponding pattern and an extension pattern connected with each other, and each extension pattern is connected with one pixel driving circuit through one planar via; the anode layer comprises a plurality of anode patterns, and each anode pattern at least partially overlaps with one anode corresponding pattern.

[0028] In some embodiments, the driving element layer further comprises a pixel defining layer disposed on a side of the anode layer away from the substrate, a light emitting layer disposed on a side of the pixel defining layer away from the substrate, and a cathode layer disposed on a side of the light emitting layer away from the substrate; the pixel defining layer comprises a plurality of openings, and each opening exposes one anode pattern; the light emitting layer comprises a plurality of light emitting patterns, and each light emitting pattern is disposed corresponding to one opening.

[0029] In some embodiments, a projection of the anode corresponding pattern on the anode layer is located within a boundary of the anode pattern.

[0030] In another aspect, a display device is provided, comprising the display panel described above. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to make the technical solutions clearer, the following will briefly introduce the drawings needed to be used in some embodiments. Obviously, the drawings described in the following description are only some of the drawings of some embodiments, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size of the product, the actual flow of the method, the actual timing of the signal, etc. involved in some embodiments.

[0032] Fig. 1 is a plan view of a display panel in some embodiments;

[0033] Fig. 2A is a circuit diagram of a pixel driving circuit in some embodiments;

[0034] Fig. 2B is another circuit diagram of a pixel driving circuit in some embodiments;

[0035] Fig. 2C is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0036] Fig. 2D is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0037] Fig. 3 is a circuit diagram of a driving sub-circuit in some embodiments;

[0038] Fig. 4 is a circuit diagram of a writing sub-circuit in some embodiments;

[0039] Fig. 5 is a circuit diagram of a second reset circuit in some embodiments;

[0040] Fig. 6 is a circuit diagram of a first reset circuit in some embodiments;

[0041] Fig. 7 is a circuit diagram of a modulation sub-circuit in some embodiments;

[0042] Fig. 8 is another circuit diagram of a modulation sub-circuit in some embodiments;

[0043] Fig. 9 is a circuit diagram of a coupling sub-circuit in some embodiments;

[0044] Fig. 10A is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0045] Fig. 10B is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0046] Fig. 11A is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0047] Fig. 11B is yet another circuit diagram of a pixel driving circuit in some embodiments;

[0048] Fig. 12 is a circuit diagram of a direct current sub-circuit in some embodiments;

[0049] FIG. 13 is another circuit diagram of the direct current sub-circuit in some embodiments;

[0050] FIG. 14 is a control timing diagram of the pixel driving circuit in FIGS. 2B and 10B;

[0051] FIG. 15A is a state diagram of the pixel driving circuit in FIG. 2B in a first stage;

[0052] FIG. 15B is a state diagram of the pixel driving circuit in FIG. 2B in a second stage;

[0053] FIG. 15C is a state diagram of the pixel driving circuit in FIG. 2B in a third stage;

[0054] FIG. 15D is a state diagram of the pixel driving circuit in FIG. 2B in a fourth stage;

[0055] FIG. 15E is a state diagram of the pixel driving circuit in FIG. 2B in a fifth stage;

[0056] FIG. 16A is a state diagram of the pixel driving circuit in FIG. 10B in a first stage;

[0057] FIG. 16B is a state diagram of the pixel driving circuit in FIG. 10B in a second stage;

[0058] FIG. 16C is a state diagram of the pixel driving circuit in FIG. 10B in a third stage;

[0059] FIG. 16D is a state diagram of the pixel driving circuit in FIG. 10B in a fourth stage;

[0060] FIG. 16E is a state diagram of the pixel driving circuit in FIG. 10B in a fifth stage;

[0061] FIG. 17 is a control timing diagram of the pixel driving circuit in FIG. 11B;

[0062] FIG. 18A is a state diagram of the pixel driving circuit in FIG. 11B in a first stage;

[0063] FIG. 18B is a state diagram of the pixel driving circuit in FIG. 11B in a second stage;

[0064] FIG. 18C is a state diagram of the pixel driving circuit in FIG. 11B in a third stage;

[0065] FIG. 18D is a state diagram of the pixel driving circuit in FIG. 11B in a fourth stage;

[0066] FIG. 18E is a state diagram of the pixel driving circuit in FIG. 11B in a fifth stage;

[0067] FIG. 19A is another plan view of a display panel in some embodiments;

[0068] FIG. 19B is a cross-sectional view of a display panel in some embodiments;

[0069] Figure 20 is a plan view of a bottom metal layer in some embodiments;

[0070] Figure 21 is a plan view of a buffer layer in some embodiments;

[0071] Figure 22 is a plan view of a first active layer in some embodiments;

[0072] Figure 23 is a plan view of a first gate insulator layer in some embodiments;

[0073] Figure 24 is a plan view of a first gate metal layer in some embodiments;

[0074] Figure 25 is a plan view of a first interlayer dielectric layer in some embodiments;

[0075] Figure 26 is a plan view of a first source-drain metal layer in some embodiments;

[0076] Figure 27 is a plan view of a stack of some of the layers in some embodiments;

[0077] Figure 28 is a plan view of a second gate insulator layer in some embodiments;

[0078] Figure 29 is a plan view of a second gate metal layer in some embodiments;

[0079] Figure 30 is a plan view of a third gate insulator layer in some embodiments;

[0080] Figure 31 is a plan view of a third gate metal layer in some embodiments;

[0081] Figure 32 is a plan view of a fourth gate insulator layer in some embodiments;

[0082] Figure 33 is a plan view of a second active layer in some embodiments;

[0083] Figure 34 is a plan view of a mask layer in some embodiments;

[0084] Figure 35 is a plan view of a fifth gate insulator layer in some embodiments;

[0085] Figure 36 is a plan view of another stack of some of the layers in some embodiments;

[0086] Figure 37 is a plan view of a fourth gate metal layer in some embodiments;

[0087] Figure 38 is a plan view of a sixth gate insulator layer in some embodiments;

[0088] Figure 39 is a plan view of a fifth gate metal layer in some embodiments;

[0089] Figure 40 is a plan view of a second interlayer dielectric layer in some embodiments;

[0090] FIG. 41 is a plan view of a second source-drain metal layer in some embodiments;

[0091] FIG. 42 is another plan view of a stack of partial film layers in some embodiments;

[0092] FIG. 43 is a plan view of a planarization layer in some embodiments;

[0093] FIG. 44 is a plan view of an anode extension layer in some embodiments;

[0094] FIG. 45 is a plan view of an anode layer in some embodiments;

[0095] FIG. 46 is a plan view of a pixel definition layer in some embodiments;

[0096] FIG. 47A is another plan view of a stack of partial film layers in some embodiments;

[0097] FIG. 47B is another plan view of a stack of partial film layers in some embodiments;

[0098] FIG. 48 is a cross-sectional view of FIG. 42 along the AA cross-sectional line;

[0099] FIG. 49 is a cross-sectional view of FIG. 42 along the BB cross-sectional line;

[0100] FIG. 50 is another plan view of a stack of partial film layers in some embodiments;

[0101] FIG. 51 is another plan view of a stack of partial film layers in some embodiments;

[0102] FIG. 52 is a cross-sectional view of partial film layers in some embodiments;

[0103] FIG. 53 is a plan view of a display module in some embodiments. DETAILED DESCRIPTION

[0104] The technical solutions in some embodiments will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments, but not all the embodiments. Based on the provided embodiments, all other embodiments obtained by those skilled in the art belong to the scope of protection.

[0105] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0106] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments, unless otherwise stated, "a plurality of" means two or more.

[0107] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0108] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0109] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0110] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0111] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0112] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0113] High PPI display panels are increasingly widely used in the display field due to their superior display effect and high image clarity. For example, high PPI display panels are often used in VR (Virtual Reality) display devices or AR (Augmented Reality) display devices.

[0114] As shown in Figure 1, the display panel 1000 includes a display area AA (Active Area, also known as effective display area) and a peripheral area BB located on at least one side of the display area AA.

[0115] As shown in Figure 1, the display area AA of the display panel 1000 is provided with multiple sub-pixels P, multiple gate signal lines GT extending in the horizontal direction X, and multiple data signal lines Data extending in the vertical direction Y. For ease of explanation, the above-mentioned multiple sub-pixels P are illustrated by arranging them in a matrix form, for example, the multiple sub-pixels P are arranged in N rows and M columns. At this time, the sub-pixels P arranged in a row along the horizontal direction X are called row sub-pixels P, and the sub-pixels P arranged in a column along the vertical direction Y are called column sub-pixels P. Each sub-pixel P is provided with a pixel driving circuit 2 for controlling the display of the sub-pixel P, and a light-emitting device M connected to the pixel driving circuit 2. The light-emitting device M emits light under the control of the pixel driving circuit 2, thereby enabling the display panel 1000 to display.

[0116] The more subpixels a display panel has, the higher its PPI (pixel count) will be, and the denser the arrangement of the subpixels will be. To increase the PPI of a display panel, the area occupied by a single subpixel needs to be reduced, and the area occupied by a subpixel is related to the number of transistors in the pixel driving circuit.

[0117] In some embodiments, the pixel driving circuit is of 7T1C or 6T1C type, i.e., the pixel driving circuit includes seven or six transistors and one capacitor, the pixel driving circuit at least includes a driving transistor, a writing transistor and at least one light-emitting control transistor, exemplarily, the first voltage signal line is connected with the driving transistor, the light-emitting control transistor and the light-emitting device in sequence, and the whole formed by the three is connected between the first voltage signal line and the second voltage signal line, the driving transistor is configured to generate a driving current, the light-emitting control transistor is configured to control the on-off of the current path between the first voltage signal line and the second voltage signal line, thereby controlling the duration of the driving current flowing to the light-emitting device, and controlling the light-emitting brightness of the light-emitting device.

[0118] Some embodiments of the present application provide a pixel driving circuit 2, as shown in FIGS. 2A and 2C, the pixel driving circuit 2 includes a driving sub-circuit 30, a reset sub-circuit 70, a writing sub-circuit 20, a coupling sub-circuit 60 and a modulation sub-circuit 50. The reset sub-circuit 70 is coupled with a reference signal line Vref, an initialization signal line Vint, a first node N1 and a second node N2, and the reset sub-circuit 70 is configured to transmit a reference signal vref received at the reference signal line Vref to the first node N1 and transmit an initialization signal vint received at the initialization signal line Vint to the second node N2; the writing sub-circuit 20 is coupled with a data signal line Data and the first node N1, and the writing sub-circuit 20 is configured to transmit a data signal data received at the data signal line Data to the first node N1; the driving sub-circuit 30 is coupled with a first power signal line VDD, the first node N1 and the second node N2, and the second node N2 is coupled with a to-be-driven element 1; the driving sub-circuit 30 is configured to be turned on under the control of a first power signal vdd transmitted by the first power signal line VDD, the voltage of the first node N1 and the voltage of the second node N2, to generate a driving signal to drive the to-be-driven element 1, exemplarily, the to-be-driven element 1 is a light-emitting device, for example, an OLED; the coupling sub-circuit 60 is coupled with the first node N1 and the second node N2, and the coupling sub-circuit 60 is configured to couple the voltage variation of the first node N1 to the second node N2.

[0119] In some embodiments, as shown in FIG. 2A, the modulation sub-circuit 50 is coupled with the modulation signal line VB and the first node N1, and the modulation sub-circuit 50 is configured to couple the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1, so as to make the drive sub-circuit 30 be turned off under the control of the voltage of the first node N1 and the voltage of the second node N2. In other embodiments, as shown in FIG. 2C, the modulation sub-circuit 50 is coupled with the modulation signal line VB and the second node N2, and the modulation sub-circuit 50 is configured to couple the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the second node N2, so as to make the drive sub-circuit 30 be turned off under the control of the voltage of the first node N1 and the voltage of the second node N2.

[0120] Exemplarily, as shown in FIG. 3, the drive sub-circuit 30 includes a control end 33, a first end 31 and a second end 32, the control end 33 of the drive sub-circuit 30 is coupled with the first node N1; the first end 31 of the drive sub-circuit 30 is coupled with the first power signal line VDD; and the second end 32 of the drive sub-circuit 30 is coupled with the second node N2.

[0121] Exemplarily, as shown in FIG. 2A and FIG. 2C, one end of the to-be-driven element 1 is coupled with the second node N2, so as to realize the coupling of the to-be-driven element 1 to the drive sub-circuit 30; and the other end of the to-be-driven element 1 is coupled with the second power signal line VSS.

[0122] Exemplarily, as shown in FIG. 3, the first power signal line VDD provides the first end 31 of the drive sub-circuit 30 with the first power signal vdd, and the voltage difference between the voltage of the first node N1 and the voltage of the second node N2, i.e. the voltage difference between the voltage of the control end 33 of the drive sub-circuit 30 and the voltage of the second end 32 of the drive sub-circuit 30, can be used to control the turn-on and turn-off of the drive sub-circuit 30, i.e. the voltage difference between the voltage of the first node N1 and the voltage of the second node N2 can be used to control the drive current flowing through the first end 31 of the drive sub-circuit 30 and the second end 32 of the drive sub-circuit 30, and the drive current flows into the to-be-driven element 1 after flowing through the second node N2, so as to control the to-be-driven element 1 to work or stop working. That is, the voltage difference between the voltage of the first node N1 and the voltage of the second node N2 can be used to control the drive current flowing through the to-be-driven element 1, so as to control the to-be-driven element 1 to work or stop working.

[0123] Exemplarily, the reset sub-circuit 70 includes a first reset circuit 40 and a second reset circuit 10. As shown in FIG. 6, the first reset circuit 40 includes a first end 41 and a second end 42, the first end 41 of the first reset circuit 40 is coupled with the reference signal line Vref, and the second end 42 of the first reset circuit 40 is coupled with the first node N1. The first reset circuit 40 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and resets the voltage of the first node N1 to the voltage of the reference signal vref. As shown in FIG. 5, the second reset circuit 10 includes a first end 11 and a second end 12, the first end 11 of the second reset circuit 10 is coupled with the initialization signal line Vint, and the second end 12 of the second reset circuit 10 is coupled with the second node N2. The second reset circuit 10 transmits the initialization signal vint received at the initialization signal line Vint to the second node N2, and resets the voltage of the second node N2 to the voltage of the initialization signal vint.

[0124] Exemplarily, as shown in FIG. 4, the write sub-circuit 20 includes a first end 21 and a second end 22, the first end 21 of the write sub-circuit 20 is coupled with the data signal line Data, and the second end 22 of the write sub-circuit 20 is coupled with the first node N1. The write sub-circuit 20 transmits the data signal data received at the data signal line Data to the first node N1.

[0125] Exemplarily, as shown in FIG. 9, the coupling sub-circuit 60 includes a first end 61 and a second end 62, the first end 61 of the coupling sub-circuit 60 is coupled with the first node N1, and the second end 62 of the coupling sub-circuit 60 is coupled with the second node N2. The coupling sub-circuit 60 couples the voltage variation of the first node N1 to the second node N2, that is, the voltage variation of the first node N1 and the voltage variation of the second node N2 are synchronized.

[0126] Exemplarily, as shown in FIG. 7, the modulation sub-circuit 50 includes a first end 51 and a second end 52, the first end 51 of the modulation sub-circuit 50 is coupled with the modulation signal line VB, and the second end 52 of the modulation sub-circuit 50 is coupled with the first node N1. The modulation sub-circuit 50 couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1 in a capacitive coupling manner, adjusts the voltage difference between the voltage of the first node N1 and the voltage of the second node N2, that is, adjusts the voltage difference between the voltage of the control end 33 of the driving sub-circuit 30 and the voltage of the second end 32 of the driving sub-circuit 30, so as to make the driving sub-circuit 30 be controlled to be turned off under the voltage of the first node N1 and the voltage of the second node N2, and make the to-be-driven element 1 stop working.

[0127] Alternatively, as shown in FIG. 8, the first end 51 of the modulation sub-circuit 50 is coupled with the modulation signal line VB, the second end 52 of the modulation sub-circuit 50 is coupled with the second node N2, the modulation sub-circuit 50 couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the second node N2 in a capacitive coupling manner, and the voltage difference between the voltage of the first node N1 and the voltage of the second node N2 is adjusted, that is, the voltage difference between the voltage of the control end 33 of the driving sub-circuit 30 and the voltage of the second end 32 of the driving sub-circuit 30 is adjusted, so that the driving sub-circuit 30 is turned off under the control of the voltage of the first node N1 and the voltage of the second node N2, and the to-be-driven element 1 stops working.

[0128] In the pixel driving circuit 2 provided by some embodiments of the present application, the voltage variation of the modulation signal vb transmitted by the modulation signal line VB is coupled to the first node N1 or the second node N2 in a capacitive coupling manner by the modulation sub-circuit 50, the voltage of the first node N1 or the second node N2 is adjusted, and the driving sub-circuit 30 is turned off under the control of the voltage of the first node N1 and the voltage of the second node N2, so that the to-be-driven element 1 stops working; therefore, the voltage of the first node N1 or the second node N2 can be adjusted by adjusting the modulation signal vb transmitted by the modulation signal line VB, and the driving sub-circuit 30 is turned off under the control of the voltage of the first node N1 and the voltage of the second node N2, so that the to-be-driven element 1 stops working.

[0129] The pixel driving circuit 2 can control the size of the driving current generated by the driving sub-circuit 30 through the data signal data input by the writing sub-circuit 20, and control the on-off of the driving sub-circuit 30 through the modulation sub-circuit 50, so as to adjust the working time length of the to-be-driven element 1, thereby replacing the traditional way of using a transistor (for example, a light-emitting control transistor) to control the driving sub-circuit 30 to be turned on or turned off, and then controlling the to-be-driven element 1 to work or stop working; the pixel driving circuit 2 provided by some embodiments reduces the number of transistors, reduces the area occupied by the pixel driving circuit 2 on the display panel, and more pixel driving circuits 2 can be accommodated in the unit area of the display panel, that is, more sub-pixels can be accommodated in the unit area of the display panel, thereby improving the PPI of the display panel and improving the resolution of the display panel.

[0130] It should be noted that the first node N1 and the second node N2 do not represent actual components, but represent the convergence points of related electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of related electrical connections in the circuit diagram.

[0131] In some embodiments, as shown in FIG. 2B, FIG. 2D, the modulation sub-circuit 50 comprises a modulation capacitor CB, as shown in FIG. 7, FIG. 8, a first plate CB1 of the modulation capacitor CB is coupled with the modulation signal line VB, and a second plate CB2 of the modulation capacitor CB is coupled with the first node N1 or the second node N2.

[0132] Exemplarily, as shown in FIG. 7, FIG. 8, the modulation sub-circuit 50 comprises a modulation capacitor CB, the modulation capacitor CB comprises a first plate CB1 and a second plate CB2; the first end 51 of the modulation sub-circuit 50 is the first plate CB1 of the modulation capacitor CB, and the first end 51 of the modulation sub-circuit 50 is coupled with the modulation signal line VB, i.e., the first plate CB1 of the modulation capacitor CB is coupled with the modulation signal line VB; the second end 52 of the modulation sub-circuit 50 is the second plate CB2 of the modulation capacitor CB, and the second end 52 of the modulation sub-circuit 50 is coupled with the first node N1 or the second node N2, i.e., the second plate CB2 of the modulation capacitor CB is coupled with the first node N1 or the second node N2.

[0133] The modulation capacitor CB couples the voltage variation of the modulation signal vb of the modulation signal line VB transmitted to the first plate CB1 of the modulation capacitor CB to the second plate CB2 of the modulation capacitor CB by capacitive coupling, and then transmits the voltage variation to the first node N1 or the second node N2 by the second plate CB2 of the modulation capacitor CB, so as to adjust the voltage difference between the first node N1 voltage and the second node N2 voltage, i.e., the voltage difference between the control end 33 voltage of the drive sub-circuit 30 and the second end 32 voltage of the drive sub-circuit 30, thereby controlling the drive current flowing through the first end 31 of the drive sub-circuit 30 and the second end 32 of the drive sub-circuit 30, and further controlling the drive current flowing through the to-be-driven element 1, so as to make the to-be-driven element 1 close.

[0134] In some embodiments, as shown in FIG. 2B, FIG. 2D, the drive sub-circuit 30 comprises a third transistor T3, as shown in FIG. 3, a first gate T33 of the third transistor T3 is coupled with the first node N1, a first pole T31 of the third transistor T3 is coupled with the first power signal line VDD, and a second pole T32 of the third transistor T3 is coupled with the second node N2.

[0135] Exemplarily, as shown in FIG. 3, the driving sub-circuit 30 includes a third transistor T3, the third transistor T3 includes a first gate T33, a first pole T31 and a second pole T32; the control end 33 of the driving sub-circuit 30 is the first gate T33 of the third transistor T3, the control end 33 of the driving sub-circuit 30 is coupled with the first node N1, that is, the first gate T33 of the third transistor T3 is coupled with the first node N1; the first end 31 of the driving sub-circuit 30 is the first pole T31 of the third transistor T3, the first end 31 of the driving sub-circuit 30 is coupled with the first power signal line VDD, that is, the first pole T31 of the third transistor T3 is coupled with the first power signal line VDD; the second end 32 of the driving sub-circuit 30 is the second pole T32 of the third transistor T3, the second end 32 of the driving sub-circuit 30 is coupled with the second node N2, that is, the second pole T32 of the third transistor T3 is coupled with the second node N2.

[0136] Exemplarily, the first power signal line VDD provides the first power signal vdd for the first pole T31 of the third transistor T3, and the voltage difference between the voltage of the first node N1 and the voltage of the second node N2, that is, the voltage difference between the voltage of the first gate T33 of the third transistor T3 and the voltage of the second pole T32 of the third transistor T3, can be used to control the conduction and disconnection of the first pole T31 of the third transistor T3 and the second pole T32 of the third transistor T3, that is, the voltage difference between the voltage of the first node N1 and the voltage of the second node N2 can be used to control the driving current flowing through the first pole T31 of the third transistor T3 and the second pole T32 of the third transistor T3, the driving current flows into the to-be-driven element 1 after flowing through the second node N2, thereby realizing the opening or closing of the to-be-driven element 1. That is, the voltage difference between the voltage of the first node N1 and the voltage of the second node N2 can be used to control the driving current flowing through the to-be-driven element 1, thereby realizing the opening or closing of the to-be-driven element 1.

[0137] In some embodiments, as shown in FIG. 3, the third transistor T3 further includes a second gate T34, the second gate T34 of the third transistor T3 is coupled with the second node N2, that is, the second gate T34 of the third transistor T3 is coupled with the second pole T32 of the third transistor T3; the coupling of the second gate T34 of the third transistor T3 and the second pole T32 of the third transistor T3 can increase the sub-threshold swing of the third transistor T3, thereby the range of the data signal data can be increased.

[0138] In some embodiments, as shown in FIG. 2B, FIG. 2D, the first reset circuit 40 of the reset sub-circuit 70 includes a fourth transistor T4; the second reset circuit 10 of the reset sub-circuit 70 includes a first transistor T1; as shown in FIG. 5, a first gate T13 of the first transistor T1 is coupled with the reset signal line Reset, a first pole T11 of the first transistor T1 is coupled with the initialization signal line Vint, and a second pole T12 of the first transistor T1 is coupled with the second node N2; as shown in FIG. 6, a gate T43 of the fourth transistor T4 is coupled with the first gate signal line GT1, a first pole T41 of the fourth transistor T4 is coupled with the reference signal line Vref, and a second pole T42 of the fourth transistor T4 is coupled with the first node N1.

[0139] Exemplarily, as shown in FIG. 6, the fourth transistor T4 includes the gate T43, the first pole T41 and the second pole T42; the gate T43 of the fourth transistor T4 is coupled with the first gate signal line GT1, the first gate signal line GT1 provides a first gate signal gt1 for controlling the turn-on and turn-off of the fourth transistor T4; the first end 41 of the first reset circuit 40 is the first pole T41 of the fourth transistor T4, and the first end 41 of the first reset circuit 40 is coupled with the reference signal line Vref, i.e., the first pole T41 of the fourth transistor T4 is coupled with the reference signal line Vref; the second end 42 of the first reset circuit 40 is the second pole T42 of the fourth transistor T4, and the second end 42 of the first reset circuit 40 is coupled with the first node N1, i.e., the second pole T42 of the fourth transistor T4 is coupled with the first node N1; the fourth transistor T4 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and resets the voltage of the first node N1 to the reference signal vref.

[0140] Exemplarily, as shown in FIG. 5, the first transistor T1 includes the first gate T13, the first pole T11 and the second pole T12; the first gate T13 of the first transistor T1 is coupled with the reset signal line Reset, the reset signal line Reset provides a reset signal reset for controlling the turn-on and turn-off of the first transistor T1; the first end 11 of the second reset circuit 10 is the first pole T11 of the first transistor T1, and the first end 11 of the second reset circuit 10 is coupled with the initialization signal line Vint, i.e., the first pole T11 of the first transistor T1 is coupled with the initialization signal line Vint; the second end 12 of the second reset circuit 10 is the second pole T12 of the first transistor T1, and the second end 12 of the second reset circuit 10 is coupled with the second node N2, i.e., the second pole T12 of the first transistor T1 is coupled with the second node N2; the first transistor T1 transmits the initialization signal vint received at the initialization signal line Vint to the second node N2, and resets the voltage of the second node N2 to the initialization signal vint.

[0141] In some embodiments, as shown in FIG. 5, the first transistor T1 further includes a second gate T14, and the first gate T13 of the first transistor T1 is coupled with the second gate T14 of the first transistor T1.

[0142] Exemplarily, the first gate T13 of the first transistor T1 is coupled with the second gate T14 of the first transistor T1, which is equivalent to that the first transistor T1 includes a top gate and a bottom gate, and the on-state current of the first transistor T1 can be increased by the joint action of the two gates.

[0143] In some embodiments, as shown in FIG. 2B and FIG. 2D, the write sub-circuit 20 includes a second transistor T2, as shown in FIG. 4, the gate T23 of the second transistor T2 is coupled with the second gate signal line GT2, the first pole T21 of the second transistor T2 is coupled with the data signal line Data, and the second pole T22 of the second transistor T2 is coupled with the first node N1.

[0144] Exemplarily, as shown in FIG. 4, the write sub-circuit 20 includes a second transistor T2, and the second transistor T2 includes a gate T23, a first pole T21 and a second pole T22; the gate T23 of the second transistor T2 is coupled with the second gate signal line GT2, and the second gate signal line GT2 provides a second gate signal gt2 for controlling the on and off of the second transistor T2; the first end 21 of the write sub-circuit 20 is the first pole T21 of the second transistor T2, and the first end 21 of the write sub-circuit 20 is coupled with the data signal line Data, i.e., the first pole T21 of the second transistor T2 is coupled with the data signal line Data; the second end 22 of the write sub-circuit 20 is the second pole T22 of the second transistor T2, and the second end 22 of the write sub-circuit 20 is coupled with the first node N1, i.e., the second pole T22 of the second transistor T2 is coupled with the first node N1; the second transistor T2 transmits the data signal data received at the data signal line Data to the first node N1.

[0145] In some embodiments, as shown in FIG. 2B and FIG. 2D, the coupling sub-circuit 60 includes a coupling capacitor Cst, as shown in FIG. 9, the first plate Cst1 of the coupling capacitor Cst is coupled with the first node N1, and the second plate Cst2 of the coupling capacitor Cst is coupled with the second node N2.

[0146] Exemplarily, as shown in FIG. 9, the coupling capacitor Cst includes a first plate Cst1 and a second plate Cst2; the first end 61 of the coupling sub-circuit 60 is the first plate Cst1 of the coupling capacitor Cst, and the first end 61 of the coupling sub-circuit 60 is coupled to the first node N1, i.e., the first plate Cst1 of the coupling capacitor Cst is coupled to the first node N1; the second end 62 of the coupling sub-circuit 60 is the second plate Cst2 of the coupling capacitor Cst, and the second end 62 of the coupling sub-circuit 60 is coupled to the second node N2, i.e., the second plate Cst2 of the coupling capacitor Cst is coupled to the second node N2; the coupling capacitor Cst couples the voltage variation of the first node N1 to the second node N2.

[0147] In some embodiments, the second transistor T2 and the fourth transistor T4 are first type transistors, and the first type transistors are P-type low-temperature polysilicon transistors; the first transistor T1 and the third transistor T3 are second type transistors, and the second type transistors are N-type oxide transistors.

[0148] Exemplarily, transistors can be divided into N-type transistors and P-type transistors according to driving modes, and transistors can be divided into oxide transistors and low-temperature polysilicon transistors according to materials. The transistors mentioned in some embodiments can use any type of transistors mentioned above.

[0149] In some embodiments, the second transistor T2 of the writing sub-circuit 20 and the fourth transistor T4 of the reset sub-circuit 70 are taken as examples of P-type low-temperature polysilicon transistors, mainly because the P-type low-temperature polysilicon transistors have smaller area of the pixel driving circuit 2 than N-type low-temperature polysilicon transistors or N-type oxide transistors of the same size channel width-length ratio, which is more conducive to improving PPI.

[0150] In some embodiments, the first transistor T1 of the reset sub-circuit 70 and the third transistor T3 of the driving sub-circuit 30 are taken as examples of N-type oxide transistors, mainly because the low-temperature polysilicon transistors have quasi-molecular laser annealing and high-temperature processes in the process, and the high temperature can reach more than 400℃. If the first transistor T1 and the third transistor T3 use low-temperature polysilicon transistors, the quasi-molecular laser annealing can affect the characteristics of the second transistor T2 and the fourth transistor T4 made earlier, and at the same time, the high temperature can also affect the characteristics of the second transistor T2 and the fourth transistor T4. Therefore, the first transistor T1 and the third transistor T3 use N-type oxide transistors, and the yield of finished products can be greatly improved.

[0151] In some embodiments, as shown in FIG. 10A, FIG. 11A, the pixel driving circuit 2 further comprises a direct current sub-circuit 80; as shown in FIG. 10A, in the case where the modulation sub-circuit 50 is coupled to the first node N1, the direct current sub-circuit 80 is coupled to the direct current signal line DC and the second node N2, and the direct current sub-circuit 80 is configured to stabilize the voltage of the second node N2 under the action of the direct current signal dc transmitted by the direct current signal line DC; as shown in FIG. 11A, in the case where the modulation sub-circuit 50 is coupled to the second node N2, the direct current sub-circuit 80 is coupled to the direct current signal line DC and the first node N1, and the direct current sub-circuit 80 is configured to stabilize the voltage of the first node N1 under the action of the direct current signal dc transmitted by the direct current signal line DC.

[0152] Exemplarily, as shown in FIG. 12, the direct current sub-circuit 80 comprises a first end 81 and a second end 82; as shown in FIG. 10A, in the case where the modulation sub-circuit 50 is coupled to the first node N1, the first end 81 of the direct current sub-circuit 80 is coupled to the direct current signal line DC, and the second end 82 of the direct current sub-circuit 80 is coupled to the second node N2; the direct current sub-circuit 80 is used to stabilize the voltage of the second node N2 and improve the writing efficiency of the data signal data; as shown in FIG. 13, in the case where the modulation sub-circuit 50 is coupled to the second node N2, the first end 81 of the direct current sub-circuit 80 is coupled to the direct current signal line DC, and the second end 82 of the direct current sub-circuit 80 is coupled to the first node N1; the direct current sub-circuit 80 is used to stabilize the voltage of the second node N2 and improve the writing efficiency of the data signal data.

[0153] In some embodiments, as shown in FIG. 10B, FIG. 11B, the direct current sub-circuit 80 comprises a direct current capacitor CA, and as shown in FIG. 12, FIG. 13, a first pole plate CA1 of the direct current capacitor CA is coupled to the direct current signal line DC, and a second pole plate CA2 of the direct current capacitor CA is coupled to the second node N2 or the first node N1.

[0154] Exemplarily, as shown in FIG. 10B, FIG. 11B, the direct current sub-circuit 80 comprises a direct current capacitor CA, and as shown in FIG. 12, FIG. 13, the direct current capacitor CA comprises a first pole plate CA1 and a second pole plate CA2; the first end 81 of the direct current sub-circuit 80 is the first pole plate CA1 of the direct current capacitor CA, and the first end 81 of the direct current sub-circuit 80 is coupled to the direct current signal line DC, i.e., the first pole plate CA1 of the direct current capacitor CA is coupled to the direct current signal line DC; as shown in FIG. 12, in the case where the modulation sub-circuit 50 is coupled to the first node N1, the second end 82 of the direct current sub-circuit 80 is coupled to the second node N2, i.e., the second pole plate CA2 of the direct current capacitor CA is coupled to the second node N2; as shown in FIG. 13, in the case where the modulation sub-circuit 50 is coupled to the second node N2, the second end 82 of the direct current sub-circuit 80 is coupled to the first node N1, i.e., the second pole plate CA2 of the direct current capacitor CA is coupled to the first node N1.

[0155] In another aspect, some embodiments also provide a pixel driving method applied to the pixel driving circuit 2 described above, the pixel driving method comprising: a frame period Frame comprising a reset stage ①, a compensation stage ②, a write stage ③, a light emitting stage ④ and a modulation stage ⑤; as shown in FIG. 15A, FIG. 16A, FIG. 18A, in the reset stage ①, the reset sub-circuit 70 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and resets the voltage of the first node N1 to the voltage of the reference signal vref; the reset sub-circuit 70 transmits the initialization signal vint received at the initialization signal line Vint to the second node N2, and resets the voltage of the second node N2 to the voltage of the initialization signal vint; as shown in FIG. 15B, FIG. 16B, FIG. 18B, in the compensation stage ②, the reset sub-circuit 70 continues to transmit the reference signal vref received at the reference signal line Vref to the first node N1; the drive sub-circuit 30 is turned on under the control of the voltage of the first node N1 until the threshold voltage Vth of the drive sub-circuit 30 is stored in the second node N2, and the drive sub-circuit 30 is turned off; as shown in FIG. 15C, FIG. 16C, FIG. 18C, in the write stage ③, the write sub-circuit 20 transmits the data signal data received at the data signal line Data to the first node N1; the coupling sub-circuit 60 couples the voltage variation of the first node N1 to the second node N2; the drive sub-circuit 30 is turned on under the control of the first power signal vdd transmitted by the first power signal line VDD, the voltage of the first node N1 and the voltage of the second node N2; as shown in FIG. 15D, FIG. 16D, FIG. 18D, in the light emitting stage ④, the drive sub-circuit 30 is turned on and outputs the drive current; as shown in FIG. 15E, FIG. 16E, in the modulation stage ⑤, the modulation sub-circuit 50 couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1; the coupling sub-circuit 60 couples the voltage variation of the first node N1 to the second node N2; the drive sub-circuit 30 is turned off under the control of the first power signal vdd transmitted by the first power signal line VDD, the voltage of the first node N1 and the voltage of the second node N2; or as shown in FIG. 18E, the modulation sub-circuit 50 couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the second node N2; the coupling sub-circuit 60 couples the voltage variation of the second node N2 to the first node N1; the drive sub-circuit 30 is turned off under the control of the first power signal vdd transmitted by the first power signal line VDD, the voltage of the first node N1 and the voltage of the second node N2.

[0156] Exemplarily, the pixel driving method of the pixel driving circuit 2 as shown in FIG. 2B is introduced below.

[0157] The first transistor T1 of the reset sub-circuit 70 and the third transistor T3 of the driving sub-circuit 30 are N-type oxide transistors, and the first transistor T1 includes a first gate T13 and a second gate T14, and the third transistor T3 includes a first gate T33 and a second gate T34; the second transistor T2 of the write sub-circuit 20 and the fourth transistor T4 of the reset sub-circuit 70 are P-type low-temperature polysilicon transistors. The pixel driving circuit 2 shown in FIG. 2B can refer to the description of the pixel driving circuit 2 above, and will not be described here again.

[0158] Exemplarily, one frame period Frame includes a reset stage ①, a compensation stage ②, a write stage ③, a light-emitting stage ④ and a modulation stage ⑤; the corresponding timing is shown in FIG. 14.

[0159] The reset stage ① is shown in FIG. 15A: the reset sub-circuit 70 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and the voltage V N1 reset of the first node N1 is reset to the voltage V vref of the reference signal vref; the reset sub-circuit 70 transmits the initialization signal vint received at the initialization signal line Vint to the second node N2, and the voltage V N2 reset of the second node N2 is reset to the voltage V vint of the initialization signal vint.

[0160] In the reset stage ①, the first gate signal gt1 provided by the first gate signal line GT1 is low, and the fourth transistor T4 is turned on; the reset signal reset provided by the reset signal line Reset is high, and the first transistor T1 is turned on; the second gate signal gt2 provided by the second gate signal line GT2 is high, and the second transistor T2 is turned off; the modulation signal vb provided by the modulation signal line VB changes from low to high.

[0161] At this time, the first transistor T1 transmits the initialization signal vint received at the initialization signal line Vint to the second node N2, and the voltage V N2 reset of the second node N2 is reset to the voltage V vint of the initialization signal vint; the voltage V N2 of the second node N2 is V vint .

[0162] The fourth transistor T4 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and the voltage V N1 reset of the first node N1 is reset to the voltage V vref of the reference signal vref; the voltage V N1 of the first node N1 is V vref .

[0163] It should be noted that, in the reset stage ①, the voltage setting V vref -V vint ≥ Vth, where Vth is the threshold voltage of the third transistor T3; Vgs is the gate-source voltage of the transistor, i.e. the gate voltage minus the source voltage. When Vgs≥Vth, the transistor is turned on. Vgs1 of the third transistor T3 = V N1 -V N2 = V vref -V vint ≥ Vth, the third transistor T3 is turned on, which can compensate for the Vth of the third transistor T3 in the next stage.

[0164] The compensation stage ②, as shown in FIG. 15B: the reset sub-circuit 70 continues to transmit the reference signal vref received at the reference signal line Vref to the first node N1; the driving sub-circuit 30 is opened under the control of the voltage V N1 of the first node N1 until the threshold voltage Vth of the driving sub-circuit 30 is stored in the second node N2, and the driving sub-circuit 30 is disconnected.

[0165] In the compensation stage ②, the first gate signal gt1 provided by the first gate signal line GT1 is low, and the fourth transistor T4 is turned on; the reset signal reset provided by the reset signal line Reset is low, and the first transistor T1 is disconnected; the second gate signal gt2 provided by the second gate signal line GT2 is high, and the second transistor T2 is disconnected; the third transistor T3 continues the turned-on state in the reset stage ①; the modulation signal vb provided by the modulation signal line VB is high.

[0166] At this time, the fourth transistor T4 transmits the reference signal vref received at the reference signal line Vref to the first node N1, and the voltage V N1 of the first node N1 is V vref .

[0167] The driving sub-circuit 30 is opened until the threshold voltage Vth of the driving sub-circuit 30 is stored in the second node N2, and the voltage V N2 of the second node N2 becomes V vref -Vth.

[0168] Vgs2 of the third transistor T3 = V N1 -V N2 = V vref -(V vref -Vth) = Vth, and the Vth compensation of the third transistor T3 is completed, and the third transistor T3 is disconnected.

[0169] The write phase ③, as shown in FIG. 15C: the write sub-circuit 20 transmits the data signal data received at the data signal line Data to the first node N1; the coupling sub-circuit 60 couples the voltage variation AV N1 of the first node N1 to the second node N2; the drive sub-circuit 30 is turned on under the control of the first power signal vdd transmitted at the first power signal line VDD, the voltage V N1 of the first node N1, and the voltage V N2 of the second node N2.

[0170] In the write phase ③, the first gate signal gt1 provided by the first gate signal line GT1 is high, the fourth transistor T4 is off; the reset signal reset provided by the reset signal line Reset is low, the first transistor T1 is off; the second gate signal gt2 provided by the second gate signal line GT2 is low, the second transistor T2 is turned on; the third transistor T3 continues the off state in the compensation phase ②; the modulation signal vb provided by the modulation signal line VB is high.

[0171] At this time, the second transistor T2 transmits the data signal data received at the data signal line Data to the first node N1, and the voltage of the first node N1 is V data .

[0172] The coupling capacitor Cst couples the voltage variation AV N1 of the first node N1 to the second node N2, and the voltage variation AV N1 of the first node N1 is V data -V vref ; the voltage V N2 of the second node N2 becomes V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C N2 ), wherein C cst is the capacitance value of the coupling capacitor Cst; C oled is the capacitance value of the parasitic capacitance Cod of the to-be-driven element 1; C N2 is the capacitance value of the parasitic capacitance of the second node N2. As shown in FIGS. 2B, 2D, 10B and 11B, the to-be-driven element 1 is, for example, a light emitting device, and the light emitting device has a parasitic capacitance Cod.

[0173] The Vgs3 of the third transistor T3 is V N1 -V N2 = V data -[V vref -Vth+(V data -Vvref )*C cst / (C cst +C oled +C N2 )]

[0174] =V data -V vref +Vth-(V data -V vref )*C cst / (C cst +C oled +C N2 )]

[0175] =(V data -V vref )*[1-C cst / (C cst +C oled +C N2 )]+Vth

[0176] At this time, Vgs3 of the third transistor T3 is greater than Vth, and the third transistor T3 is turned on.

[0177] When the voltage V N2 of the second node N2 is greater than the voltage of the second power signal line VSS coupled with the to-be-driven element 1 by a threshold voltage of the to-be-driven element 1, the to-be-driven element 1 emits light.

[0178] It should be noted that, in the writing stage ③, the voltage V N1 of the first node N1 is changed from V vref to V data , and the voltage variation ΔV N1 of the first node N1 is V data -V vref ; the coupling capacitor Cst is coupled between the first node N1 and the second node N2, and therefore, the voltage variation ΔV N2 of the second node N2 is (V data -V vref )*C cst / (C cst +C oled +C N2 ).

[0179] Therefore, the voltage of the second node N2 is changed from V vref -Vth in the compensation stage ② to V

[0180] V vref -Vth+(V data -V vref )*C cst / (C cst +Coled +C N2 )。

[0181] Light-emitting stage IV, as shown in Fig. 15D: the driving sub-circuit 30 is turned on and outputs a driving current.

[0182] In the light-emitting stage IV, the first gate signal gt1 provided by the first gate signal line GT1 is at a high level, and the fourth transistor T4 is turned off; the reset signal reset provided by the reset signal line Reset is at a low level, and the first transistor T1 is turned off; the second gate signal gt2 provided by the second gate signal line GT2 is at a high level, and the second transistor T2 is turned off; the third transistor T3 continues the on state in the writing stage III; the modulation signal vb provided by the modulation signal line VB is at a high level. The driving element 1 emits light.

[0183] Modulation stage V, as shown in Fig. 15E: the modulation sub-circuit 50 couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1; the coupling sub-circuit 60 couples the voltage variation AV N1 of the first node N1 to the second node N2; the driving sub-circuit 30 is turned off under the control of the first power signal vdd transmitted by the first power signal line VDD, the voltage V N1 of the first node N1, and the voltage V N2 of the second node N2.

[0184] In the modulation stage V, the first gate signal gt1 provided by the first gate signal line GT1 is at a high level, and the fourth transistor T4 is turned off; the reset signal reset provided by the reset signal line Reset is at a low level, and the first transistor T1 is turned off; the second gate signal gt2 provided by the second gate signal line GT2 is at a high level, and the second transistor T2 is turned off; the third transistor T3 continues the on state in the light-emitting stage IV; the modulation signal vb provided by the modulation signal line VB changes from a high level to a low level.

[0185] The modulation capacitor CB couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1, and the voltage variation of the first node N1 is AV N1 =C B *(V BH -V BL ) / (C B +C cst +C N1 ), wherein V BH is the high voltage of the modulation signal vb; V BL is the low voltage of the modulation signal vb; C B is the capacitance value of the modulation capacitor CB; and C N1 is the parasitic capacitance value of the first node N1.

[0186] The coupling capacitance Cst changes the voltage of the first node N1 by ΔV N1 The coupling capacitance Cst changes the voltage of the first node N1 by ΔV N2 = C cst * ΔV N1 / (C cst +C oled +C N2 ).

[0187] It should be noted that the parasitic capacitances of the first node N1 and the second node N2 are generally small and can be ignored, but some embodiments involve ultra-high PPI, and although the total parasitic capacitances of the first node N1 and the second node N2 are, for example, 2fF~3fF, the coupling capacitance Cst is, for example, 20fF~30fF, and thus this influence cannot be ignored.

[0188] It is obvious that ΔV N1 > ΔV N2 , that is, the voltage V N1 of the first node N1 decreases more.

[0189] In the modulation phase (5), the voltage V N1 of the first node N1 changes from V data of the write phase (3) to V data - ΔV N1 .

[0190] The voltage V N2 of the second node N2 changes from V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C N2 ) of the write phase (3) to V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C N2 )- ΔV N2 .

[0191] Vgs4 of the third transistor T3 = V N1 -V N2

[0192] = V data - ΔV N1 -[V vref -Vth+(V data -V vref )*C cstV cst + C oled + C N2 - ΔV N2 ]

[0193] = V data - ΔV N1 - V vref + Vth- (V data - V vref ) * C cst / (C cst + C oled + C N2 ) + ΔV N2

[0194] = (V data - V vref ) * [1 - C cst / (C cst + C oled + C N2 )] + Vth- ΔV N1 + ΔV N2

[0195] = Vgs3- (ΔV N1 - ΔV N2 )

[0196] At this time, the third transistor T3 needs to be turned off to stop the to-be-driven element 1 from emitting light, and Vgs4 of the third transistor T3 is less than Vth, that is:

[0197] (V data - V vref ) * [1 - C cst / (C cst + C oled + C N2 )] + Vth- ΔV N1 + ΔV N2 < Vth

[0198] (V data - V vref ) * [1 - C cst / (C cst + C oled + C N2 )] < ΔV N1 - ΔV N2

[0199] (V data - V vref ) * [1 - C cst / (C cst + C oled + C N2 )] < ΔVN1 *[1-C cst / (C cst +C oled +C N2 )]

[0200] V data -V vref <C B *(V BH -V BL ) / (C B +C cst +C N1 )。

[0201] Therefore, when the above condition is satisfied, the third transistor T3 is turned off, and the to-be-driven element 1 stops emitting light.

[0202] Exemplarily, C N1 is the parasitic capacitance of the first node N1, and the proportion is small; for example, C B and C cst are set to be in a proportion of 1:1; for example, V data is set to be 7V; for example, V vref is set to be 0V; for example, V BH -V BL is set to be 16V, the condition for the third transistor T3 to be turned off is satisfied, the third transistor T3 is turned off, and the to-be-driven element 1 stops emitting light.

[0203] Therefore, as shown in FIG. 2B, the pixel driving circuit 2 can adjust the light-emitting duty cycle of the to-be-driven element 1 by adjusting the duty cycle of the low level of the modulation signal vb, that is, the greater the duty cycle of the low level of the modulation signal vb, the longer the time for which the modulation signal vb is at the low level, and the longer the time for which the to-be-driven element 1 stops emitting light. In this case, the longer the time for which the to-be-driven element 1 stops emitting light, the darker the brightness perceived by the human eye in a frame, in order to make the brightness perceived by the human eye in a frame the same as that when the to-be-driven element 1 emits light all the time, the driving current of the to-be-driven element 1 in the light-emitting stage ④ can be increased, the brightness of the to-be-driven element 1 when emitting light can be increased, so that the average brightness of the to-be-driven element 1 in a frame is the same as that when the to-be-driven element 1 emits light all the time, and further, the brightness perceived by the human eye in a frame is the same as that when the to-be-driven element 1 emits light all the time.

[0204] Exemplarily, the pixel driving method of the pixel driving circuit 2 shown in FIG. 10B is introduced below.

[0205] The pixel driving circuit 2 as shown in FIG. 10B is different from the pixel driving circuit 2 as shown in FIG. 2B in that a direct current sub-circuit 80 is added, which is coupled to the second node N2. The pixel driving circuit 2 as shown in FIG. 10B can refer to the description of the pixel driving circuit 2, which will not be repeated here.

[0206] Exemplarily, one frame period Frame includes a reset stage ①, a compensation stage ②, a writing stage ③, a light emitting stage ④ and a modulation stage ⑤. The corresponding timing is shown in FIG. 14.

[0207] The reset stage ① is shown in FIG. 16A. The driving method of the pixel driving circuit 2 as shown in FIG. 10B in the reset stage ① is consistent with the driving method of the pixel driving circuit 2 as shown in FIG. 2B in the reset stage ①, which will not be repeated here. At this time, the modulation signal vb provided by the modulation signal line VB changes from low level to high level.

[0208] At this time, the voltage V N1 of the first node N1 is V vref ; and the voltage V N2 of the second node N2 is V vint .

[0209] The compensation stage ② is shown in FIG. 16B. The driving method of the pixel driving circuit 2 as shown in FIG. 10B in the compensation stage ② is consistent with the driving method of the pixel driving circuit 2 as shown in FIG. 2B in the compensation stage ②, which will not be repeated here. At this time, the modulation signal vb provided by the modulation signal line VB is high level.

[0210] At this time, the voltage V N1 of the first node N1 is V vref ; and the voltage V N2 of the second node N2 changes to V vref -Vth.

[0211] The writing stage ③ is shown in FIG. 16C. At this time, the modulation signal vb provided by the modulation signal line VB is high level.

[0212] At this time, the second transistor T2 transmits the data signal data received at the data signal line Data to the first node N1, and the voltage of the first node N1 is V data .

[0213] The coupling capacitor Cst couples the voltage variation AV N1 of the first node N1 to the second node N2, and the voltage variation AV N1 of the first node N1 is V data -V vref ; and the voltage of the second node N2 changes to V vref -Vth+(V data -Vvref )*C cst / (C cst +C oled +C A ), wherein C cst is a capacitance value of the coupling capacitance Cst; C oled is a capacitance value of the parasitic capacitance Cod of the to-be-driven element 1; C A is a capacitance value of the direct current capacitance CA.

[0214] Vgs3 of the third transistor T3 = V N1 -V N2 = V data -[V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C A ]

[0215] = V data -V vref +Vth-(V data -V vref )*C cst / (C cst +C oled +C A ]

[0216] = (V data -V vref )*[1-C cst / (C cst +C oled +C A )]+Vth

[0217] At this time, Vgs3 of the third transistor T3 > Vth, and the third transistor T3 is turned on.

[0218] When the voltage V N2 of the second node N2 is greater than the threshold voltage of the to-be-driven element 1, the to-be-driven element 1 emits light.

[0219] It should be noted that, from the compensation stage ② to the writing stage ③, the voltage variation ΔV N2 of the second node N2 is (V data -V vref )*C cst / (C cst +C oled +C A ), and in the process of writing the data signal data, the voltage variation ΔVN2 The voltage variation ΔV of the first node N1 N1 The smaller the variation, the higher the writing efficiency of the data signal data, i.e. C cst / (C cst +C oled +C A The smaller the value of C

[0220] The pixel driving circuit 2 as shown in Fig. 2B has a larger C cst (e.g. 30 fF) than C oled (e.g. 1-3.5 fF) and the parasitic capacitance of the second node N2, C N2 (e.g. 4 fF), so the value of C cst / (C cst +C oled +C N2 is relatively large, and the writing efficiency of the data signal data is relatively low.

[0221] The pixel driving circuit 2 as shown in Fig. 10B can add a direct current capacitor CA at the second node N2, C A is larger than C N2 , and the value of C cst / (C cst +C oled +C A is smaller than the value of C cst / (C cst +C oled +C N2 , so the pixel driving circuit 2 as shown in Fig. 10B improves the stability of the second node N2, reduces the voltage variation of the second node N2, and improves the writing efficiency of the data signal data.

[0222] The light emitting stage IV as shown in Fig. 16D: At this time, the modulation signal vb provided by the modulation signal line VB is at a high level. The to-be-driven element 1 emits light.

[0223] The modulation stage V as shown in Fig. 16E: At this time, the modulation signal vb provided by the modulation signal line VB changes from a high level to a low level.

[0224] The modulation capacitor CB couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the first node N1, and the voltage variation of the first node N1 is ΔV N1 =C B *(V BH -V BL ) / (C B +C cst , wherein V BHV is the high potential voltage of the modulation signal vb; BL C is the low potential voltage of the modulation signal vb; B This is the capacitance value of the modulation capacitor CB.

[0225] The coupling capacitor Cst will convert the voltage change ΔV at the first node N1. N1 Coupled to the second node N2, the voltage change at the second node N2 is ΔV. N2 =C cst *ΔV N1 / (C cst +C oled +C A ).

[0226] It should be noted that the parasitic capacitances of the first node N1 and the second node N2 are generally very small and can be ignored in the pixel driving circuit 2 shown in Figure 10B.

[0227] It is obvious that ΔV N1 >ΔV N2 That is, the voltage V at the first node N1 N1 The decrease was significant.

[0228] During the modulation phase ⑤, the voltage V at the first node N1 N1 V from writing stage ③ data Change to V data -ΔV N1 .

[0229] The voltage V at the second node N2 N2 V from writing stage ③ vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C A ) becomes V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C A )-ΔV N2 .

[0230] The third transistor T3 has Vgs4 = V N1 -V N2

[0231] =V data -ΔV N1 -[V vref -Vth+(V data -Vvref )*C cst / cst +C oled +C A )-ΔV N2 ]

[0232] = V data -ΔV N1 -V vref +Vth- (V data -V vref )*C cst / cst +C oled +C A )+ΔV N2

[0233] = (V data -V vref )*[1-C cst / cst +C oled +C A )]+Vth-ΔV N1 +ΔV N2

[0234] = Vgs3- (ΔV N1 -ΔV N2 )

[0235] At this time, the third transistor T3 needs to be turned off to stop the light emitting element 1 from emitting light, and Vgs4 of the third transistor T3 is less than Vth, i.e.:

[0236] (V data -V vref )*[1-C cst / cst +C oled +C A )]+Vth-ΔV N1 +ΔV N2 <Vth

[0237] (V data -V vref )*[1-C cst / cst +C oled +C A )]<ΔV N1 -ΔV N2

[0238] (V data -V vref )*[1-C cst / cst +C oled +CA )] < AV N1 *[1-C cst / (C cst +C oled +C A )]

[0239] V data -V vref <C B *(V BH -V BL ) / (C B +C cst )。

[0240] Therefore, when the above conditions are satisfied, the third transistor T3 is turned off, and the to-be-driven element 1 stops emitting light.

[0241] Therefore, as shown in FIG. 10B, the pixel driving circuit 2 can adjust the light-emitting duty cycle of the to-be-driven element 1 by adjusting the duty cycle of the low level of the modulation signal vb, that is, the greater the duty cycle of the low level of the modulation signal vb, the longer the time for which the modulation signal vb is at the low level, and the longer the time for which the to-be-driven element 1 stops emitting light. In this case, the longer the time for which the to-be-driven element 1 stops emitting light, the darker the brightness perceived by the human eye within a frame. In order to make the brightness perceived by the human eye within a frame the same as that when the to-be-driven element 1 emits light all the time, the driving current of the to-be-driven element 1 in the light-emitting stage ④ can be increased, and the brightness of the to-be-driven element 1 when emitting light can be increased, so that the average brightness of the to-be-driven element 1 within a frame is the same as that when the to-be-driven element 1 emits light all the time, and the brightness perceived by the human eye within a frame is the same as that when the to-be-driven element 1 emits light all the time.

[0242] Exemplarily, the pixel driving method of the pixel driving circuit 2 as shown in FIG. 11B is introduced as follows.

[0243] The pixel driving circuit 2 as shown in FIG. 11B is different from the pixel driving circuit 2 as shown in FIG. 10B in that the modulation sub-circuit 50 is coupled to the second node N2, and the direct current sub-circuit 80 is coupled to the first node N1. The introduction of the pixel driving circuit 2 as shown in FIG. 11B can refer to the previous description of the pixel driving circuit 2, which will not be described herein again.

[0244] Exemplarily, one frame period Frame includes a reset stage ①, a compensation stage ②, a writing stage ③, a light-emitting stage ④, and a modulation stage ⑤. The corresponding timing is shown in FIG. 17.

[0245] Reset stage ①, as shown in FIG. 18A: the driving method of the pixel driving circuit 2 in the reset stage ① as shown in FIG. 11B is consistent with the driving method of the pixel driving circuit 2 in the reset stage ① as shown in FIG. 10B, which will not be described here. At this time, the modulation signal vb provided by the modulation signal line VB changes from high level to low level.

[0246] At this time, the voltage V N1 of the first node N1 is V vref ; and the voltage V N2 of the second node N2 is V vint .

[0247] Compensation stage ②, as shown in FIG. 18B: the driving method of the pixel driving circuit 2 in the compensation stage ② as shown in FIG. 11B is consistent with the driving method of the pixel driving circuit 2 in the compensation stage ② as shown in FIG. 10B, which will not be described here. At this time, the modulation signal vb provided by the modulation signal line VB is low level.

[0248] At this time, the voltage V N1 of the first node N1 is V vref ; and the voltage V N2 of the second node N2 changes to V vref -Vth.

[0249] Write stage ③, as shown in FIG. 18C: at this time, the modulation signal vb provided by the modulation signal line VB is low level.

[0250] At this time, the second transistor T2 transmits the data signal data received at the data signal line Data to the first node N1, and the voltage V N1 of the first node N1 is V data .

[0251] The coupling capacitor Cst couples the voltage variation AV N1 of the first node N1 to the second node N2, and the voltage variation AV N1 of the first node N1 is V data -V vref ; and the voltage V N2 of the second node N2 changes to V vref -Vth+(V data -V vref )*C cst / (C cst +C oled +C B ), wherein C cst is the capacitance value of the coupling capacitor Cst; C oled is the capacitance value of the parasitic capacitance Cod of the to-be-driven element 1; and C B is the capacitance value of the modulation capacitor CB.

[0252] Vgs3 of the third transistor T3 = V N1 - N2 = V data - vref -Vth + (V data - vref )*C cst / (C cst +C oled +C B )

[0253] = V data - vref +Vth - (V data - vref )*C cst / (C cst +C oled +C B )

[0254] = (V data - vref )*[1-C cst / (C cst +C oled +C B )]+Vth

[0255] At this time, Vgs3 of the third transistor T3 > Vth, and the third transistor T3 is turned on.

[0256] When the voltage V N2 of the second node N2 is greater than the threshold voltage of the to-be-driven element 1 by more than the voltage of the second power signal line VSS coupled to the to-be-driven element 1, the to-be-driven element 1 emits light.

[0257] It should be noted that, from the compensation stage ② to the writing stage ③, the voltage change amount ΔV N2 of the second node N2 is (V data - vref )*C cst / (C cst +C oled +C B ), and in the process of writing the data signal data, the voltage change amount ΔV N2 of the second node N2 changes less with the voltage change amount ΔV N1 of the first node N1, and the writing efficiency of the data signal data is higher, that is, the value of C cst / (C cst +C oled +C B ) is smaller, and the writing efficiency of the data signal data is higher.

[0258] As shown in FIG. 11B, the pixel driving circuit 2, the modulation capacitor CB is coupled between the second node N2 and the first node N1. B Compared with C N2 , the value of C cst / (C cst +C oled +C B ) is smaller than that of C cst / (C cst +C oled +C N2 ) of the pixel driving circuit 2 as shown in FIG. 2B, thus the pixel driving circuit 2 as shown in FIG. 11B improves the stability of the second node N2, reduces the voltage variation ΔV N2 of the second node N2, and improves the writing efficiency of the data signal data.

[0259] The light emitting stage ④, as shown in FIG. 18D: at this time, the modulation signal vb provided by the modulation signal line VB is at low level. The driving element 1 emits light.

[0260] The modulation stage ⑤, as shown in FIG. 18E: at this time, the modulation signal vb provided by the modulation signal line VB changes from low level to high level.

[0261] The modulation capacitor CB couples the voltage variation of the modulation signal vb transmitted by the modulation signal line VB to the second node N2, and the voltage variation of the second node N2 is ΔV N2 =C B *(V BH -V BL ) / (C cst +C oled +C B ), wherein V BH is the high voltage of the modulation signal vb; V BL is the low voltage of the modulation signal vb.

[0262] The coupling capacitor Cst couples the voltage variation ΔV N2 of the second node N2 to the first node N1, and the voltage variation of the first node N1 is ΔV N1 =C cst *ΔV N2 / (C cst +C A ), wherein C A is the capacitance value of the direct current capacitor CA.

[0263] It should be noted that the parasitic capacitance of the first node N1 and the second node N2 is generally small and can be ignored in the pixel driving circuit 2 as shown in FIG. 11B.

[0264] It is obvious that ΔV N2> ΔV N1 , i.e. the voltage of the second node N2 rises greatly.

[0265] In the modulation phase (5), the voltage V N1 of the first node N1 becomes V data . data + ΔV N1 .

[0266] The voltage V N2 of the second node N2 becomes V vref -Vth+ (V data -V vref )*C cst / (C cst +C oled +C B ). vref -Vth+ (V data -V vref )*C cst / (C cst +C oled +C B ) + ΔV N2 .

[0267] The Vgs4 of the third transistor T3 becomes V N1 -V N2

[0268] = V data + ΔV N1 -[V vref -Vth+ (V data -V vref )*C cst / (C cst +C oled +C B ) + ΔV N2 ]

[0269] = V data + ΔV N1 -V vref + Vth- (V data -V vref )*C cst / (C cst +C oled +C B ) - ΔV N2

[0270] = (V data -V vref )*[1-C cst / (C cst +C oled +CB )] + Vth + ΔV N1 - ΔV N2

[0271] = Vgs3 - ΔV N2 + ΔV N1

[0272] At this time, the third transistor T3 needs to be turned off to stop the light emitting of the element to be driven 1, and Vgs4 of the third transistor T3 < Vth, that is:

[0273] (V data - V vref )* [1 - C cst / (C cst + C oled + C B )] + Vth + ΔV N1 - ΔV N2 < Vth

[0274] (V data - V vref )* [1 - C cst / (C cst + C oled + C B )] < ΔV N2 - ΔV N1

[0275] (V data - V vref )* [1 - C cst / (C cst + C oled + C B )] < ΔV N2 *[1 - C cst / (C cst + C A )]

[0276] (V data - V vref )* [1 - C cst / (C cst + C oled + C B )] < [C B *(V BH - V BL ) / (C cst + C oled + C B )]*[1 - C cst / (C cst + C A )]

[0277] Therefore, when the above conditions are met, the third transistor T3 is turned off, and the to-be-driven element 1 stops emitting light.

[0278] It can be seen that, as shown in FIG. 11B, the pixel driving circuit 2 can adjust the light-emitting duty cycle of the to-be-driven element 1 by adjusting the duty cycle of the high level of the modulation signal vb, that is, the greater the duty cycle of the high level of the modulation signal vb, the longer the time during which the modulation signal vb is at the high level, and the longer the time during which the to-be-driven element 1 stops emitting light. In this case, the longer the time during which the to-be-driven element 1 stops emitting light, the darker the brightness perceived by the human eye within a frame. In order to make the brightness perceived by the human eye within a frame the same as that when the to-be-driven element 1 emits light all the time, the driving current of the to-be-driven element 1 in the light-emitting stage ④ can be increased, and the brightness of the to-be-driven element 1 during light emission can be increased, so that the average brightness of the to-be-driven element 1 within a frame is the same as that when the to-be-driven element 1 emits light all the time, and the brightness perceived by the human eye within a frame is the same as that when the to-be-driven element 1 emits light all the time.

[0279] In another aspect, some embodiments of the present application also provide a display panel 1000, as shown in FIG. 19A, the display panel 1000 includes a display area AA and a peripheral area BB located at least one side of the display area AA, and the peripheral area BB exemplarily surrounds the display area AA. As shown in FIG. 19B, the display panel 1000 includes a substrate 1001, a driving circuit layer 1002 disposed on one side of the substrate 1001, and a driving element layer 1003 disposed on a side of the driving circuit layer 1002 away from the substrate 1001; the driving circuit layer 1002 is provided with a plurality of pixel driving circuits 2 as described above; and the driving element layer 1003 includes a plurality of to-be-driven elements 1, and each to-be-driven element 1 is coupled with a pixel driving circuit 2.

[0280] Exemplarily, in some embodiments, the display panel 1000 includes a plurality of sub-pixels P, as shown in FIG. 19B, the display panel 1000 can include the substrate 1001, the driving circuit layer 1002, the driving element layer 1003, and the encapsulation layer 1004 which are disposed in layers.

[0281] The substrate 1001 is a base layer of the display panel 1000, and provides a bearing basis for the driving circuit layer 1002 and the driving element layer 1003, for example; the driving circuit layer 1002 is provided with a plurality of pixel driving circuits 2 as described in some embodiments above; the driving element layer 1003 is provided with a plurality of to-be-driven elements 1; one to-be-driven element 1 is coupled with one pixel driving circuit 2, and a sub-pixel P includes a pixel driving circuit 2 and a to-be-driven element 1 connected together.

[0282] As shown in FIG. 19B, in some embodiments, the driving circuit layer 1002 can include a bottom metal layer 100, a buffer layer 110, a first active layer 120, a first gate insulating layer 130, a first gate metal layer 140, a first interlayer dielectric layer 150, a first source-drain metal layer 160, a second gate insulating layer 170, a second gate metal layer 180, a third gate insulating layer 190, a third gate metal layer 200, a fourth gate insulating layer 210, a second active layer 220, a fifth gate insulating layer 230, a fourth gate metal layer 240, a sixth gate insulating layer 250, a fifth gate metal layer 260, a second interlayer dielectric layer 270, a second source-drain metal layer 280, and a planarization layer 290, which are stacked.

[0283] As shown in FIG. 19B, in some embodiments, the driving element layer 1003 can include an anode layer 310, a pixel defining layer 320, a light-emitting layer 330, and a cathode layer 340, which are stacked.

[0284] As shown in FIG. 19B, in some embodiments, the encapsulation layer 1004 can include a first encapsulation layer 350, a second encapsulation layer 360, and a third encapsulation layer 370, which are stacked.

[0285] The display panel 1000 of some embodiments includes the pixel driving circuit 2 described in some of the above embodiments. Since the pixel driving circuit 2 described above reduces the number of transistors, the area of the display panel 1000 occupied by the pixel driving circuit 2 is reduced, so that more pixel driving circuits 2 can be accommodated in the unit area of the display panel 1000, i.e., more sub-pixels can be accommodated in the unit area of the display panel 1000, the PPI of the display panel 1000 is improved, the resolution of the display panel 1000 is improved, and thus the display effect of the display panel 1000, such as picture clarity and delicacy, is improved.

[0286] The following describes the film layer structure arrangement of the display panel 1000 including the pixel driving circuit 2 as shown in FIG. 2B. In some embodiments, the sub-pixels P are arranged in an array, the pixel driving circuits 2 in the sub-pixels P are arranged in a row along the row direction and in a column along the column direction, and the film layers in the driving circuit layer 1002 of adjacent sub-pixels P in the smallest repeating unit of 2 rows and 2 columns of 4 sub-pixels P are left-right mirror symmetrical.

[0287] In some embodiments, as shown in FIGS. 2B, 2D, 10B, and 11B, the pixel driving circuit 2 includes the coupling capacitor Cst and further includes a second transistor T2, a first electrode T21 of the second transistor T2 being coupled to the data signal line Data.

[0288] As shown in FIG. 19B, the driving circuit layer 1002 includes a bottom metal layer 100 disposed on one side of the substrate 1001; as shown in FIG. 20, the bottom metal layer 100 includes a data signal line pattern 101.

[0289] As shown in FIG. 19B, the driving circuit layer 1002 further includes at least one active layer, such as a first active layer 120 and a second active layer 220, disposed on a side of the bottom metal layer 100 away from the substrate 1001.

[0290] The driving circuit layer 1002 further includes a top metal layer disposed on a side of the at least one active layer away from the substrate 1001; the top metal layer includes an electrode plate pattern of the coupling capacitor Cst. The top metal layer is the metal layer farthest from the substrate 1001 among the metal layers included in the driving circuit layer 1002, and exemplarily, as shown in FIG. 19B, the top metal layer is the second source-drain metal layer 280.

[0291] It should be noted that the data signal line pattern 101 is disposed on the bottom metal layer 100, and the bottom metal layer 100 can be made of a low-resistance material, such as titanium, aluminum, a multilayer metal stack, an alloy metal, etc., which can effectively reduce the resistance of the data signal line. In the display panel 1000, the data signal line pattern 101 is disposed on the bottom metal layer, and the electrode plate pattern of the coupling capacitor Cst is disposed on the top metal layer, as shown in FIGS. 2B, 2D, 10B and 11B, the coupling capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2, the first electrode plate Cst1 of the coupling capacitor Cst is coupled to the first node N1, and the second electrode plate Cst2 of the coupling capacitor Cst is coupled to the second node N2. In the pixel driving circuit 2, the first node N1 and the second node N2 are not actually existing structures, for example, the second node N2 is the confluence point of the second electrode plate Cst2 of the coupling capacitor Cst and the first electrode pattern of the driving transistor, and exemplarily, the second electrode plate pattern of the coupling capacitor Cst is disposed on the top metal layer, i.e., the second node N2 is located at or close to the top metal layer, which increases the distance between the data signal line pattern 101 and the electrode plate pattern of the coupling capacitor Cst, i.e., increases the distance between the data signal line pattern 101 and the second node N2, reduces the parasitic capacitance between the data signal line and the second node, avoids the voltage jump of the transmitted data signal of the data signal line when the signal is scanned to the nth row, which affects the voltage of the second node in the previous row through the parasitic capacitance between the data signal line and the second node, thereby reducing the occurrence of the row-to-row crosstalk, and further improving the situation that the luminous brightness of the light emitting device of a certain row of sub-pixels P is affected by the adjacent row of sub-pixels P, and improving the stability of the light emission of the display panel 1000.

[0292] In some embodiments, as shown in FIG. 2B, the pixel driving circuit 2 includes a second transistor T2 and a fourth transistor T4; as shown in FIG. 4, the gate T23 of the second transistor T2 is coupled with the second gate signal line GT2, and as shown in FIG. 6, the gate T43 of the fourth transistor T4 is coupled with the first gate signal line GT1.

[0293] Specifically, as shown in FIG. 19B, the driving circuit layer 1002 of the display panel 1000 can include a first active layer 120 disposed on the side of the bottom metal layer 100 away from the substrate 1001, a first gate metal layer 140 disposed on the side of the first active layer 120 away from the substrate 1001, and a first source-drain metal layer 160 disposed on the side of the first gate metal layer 140 away from the substrate 1001. The first active layer 120, the first gate metal layer 140, and the first source-drain metal layer 160 can be used to dispose the second transistor T2 and the fourth transistor T4 of the pixel driving circuit 2.

[0294] Exemplarily, as shown in FIG. 22, the first active layer 120 can include an active layer pattern 122 of the second transistor T2 and an active layer pattern 121 of the fourth transistor T4, wherein the active layer pattern 122 of the second transistor T2 can include a first active layer pattern 1221 of the second transistor T2, an active layer channel pattern 1223 of the second transistor T2, and a second active layer pattern 1222 of the second transistor T2, and the first active layer pattern 1221 and the second active layer pattern 1222 of the second transistor T2 are connected with the active layer channel pattern 1223 of the second transistor T2, respectively; the active layer pattern 121 of the fourth transistor T4 can include a first active layer pattern 1211 of the fourth transistor T4, an active layer channel pattern 1213 of the fourth transistor T4, and a second active layer pattern 1212 of the fourth transistor T4, and the first active layer pattern 1211 and the second active layer pattern 1212 of the fourth transistor T4 are connected with the active layer channel pattern 1213 of the fourth transistor T4, respectively; the second active layer pattern 1222 of the second transistor T2 is connected with the second active layer pattern 1212 of the fourth transistor T4. In some embodiments, the second active layer pattern 1222 of the second transistor T2 can also serve as the second active layer pattern 1212 of the fourth transistor T4.

[0295] As shown in FIG. 22, the position where the active layer second electrode pattern 1222 of the second transistor T2 is connected with the active layer second electrode pattern 1212 of the fourth transistor T4 is the first node N1. Any position on the active layer second electrode pattern 1222 of the second transistor T2 or the active layer second electrode pattern 1212 of the fourth transistor T4 can be the first node N1 when the active layer second electrode pattern 1222 of the second transistor T2 also serves as the active layer second electrode pattern 1212 of the fourth transistor T4.

[0296] Exemplarily, as shown in FIG. 24, the first gate metal layer 140 can include a second gate signal line pattern 142 and a first gate signal line pattern 141; as shown in FIG. 22 and FIG. 24, the second gate signal line pattern 142 overlaps with the active layer pattern 122 of the second transistor T2, for example, the active layer channel groove pattern 1223 of the second transistor T2, the part of the second gate signal line pattern 142 overlapping with the active layer channel groove pattern 1223 of the second transistor T2 is the gate pattern 1421 of the second transistor T2; the first gate signal line pattern 141 overlaps with the active layer pattern 121 of the fourth transistor T4, for example, the active layer channel groove pattern 1213 of the fourth transistor T4, the part of the first gate signal line pattern 141 overlapping with the active layer channel groove pattern 1213 of the fourth transistor T4 is the gate pattern 1411 of the fourth transistor T4.

[0297] It should be noted that the overlap mentioned in some embodiments refers to the corresponding arrangement of part of the pattern of one film layer and part of the pattern of another film layer in the direction perpendicular to the substrate 1001, and the corresponding arrangement is the overlapping part. There can be other film layers, such as insulating layers, between the part of the pattern of one film layer and the part of the pattern of another film layer.

[0298] Exemplarily, as shown in FIG. 26, the first source-drain metal layer 160 can include the first electrode pattern 1621 and the second electrode pattern 1622 of the second transistor T2 and the first electrode pattern 1611 and the second electrode pattern 1612 of the fourth transistor T4; the second electrode pattern 1622 of the second transistor T2 is connected with the second electrode pattern 1612 of the fourth transistor T4. In some embodiments, the second electrode pattern 1622 of the second transistor T2 can also serve as the second electrode pattern 1612 of the fourth transistor T4.

[0299] In some embodiments, as shown in FIG. 19B, the driving circuit layer 1002 of the display panel 1000 can further include a buffer layer 110 (as shown in FIG. 21, the buffer layer 110 has a plurality of vias) disposed between the bottom metal layer 100 and the first active layer 120, a first gate insulating layer 130 (as shown in FIG. 23, the first gate insulating layer 130 has a plurality of vias) disposed between the first active layer 120 and the first gate metal layer 140, and a first interlayer dielectric layer 150 (as shown in FIG. 25, the first interlayer dielectric layer 150 has a plurality of vias) disposed between the first gate metal layer 140 and the first source-drain metal layer 160. The buffer layer 110, the first gate insulating layer 130, and the first interlayer dielectric layer 150 are all insulating layers, and are respectively disposed between adjacent metal layers to isolate the adjacent metal layers.

[0300] Exemplarily, as shown in FIG. 27, the first electrode pattern 1621 of the second transistor T2 in the first source-drain metal layer 160 is connected with the active layer first electrode pattern 1221 of the second transistor T2 in the first active layer 120 through the via penetrating the first interlayer dielectric layer 150 and the first gate insulating layer 130; and the second electrode pattern 1622 of the second transistor T2 in the first source-drain metal layer 160 is connected with the active layer second electrode pattern 1222 of the second transistor T2 in the first active layer 120 through the via penetrating the first interlayer dielectric layer 150 and the first gate insulating layer 130.

[0301] Exemplarily, as shown in FIG. 27, the first electrode pattern 1611 of the fourth transistor T4 in the first source-drain metal layer 160 is connected with the active layer first electrode pattern 1211 of the fourth transistor T4 in the first active layer 120 through the via penetrating the first interlayer dielectric layer 150 and the first gate insulating layer 130; and the second electrode pattern 1612 of the fourth transistor T4 in the first source-drain metal layer 160 is connected with the active layer second electrode pattern 1212 of the fourth transistor T4 in the first active layer 120 through the via penetrating the first interlayer dielectric layer 150 and the first gate insulating layer 130.

[0302] In some embodiments, as shown in FIG. 20, the bottom metal layer 100 further includes a reference signal line pattern 102; and as shown in FIG. 27, the first electrode pattern 1611 of the fourth transistor T4 is connected with the reference signal line pattern 102 through the via; and the first electrode pattern 1621 of the second transistor T2 is connected with the data signal line pattern 101 through the via.

[0303] Exemplarily, as shown in FIG. 27, the first electrode pattern 1611 of the fourth transistor T4 in the first source-drain metal layer 160 is connected with the reference signal line pattern 102 in the bottom metal layer 100 through the via penetrating through the first interlayer dielectric layer 150, the first gate insulating layer 130 and the buffer layer 110; the first electrode pattern 1621 of the second transistor T2 in the first source-drain metal layer 160 is connected with the data signal line pattern 101 in the bottom metal layer 100 through the via penetrating through the first interlayer dielectric layer 150, the first gate insulating layer 130 and the buffer layer 110.

[0304] It should be noted that the reference signal line pattern 102 is arranged in the bottom metal layer 100 of the display panel 1000, which can shield the parasitic capacitance between the data signal line and the first node N1, and reduce the interference of the second gate signal of the second transistor T2 and the first gate signal of the fourth transistor T4 on the data signal.

[0305] In some embodiments, as shown in FIG. 2B, the pixel driving circuit 2 includes the first transistor T1 and the third transistor T3; as shown in FIG. 5, the first gate T13 of the first transistor T1 is coupled with the reset signal line Reset and the second gate T14 of the first transistor T1, and the reset signal line Reset includes the first sub-reset signal line Reset1 and the second sub-reset signal line Reset2.

[0306] Specifically, as shown in FIG. 19B, the driving circuit layer 1002 can include the third gate metal layer 200 arranged on the far side of the first source-drain metal layer 160 away from the substrate 1001, the second active layer 220 arranged on the far side of the third gate metal layer 200 away from the substrate 1001, the fourth gate metal layer 240 arranged on the far side of the second active layer 220 away from the substrate 1001, and the second source-drain metal layer 280 arranged on the far side of the fourth gate metal layer 240 away from the substrate 1001. The third gate metal layer 200, the second active layer 220, the fourth gate metal layer 240 and the second source-drain metal layer 280 can be used to arrange the first transistor T1 and the third transistor T3 of the pixel driving circuit 2.

[0307] Exemplarily, as shown in FIG. 31, the third gate metal layer 200 can include the first sub-reset signal line pattern 201 and the second gate pattern 202 of the third transistor T3.

[0308] Exemplarily, as shown in FIG. 33, the second active layer 220 can include an active layer pattern 221 of the first transistor T1 and an active layer pattern 222 of the third transistor T3, wherein the active layer pattern 221 of the first transistor T1 can include an active layer first electrode pattern 2211 of the first transistor T1, an active layer channel trench pattern 2213 of the first transistor T1, and an active layer second electrode pattern 2212 of the first transistor T1, and the active layer first electrode pattern 2211 and the active layer second electrode pattern 2212 of the first transistor T1 are connected with the active layer channel trench pattern 2213 of the first transistor T1, respectively; the active layer pattern 222 of the third transistor T3 can include an active layer first electrode pattern 2221 of the third transistor T3, an active layer channel trench pattern 2223 of the third transistor T3, and an active layer second electrode pattern 2222 of the third transistor T3, and the active layer first electrode pattern 2221 and the active layer second electrode pattern 2222 of the third transistor T3 are connected with the active layer channel trench pattern 2223 of the third transistor T3, respectively; the active layer second electrode pattern 2212 of the first transistor T1 is connected with the active layer second electrode pattern 2222 of the third transistor T3. In some embodiments, the active layer second electrode pattern 2212 of the first transistor T1 can also serve as the active layer second electrode pattern 2222 of the third transistor T3.

[0309] As shown in FIG. 33, the position where the active layer second electrode pattern 2212 of the first transistor T1 is connected with the active layer second electrode pattern 2222 of the third transistor T3 is the second node N2; when the active layer second electrode pattern 2212 of the first transistor T1 also serves as the active layer second electrode pattern 2222 of the third transistor T3, any position on the active layer second electrode pattern 2212 of the first transistor T1 or the active layer second electrode pattern 2222 of the third transistor T3 can serve as the second node N2.

[0310] As shown in FIG. 31 and FIG. 33, the first sub-reset signal line pattern 201 in the third gate metal layer 200 and the active layer pattern 221 of the first transistor T1 in the second active layer 220, for example, the active layer channel trench pattern 2213 of the first transistor T1, have an overlap, and the part of the first sub-reset signal line pattern 201 that overlaps with the active layer channel trench pattern 2213 of the first transistor T1 serves as the second gate pattern 2011 of the first transistor T1.

[0311] Exemplarily, as shown in FIG. 37, the fourth gate metal layer 240 can include the second sub-reset signal line pattern 241 and the first gate pattern 242 of the third transistor T3; as shown in FIG. 33 and FIG. 37, the second sub-reset signal line pattern 241 and the active layer pattern 221 of the first transistor T1 in the second active layer 220, for example, the active layer channel trench pattern 2213 of the first transistor T1, have an overlap, and the part of the second sub-reset signal line pattern 241 that overlaps with the active layer channel trench pattern 2213 of the first transistor T1 serves as the first gate pattern 2411 of the first transistor T1.

[0312] Exemplarily, as shown in FIG. 41, the second source-drain metal layer 280 includes the first electrode pattern 2811, the second electrode pattern 2812 of the first transistor T1, and the first electrode pattern 2821, the second electrode pattern 2822 of the third transistor T3; the second electrode pattern 2812 of the first transistor T1 is connected with the second electrode pattern 2822 of the third transistor T3; in some embodiments, the second electrode pattern 2812 of the first transistor T1 can also serve as the second electrode pattern 2822 of the third transistor T3.

[0313] In some embodiments, as shown in FIG. 19B, the driving circuit layer 1002 of the display panel 1000 can further include the fourth gate insulating layer 210 (as shown in FIG. 32, the fourth gate insulating layer 210 has a plurality of through holes) disposed between the third gate metal layer 200 and the second active layer 220, the fifth gate insulating layer 230 (as shown in FIG. 35, the fifth gate insulating layer 230 has a plurality of through holes) disposed between the second active layer 220 and the fourth gate metal layer 240, and the second interlayer dielectric layer 270 (as shown in FIG. 40, the second interlayer dielectric layer 270 has a plurality of through holes) disposed between the fourth gate metal layer 240 and the second source-drain metal layer 280.

[0314] FIG. 42 is a stack plan view of part of the film layers of the display panel 1000; FIG. 48 is a sectional view of FIG. 42 along the A-A sectional line; and FIG. 49 is a sectional view of FIG. 42 along the B-B sectional line.

[0315] Exemplarily, as shown in FIG. 42, and with reference to FIG. 42, the active layer second electrode pattern 2222 of the third transistor T3 in the second active layer 220 is connected with the second gate pattern 202 of the third transistor T3 in the third gate metal layer 200 through the through hole penetrating the fourth gate insulating layer 210.

[0316] Exemplarily, as shown in FIG. 42, and with reference to FIG. 42, the first electrode pattern 2811 of the first transistor T1 in the second source-drain metal layer 280 is connected with the active layer first electrode pattern 2211 of the first transistor T1 in the second active layer 220 through a via hole penetrating through the second interlayer dielectric layer 270 and the fifth gate insulating layer 230; the second electrode pattern 2812 of the first transistor T1 in the second source-drain metal layer 280 is connected with the active layer second electrode pattern 2212 of the first transistor T1 in the second active layer 220 through a via hole penetrating through the second interlayer dielectric layer 270 and the fifth gate insulating layer 230.

[0317] Exemplarily, as shown in FIG. 42, and with reference to FIG. 42, the first electrode pattern 2821 of the third transistor T3 in the second source-drain metal layer 280 is connected with the active layer first electrode pattern 2221 of the third transistor T3 in the second active layer 220 through a via hole penetrating through the second interlayer dielectric layer 270 and the fifth gate insulating layer 230; the second electrode pattern 2822 of the third transistor T3 in the second source-drain metal layer 280 is connected with the active layer second electrode pattern 2222 of the third transistor T3 in the second active layer 220 through a via hole penetrating through the second interlayer dielectric layer 270 and the fifth gate insulating layer 230.

[0318] Exemplarily, the driving circuit layer 1002 of the display panel 1000 can further include a mask layer 380 disposed between the second active layer 220 and the fifth gate insulating layer 230, as shown in FIG. 34, the mask layer 380 is a mask layer for the conductorization doping of the second active layer 220, the mask layer 380 can adopt a photoresist material, the mask layer 380 acts as a mask to shield the part of the second active layer 220 which is not to be conductorized, and the semiconductor channel pattern of the second active layer 220 is reserved.

[0319] Exemplarily, the first sub-reset signal line pattern 201 and the second sub-reset signal line pattern 241 are connected.

[0320] In some embodiments, as shown in FIG. 19A, the display panel 1000 includes a display area AA and a peripheral area BB, the first sub-reset signal line pattern 201 and the second sub-reset signal line pattern 241 are connected through a via hole in the peripheral area BB.

[0321] Exemplarily, in the peripheral region BB of the display panel 1000, the second source-drain metal layer 280 includes a connection pattern, and the connection pattern of the second source-drain metal layer 280 is connected with the second sub-reset signal line pattern 241 in the fourth gate metal layer 240 through a via penetrating the second interlayer dielectric layer 270; the connection pattern of the second source-drain metal layer 280 is connected with the first sub-reset signal line pattern 201 in the third gate metal layer 200 through a via penetrating the second interlayer dielectric layer 270, the fifth gate insulating layer 230 and the fourth gate insulating layer 210, so as to realize the connection between the first sub-reset signal line pattern 201 and the second sub-reset signal line pattern 241. This setting can reduce the film layer pattern of the display region AA of the display panel 1000, simplify the film layer pattern setting of the display region of the display panel 1000, and increase the manufacturing yield of the display panel 1000.

[0322] In some embodiments, as shown in FIG. 19B, the driving circuit layer 1002 further includes a second gate metal layer 180 arranged between the first source-drain metal layer 160 and the third gate metal layer 200, as shown in FIG. 29, the second gate metal layer 180 includes a first power signal line pattern 182 and an initialization signal line pattern 183, and the first power signal line pattern 182 and the initialization signal line pattern 183 are arranged alternately.

[0323] In some embodiments, as shown in FIG. 19B, the driving circuit layer 1002 further includes a third gate insulating layer 190 arranged between the second gate metal layer 180 and the third gate metal layer 200 (as shown in FIG. 30, the third gate insulating layer 190 has a plurality of vias).

[0324] Exemplarily, as shown in FIG. 42, in the two adjacent rows of pixel driving circuits 2, the active layer pattern 222 of the third transistor T3 in the second active layer 220 of one of the rows, for example, the active layer first electrode pattern 2221 of the third transistor T3 of the second row is connected with the first power signal line pattern 182 in the second gate metal layer 180 through a via penetrating the fourth gate insulating layer 210 and the third gate insulating layer 190; the active layer pattern 221 of the first transistor T1 in the second active layer 220 of one of the rows, for example, the active layer first electrode pattern 2211 of the first transistor T1 of the second row is connected with the initialization signal line pattern 183 in the second gate metal layer 180 through a via penetrating the fourth gate insulating layer 210 and the third gate insulating layer 190.

[0325] It should be noted that the active layer pattern 222 of the third transistor T3 in the second active layer 220 of one row is the same row as the active layer pattern 221 of the first transistor T1 in the second active layer 220 of one row, that is, the two "one row" described above are actually the same row.

[0326] Exemplarily, as shown in FIG. 41, the first electrode patterns 2821 of the third transistors T3 in the same column in the second source-drain metal layer 280 are sequentially connected, and the first electrode patterns 2811 of the first transistors T1 in the same column are sequentially connected; in this way, in the adjacent two rows of pixel driving circuits 2, for example, the active layer pattern 222 of the third transistor T3 in the second active layer 220 of the first row is not connected with the first power signal line pattern 182 in the second gate metal layer 180, but the first electrode pattern 2821 of the third transistor T3 in the first row is connected with the first electrode pattern 2821 of the third transistor T3 in the second row in the same column, so that the third transistor T3 in the first row is connected with the first power signal line pattern 182; similarly, for example, the active layer pattern 221 of the first transistor T1 in the second active layer 220 of the first row is not connected with the initialization signal line pattern 183, but the active layer first electrode pattern 2211 of the first transistor T1 in the first row is connected with the active layer first electrode pattern 2211 of the first transistor T1 in the second row in the same column, so that the first transistor T1 in the first row is connected with the initialization signal line pattern 183. This setting ensures that the first electrode pattern 2821 of the third transistor T3 in each row is connected with the first power signal line pattern 182 in the second gate metal layer 180 through the active layer pattern 222 of the third transistor T3 in the second active layer 220, for example, the active layer first electrode pattern 2221 of the third transistor T3; and ensures that the first electrode pattern 2811 of the first transistor T1 in each row is connected with the initialization signal line pattern 183 in the second gate metal layer 180 through the active layer pattern 221 of the first transistor T1 in the second active layer 220, for example, the active layer first electrode pattern 2211 of the first transistor T1.

[0327] In some embodiments, as shown in FIG. 2B, the pixel driving circuit 2 further includes a coupling capacitor Cst, as shown in FIG. 48, the coupling capacitor Cst includes a first sub-coupling capacitor C1, a second sub-coupling capacitor C2, and a third sub-coupling capacitor C3.

[0328] Exemplarily, as shown in FIG. 29, the second gate metal layer 180 further includes a first electrode plate pattern 181 of the first sub-coupling capacitor; and the second gate pattern 202 of the third transistor T3 in the third gate metal layer 200 serves as a second electrode plate pattern of the first sub-coupling capacitor.

[0329] Exemplarily, as shown in FIG. 19B, the driving circuit layer 1002 further comprises a second gate insulating layer 170 (as shown in FIG. 28, the second gate insulating layer 170 has a plurality of through holes) arranged between the first source-drain metal layer 160 and the second gate metal layer 180, as shown in FIG. 36, the first plate pattern 181 of the first sub-coupling capacitor in the second gate metal layer 180 is connected with the second electrode pattern 1622 of the second transistor T2 in the first source-drain metal layer 160 through the through hole penetrating the second gate insulating layer 170, so as to realize the connection between the first plate pattern 181 of the first sub-coupling capacitor and the first node N1.

[0330] Exemplarily, the active layer pattern 222 of the third transistor T3 of the second active layer 220 serves as the first plate pattern of the second sub-coupling capacitor; and the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 serves as the second plate pattern of the second sub-coupling capacitor.

[0331] Exemplarily, the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 further serves as the first plate pattern of the third sub-coupling capacitor; and the second electrode pattern 2822 of the third transistor T3 of the second source-drain metal layer 280 serves as the second plate pattern of the third sub-coupling capacitor.

[0332] Exemplarily, as shown in FIG. 42, the second plate pattern of the second sub-coupling capacitor, i.e., the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 is connected with the first plate pattern 181 of the first sub-coupling capacitor in the second gate metal layer 180 through the through hole penetrating the fifth gate insulating layer 230, the fourth gate insulating layer 210 and the third gate insulating layer 190; so as to realize the connection between the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 and the first node N1.

[0333] It should be noted that arranging the second gate metal layer 180 can increase the capacitance value of the first sub-coupling capacitor C1, and meanwhile can avoid the situation that when the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 is connected with the first node N1, the first source-drain metal layer 160 is directly connected through the through hole, which leads to a larger depth of the through hole and increases the manufacturing failure rate of the display panel 1000.

[0334] In some embodiments, as shown in FIG. 2B, the pixel driving circuit 2 further comprises a modulation capacitor CB.

[0335] Exemplarily, the first gate pattern 242 of the third transistor T3 of the fourth gate metal layer 240 serves as the first plate pattern of the modulation capacitor CB.

[0336] Exemplarily, as shown in FIG. 19B, the driving circuit layer 1002 can further include a fifth gate metal layer 260 disposed between the fourth gate metal layer 240 and the second source-drain metal layer 280, the fifth gate metal layer 260 being disposed on the side of the second interlayer dielectric layer 270 close to the substrate 1001. As shown in FIG. 39, the fifth gate metal layer 260 includes a modulation signal line pattern 261, the modulation signal line pattern 261 overlapping with the first plate pattern of the modulation capacitor CB, the portion of the modulation signal line pattern 261 overlapping with the first plate pattern of the modulation capacitor CB being the second plate pattern 2611 of the modulation capacitor.

[0337] Exemplarily, as shown in FIG. 19B, the driving circuit layer 1002 can further include a sixth gate insulating layer 250 (as shown in FIG. 38, the sixth gate insulating layer 250 has a plurality of through holes) disposed between the fourth gate metal layer 240 and the fifth gate metal layer 260. At this time, as shown in FIG. 42, the first electrode pattern 2811 of the first transistor T1 in the second source-drain metal layer 280 is connected with the active layer first electrode pattern 2211 of the first transistor T1 in the second active layer 220 through the through hole penetrating through the second interlayer dielectric layer 270, the sixth gate insulating layer 250 and the fifth gate insulating layer 230; the second electrode pattern 2812 of the first transistor T1 in the second source-drain metal layer 280 is connected with the active layer second electrode pattern 2212 of the first transistor T1 in the second active layer 220 through the through hole penetrating through the second interlayer dielectric layer 270, the sixth gate insulating layer 250 and the fifth gate insulating layer 230; the first electrode pattern 2821 of the third transistor T3 in the second source-drain metal layer 280 is connected with the active layer first electrode pattern 2221 of the third transistor T3 in the second active layer 220 through the through hole penetrating through the second interlayer dielectric layer 270, the sixth gate insulating layer 250 and the fifth gate insulating layer 230; the second electrode pattern 2822 of the third transistor T3 in the second source-drain metal layer 280 is connected with the active layer second electrode pattern 2222 of the third transistor T3 in the second active layer 220 through the through hole penetrating through the second interlayer dielectric layer 270, the sixth gate insulating layer 250 and the fifth gate insulating layer 230.

[0338] Exemplarily, as shown in FIG. 19B, the driving circuit layer 1002 can further include a planar layer 290 disposed on the side of the second source-drain metal layer 280 away from the substrate 1001, as shown in FIG. 43, the planar layer 290 includes a plurality of planar through holes 291.

[0339] In some embodiments, the driving element layer 1003 of the display panel 1000 includes an anode layer 310, a pixel defining layer 320, a light emitting layer 330, and a cathode layer 340 arranged in a stack; the display panel 1000 of some embodiments has a high PPI (pixel density unit), and in the display panel 1000 with a high PPI, as shown in FIG. 50, the minimum distance a between two adjacent openings 321 of the pixel defining layer 320 is small, and a needs to be in a range of 7 um to 10 um, for example, can be 7 um, 8 um, 9 um, or 10 um.

[0340] As shown in FIG. 50, one opening 321 of the pixel defining layer 320 is arranged above one anode pattern 311, the orthographic projection of the one opening 321 of the pixel defining layer 320 on the anode layer 310 is located within the boundary range of the one anode pattern 311, that is, the area of the one anode pattern 311 is greater than the area of the one opening 321 of the pixel defining layer 320, and the one opening 321 of the pixel defining layer 320 completely exposes the one anode pattern 311; the distance b by which the one anode pattern 311 extends outwardly relative to the one opening 321 of the pixel defining layer 320 needs to be greater than or equal to 2.5 um to 3 um, for example, can be 2.5 um, 2.7 um, 3 um, 3.2 um, 3.3 um, 3.5 um, or the like.

[0341] In order to avoid short circuit caused by too close distance between anodes, in combination with process deviation, as shown in FIG. 50, the minimum distance c of the anode pattern 311 needs to be greater than or equal to 3 um, for example, can be 3 um, 3.1 um, 3.2 um, 3.3 um, 3.4 um, 3.5 um, or the like.

[0342] As shown in FIG. 50, the planar layer 290 is arranged below the anode layer 310, and the anode pattern 311 needs to be connected to the pixel driving circuit 2 of the driving circuit layer 1002 through the planar via 291 of the planar layer 290, and the aperture d of the planar via 291 needs to be greater than or equal to 2.5 um, for example, can be 2.5 um, 2.6 um, 2.7 um, 2.8 um, 2.9 um, 3 um, or the like.

[0343] In order to ensure the planarity of the anode in the opening 321 of the pixel defining layer 320 and avoid the overlap between the opening 321 of the pixel defining layer 320 and the planar via 291, at this time, the minimum distance a between the two adjacent openings 321 of the pixel defining layer 320 needs to satisfy a≥2*b+c+d, and 2*b+c+d≥10.5 um, that is, a≥10.5 um; since a needs to be in a range of 7 um to 10 um, in some embodiments, the display panel 1000 with a high PPI does not have space to arrange the planar via 291 of the anode pattern 311 connected to the pixel driving circuit 2 of the driving circuit layer 1002.

[0344] To solve the above technical problems, in some embodiments, as shown in FIG. 19B, the driving element layer 1003 includes an anode extension layer 300 disposed on the far side of the planar layer 290 from the substrate 1001, an anode layer 310 disposed on the far side of the anode extension layer 300 from the substrate 1001, a pixel defining layer 320 disposed on the far side of the anode layer 310 from the substrate 1001, a light emitting layer 330 disposed on the far side of the pixel defining layer 320 from the substrate 1001, and a cathode layer 340 disposed on the far side of the light emitting layer 330 from the substrate 1001. As shown in FIG. 44, the anode extension layer 300 includes a plurality of anode extension patterns 301, each of which includes an anode corresponding pattern 3011 and an extension pattern 3012 connected to each other, and as shown in FIG. 47A, one extension pattern 3012 is connected to one pixel driving circuit 2 of the driving circuit layer 1002 through one planar via hole 291. As shown in FIG. 45, the anode layer 310 includes a plurality of anode patterns 311, each of which at least partially overlaps with one anode corresponding pattern 3011, and the orthographic projection of one anode corresponding pattern 3011 on the anode layer 310 is located within the boundary of one anode pattern 311. The partial film layer cross-sectional view of the driving element layer 1003 is shown in FIG. 52.

[0345] As shown in FIG. 46, the pixel defining layer 320 includes a plurality of openings 321, each of which defines one sub-pixel and exposes one anode pattern 311, and the light emitting layer 330 includes a plurality of light emitting patterns, each of which is disposed corresponding to one opening 321. One anode extension pattern 301, one anode pattern 311, one light emitting pattern, and the cathode layer corresponding to each other constitute one to-be-driven element 1.

[0346] The anode extension layer 300 is a metal layer prepared by using a metal material, for example, a titanium-aluminum-titanium (Ti-AL-Ti) material. The anode extension layer 300 made of the titanium-aluminum-titanium (Ti-AL-Ti) material can be prepared by using a dry etching process. The process deviation of the titanium-aluminum-titanium (Ti-AL-Ti) material of the anode extension layer 300 by dry etching is smaller than the process deviation of the ITO / Ag / ITO material of the anode layer 310 by wet etching.

[0347] As shown in FIG. 44, the anode extension layer 300 includes a plurality of anode extension patterns 301, and each anode extension pattern 301 includes an anode corresponding pattern 3011 and an extension pattern 3012. As shown in FIG. 51, the area of one anode corresponding pattern 3011 is smaller than the area of one anode pattern 311, and one anode corresponding pattern 3011 overlaps one anode pattern 311, i.e., the orthographic projection of one anode corresponding pattern 3011 on the anode layer 310 is within the boundary range of one anode pattern 311. Meanwhile, the area of one anode corresponding pattern 3011 is larger than the area of one opening 321 of the pixel definition layer 320, i.e., the orthographic projection of one opening 321 of the pixel definition layer 320 on the anode extension layer 300 is within the boundary range of one anode corresponding pattern 3011. At this time, the outward extension distance e of one anode corresponding pattern 3011 compared to one opening 321 of the pixel definition layer 320 can be greater than or equal to 1.5 um. Since the process deviation of the dry etching of the Ti-AL-Ti material of the anode extension layer 300 is smaller than the process deviation of the wet etching of the ITO / Ag / ITO material of the anode layer 310, the minimum distance f between one anode extension pattern 301 and the adjacent anode extension pattern 301 can be greater than or equal to 2.3 um. At this time, the minimum distance a between the openings 321 of the adjacent two pixel definition layers 320 satisfies a ≥ 2*e+f+d, and 2*e+f+d ≥ 7.8 um, i.e., a ≥ 7.8 um. Since the range of a needs to be 7 um to 10 um, some embodiments of the high-PPI display panel 1000 have space to arrange the anode extension patterns 301 of the anode extension layer 300, as shown in FIG. 47A, and the extension pattern 3012 of the anode extension layer 300 is connected to the pixel driving circuit 2 of the driving circuit layer 1002 through the flat via 291.

[0348] It should be noted that one extension pattern 3012 is connected to one pixel driving circuit 2 of the driving circuit layer 1002 through one flat via 291, as shown in FIG. 47A and FIG. 52, specifically, one extension pattern 3012 is connected to the second electrode pattern 2822 of the third transistor T3 in the second source-drain metal layer 280 of the driving circuit layer 1002 through one flat via 291.

[0349] As shown in FIG. 47B, it is a partial membrane layer stack plan view of the display panel 1000.

[0350] In another aspect, a display device 10000 is provided, including the display panel 1000 described above.

[0351] As shown in FIG. 53, the display device 10000 can display an image, for example, can display a still image or a dynamic image, and the like. Exemplarily, the display device 10000 can be a display, a television, a billboard, a household appliance, a large-area wall, an information inquiry device (such as a service inquiry device of a department of electronic government, bank, hospital or power, and the like), a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a navigator, or the like.

[0352] The display device of some embodiments includes the display panel 1000 described in some embodiments above, which can accommodate more sub-pixels in a unit area, has high PPI and high resolution, and therefore, the display device of some embodiments also has high PPI and high resolution.

[0353] In the description of the specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0354] The above describes only specific embodiments of some embodiments, but the protection scope of some embodiments is not limited thereto, and any person skilled in the art should think of changes or replacements within the technical range disclosed by some embodiments, which should be covered in the protection scope of some embodiments. Therefore, the protection scope of some embodiments should be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, wherein, include A reset sub-circuit, the reset sub-circuit being coupled to a reference signal line, an initialization signal line, a first node, and a second node, the reset sub-circuit being configured to transmit a reference signal received at the reference signal line to the first node, and an initialization signal received at the initialization signal line to the second node; A write sub-circuit, which is coupled to a data signal line and the first node, is configured to transmit a data signal received at the data signal line to the first node. A driving sub-circuit, wherein the driving sub-circuit is coupled to a first power signal line, a first node, and a second node, and the second node is coupled to the element to be driven; The driving sub-circuit is configured to conduct under the control of a first power signal transmitted on the first power signal line, the voltage of the first node, and the voltage of the second node, generating a driving signal to drive the element to be driven. A coupling sub-circuit, which is coupled to the first node and the second node, and is configured to couple the voltage change of the first node to the second node; A modulation sub-circuit, coupled to a modulation signal line and a first node, is configured to couple the voltage change of the modulation signal transmitted by the modulation signal line to the first node, so that the driving sub-circuit is disconnected under the control of the voltage of the first node and the voltage of the second node; or, the modulation sub-circuit, coupled to a modulation signal line and a second node, is configured to couple the voltage change of the modulation signal transmitted by the modulation signal line to the second node, so that the driving sub-circuit is disconnected under the control of the voltage of the first node and the voltage of the second node.

2. The pixel driving circuit according to claim 1, wherein, The modulation sub-circuit includes a modulation capacitor, the first plate of which is coupled to the modulation signal line, and the second plate of which is coupled to the first node or the second node.

3. The pixel driving circuit according to any one of claims 1 to 2, wherein, The driving sub-circuit includes a third transistor, the first gate of which is coupled to the first node, the first electrode of which is coupled to the first power signal line, and the second electrode of which is coupled to the second node.

4. The pixel driving circuit according to claim 3, wherein, The third transistor further includes a second gate, which is coupled to the second node.

5. The pixel driving circuit according to any one of claims 1 to 4, wherein, The reset sub-circuit includes a first transistor and a fourth transistor; The first gate of the first transistor is coupled to the reset signal line, the first electrode of the first transistor is coupled to the initialization signal line, and the second electrode of the first transistor is coupled to the second node; The gate of the fourth transistor is coupled to the first gate signal line, and the first electrode of the fourth transistor is coupled to the reference. The signal line is coupled, and the second terminal of the fourth transistor is coupled to the first node.

6. The pixel driving circuit according to claim 5, wherein, The first transistor further includes a second gate, wherein the first gate of the first transistor is coupled to the second gate of the first transistor.

7. The pixel driving circuit according to any one of claims 1 to 6, wherein, The write sub-circuit includes a second transistor, the gate of which is coupled to a second gate signal line, the first terminal of which is coupled to the data signal line, and the second terminal of which is coupled to the first node.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein, The coupling sub-circuit includes a coupling capacitor, the first plate of which is coupled to the first node, and the second plate of which is coupled to the second node.

9. The pixel driving circuit according to any one of claims 1 to 8, wherein, The second transistor and the fourth transistor are of the first type of transistor, which is a P-type low-temperature polysilicon transistor; The first transistor and the third transistor are second-type transistors, and the second-type transistors are N-type oxide transistors.

10. The pixel driving circuit according to any one of claims 1 to 9, wherein, The pixel driving circuit also includes a DC sub-circuit; When the modulation sub-circuit is coupled to the first node, the DC sub-circuit is coupled to the DC signal line and the second node, and the DC sub-circuit is configured to stabilize the voltage of the second node under the action of the DC signal transmitted on the DC signal line; When the modulation sub-circuit is coupled to the second node, the DC sub-circuit is coupled to the DC signal line and the first node, and the DC sub-circuit is configured to stabilize the voltage of the first node under the action of the DC signal transmitted on the DC signal line.

11. The pixel driving circuit according to claim 10, wherein, The DC sub-circuit includes a DC capacitor, the first plate of which is coupled to the DC signal line, and the second plate of which is coupled to the second node or the first node.

12. A pixel driving method, wherein, Applied to the pixel driving circuit as described in any one of claims 1 to 11, the pixel driving method includes: a frame period including a reset phase, a compensation phase, a writing phase, a light emission phase, and a modulation phase; During the reset phase, The reset sub-circuit transmits the reference signal received at the reference signal line to the first node, resetting the voltage of the first node to the voltage of the reference signal; the reset sub-circuit transmits the reference signal received at the reference signal line to the first node. The initialization signal received at the point is transmitted to the second node, and the voltage of the second node is reset to the voltage of the initialization signal; During the compensation phase, The reset sub-circuit continues to transmit the reference signal received at the reference signal line to the first node; the drive sub-circuit is turned on under the control of the voltage of the first node until the threshold voltage of the drive sub-circuit is stored in the second node, at which point the drive sub-circuit is turned off. During the writing phase, The write sub-circuit transmits the data signal received at the data signal line to the first node; the coupling sub-circuit couples the voltage change of the first node to the second node; the drive sub-circuit is turned on under the control of the first power signal transmitted on the first power signal line, the voltage of the first node, and the voltage of the second node; During the light-emitting phase, the driving sub-circuit is turned on and outputs a driving current; During the modulation phase, The modulation sub-circuit couples the voltage change of the modulation signal transmitted by the modulation signal line to the first node; the coupling sub-circuit couples the voltage change of the first node to the second node; the driving sub-circuit is disconnected under the control of the first power signal transmitted by the first power signal line, the voltage of the first node, and the voltage of the second node. Alternatively, the modulation sub-circuit couples the voltage change of the modulation signal transmitted by the modulation signal line to the second node; the coupling sub-circuit couples the voltage change of the second node to the first node; and the driving sub-circuit is disconnected under the control of the first power signal transmitted by the first power signal line, the voltage of the first node, and the voltage of the second node.

13. A display panel, wherein, include: Substrate; A driving circuit layer is disposed on one side of the substrate, and the driving circuit layer is provided with a plurality of pixel driving circuits as described in any one of claims 1 to 11. A driving element layer is disposed on the side of the driving circuit layer away from the substrate. The driving element layer includes a plurality of driving elements, which are coupled to the pixel driving circuit.

14. The display panel according to claim 13, wherein, The pixel driving circuit includes a coupling capacitor; The driving circuit layer includes: A bottom metal layer is disposed on one side of the substrate, the bottom metal layer including a data signal line pattern; At least one active layer is disposed on the side of the bottom metal layer away from the substrate; A top metal layer disposed on the side of the at least one active layer away from the substrate, the top metal layer comprising the electrode pattern of the coupling capacitor.

15. The display panel according to claim 14, wherein, The pixel driving circuit includes a second transistor and a fourth transistor; the gate of the second transistor is coupled to a second gate signal line, and the gate of the fourth transistor is coupled to a first gate signal line. The driving circuit layer includes: A first active layer is disposed on the side of the bottom metal layer away from the substrate. The first active layer includes an active layer pattern of the second transistor and an active layer pattern of the fourth transistor, and the active layer pattern of the second transistor and the active layer pattern of the fourth transistor are connected. A first gate metal layer is disposed on the side of the first active layer away from the substrate. The first gate metal layer includes a second gate signal line pattern and a first gate signal line pattern. The second gate signal line pattern overlaps with the active layer pattern of the second transistor, and the portion of the second gate signal line pattern that overlaps with the active layer pattern of the second transistor is the gate pattern of the second transistor. The first gate signal line pattern overlaps with the active layer pattern of the fourth transistor, and the portion of the first gate signal line pattern that overlaps with the active layer pattern of the fourth transistor is the gate pattern of the fourth transistor. A first source / drain metal layer is disposed on the side of the first gate metal layer away from the substrate. The first source / drain metal layer includes a first electrode pattern and a second electrode pattern of the second transistor and a first electrode pattern and a second electrode pattern of the fourth transistor. The second electrode pattern of the second transistor is connected to the second electrode pattern of the fourth transistor. The first electrode pattern and the second electrode pattern of the second transistor are connected to the active layer pattern of the second transistor through vias. The first electrode pattern and the second electrode pattern of the fourth transistor are connected to the active layer pattern of the fourth transistor through vias.

16. The display panel according to claim 15, wherein, The underlying metal layer also includes a reference signal line pattern; the first electrode pattern of the fourth transistor is connected to the reference signal line pattern through a via; the first electrode pattern of the second transistor is connected to the data signal line pattern through a via.

17. The display panel according to claim 15 or 16, wherein, The pixel driving circuit includes a first transistor and a third transistor; the first gate of the first transistor is coupled to a reset signal line and a second gate of the first transistor, and the reset signal line includes a first sub-reset signal line and a second sub-reset signal line. The driving circuit layer further includes: A third gate metal layer is disposed on the side of the first source / drain metal layer away from the substrate, the third gate metal layer including a first sub-reset signal line pattern and a second gate pattern of the third transistor; A second active layer is disposed on the side of the third gate metal layer away from the substrate. The second active layer includes the active layer pattern of the first transistor and the active layer pattern of the third transistor, and the active layer pattern of the first transistor and the active layer pattern of the third transistor are connected. The first sub-reset signal line pattern overlaps with the active layer pattern of the first transistor, and the portion of the first sub-reset signal line pattern that overlaps with the active layer pattern of the first transistor serves as the second gate pattern of the first transistor. A fourth gate metal layer is disposed on the side of the second active layer away from the substrate. The fourth gate metal layer includes a second sub-reset signal line pattern and a first gate pattern of the third transistor. The second sub-reset signal line pattern overlaps with the active layer pattern of the first transistor, and the portion of the second sub-reset signal line pattern that overlaps with the active layer pattern of the first transistor serves as the first gate pattern of the first transistor. The first sub-reset signal line pattern and the second sub-reset signal line pattern are connected. A second source / drain metal layer is disposed on the side of the fourth gate metal layer away from the substrate. The second source / drain metal layer includes a first electrode pattern and a second electrode pattern of the first transistor and a first electrode pattern and a second electrode pattern of the third transistor. The second electrode pattern of the first transistor is connected to the second electrode pattern of the third transistor. The first electrode pattern and the second electrode pattern of the first transistor are connected to the active layer pattern of the first transistor through vias. The first electrode pattern and the second electrode pattern of the third transistor are connected to the active layer pattern of the third transistor through vias.

18. The display panel according to claim 17, wherein, The display panel includes a display area and a peripheral area, and the first sub-reset signal line pattern and the second sub-reset signal line pattern are connected in the peripheral area.

19. The display panel according to claim 17 or 18, wherein, The driving circuit layer further includes: A second gate metal layer is disposed between the first source / drain metal layer and the third gate metal layer. The second gate metal layer includes a first power signal line pattern and an initialization signal line pattern. The first power signal line pattern and the initialization signal line pattern are alternately arranged. In two adjacent rows of pixel driving circuits, the active layer pattern of the third transistor in one row is connected to the first power signal line pattern, and the active layer pattern of the first transistor in one row is connected to the initialization signal line pattern. The first electrode patterns of the third transistors in the same column are connected sequentially, and the first electrode patterns of the first transistors in the same column are connected sequentially.

20. The display panel according to claim 19, wherein, The pixel driving circuit also includes a coupling capacitor, which includes a first sub-coupling capacitor, a second sub-coupling capacitor, and a third sub-coupling capacitor. The second gate metal layer also includes the first plate pattern of the first sub-coupled capacitor; The second gate pattern of the third transistor in the third gate metal layer serves as the second plate pattern of the first sub-coupled capacitor. The active layer pattern of the third transistor in the second active layer serves as the first plate pattern of the second sub-coupled capacitor; The first gate pattern of the third transistor in the fourth gate metal layer serves as the second plate pattern of the second sub-coupled capacitor; the second plate pattern of the second sub-coupled capacitor is connected to the first plate pattern of the first sub-coupled capacitor through a via. The first gate pattern of the third transistor in the fourth gate metal layer also serves as the first plate pattern of the third sub-coupled capacitor. The second electrode pattern of the third transistor in the second source-drain metal layer serves as the second electrode plate pattern of the third sub-coupling capacitor.

21. The display panel according to any one of claims 17 to 20, wherein, The pixel driving circuit also includes a modulation capacitor; The first gate pattern of the third transistor in the fourth gate metal layer serves as the first plate pattern of the modulation capacitor. The driving circuit layer further includes a fifth gate metal layer disposed between the fourth gate metal layer and the second source / drain metal layer. The fifth gate metal layer includes a modulation signal line pattern, which overlaps with the first plate pattern of the modulation capacitor. The portion of the modulation signal line pattern that overlaps with the first plate pattern of the modulation capacitor is the second plate pattern of the modulation capacitor.

22. The display panel according to any one of claims 13 to 21, wherein, The driving circuit layer further includes a planarization layer, which includes a plurality of planar vias; The driving element layer includes: An anode extension layer is disposed on the side of the planar layer away from the substrate. The anode extension layer includes a plurality of anode extension patterns. The anode extension pattern includes connected anode corresponding patterns and extension patterns. One of the extension patterns is connected to one of the pixel driving circuits through one of the planar vias. An anode layer disposed on the side of the anode extension layer away from the substrate, the anode layer comprising a plurality of anode patterns, wherein one anode pattern at least partially overlaps with one anode corresponding pattern.

23. The display panel according to claim 22, wherein, The driving element layer also includes: A pixel defining layer is disposed on the side of the anode layer away from the substrate, the pixel defining layer including a plurality of openings, one of the openings exposing one of the anode patterns; A light-emitting layer is disposed on the side of the pixel defining layer away from the substrate, the light-emitting layer including a plurality of light-emitting patterns, and one light-emitting pattern is disposed corresponding to one opening; A cathode layer is disposed on the side of the light-emitting layer away from the substrate.

24. The display panel according to claim 22 or 23, wherein, The projection of the anode corresponding pattern onto the anode layer is located within the boundary of the anode pattern.

25. A display device, wherein, Includes the display panel as described in any one of claims 13 to 24.

Images