Display panel and display apparatus

Abstract

A display panel (100) and a display apparatus (1000), the display panel having a display area (A) and a peripheral area (B) surrounding the display area, and the peripheral area comprising a first bezel area (B1). The display panel comprises a substrate (10), a plurality of sub-pixels (20), a first initialization signal line (VL1), a plurality of first-type binding pins (60) and a first initialization connection line (71). The plurality of sub-pixels are located on the substrate and located in the display area, the sub-pixels comprise pixel circuits (21) and light-emitting devices (22), and the pixel circuits drive the light-emitting devices to emit light. The first initialization signal line is located on the substrate and electrically connected to the plurality of sub-pixels, and at least part of the first initialization signal line is located in the display area. The plurality of first-type binding pins are located on the substrate and located in the first bezel area, the plurality of first-type binding pins comprise first binding pins (61), and the plurality of first-type binding pins are configured to be bound to an external circuit board. The first initialization connection line is located on the substrate and located in the first bezel area, and the first initialization connection line is electrically connected to the first binding pins and the first initialization signal line.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, display devices such as mobile phones, notebook computers or tablet computers are increasingly applied to people's lives. Among them, organic light-emitting diode (OLED) display devices have the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore are widely concerned.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided. The display panel has a display area and a peripheral area surrounding the display area, the peripheral area includes a first bezel area, the first bezel area extends along a first direction, and along a second direction, the first bezel area is located at one side of the display area; the first direction and the second direction intersect; the display panel includes a substrate, a plurality of sub-pixels, a first initialization signal line, a plurality of first type binding pins and a first initialization connection line; the plurality of sub-pixels are located on the substrate and in the display area, the sub-pixel includes a pixel circuit and a light-emitting device, the pixel circuit drives the light-emitting device to emit light; the first initialization signal line is located on the substrate and electrically connected with the plurality of sub-pixels, at least part of the first initialization signal line is located in the display area; the plurality of first type binding pins are located on the substrate and in the first bezel area; the plurality of first type binding pins include a first binding pin; the plurality of first type binding pins are configured to be bound with an external circuit board; the first initialization connection line is located on the substrate and in the first bezel area, the first initialization connection line is electrically connected with the first binding pin and the first initialization signal line.

[0005] In some embodiments, the first initialization signal line includes a plurality of first sub-lines and a plurality of second sub-lines. The plurality of first sub-lines are at least partially located in the display area and extend along the first direction; the plurality of second sub-lines are at least partially located in the display area and extend along the second direction; the plurality of second sub-lines and the plurality of first sub-lines are electrically connected and form a mesh structure; the first initialization connection line includes a first trunk line and at least one first branch line. The first trunk line is located in the first frame area and extends along the first direction; the plurality of second sub-lines extend to the first frame area and are electrically connected with the first trunk line; the at least one first branch line is located in the first frame area and is located on a side of the first trunk line away from the display area; the at least one first branch line is electrically connected with the first trunk line and the first binding pin.

[0006] In some embodiments, the first branch line includes a first wire segment and a plurality of second wire segments. The first wire segment extends along the first direction; the plurality of second wire segments extend along the second direction and are arranged at intervals along the first direction; the plurality of second wire segments are electrically connected with the first wire segment and the first trunk line.

[0007] In some embodiments, the second wire segment includes a first sub-segment and a second sub-segment. The first sub-segment extends along the second direction and is directly connected with the first wire segment; the second sub-segment extends along the second direction and is directly connected with the first trunk line; the second sub-segment is connected with the first sub-segment.

[0008] In some embodiments, the second wire segment is directly connected with the first wire segment.

[0009] In some embodiments, the first initialization connection line includes two first branch lines, and the two first branch lines are respectively located near edges of the display panel on opposite sides along the first direction.

[0010] In some embodiments, the display panel further includes a plurality of second-type binding pins. The plurality of second-type binding pins are located in the first frame area, the plurality of second-type binding pins are located between the first trunk line and the plurality of first-type binding pins, and the two first branch lines are respectively located on a side of the plurality of second-type binding pins close to a boundary of the first frame area; the second-type binding pins are configured to be bound with an external driving chip.

[0011] In some embodiments, the plurality of first type of binding pins further comprises a second binding pin; and the display panel further comprises a second initialization signal and a second initialization connection line. The second initialization signal line is located on the substrate and electrically connected with the plurality of sub-pixels, at least part of the second initialization signal line is located in the display area; and the second initialization connection line is located on the substrate and located in the first frame area, the second initialization connection line is electrically connected with the second binding pin and the second initialization signal line.

[0012] In some embodiments, the second initialization signal line comprises a plurality of third sub-lines and a plurality of fourth sub-lines. The plurality of third sub-lines are at least partially located in the display area and extend along the first direction, and the plurality of fourth sub-lines are at least partially located in the display area and extend along the second direction; the plurality of fourth sub-lines and the plurality of third sub-lines are electrically connected and form a mesh structure; and the second initialization connection line comprises a second trunk line and at least one second branch line. The second trunk line is located in the first frame area and extends along the first direction; the plurality of fourth sub-lines extend to the first frame area and are connected with the second trunk line; the at least one second branch line is located in the first frame area and located on a side of the second trunk line away from the display area; and the at least one second branch line is electrically connected with the second trunk line and the second binding pin.

[0013] In some embodiments, the first initialization connection line comprises a first trunk line; the second trunk line is located on a side of the first trunk line close to the display area, and the second branch line crosses the first trunk line along the second direction and is connected with the second trunk line.

[0014] In some embodiments, the second sub-line crosses the second trunk line along the second direction and is connected with the first trunk line.

[0015] In some embodiments, along the second direction, the second branch line is located on a side of the first branch line close to a boundary of the first frame area.

[0016] In some embodiments, the second branch line comprises a third trace segment and a plurality of fourth trace segments. The third trace segment extends along the first direction; the plurality of fourth trace segments extend along the second direction and are arranged along the first direction at intervals; and the plurality of fourth trace segments are electrically connected with the third trace segment and the second trunk line.

[0017] In some embodiments, the display panel further comprises at least one second frame area extending along the second direction, and located at one side of the display area along the first direction; the plurality of first type of binding pins further comprises a third binding pin; and the display panel further comprises a third initialization signal line and a third initialization connection line. The third initialization signal line is located on the substrate and electrically connected with the plurality of sub-pixels, and at least part of the third initialization signal line is located in the display area; the third initialization connection line is located on the substrate and located at one side of the first initialization connection line close to the boundary of the first frame area; the third initialization connection line is located in the first frame area and extends to the second frame area; and the third initialization connection line is electrically connected with the third binding pin and the third initialization signal line.

[0018] In some embodiments, the third initialization signal line comprises a plurality of fifth sub-lines, and the plurality of fifth sub-lines are at least partially located in the display area and extend along the first direction, and the plurality of fifth sub-lines are spaced apart along the second direction; and the third initialization connection line comprises a fifth wire segment and a plurality of sixth wire segments. The fifth wire segment extends along the second direction and is located in the second frame area; the plurality of sixth wire segments extend along the first direction and are located in the second frame area; the plurality of fifth wire segments are spaced apart along the second direction; and one of the fifth sub-lines is electrically connected with one of the sixth wire segments extending to the second frame area.

[0019] In some embodiments, the display panel further comprises a plurality of gate control signal lines, and the plurality of gate control signal lines comprises a first fan-out segment and a second fan-out segment. The first fan-out segment is located in the first frame area and extends along the second direction, and along the second direction, the first fan-out segment is located at one side of the first initialization connection line close to the boundary of the first frame area; the second fan-out segment is located in the first frame area and extends along the first direction; the second fan-out segment is located at one side of the first fan-out segment away from the display area and is connected with the first fan-out segment; and the first initialization connection line crosses the second fan-out segment along the second direction.

[0020] In some embodiments, the third initialization connection line comprises a seventh wire segment, and the seventh wire segment is located in the first frame area and extends along the second direction; and the seventh wire segment is located between the first fan-out segment and the first initialization connection line.

[0021] In some embodiments, the pixel circuit comprises a first reset transistor, a second reset transistor and a third reset transistor. The control electrode of the first reset transistor is connected with a first reset signal terminal, the first electrode is connected with a first initialization signal terminal, and the second electrode is connected with a first node. The control electrode of the second reset transistor is connected with a second reset signal terminal, the first electrode is connected with a second initialization signal terminal, and the second electrode is connected with a third node. The control electrode of the third reset transistor is connected with a third reset signal terminal, the first electrode is connected with a third initialization signal terminal, and the second electrode is connected with the anode of the light-emitting device. The first initialization signal terminal is connected with a first initialization signal line and is configured to transmit a first initialization signal. The second initialization signal terminal is connected with a second initialization signal line and is configured to transmit a second initialization signal. The third initialization signal terminal is connected with a third initialization signal line and is configured to transmit a third initialization signal.

[0022] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0024] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0025] FIG. 2 is another structural diagram of a display device according to some embodiments;

[0026] FIG. 3 is a structural diagram of a display device comprising a housing and a cover plate according to some embodiments;

[0027] FIG. 4 is a structural diagram of a display panel according to some embodiments;

[0028] FIG. 5 is a sectional view along the section line C-C in FIG. 4;

[0029] FIG. 6 is another structural diagram of a display panel according to some embodiments;

[0030] FIG. 7 is yet another structural diagram of a display panel according to some embodiments;

[0031] FIG. 8 is a partial enlarged view of D in FIG. 7;

[0032] FIG. 9 is a partial enlarged view of E in FIG. 8;

[0033] FIG. 10 is another structural diagram of a display panel according to some embodiments;

[0034] FIG. 11 is a partial enlarged view of F in FIG. 10;

[0035] FIG. 12 is a partial enlarged view of G in FIG. 11;

[0036] FIG. 13 is a structural diagram of a second type of binding pin according to some embodiments;

[0037] FIG. 14 is a partial enlarged view of H in FIG. 7;

[0038] FIG. 15 is a structural diagram of a display panel including a first initialization signal line, a second initialization signal line, and a third initialization signal line according to some embodiments;

[0039] FIG. 16 is another structural diagram of a display panel according to some embodiments;

[0040] FIG. 17 is a structural diagram of a display panel having a main area, a bending area, and a binding area according to some embodiments;

[0041] FIG. 18 is a partial enlarged view of I in FIG. 17;

[0042] FIG. 19 is another structural diagram of a display panel having a main area, a bending area, and a binding area according to some embodiments;

[0043] FIG. 20 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0044] FIG. 21 is a film layer structural diagram of a transistor according to some embodiments;

[0045] FIG. 22 is a film layer structural diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0046] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0047] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples," and the like, mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but that it can not be included in other embodiments or examples. The illustrative appearance of the foregoing terms in various places in the description are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0048] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0049] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0050] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0051] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0052] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] Use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0054] Additionally, use of "based on" means open and inclusive, as the process, step, calculation, or other action based on a stated condition or value can actually be based on additional conditions or values beyond those stated.

[0055] As used herein, "about," "approximately," or "circa" includes the recited value and the mean within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0057] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges when etched due to the fact that the etching process often does not proceed at 90° angles. Thus, the regions illustrated in the figures are schematic and not drawn to scale. As used herein, the term "schematic" means that the drawings are not drawn to scale and are intended to be illustrative only.

[0059] It should be noted that the terms "upper", "lower", "left", "right", and the like used herein are described in the angle shown in the drawings, and should not be understood as limiting the embodiments of the present application. In addition, in the context, it should also be understood that when referring to an element connected to another element "on" or "under", it can be directly connected to another element "on" or "under" or indirectly connected to another element "on" or "under" through an intermediate element.

[0060] The first node, the second node, and the third node described in the embodiments of the present application are not actual components, but are convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to convergence points of relevant electrical connections in a circuit diagram.

[0061] In some embodiments, the control electrode of each transistor adopted by the pixel circuit is the gate of the transistor, the first electrode is one of the source and the drain of the transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present application can be indistinguishable in structure. For example, in the case of a P-type transistor, the first electrode of the transistor is the source and the second electrode of the transistor is the drain; for example, in the case of an N-type transistor, the first electrode of the transistor is the drain and the second electrode of the transistor is the source.

[0062] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays both motion (e.g., video) and still (e.g., still images) and both text and images.

[0063] Exemplarily, the display device 1000 can be any product or component with display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle-mounted display, a flight display, etc.

[0064] In some examples, as shown in FIG. 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in FIG. 1.

[0065] In yet some examples, as shown in FIG. 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in FIG. 2.

[0066] In the following, some embodiments of the present disclosure are illustratively described by taking the display device as a mobile phone as an example, but the embodiments of the present disclosure are not limited thereto, and the display device can also be taken as a watch as long as the same technical idea is applied.

[0067] In some embodiments, as shown in FIG. 3, the display device 1000 includes a display panel 100, a housing 200, and a cover plate 300.

[0068] The display panel 100 has opposite display side 100A and non-display side 100B, the display side 100A refers to a side (the upper side of the display panel 100 in FIG. 3) at which the display panel 100 can emit light, and the non-display side 100B refers to the other side (the lower side of the display panel 100 in FIG. 3) opposite to the display side 100A.

[0069] The type of the display panel 100 described above includes a variety of types, which can be selected and arranged according to actual needs.

[0070] Exemplarily, the display panel 100 can be an organic light-emitting diode (OLED) display panel 100, a quantum dot light-emitting diode (QLED) display panel 100, an active matrix organic light-emitting diode (AMOLED) display panel 100, a liquid crystal display (LCD) display panel 100, a mini / micro light-emitting display (MLED) display panel 100, or the like, which is not specifically limited in the embodiments of the present disclosure.

[0071] As shown in FIG. 3, the shell 200 can be a box-shaped structure with an opening, the display panel 100 can be located in the shell 200, the cover plate 300 is located on the display side of the display panel 100 and at the opening of the shell 200.

[0072] As shown in FIG. 3, the longitudinal section of the shell 200 can be U-shaped, for example, the display panel 100 is located in the shell 200, and the cover plate 300 is located at the opening of the shell 200.

[0073] In some embodiments, as shown in FIG. 4, the display panel 100 has a display area A and a peripheral area B arranged on at least one side of the display area A. In FIG. 4, the peripheral area B is arranged around the display area A as an example. The peripheral area B is a region that does not display images, and the peripheral area B is configured to arrange display driving circuits, such as gate driving circuits and source driving circuits.

[0074] In some embodiments, as shown in FIGS. 4 and 5, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0075] In some embodiments, the substrate 10 can be a flexible substrate 10 or a rigid substrate 10. The material used for the substrate 10 can include a polymer resin or glass. For example, the substrate 10 can be flexible, and the material used for the substrate 10 can include one of a polyethersulfone (PES), a polyarylate (PAR), a polyetherimide (PEI), a polyethylene naphthalate two formic acid glycol ester (PEN), a polyethylene terephthalate (PET), a polyphenyl sulfide granula (PPS), a polyimide (PI), a polycarbonate (PC), and a cellulose acetate propionate (CAP). For example, the substrate 10 can be rigid, and the material used for the substrate 10 can include a glass containing SiO2 as a main component.

[0076] It should be noted that the substrate 10 can be a single-layer structure or a multi-layer structure. For example, when the substrate 10 is a multi-layer structure, the substrate 10 can include a base and a buffer layer disposed on the base. The buffer layer is disposed on the base. The material used for the buffer layer can include an inorganic insulating material such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON), and silicon oxide (SiOx, x>0). The buffer layer is used to provide a good foundation for the thin film when the thin film is made on the substrate 10.

[0077] As shown in FIGS. 4 and 5, a plurality of sub-pixels 20 are located on the substrate 10, and the plurality of sub-pixels 20 are located in the display area A.

[0078] In some examples, the plurality of sub-pixels 20 can include a first sub-pixel having a first color, a second sub-pixel having a second color, and a third sub-pixel having a third color. The first color, the second color, and the third color can be three primary colors. For example, the first color can be red, the second color can be blue, and the third color can be green.

[0079] In some examples, the plurality of sub-pixels 20 can include a first sub-pixel 20 emitting a first color, a second sub-pixel 20 emitting a second color, and a third sub-pixel 20 emitting a third color. The first color, the second color, and the third color can be three primary colors. For example, the first color can be red, the second color can be blue, and the third color can be green.

[0080] As shown in FIG. 6, the plurality of sub-pixels 20 can be arranged in a plurality of rows and a plurality of columns, for example. Each row of sub-pixels 20 can include at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 can include at least two sub-pixels 20 arranged along a second direction Y. The first direction X can intersect the second direction Y, for example, the first direction X can be perpendicular to the second direction Y.

[0081] As shown in FIGS. 5 and 6, the sub-pixel 20 can include a pixel circuit 21 and a light emitting device 22.

[0082] As shown in FIG. 5, the display panel 100 can further include a pixel circuit layer 30 and a light emitting device layer 40 on the substrate 10 in a direction perpendicular to the substrate 10 and away from the substrate 10.

[0083] The pixel circuit layer 30 can include a plurality of pixel circuits 21. Each pixel circuit 21 can include a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C for short).

[0084] The transistors 211 used in the circuit provided by the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as an example.

[0085] As an example, the transistor 211 can be an oxide thin film transistor. The oxide thin film transistor has a high carrier mobility, which can improve the response speed of the transistor 211.

[0086] Alternatively, as an example, the transistor 211 can be an oxide low-temperature polysilicon thin film transistor. The low-temperature polysilicon thin film transistor has a high mobility and fast charging.

[0087] As shown in FIG. 5, the plurality of transistors 211 can include a first type of transistor 201 and a second type of transistor 202. The first type of transistor 201 can be a low-temperature polysilicon thin film transistor, and the second type of transistor 202 can be an oxide thin film transistor. In this way, the low-temperature polysilicon transistor and the oxide transistor can be integrated on one display panel 100, which can reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.

[0088] As shown in FIG. 5, the transistor 211 includes an active part 2111, a source 2112, a drain 2113 and a gate 2114, and the source 2112 and the drain 2113 are in contact with the active part 2111 respectively. The storage capacitor 212 includes a first plate and a second plate arranged oppositely.

[0089] It should be noted that the source 2112 and the drain 2113 can be exchanged, that is, 2112 in FIG. 5 represents the drain and 2113 represents the source.

[0090] The structure of the pixel circuit 21 can include various structures, which can be selected according to actual needs. For example, the structure of the pixel circuit 21 can include a "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structure. Among them, "T" represents the transistor 211, the number before "T" represents the number of transistors 211, and "C" represents the storage capacitor 212, and the number before "C" represents the number of storage capacitors 212.

[0091] In some examples, the plurality of transistors in the pixel circuit 21 can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit 21 can all be P-type transistors or can all be N-type transistors, which can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0092] As shown in FIG. 5, the light emitting device layer 40 includes a plurality of light emitting devices 22. Each light emitting device 22 includes an anode 221, a light emitting functional layer 222 and a cathode 223. The anode 221 can be electrically connected to the source 2112 or the drain 2113 of the plurality of transistors 211 as a driving transistor, for example, and is electrically connected to the drain 2113 of the transistor 211 in FIG. 5. In this way, the pixel circuit 21 can drive the corresponding light emitting device 22 to emit light.

[0093] The material of the anode 221 includes indium tin oxide (English: Indium Tin Oxide, abbreviated: ITO), for example, the anode includes a first sub-layer, a second sub-layer and a third sub-layer arranged in layers, the materials of the first sub-layer and the third sub-layer include silver (Ag), and the material of the second sub-layer includes ITO. The material of the cathode 223 also includes magnesium-aluminum alloy or indium tin oxide.

[0094] The light-emitting functional layer 222 can include only a light-emitting layer, or can further include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transporting layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL) in addition to the light-emitting layer.

[0095] In some embodiments, as shown in FIG. 5, the display panel 100 further includes an encapsulation layer 50 located on a side of the plurality of light-emitting devices 22 away from the substrate 10, and the encapsulation layer 50 is configured to encapsulate the light-emitting devices 22 and improve the service life of the light-emitting devices 22. The encapsulation layer 50 can be an encapsulation film or an encapsulation substrate, and the embodiments of the present disclosure are not limited herein.

[0096] For example, as shown in FIG. 5, the encapsulation layer 50 can include one encapsulation film, or two or more encapsulation films stacked. For example, as shown in FIG. 5, the encapsulation layer 50 includes a first inorganic encapsulation layer 51, a first organic encapsulation layer 52, and a second inorganic encapsulation layer 53 stacked in a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 51 and the second inorganic encapsulation layer 53 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 52 includes a polymer resin, such as polyimide.

[0097] In some embodiments, as shown in FIG. 6, the display panel 100 further includes a plurality of initialization signal lines VL. The initialization signal lines VL are at least partially located in the display area A and connected to the pixel circuits 21 in the plurality of sub-pixels 20. The initialization signal lines VL are configured to transmit an initialization signal. In this way, the initialization signal can be transmitted to the pixel circuits 21 through the initialization signal lines VL, so as to initialize the nodes in the pixel circuits 21, and thus the problem that the electric potential of the residual image of the previous image frame affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display panel 100.

[0098] In some embodiments, the display area A has a shape of any one of a circle, an ellipse, and a rectangle, and the embodiments of the present disclosure are not limited herein.

[0099] In the present text, "substantially circular or elliptical" means that the shape is generally circular or elliptical, but is not limited to a standard circular or elliptical shape. That is, "circular or elliptical" herein includes not only a substantially circular or elliptical shape, but also a shape similar to a circular or elliptical shape.

[0100] In the present text, "substantially rectangular" means that the shape is generally rectangular, but is not limited to a standard rectangular shape. That is, "rectangular" herein includes not only a substantially rectangular shape, but also a shape similar to a rectangular shape. For example, the long side and the short side of the rectangle are curved at each intersection (i.e., at the corners), i.e., the corners are smooth, and the shape is a rounded rectangular shape. Hereinafter, the shape of the display area A shown in FIG. 7 is taken as an example of a substantially rounded rectangular shape.

[0101] As shown in FIG. 7, the peripheral area B can include a first bezel area B1 (a lower bezel area), two second bezel areas B2 (left or right bezel areas), and a third bezel area B3 (an upper bezel area).

[0102] The first bezel area B1 extends along the first direction X and is located at one side of the display area A along the second direction Y. The second bezel area B2 extends along the second direction Y and is located at one side of the display area A along the first direction X. The two second bezel areas B2 are oppositely arranged along the first direction X and are respectively located at opposite sides of the display area A, i.e., one second bezel area B2 is located at the left side of the display area A, and the other second bezel area B2 is located at the right side of the display area A. The third bezel area B3 extends along the first direction X and is located at a side of the display area A away from the first bezel area B1.

[0103] On this basis, as shown in FIG. 7, the peripheral area B further includes four corner areas B4, one corner area B4 being located between two adjacent bezel areas, wherein the shape of the inner side boundary and the outer side boundary of the corner area B4 is an arc (a circular arc). And the two adjacent bezel areas are connected through a corner area B4.

[0104] As shown in FIG. 7, the display panel 100 includes a plurality of first type binding pins 60. The plurality of first type binding pins 60 are located on the substrate 10, and the plurality of first type binding pins 60 are located in the first bezel area B1. The plurality of first type binding pins 60 are used for binding with an external circuit board.

[0105] On this basis, the display panel 100 further comprises a plurality of initialization connection lines 70, the plurality of initialization connection lines 70 are connected with the partial first type binding pins 60 and a plurality of initialization signal lines VL, so that the external circuit board binding can provide an initialization signal to the pixel circuit 21 through the initialization signal line VL, and then initialize the node in the pixel circuit 21. In turn, it can improve the problem that the potential of the last image frame remaining in the node affects the display image of the next image frame, thereby improving the brightness uniformity of the display panel 100.

[0106] In the related art, all the initialization connection lines are extended from the first frame area to the second frame area around the first frame area, and are connected with the initialization signal lines. The extension of all the initialization connection lines from the first frame area to the second frame area around the first frame area through the corner area causes the width of the second frame area and the corner area to be relatively wide, for example, the width of the second frame area is 900 μm. The width of the corner area is 950 μm to 1000 μm.

[0107] In order to solve the above technical problems, as shown in FIG. 7, some embodiments of the present disclosure provide a display panel 100. In the display panel 100, the plurality of first type binding pins 60 comprises a first binding pin 61, and the plurality of initialization signal lines VL comprises a first initialization signal line VL1. The plurality of initialization connection lines 70 comprises a first initialization connection line 71, the first initialization connection line 71 is located on the substrate 10, the first initialization connection line 71 is located in the first frame area B1, and the first initialization connection line 71 is electrically connected with the first binding pin 61 and the first initialization signal line VL1.

[0108] In this way, the first initialization connection line 71 is located in the first frame area B1, and does not need to extend to the second frame area B2 around the corner area B4. In this way, on the one hand, the number of initialization connection lines 70 located in the second frame area B2 and the corner area B4, and the number of connection points for connecting the initialization signal line VL and the initialization connection line 70 in the first frame area B1 can be reduced, thereby the width of the first frame area B1 can be reduced.

[0109] Through experiments, some embodiments of the present disclosure provide that the width of the second frame area B2 along the first direction X is reduced from 900 μm to 860 μm to 880 μm. The distance between the inner side boundary and the outer side boundary of the corner area B4 is reduced from 950 μm to 1000 μm to 890 μm to 960 μm.

[0110] For example, the width of the first frame area B1 along the first direction X is 860 μm, 862 μm, 865 μm, 869 μm, 870 μm, 873 μm, 876 μm, or 880 μm.

[0111] For example, the distance between the inner side boundary and the outer side boundary of the corner area B4 is 890 μm, 895 μm, 900 μm, 910 μm, 916 μm, 924 μm, 930 μm, 935 μm, 942 μm, 948 μm, 950 μm, and 960 μm.

[0112] In some examples, as shown in FIG. 7, the plurality of corner areas B4 includes a first corner area B41 and a second corner area B42. The first corner area B41 is located between the first bezel area B1 and the second bezel area B2, and the second corner area B42 is located between the second bezel area B2 and the third bezel area B3.

[0113] Experiments show that the distance between the inner side boundary and the outer side boundary of the first corner area B41 provided by some embodiments of the present disclosure is reduced from 970 μm to 1000 μm to 920 μm to 960 μm.

[0114] For example, the distance between the inner side boundary and the outer side boundary of the first corner area B41 is 920 μm, 925 μm, 931 μm, 938 μm, 940 μm, 944 μm, 949 μm, 953 μm, or 960 μm.

[0115] Experiments show that the distance between the inner side boundary and the outer side boundary of the second corner area B42 provided by some embodiments of the present disclosure is reduced from 950 μm to 980 μm to 860 μm to 930 μm.

[0116] For example, the distance between the inner side boundary and the outer side boundary of the second corner area B42 is 860 μm, 865 μm, 870 μm, 878 μm, 886 μm, 890 μm, 900 μm, 905 μm, 910 μm, 915 μm, 920 μm, or 930 μm.

[0117] On the other hand, the first initialization connection line 71 is located in the first bezel area B1, does not need to extend to the second bezel area B2 through the corner area B4, and can shorten the length of the first initialization connection line 71, thereby reducing the resistance of the first initialization connection line 71, and further reducing the voltage drop on the first initialization connection line 71. The initialization potential of the node in the pixel circuit 21 is improved, thereby reducing the risk of display panel 100 display unevenness as a three-way screen or at low gray scale. For example, the resistance of the first initialization connection line 71 is less than or equal to 50 Ω.

[0118] In some embodiments, as shown in FIGS. 7 and 8, the first initialization signal line VL1 includes a plurality of first sub-lines VL11 and a plurality of second sub-lines VL12.

[0119] The first sub-lines VL11 are at least partially located in the display area A, extend along the first direction X, and are spaced apart along the second direction Y. The second sub-lines VL12 are at least partially located in the display area A, extend along the second direction Y, and are spaced apart along the first direction X. The second sub-lines VL12 are electrically connected to the first sub-lines VL11 and form a mesh structure. In this way, the power consumption of the display panel 100 can be reduced.

[0120] On this basis, as shown in FIG. 7, the first initialization connection line 71 includes a first trunk line 711 and at least one first branch line 712. For example, the first initialization connection line 71 includes one, two, or three first branch lines 712.

[0121] The first trunk line 711 is located in the first frame area B1 and extends along the first direction X. The second sub-lines VL12 extend to the first frame area B1 and are electrically connected to the first trunk line 711. The at least one first branch line 712 is located in the first frame area B1. The at least one first branch line 712 is located on a side of the first trunk line 711 away from the display area A. The at least one first branch line 712 is electrically connected to the first trunk line 711 and the first binding pin 61.

[0122] In this way, the initialization signal on the first binding pin 61 can be transmitted to the second sub-lines VL12 through the first branch line 712 and the first trunk line 711, and then to the first sub-lines VL11, and further to the pixel circuit 21 in the sub-pixel 20.

[0123] In some embodiments, as shown in FIGS. 8 and 9, the first branch line 712 includes a first wire segment 7121 and a second wire segment 7122.

[0124] The first wire segment 7121 extends along the first direction X. The second wire segments 7122 extend along the second direction Y and are spaced apart along the first direction X. The second wire segments 7122 are electrically connected to the first wire segment 7121 and the first trunk line 711.

[0125] It can be understood that the first branch line 712 also includes other wire segments. For example, the first branch line 712 also includes an eighth wire segment 7123. One end of the eighth wire segment 7123 is connected to the first wire segment 7121, and the other end is connected to the first binding pin 61.

[0126] In some embodiments, as shown in FIG. 8 and FIG. 9, the second trace segment 7122 includes a first sub-segment 71211 and a second sub-segment 71212. The first sub-segment 71211 extends along the second direction Y, and the first sub-segment 71211 is directly connected with the first trace segment 7121. Here, the first sub-segment 71211 being directly connected with the first trace segment 7121 means that the first sub-segment 71211 and the first trace segment 7121 are not connected through other connecting structures (for example, connecting lines and connecting holes), for example, the first sub-segment 71211 and the first trace segment 7121 are an integral structure.

[0127] The second sub-segment 71212 extends along the second direction Y, and the second sub-segment 71212 is directly connected with the first main trace 711, and the second sub-segment 71212 is connected with the first sub-segment 71211. Here, the second sub-segment 71212 being directly connected with the first main trace 711 means that the second sub-segment 71212 and the first main trace 711 are not connected through other connecting structures (for example, connecting lines and connecting holes), for example, the second sub-segment 71212 and the first main trace 711 are an integral structure.

[0128] In other embodiments, as shown in FIG. 10, FIG. 11 and FIG. 12, the second trace segment 7122 is directly connected with the first trace segment 7121. Here, the second trace segment 7122 being directly connected with the first trace segment 7121 means that the second trace segment 7122 and the first trace segment 7121 are not connected through other connecting structures (for example, connecting lines and connecting holes), for example, the second trace segment 7122 and the first trace segment 7121 are an integral structure.

[0129] In some embodiments, as shown in FIG. 7 and FIG. 10, the plurality of first type binding pins 60 includes a plurality of first binding pins 61, for example, the plurality of first type binding pins 60 includes two, three or four first binding pins 61. The first initialization connecting line 71 includes a plurality of first branch lines 712, for example, the first initialization connecting line 71 includes two, three or four first branch lines 712.

[0130] On this basis, as shown in FIG. 7 and FIG. 10, the plurality of first binding pins 61 are symmetrically arranged about the first axis X1. And / or, the plurality of first branch lines 712 are symmetrically arranged about the first axis X1. In this way, the circuit structure can be simplified, the regularity of the circuit trace can be improved, and the preparation cost can be reduced. The first axis X1 extends along the second direction Y and passes through the center of the display area A.

[0131] It can be understood that the plurality of first binding pins 61 can also be arranged asymmetrically about the first axis X1. For example, the number of first binding pins 61 and first branch lines 712 on one side of the first axis X1 is greater than the number of first binding pins 61 and first branch lines 712 on the other side of the first axis X1.

[0132] In some examples, as shown in FIGS. 7 and 10, the first initialization connection line 71 includes two first branch lines 712, and the two first branch lines 712 are located on opposite sides of the edge of the display panel 100 along the first direction X, i.e., the two first branch lines 712 are located on both sides of the first axis X1.

[0133] In some embodiments, as shown in FIGS. 7 and 10, the display panel 100 further includes a plurality of second type binding pins 80. The plurality of second type binding pins 80 are located in the first border area B1, and the plurality of second type binding pins 80 are located between the first trunk line 711 and the plurality of first type binding pins 60. The two first branch lines 712 are respectively located on one side of the plurality of second type binding pins 80 close to the boundary of the first border area B1. Among them, the second type binding pin 80 is configured to be bound with an external driving chip (driving IC) and connected with the first type binding pin 60.

[0134] In some examples, as shown in FIG. 13, the plurality of second type binding pins 80 includes a plurality of fourth binding pins 81 and a plurality of fifth binding pins 82. The plurality of fourth binding pins 81 are located on one side of the plurality of fifth binding pins 82 close to the display area A. The plurality of fourth binding pins 81 are connected with the data line, and the plurality of fifth binding pins 82 are connected with the first type binding pin 60. Exemplarily, the length of the fourth binding pin 81 along the second direction Y is less than the length of the fifth binding pin 82 along the second direction Y.

[0135] Exemplarily, the plurality of fourth binding pins 81 can be arranged in multiple rows and multiple columns, each row of fourth binding pins 81 includes at least two fourth binding pins 81 arranged along the first direction X, and each column of fourth binding pins 81 includes at least two fourth binding pins 81 arranged along the second direction Y. The shape of the middle fourth binding pin 81 is approximately rectangular, and the shape of the edge fourth binding pin 81 is approximately parallelogram and inclined towards the middle. The plurality of fifth binding pins 82 can be arranged in a row, and the shape of the middle fifth binding pin 82 is approximately rectangular, and the shape of the edge fifth binding pin 82 is approximately parallelogram and inclined towards the middle.

[0136] In some embodiments, as shown in FIGS. 7 and 10, the plurality of first type binding pins 60 further includes a plurality of second binding pins 62. The plurality of initialization signal lines VL further includes a second initialization signal line VL2, and the initialization signals transmitted by the first initialization signal line VL1 and the second initialization signal line VL2 are different, for example, the first initialization signal line VL1 transmits a first initialization signal, and the second initialization signal line VL2 transmits a second initialization signal. The plurality of initialization connection lines 70 further includes a second initialization connection line 72, and the second initialization connection line 72 is located in the first border area B1. The second initialization connection line 72 is electrically connected with the second binding pin 62 and the second initialization signal line VL2.

[0137] In this way, the second initialization connection line 72 is located in the first frame area B1, and does not need to extend to the second frame area B2 through the corner area B4. In this way, the number of initialization connection lines 70 located in the second frame area B2 and the corner area B4 can be further reduced, and the number of connection points for connecting the initialization signal line VL and the initialization connection line 70 in the first frame area B1 can be reduced, so that the width of the first frame area B1 can be reduced.

[0138] In some embodiments, as shown in FIGS. 7 and 10, the second initialization signal line VL2 includes a plurality of third sub-lines VL21 and a plurality of fourth sub-lines VL22.

[0139] The plurality of third sub-lines VL21 are located in at least part of the display area A, the third sub-lines VL21 extend along the first direction X, and the plurality of third sub-lines VL21 are spaced apart along the second direction Y. The plurality of fourth sub-lines VL22 are located in at least part of the display area A, the fourth sub-lines VL22 extend along the second direction Y, and the plurality of fourth sub-lines VL22 are spaced apart along the first direction X. The plurality of fourth sub-lines VL22 and the plurality of third sub-lines VL21 are electrically connected and form a mesh structure. In this way, the power consumption of the display panel 100 can be reduced.

[0140] On this basis, as shown in FIGS. 7 and 10, the second initialization connection line 72 includes a second trunk line 721 and a second branch line 722.

[0141] The second trunk line 721 is located in the first frame area B1 and extends along the first direction X, and the plurality of fourth sub-lines VL22 extend to the first frame area B1 and are electrically connected to the second trunk line 721. At least one second branch line 722 is located in the first frame area B1, the at least one second branch line 722 is located on a side of the second trunk line 721 away from the display area A, and the at least one second branch line 722 is electrically connected to the second trunk line 721 and the second binding pin 62.

[0142] In this way, the initialization signal on the second binding pin 62 can be transmitted to the fourth sub-line VL22 through the second branch line 722 and the second trunk line 721, and then transmitted to the plurality of third sub-lines VL21, and then transmitted to the pixel circuit 21 of the sub-pixel 20.

[0143] The positional relationship between the first trunk line 711 and the second trunk line 721 is described below.

[0144] In some embodiments, as shown in FIG. 7, the second trunk line 721 is located on the side of the first trunk line 711 close to the display area A. At this time, the second branch line 722 is connected to the first trunk line 711 and the second trunk line 721 across the first trunk line 711 in the second direction Y, and the second sub-line VL12 is connected to the first trunk line 711 and the second trunk line 721 across the second trunk line 721, and the second branch line 722 is located on the side of the first branch line 712 close to the boundary of the first frame area B1.

[0145] In some other embodiments, as shown in FIG. 10, the second trunk line 721 is located on the side of the first trunk line 711 away from the display area A. At this time, the first branch line 712 is connected to the first trunk line 711 and the second trunk line 721 across the second trunk line 721 in the second direction Y, and the fourth sub-line VL22 is connected to the first trunk line 711 and the second trunk line 721 across the first trunk line 711, and the second branch line 722 is located on the side of the first branch line 712 close to the boundary of the first frame area B1.

[0146] In some embodiments, as shown in FIGS. 8 and 11, the second branch line 722 includes a third wire segment 7221 and a plurality of fourth wire segments 7222. The third wire segment 7221 extends in the first direction X. The plurality of fourth wire segments 7222 extend in the second direction Y and are arranged at intervals in the first direction X. The plurality of fourth wire segments 7222 are electrically connected to the third wire segment 7221 and the second trunk line 721.

[0147] For example, the second trunk line 721 is located on the side of the first trunk line 711 close to the display area A, one end of the fourth wire segment 7222 is connected to the third wire segment 7221, and the other end is connected to the second trunk line 721 across the first trunk line 711.

[0148] It can be understood that the second branch line 722 also includes other wire segments. For example, the second branch line 722 also includes a ninth wire segment 7223, one end of the ninth wire segment 7223 is connected to the third wire segment 7221, and the other end is connected to the second binding pin 62.

[0149] In some embodiments, as shown in FIGS. 8 and 9, in the case where the second trunk line 721 is located on the side of the first trunk line 711 close to the display area A, the fourth wire segment 7222 is directly connected to the third wire segment 7221. Among them, the fourth wire segment 7222 is directly connected to the third wire segment 7221, which means that the fourth wire segment 7222 and the third wire segment 7221 are not connected through other connecting structures (such as connecting lines and connecting holes), for example: the fourth wire segment 7222 and the third wire segment 7221 are an integral structure.

[0150] In some embodiments, as shown in FIG. 11 and FIG. 12, when the second trunk line 721 is located on the side of the first trunk line 711 away from the display area A, the fourth wire segment 7222 includes a third sub-segment 72221 and a fourth sub-segment 72222. The third sub-segment 72221 extends along the second direction Y, and the third sub-segment 72221 is directly connected to the third wire segment 7221. Here, the third sub-segment 72221 being directly connected to the third wire segment 7221 means that the third sub-segment 72221 and the third wire segment 7221 are not connected through other connecting structures (for example, connecting lines and connecting holes), for example: the third sub-segment 72221 and the third wire segment 7221 are an integral structure.

[0151] The fourth sub-segment 72222 extends along the second direction Y, and the fourth sub-segment 72222 is directly connected to the second trunk line 721. The fourth sub-segment 72222 is connected to the third sub-segment 72221. Here, the fourth sub-segment 72222 being directly connected to the second trunk line 721 means that the fourth sub-segment 72222 and the second trunk line 721 are not connected through other connecting structures (for example, connecting lines and connecting holes), for example: the fourth sub-segment 72222 and the second trunk line 721 are an integral structure.

[0152] In some embodiments, as shown in FIG. 7 and FIG. 10, the plurality of first type binding pins 60 includes a plurality of second binding pins 62, for example, the plurality of first type binding pins 60 includes two, three or four second binding pins 62. The second initialization connecting line 72 includes a plurality of second branch lines 722, for example, the second initialization connecting line 72 includes two, three or four second branch lines 722.

[0153] On this basis, as shown in FIG. 7 and FIG. 10, the plurality of second binding pins 62 are symmetrically arranged about the first axis X1. And / or, the plurality of second branch lines 722 are symmetrically arranged about the first axis X1. In this way, the circuit structure can be simplified, the regularity of the circuit wire can be improved, and the preparation cost can be reduced.

[0154] It can be understood that the plurality of second binding pins 62 can also be arranged asymmetrically about the first axis X1. For example, the number of second binding pins 62 and second branch lines 722 located on one side of the first axis X1 is greater than the number of second binding pins 62 and second branch lines 722 located on the other side of the first axis X1.

[0155] In some examples, as shown in FIG. 7 and FIG. 10, the second initialization connecting line 72 includes two second branch lines 722, and the two second branch lines 722 are respectively close to the edges of the display panel 100 along the first direction X on opposite sides. That is, the two second branch lines 722 are located on opposite sides of the first axis X1.

[0156] In some embodiments, as shown in FIG. 7 and FIG. 10, the plurality of first type of binding pins 60 further comprises a third binding pin 63. The initialization signal lines VL further comprises a third initialization signal line VL3. The third initialization signal line VL3 and the first initialization signal line VL1 transmit different signals, for example, the third initialization signal line VL3 transmits a third initialization signal, and the first initialization signal line VL1 transmits a first initialization signal. The plurality of initialization connection lines 70 further comprises a third initialization connection line 73.

[0157] The third initialization connection line 73 is located in the first border area B1 and extends to the second border area B2. The third initialization connection line 73 is electrically connected with the third binding pin 63 and the third initialization signal line VL3. At this time, the resistance of the third initialization connection line 73 is greater than 50Ω, for example, the resistance of the third initialization connection line 73 is 55Ω, 60Ω, 66Ω, 70Ω, 74Ω, 80Ω or 90Ω.

[0158] In some embodiments, as shown in FIG. 7 and FIG. 10, the third initialization signal line VL3 comprises a plurality of fifth sub-lines VL31. The plurality of fifth sub-lines VL31 is at least partially located in the display area A. The plurality of fifth sub-lines VL31 extends along the first direction X and is spaced apart along the second direction Y.

[0159] On this basis, as shown in FIG. 14, the third initialization connection line 73 comprises a fifth wire segment 731 and a plurality of sixth wire segments 732. The fifth wire segment 731 extends along the second direction Y and is located in the second border area B2. The plurality of sixth wire segments 732 is located in the second border area B2 and extends along the first direction X. Each fifth sub-line VL31 extending to the second border area B2 is electrically connected with a sixth wire segment 732.

[0160] In other embodiments, as shown in FIG. 15 (in FIG. 15, the black small blocks represent the switching holes), on the basis that the third initialization signal line VL3 comprises a plurality of fifth sub-lines VL31, the third initialization signal line VL3 can further comprise a plurality of sixth sub-lines VL32. The plurality of sixth sub-lines VL32 extends along the second direction Y and is spaced apart along the first direction X. Each sixth sub-line VL32 is electrically connected with the plurality of fifth sub-lines VL31 and is in a mesh structure. In this way, the power consumption of the display panel 100 can be further reduced.

[0161] It can be understood that the third initialization connection line 73 further comprises other wire segments. For example, the third initialization connection line 73 further comprises a tenth wire segment 733 (as shown in FIG. 10). The tenth wire segment 733 extends from the first border area B1 to the second border area B2. One end of the tenth wire segment 733 is connected with the fifth wire segment 731, and the other end is connected with the third binding pin 63.

[0162] In some embodiments, as shown in FIG. 7 and FIG. 10, the plurality of first type of binding pins 60 comprises a plurality of third binding pins 63, for example, the plurality of first type of binding pins 60 comprises two, three or four third binding pins 63. The plurality of initialization connection lines 70 further comprises a plurality of third initialization connection lines 73. For example, the plurality of initialization connection lines 70 further comprises two, three or four third initialization connection lines 73.

[0163] On this basis, as shown in FIG. 7 and FIG. 10, the plurality of third binding pins 63 are symmetrically arranged about the first axis X1. And / or, the plurality of third initialization connection lines 73 are symmetrically arranged about the first axis X1. In this way, the circuit structure can be simplified, the regularity of the circuit layout can be improved, and the manufacturing cost can be reduced.

[0164] It can be understood that the plurality of third binding pins 63 and the plurality of third initialization connection lines 73 can also be arranged asymmetrically about the first axis X1. For example, the number of third binding pins 63 and third initialization connection lines 73 located on one side of the first axis X1 is greater than the number of third binding pins 63 and third initialization connection lines 73 located on the other side of the first axis X1.

[0165] In other embodiments, as shown in FIG. 16, the third initialization connection line 73 is located in the first frame area B1, and the third initialization connection line 73 is electrically connected with the third binding pin 63 and the third initialization signal line VL3.

[0166] In this way, the third initialization connection line 73 is located in the first frame area B1, and does not need to extend to the second frame area B2 through the corner area B4. In this way, the number of initialization connection lines 70 located in the second frame area B2 and the corner area B4, and the number of connection points of the initialization signal line VL and the initialization connection line 70 located in the second frame area B2 can be further reduced, so that the width of the second frame area B2 can be reduced.

[0167] In some embodiments, as shown in FIG. 16, the third initialization signal line VL3 comprises a plurality of fifth sub-lines VL31 and a plurality of sixth sub-lines VL32.

[0168] Among them, the plurality of fifth sub-lines VL31 are at least partially located in the display area A, the fifth sub-line VL31 extends along the first direction X, and the plurality of fifth sub-lines VL31 are arranged at intervals along the second direction Y. The plurality of sixth sub-lines VL32 are at least partially located in the display area A, the sixth sub-line VL32 extends along the second direction Y, and the plurality of sixth sub-lines VL32 are arranged at intervals along the first direction X. The plurality of sixth sub-lines VL32 and the plurality of fifth sub-lines VL31 are electrically connected and form a mesh structure. This is advantageous in reducing the power consumption of the display panel 100.

[0169] On this basis, as shown in FIG. 16, the third initialization connection line 73 includes a third trunk line 7301 and a third branch line 7302.

[0170] The third trunk line 7301 is located in the first frame area B1 and extends along the first direction X, and a plurality of fifth sub-lines VL31 extend to the first frame area B1 and are electrically connected to the third trunk line 7301. At least one third branch line 7302 is located in the first frame area B1, and the at least one third branch line 7302 is located on a side of the third trunk line 7301 away from the display area A, and the at least one third branch line 7302 is electrically connected to the third trunk line 7301 and the third binding pin 63.

[0171] The positional relationship between the first trunk line 711 and the third trunk line 7301 is exemplified as follows.

[0172] In some embodiments, as shown in FIG. 16, the third trunk line 7301 is located on a side of the first trunk line 711 close to the display area A. At this time, the third branch line 7302 is connected to the third trunk line 7301 across the first trunk line 711 along the second direction Y, the second sub-line VL12 is connected to the first trunk line 711 across the third trunk line 7301 and the second trunk line 721, and the third branch line 7302 is located on a side of the first branch line 712 close to the boundary of the first frame area B1.

[0173] In another embodiment, the third trunk line 7301 is located on a side of the first trunk line 711 away from the display area A. At this time, the first branch line 712 is connected to the first trunk line 711 across the third trunk line 7301 along the second direction Y, the sixth sub-line VL32 is connected to the third trunk line 7301 across the first trunk line 711, and the third branch line 7302 is located on a side of the first branch line 712 close to the boundary of the first frame area B1.

[0174] In some embodiments, as shown in FIG. 16, the plurality of first-type binding pins 60 include a plurality of third binding pins 63, for example, the plurality of first-type binding pins 60 include two, three or four third binding pins 63. The third initialization connection line 73 includes a plurality of third branch lines 7302, for example, the third initialization connection line 73 includes two, three or four third branch lines 7302.

[0175] On this basis, as shown in FIG. 16, the plurality of third binding pins 63 are symmetrically arranged about the first axis X1. And / or, the plurality of third branch lines 7302 are symmetrically arranged about the first axis X1. In this way, the circuit structure can be simplified, the regularity of the circuit layout can be improved, and the manufacturing cost can be reduced.

[0176] It can be understood that the plurality of third binding pins 63 can also be arranged asymmetrically about the first axis X1. For example, the number of third binding pins 63 and third branch lines 7302 located on one side of the first axis X1 is greater than the number of third binding pins 63 and third branch lines 7302 located on the other side of the first axis X1.

[0177] In some examples, as shown in FIG. 16, the third initialization connection line 73 includes two third branch lines 7302, which are located near the edges of the display panel 100 on opposite sides in the first direction X. That is, the two third branch lines 7302 are located on opposite sides of the first axis X1.

[0178] As shown in FIG. 16, in the case where the display panel 100 further includes a plurality of second type binding pins 80, the two first branch lines 712 are located on one side of the boundary of the first frame area B1.

[0179] In some embodiments, as shown in FIG. 17, the display panel 100 further includes a gate drive circuit 90 and a plurality of gate control signal lines 110.

[0180] The gate drive circuit 90 is located on the substrate 10, and the gate drive circuit 90 is located in the first frame area B1 and the corner area B4.

[0181] The gate control signal lines 110 are located on the substrate 10 and connected to the gate drive circuit 90. The gate control signal lines 110 include a first fan-out segment 111 and a second fan-out segment 112. The first fan-out segment 111 is located in the first frame area B1 and extends in the second direction Y. At this time, the first fan-out segment 111 is located on one side of the first initialization connection line 71 away from the display area A.

[0182] The second fan-out segment 112 is located in the first frame area B1 and extends in the first direction X. The second fan-out segment 112 is located on one side of the first fan-out segment 111 away from the display area A and is connected to the first fan-out segment 111. At this time, the first initialization connection line 71 crosses the second fan-out segment 112 in the second direction Y.

[0183] It can be understood that, as shown in FIGS. 17 and 18, the gate control signal lines 110 further include a gate connection segment 113, the gate connection segment 113 extends from the first frame area B1 to the corner area B4, one end of the gate connection segment 113 is connected to the first fan-out segment 111, and the other end of the gate connection segment 113 is connected to the gate drive circuit 90.

[0184] In some embodiments, as shown in FIG. 17, the third initialization connection line 73 further includes a seventh wire segment 734, which is located in the first bezel area B1 and extends along the second direction Y. That is, the part of the tenth wire segment 734 located in the first bezel area B1 and extending along the second direction Y constitutes the seventh wire segment 734, i.e., the seventh wire segment 734 is a part of the tenth wire segment 733.

[0185] The positional relationship between the seventh wire segment 734, the first initialization connection line 71, the first fan-out segment 111 and the second fan-out segment 112 is exemplified as follows.

[0186] In some embodiments, as shown in FIGS. 17 and 18, the seventh wire segment 734 is located between the first fan-out segment 111 and the first initialization connection line 71 and crosses the second fan-out segment 112 along the second direction Y.

[0187] In some other embodiments, as shown in FIG. 19, the seventh wire segment 734 is located on the side of the first fan-out segment 111 away from the first initialization connection line 71.

[0188] In some embodiments, as shown in FIGS. 20, 21 and 22, taking the pixel circuit 21 with an 8T1C structure as an example, the pixel circuit 21 includes a first reset transistor T1, a second reset transistor T4 and a third reset transistor T7.

[0189] The control electrode of the first reset transistor T1 is connected with a first reset signal terminal Reset1 (e.g., Reset_P), the first electrode is connected with a first initialization signal terminal Vinit1, and the second electrode is connected with a first node N1. The control electrode of the second reset transistor T4 is connected with a second reset signal terminal Reset2 (e.g., Reset_H), the first electrode is connected with a second initialization signal terminal Vinit2, and the second electrode is connected with a third node N3. The control electrode of the third reset transistor T7 is connected with a third reset signal terminal Reset3 (e.g., Reset_N), the first electrode is connected with a third initialization signal terminal Vinit3, and the second electrode is connected with the anode of the light emitting device 22.

[0190] In some embodiments, the signals received by the second reset signal terminal Reset2 and the third reset signal terminal Reset3 are the same. In this way, the control electrode of the third reset transistor T7 and the control electrode of the second reset transistor T4 can be controlled through the second reset signal terminal RESET2, so that the anode of the light emitting device 22 is initialized at the same time in the process of initializing the third node N3, simplifying the circuit structure.

[0191] It can be understood that the pixel circuit 21 further comprises a compensation transistor T2, a data writing transistor T3, a first light emitting transistor T5, a second light emitting transistor T6, a driving transistor T8 and a storage capacitor 212.

[0192] As shown in FIG. 20, the control electrode of the compensation transistor T2 is connected with the first scan signal terminal Gate 1 (Gate N), the first electrode is connected with the first node N1, and the second electrode is connected with the second node N2. The control electrode of the data writing transistor T3 is connected with the second scan signal terminal Gate 2 (Gate_P), the first electrode is connected with the data writing signal terminal Data, and the second electrode is connected with the third node N3. The control electrode of the first light emitting transistor T5 is connected with the light emitting enable signal terminal EM, the first electrode is connected with the first power voltage signal terminal VDD, and the second electrode is connected with the third node N3. The control electrode of the second light emitting transistor T6 is connected with the light emitting enable signal terminal EM, the first electrode is connected with the first node N1, and the second electrode is connected with the anode of the light emitting device 22. The control electrode of the driving transistor T8 is connected with the second node N2, the first electrode is connected with the third node N3, and the second electrode is connected with the first node N1. The first electrode of the storage capacitor 212 is connected with the second node N2, and the second electrode plate is connected with the first power voltage terminal VDD.

[0193] On this basis, as shown in FIG. 20, the cathode of the light emitting device 22 is coupled with the second voltage signal terminal VSS. Among them, the level output by the second voltage signal terminal VSS is lower than the high level output by the first voltage signal terminal VDD.

[0194] As shown in FIG. 20, the first reset transistor T1, the data writing transistor T3, the second reset transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the third reset transistor T7 and the driving transistor T8 are P-type transistors, and the compensation transistor T2 is an N-type transistor.

[0195] It should be noted that the present disclosure is not limited thereto. For example, all the transistors in the circuit provided by the embodiments of the present disclosure can also adopt P-type transistors or N-type transistors, as long as the electrodes of the selected type of transistors are connected with the corresponding electrodes of the corresponding transistors in the embodiments of the present disclosure, and the corresponding high voltage or low voltage is provided by the corresponding voltage terminal.

[0196] In some embodiments, as shown in FIG. 6, the embodiments of the present disclosure will be exemplarily described below by taking the arrangement of all the pixel circuits 21 as multiple rows and multiple columns as an example, but the embodiments of the present disclosure are not limited thereto. Moreover, the multiple pixel circuits 21 arranged along the first direction X are referred to as a row of pixel circuits 21, and the multiple pixel circuits 21 arranged along the second direction Y are referred to as a column of pixel circuits 21.

[0197] As shown in FIG. 6, the display panel 100 further includes a plurality of gate lines, a plurality of data lines DL, and a plurality of first power signal lines VDL.

[0198] Each of the gate lines extends substantially along the first direction X and is configured to transmit any one of a scan signal Gate, a reset signal RESET, and an emission control signal EM. That is, the plurality of gate lines includes a scan signal line GL, a reset signal line RL, and an emission control signal line EML.

[0199] In this context, "the gate line extends substantially along the first direction X" means that the running direction of the gate line as a whole is along the first direction X, but is not limited to "the gate line extends strictly along the first direction X at each position thereof. That is, "extends along the first direction X" herein includes not only a "gate line that extends strictly along the first direction X at each position thereof, but also a "gate line that has a locally curved section to avoid interference with other structures.

[0200] Exemplarily, as shown in FIG. 21, the plurality of gate lines includes a first scan signal line GL1, a second scan signal line GL2, a first reset signal line RL1, a second reset signal line RL2, a third reset signal line RL3, and an emission control signal line EML.

[0201] The first scan signal line GL1 is configured to transmit a first scan signal, and one first scan signal line GL1 may, for example, be connected to the first scan signal terminal Gate 1 of one row of pixel circuits 21. The orthogonal projection of the first scan signal line GL1 on the substrate 10 overlaps the orthogonal projection of the active portion of the compensation transistor T2 on the substrate 10, and the portion of the first scan signal line GL1 that coincides with the active portion of the compensation transistor T2 forms the gate of the compensation transistor T2.

[0202] The second scan signal line GL2 is configured to transmit a second scan signal, and one second scan signal line GL2 may, for example, be connected to the second scan signal terminal Gate 2 of one row of pixel circuits 21. The orthogonal projection of the second scan signal line GL2 on the substrate 10 overlaps the orthogonal projection of the active portion of the data write transistor T3 on the substrate 10, and the portion of the second scan signal line GL2 that coincides with the active portion of the data write transistor T3 forms the gate of the data write transistor T3.

[0203] The first reset signal line RL1 is configured to transmit a first reset signal, and one first reset signal line RL1 may, for example, be connected to the first reset signal terminal RESET1 of one row of pixel circuits 21. The orthogonal projection of the first reset signal line RL1 on the substrate 10 overlaps the orthogonal projection of the active portion of the first reset transistor T1 on the substrate 10, and the portion of the first reset signal line RL1 that coincides with the active portion of the first reset transistor T1 forms the gate of the first reset transistor T1.

[0204] The second reset signal line RL2 is configured to transmit a second reset signal. One second reset signal line RL2 may be connected to the second reset signal terminal RESET2 of one row of pixel circuits 21, for example. The orthogonal projection of the second reset signal line RL2 on the substrate 10 overlaps the orthogonal projection of the active portion of the second reset transistor T4 on the substrate 10, and the portion of the second reset signal line RL2 that coincides with the active portion of the second reset transistor T4 forms the gate of the second reset transistor T4.

[0205] The third reset signal line RL3 is configured to transmit a third reset signal. One third reset signal line RL3 may be connected to the third reset signal terminal RESET3 of one row of pixel circuits 21, for example. The orthogonal projection of the third reset signal line RL3 on the substrate 10 overlaps the orthogonal projection of the active portion of the third reset transistor T7 on the substrate 10, and the portion of the third reset signal line RL3 that coincides with the active portion of the third reset transistor T7 forms the gate of the third reset transistor T7.

[0206] Exemplarily, as shown in Fig. 21, the second reset signal line RL2 and the third reset signal line RL3 are the same gate line.

[0207] The light emission control signal line EML is configured to transmit a light emission control signal. One light emission control signal line EML may be connected to the light emission control signal terminal EM of one row of pixel circuits 21, for example. The orthogonal projection of the light emission control signal line EML on the substrate 10 overlaps the orthogonal projection of the active portion of the first light emission transistor T5 on the substrate 10 and the orthogonal projection of the active portion of the second light emission transistor T6 on the substrate 10. The portion of the light emission control signal line EML that coincides with the active portion of the first light emission transistor T5 forms the gate of the first light emission transistor T5, and the portion of the light emission control signal line EML that coincides with the active portion of the second light emission transistor T6 forms the gate of the second light emission transistor T6.

[0208] As shown in Fig. 6, the data line DL extends substantially along the second direction Y and is configured to transmit a data signal. One data line DL may be connected to the data signal terminal Data of one column of pixel circuits 21, for example.

[0209] As shown in Fig. 6, the first power supply signal line VDL extends substantially along the second direction Y and is configured to transmit a first power supply potential signal. One first power supply signal line VDL may be connected to the first voltage signal terminal VDD of one column of pixel circuits 21, for example.

[0210] The following describes the film layer structure included in the display panel 100. In some embodiments, as shown in FIG. 22, the display panel 100 has the following structure in the direction perpendicular to the substrate 10 and away from the substrate 10: the display panel 100 further includes a low-temperature polysilicon semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, an oxide semiconductor layer ACT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2, which are arranged in a stack. The low-temperature polysilicon semiconductor layer ACT1 includes the active layer patterns of the first reset transistor T1, the data writing transistor T3, the second reset transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the third reset transistor T7, and the driving transistor T8. The first gate conductive layer GT1 includes the gates of the first reset transistor T1, the compensation transistor T2, the data writing transistor T3, the second reset transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the third reset transistor T7, and the driving transistor T8. The oxide semiconductor layer ACT2 includes the active layer pattern of the compensation transistor T2, and the third gate conductive layer GT3 includes the gate of the compensation transistor T2. Among them, the gate of the compensation transistor T2 included in the first gate conductive layer GT1 is the bottom gate of the compensation transistor T2, and the gate of the compensation transistor T2 included in the third gate conductive layer GT3 is the top gate of the compensation transistor T2, i.e., the compensation transistor T2 is a double-gate structure transistor.

[0211] The following describes the film layer in which the first scan signal line GL1, the second scan signal line GL2, the first reset signal line RL1, the second reset signal line RL2, the third reset signal line RL3, the light-emitting signal line EML, the first initialization signal line VL1, the second initialization signal line VL2, and the third initialization signal line VL3 are located.

[0212] As shown in FIG. 21, the second scan signal line GL2, the first reset signal line RL1, the second reset signal line RL2, the third reset signal line RL3, and the light-emitting signal line EML are located in the first gate conductive layer GT1. The first scan signal line GL1 is located in the third gate conductive layer GT3. As shown in FIG. 15, the first sub-line VL11, the third sub-line VL21, and the fifth sub-line VL31 are located in the third gate conductive layer GT3. The second sub-line VL12, the fourth sub-line VL22, and the sixth sub-line VL32 are located in the first source-drain conductive layer SD1.

[0213] In some embodiments, as shown in FIG. 17, the display panel 100 is a flexible display panel 100, and the display panel 100 has a main body area 101, a binding area 102, and a bending area 103 located between the main body area 101 and the binding area 102.

[0214] In some embodiments, as shown in FIG. 17, the main body area 101 can include a portion of the display panel 100 for displaying images. That is, the main body area 101 can include a display area A. As shown in FIG. 17, the main body area 101 can also include a partial area of the peripheral area B. For example, the main body area 101 can also include a portion of the first bezel area B1 and the second bezel area B2.

[0215] In some embodiments, as shown in FIG. 17, the main body area 101 can include a portion of the display panel 100 for displaying images. That is, the main body area 101 can include a display area A. As shown in FIG. 17, the main body area 101 can also include a partial area of the peripheral area B. For example, the main body area 101 can also include a portion of the first bezel area B1 and the second bezel area B2.

[0216] By the bending process, the display panel 100 located in the bending area can be bent along the bending axis in the first direction X towards the non-display side of the display panel 100 located in the main body area 101, so that the display panel 100 located in the binding area 102 is bent to the non-display side of the display panel 100 located in the main body area 101, thereby reducing the bezel of the display device 1000 (as shown in FIG. 1). It should be noted that the bending axis is not an actual structure existing in the display panel 100, but a concept proposed only for the purpose of explaining the bending process of the display panel 100.

[0217] It should be noted that the bending radius of the display panel 100 located in the bending area can be 0.1mm-0.5mm; for example, the bending radius of the display panel 100 located in the bending area can be any one of 0.1mm, 0.2mm, 0.3mm, 0.35mm, 0.4mm and 0.5mm.

[0218] It should be understood that the smaller the bending radius of the display panel 100 located in the bending area, the narrower the bezel of the display device 1000 corresponding to the display panel 100 located in the bending area (such as the lower bezel in FIG. 1) can be designed, which is more conducive to the narrow bezel design of the display device 1000. For example, the bending radius of the display panel 100 located in the bending area can be 0.1mm-0.2mm, for example, the bending radius of the display panel 100 located in the bending area can be any one of 0.12mm, 0.15mm and 0.18mm, so that the bezel of the display device 1000 corresponding to the display panel 100 located in the bending area (such as the lower bezel in FIG. 1) can be made narrower.

[0219] On this basis, the following illustrates the film layer in which the first initialization connection line 71 is located.

[0220] As shown in FIG. 8, FIG. 9 and FIG. 17, in the case that the second sub-segment 71212 is directly connected to the first trunk line 711, the first trunk line 711 and the second sub-segment 71212 are both located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the main body region 101 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2. The portion of the first branch line 712 located in the bending region 103 is located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the binding region 102 and between the plurality of first type binding pins 60 and the second fan-out segment 112 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2, and the remaining portion is located in the first source-drain conductive layer SD1.

[0221] As shown in FIG. 11 and FIG. 12 and FIG. 17, in the case that the second sub-segment 71212 is directly connected to the first trunk line 711, the first trunk line 711 and the second sub-segment 71212 are both located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the main body region 101 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2. The portion of the first branch line 712 located in the bending region 103 is located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the binding region 102 and between the plurality of first type binding pins 60 and the second fan-out segment 112 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2, and the remaining portion is located in the first source-drain conductive layer SD1.

[0222] The following illustrates the film layers in which the second initialization connection line 72 is located.

[0223] As shown in FIG. 11 and FIG. 12 and FIG. 17, in the case that the second sub-segment 71212 is directly connected to the first trunk line 711, the first trunk line 711 and the second sub-segment 71212 are both located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the main body region 101 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2. The portion of the first branch line 712 located in the bending region 103 is located in the first source-drain conductive layer SD1. The portion of the first branch line 712 located in the binding region 102 and between the plurality of first type binding pins 60 and the second fan-out segment 112 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2, and the remaining portion is located in the first source-drain conductive layer SD1.

[0224] As shown in FIG. 8, FIG. 9 and FIG. 17, in the case that the third trace segment 7221 and the fourth trace segment 7222 are directly connected, the second trunk line 721 is located in the first source-drain conductive layer SD1. The third trace segment 7221 and the fourth trace segment 7222 are both located in the first gate conductive layer GT1 and the second gate conductive layer GT2. The second branch line 722 is located in the part of the main body region 101 which is located in the first gate conductive layer GT1 and the second gate conductive layer GT2. The part of the second branch line 722 which is located in the bending region 103 is located in the first source-drain conductive layer SD1. The segment of the second branch line 722 which is located in the binding region 102 is located in the first gate conductive layer GT1 and the second gate conductive layer GT2, and the remaining part is located in the first source-drain conductive layer SD1.

[0225] In the description of the present disclosure, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0226] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel having a display area and a peripheral area surrounding the display area, the peripheral area including a first border area extending along a first direction and along a second direction, the first border area being located on one side of the display area; The first direction and the second direction intersect; The display panel includes: Substrate; Multiple sub-pixels are located on the substrate and in the display area. Each sub-pixel includes a pixel circuit and a light-emitting device. The pixel circuit is configured to drive the light-emitting device to emit light. A first initialization signal line is located on the substrate and electrically connected to the plurality of sub-pixels, and at least a portion of the first initialization signal line is located in the display area; A plurality of first-type bonding pins are located on the substrate and in the first border area; the plurality of first-type bonding pins include first bonding pins; the plurality of first-type bonding pins are configured to bond to an external circuit board. A first initialization connection line is located on the substrate and in the first border area, and the first initialization connection line is electrically connected to the first bonding pin and the first initialization signal line.

2. The display panel according to claim 1, wherein, The first initialization signal line includes: Multiple first sub-lines, at least partially located in the display area, and extending along the first direction, Multiple second sub-lines, at least partially located in the display area, and extending along the second direction; the multiple second sub-lines and the multiple first sub-lines are electrically connected and form a mesh structure; The first initialization connection line includes: The first main line is located in the first border area and extends along the first direction; the plurality of second sub-lines extend to the first border area and are electrically connected to the first main line; At least one first branch line is located in the first border area and on the side of the first main line away from the display area; the at least one first branch line is electrically connected to the first main line and the first bonding pin.

3. The display panel according to claim 2, wherein, The first branch includes: The first line segment extends along the first direction; Multiple second wiring segments extend along the second direction and are spaced apart along the first direction; the multiple second wiring segments are electrically connected to the first wiring segment and the first main line.

4. The display panel according to claim 3, wherein, The second routing segment includes: The first sub-segment extends along the second direction and is directly connected to the first trace segment; The second sub-segment extends along the second direction and is directly connected to the first main line; the second sub-segment is connected to the first sub-segment.

5. The display panel according to claim 3, wherein, The second wiring segment is directly connected to the first wiring segment and is an integral structure.

6. The display panel according to claim 2, wherein, The first initialization connection line includes two first branches, which are respectively close to the edges of the display panel on opposite sides along the first direction.

7. The display panel according to claim 6, further comprising: Multiple second-type bonding pins are located in the first frame area. The multiple second-type bonding pins are located between the first main line and the multiple first-type bonding pins. The two first branches are located on the side of the multiple second-type bonding pins near the boundary of the first frame area. The second-type bonding pins are configured to bond with an external driver chip.

8. The display panel according to any one of claims 1 to 7, wherein, The plurality of first-type bonding pins also includes second-type bonding pins; The display panel also includes: A second initialization signal line is located on the substrate and electrically connected to the plurality of sub-pixels, and at least a portion of the second initialization signal line is located in the display area; The second initialization connection line is located on the substrate and in the first border area, and the second initialization connection line is electrically connected to the second bonding pin and the second initialization signal line.

9. The display panel according to claim 8, wherein, The second initialization signal line includes: Multiple third sub-lines, at least partially located in the display area, and extending along the first direction, Multiple fourth sub-lines, at least partially located in the display area, and extending along the second direction; the multiple fourth sub-lines and the multiple third sub-lines are electrically connected and form a mesh structure; The second initialization connection line includes: The second main line is located in the first border area and extends along the first direction; the plurality of fourth sub-lines extend to the first border area and connect with the second main line; At least one second branch line is located in the first border area and on the side of the second main line away from the display area; the at least one second branch line is electrically connected to the second main line and the second bonding pin.

10. The display panel according to claim 9, wherein the first initialization connection line includes a first trunk line; the second trunk line is located on the side of the first trunk line near the display area, and the second branch line crosses the first trunk line along the second direction and connects to the second trunk line.

11. The display panel according to claim 10, wherein, The second sub-line crosses the second main line along the second direction and connects with the first main line.

12. The display panel according to claim 11, wherein, Along the second direction, the second branch is located on the side of the first branch near the boundary of the first border area.

13. The display panel according to claim 9, wherein, The second branch includes: The third line segment extends along the first direction; Multiple fourth wiring segments extend along the second direction and are spaced apart along the first direction; the multiple fourth wiring segments are electrically connected to the third wiring segment and the second main line.

14. The display panel according to any one of claims 1 to 13, wherein, The display panel further includes at least one second border area, which extends along the second direction and is located on one side of the display area along the first direction. The plurality of first-type bonding pins also includes a third bonding pin; The display panel also includes: A third initialization signal line is located on the substrate and electrically connected to the plurality of sub-pixels, and at least a portion of the third initialization signal line is located in the display area; The third initialization connection line is located on the substrate and on the side of the first initialization connection line near the boundary of the first frame area; the third initialization connection line is located in the first frame area and extends to the second frame area of ​​the display; the third initialization connection line is electrically connected to the third bonding pin and the third initialization signal line.

15. The display panel according to claim 14, wherein the third initialization signal line comprises: Multiple fifth sub-lines, at least partially located in the display area and extending along the first direction, are spaced apart along the second direction; The third initialization connection line includes: The fifth line segment extends along the second direction and is located in the second border area; Multiple sixth traces extend along the first direction and are located in the second border area; the multiple sixth traces are spaced apart along the second direction; a fifth sub-line extends to the second border area and is electrically connected to a sixth trace.

16. The display panel according to any one of claims 1 to 15, further comprising a plurality of gate control signal lines, wherein the gate control signal lines include: The first fan-out segment is located in the first border area and extends along the second direction. Along the second direction, the first fan-out segment is located on the side of the first initialization connection line near the boundary of the first border area. The second fan-out segment is located in the first border area and extends along the first direction; the second fan-out segment is located on the side of the first fan-out segment away from the display area and is connected to the first fan-out segment; the first initialization connection line crosses the second fan-out segment along the second direction.

17. The display panel according to claim 16, further comprising a third initialization connection line, the third initialization connection line comprising: The seventh trace segment is located in the first border area and extends along the second direction; the seventh trace segment is located between the first fan-out segment and the first initialization connection line.

18. The display panel according to any one of claims 1 to 17, wherein, The pixel circuit includes: The first reset transistor has its control electrode connected to the first reset signal terminal, its first electrode connected to the first initialization signal terminal, and its second electrode connected to the first node. The second reset transistor has its control terminal connected to the second reset signal terminal, and its first terminal connected to the second reset signal terminal. Two initialization signal terminals are connected, and the second pole is connected to the third node; The third reset transistor has its control electrode connected to the third reset signal terminal, its first electrode connected to the third initialization signal terminal, and its second electrode connected to the anode of the light-emitting device. The first initialization signal line is connected to the first initialization signal terminal and is configured to transmit the first initialization signal; The second initialization signal line is connected to the second initialization signal terminal and is configured to transmit the second initialization signal; The third initialization signal line is connected to the third initialization signal terminal and is configured to transmit the third initialization signal.

19. A display device comprising a display panel as claimed in any one of claims 1 to 18.

Images