Display panel and display apparatus

Abstract

Provided in the embodiments of the present application are a display panel and a display apparatus. The display panel comprises a pixel circuit, which comprises a driving transistor and a first transistor, wherein the driving transistor is electrically connected to the first transistor. The display panel further comprises a substrate, an array layer and an organic light-emitting layer, the organic light-emitting layer comprising a first electrode layer, an organic layer and a second electrode layer, wherein the first electrode layer comprises a first electrode, which covers at least part of the first transistor in the direction perpendicular to the plane in which the display panel is located; and the array layer comprising a first power signal line, which covers at least part of the first transistor. The present application is conducive to ameliorating the problem of the brightness stability of a display panel being relatively poor, and makes it possible to synchronously block first transistors in different pixel circuits, thereby facilitating prevention of the problem of a wide-angle color shift in a display panel.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410636006.1, filed on May 21, 2024, and entitled "Display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] Organic Light-Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminous, wide viewing angle and fast response speed, and has become the focus of current display field research. In the display panel, the pixel circuit is designed to provide driving current for OLED to drive OLED to emit light, and the change of the size of the driving current has a significant impact on the luminance of OLED.

[0004] However, in the existing display panel, the thin film transistor device in the pixel circuit is easily affected by light, which causes the device characteristics to drift and the leakage current to change, resulting in poor luminance stability of the display panel and affecting the display quality.

[0005] SUMMARY

[0006] Therefore, the embodiments of the present application provide a display panel and a display device to solve the above problems.

[0007] In a first aspect, the embodiments of the present application provide a display panel, which comprises a pixel circuit, the pixel circuit comprising a driving transistor and a first transistor, the driving transistor and the first transistor being electrically connected; the display panel further comprises a substrate, an array layer and an organic light-emitting layer; the organic light-emitting layer comprises a first electrode layer, an organic layer and a second electrode layer; the first electrode layer comprises a first electrode, which covers at least part of the first transistor in a direction perpendicular to the plane in which the display panel lies; and the array layer comprises a first power signal line, which covers at least part of the first transistor.

[0008] In a second aspect, the embodiments of the present application provide a display device comprising the display panel provided in the first aspect.

[0009] In the embodiments of the present application, the first electrode and the first power signal line cover at least part of the first transistor, which can reduce the irradiation of the external ambient light on the first transistor, and is conducive to improving the influence of the large leakage current of the first transistor on the gate potential of the driving transistor, and further conducive to improving the problem of poor luminance stability of the display panel, and improving the display effect.

[0010] Meanwhile, since the first electrode and the first power signal line are located in different film layers, the first electrode and the first power signal line can shield the first transistor, which is conducive to avoiding the problem of spatial limitation of shielding the first transistor by using the same film layer, thereby being conducive to avoiding the problem of external light of a large angle entering the first transistor, and further being conducive to further improving the problem of leakage current of the first transistor. Moreover, the first electrode and the first power signal line can shield the first transistor in different pixel circuits, which is conducive to realizing synchronous shielding of the first transistor in different pixel circuits, so that it is possible for the brightness of sub-pixels of different colors to change uniformly, and is conducive to avoiding the problem of color deviation at a large angle of the display panel. In addition, the shielding degree of the first electrode and the first power signal line to the first transistor in different pixel circuits can be flexibly adjusted as needed to meet different display requirements of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a plan view of a display panel according to an embodiment of the present application;

[0012] FIG. 2 is a schematic view of a pixel circuit in FIG. 1;

[0013] FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present application;

[0014] FIG. 4 is a layout view of a display panel according to an embodiment of the present application;

[0015] FIG. 5 is a layout view of another display panel according to an embodiment of the present application;

[0016] FIG. 6 is a layout view of another display panel according to an embodiment of the present application;

[0017] FIG. 7 is a layout view of another display panel according to an embodiment of the present application;

[0018] FIG. 8 is a layout view of another display panel according to an embodiment of the present application;

[0019] FIG. 9 is a layout view of another display panel according to an embodiment of the present application;

[0020] FIG. 10 is a layout view of another display panel according to an embodiment of the present application;

[0021] FIG. 11 is a layout view of another display panel according to an embodiment of the present application;

[0022] FIG. 12 is a layout view of another display panel according to an embodiment of the present application;

[0023] FIG. 13 is a layout view of another display panel according to an embodiment of the present application;

[0024] FIG. 14 is a layout schematic diagram of another display panel according to an embodiment of the present application;

[0025] FIG. 15 is a layout schematic diagram of another display panel according to an embodiment of the present application;

[0026] FIG. 16 is a light path schematic diagram according to an embodiment of the present application;

[0027] FIG. 17 is a layout schematic diagram of another display panel according to an embodiment of the present application;

[0028] FIG. 18 is an enlarged schematic diagram of a Q region in FIG. 17;

[0029] FIG. 19 is a plan schematic diagram of another display panel according to an embodiment of the present application;

[0030] FIG. 20 is a cross-sectional schematic diagram of the display panel in FIG. 19;

[0031] FIG. 21 is a layout schematic diagram of another display panel according to an embodiment of the present application;

[0032] FIG. 22 is a layout schematic diagram of another display panel according to an embodiment of the present application;

[0033] FIG. 23 is a schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the drawings.

[0035] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0036] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0037] The applicant of the present application provides a solution to the problems existing in the prior art through careful and in-depth research.

[0038] FIG. 1 is a plan schematic diagram of a display panel according to an embodiment of the present application, FIG. 2 is a schematic diagram of a pixel circuit in FIG. 1, and FIG. 3 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present application.

[0039] Embodiments of the present application provide a display panel 01. As shown in FIG. 1 and FIG. 2, the display panel 01 includes pixel circuits 11 and light emitting devices 12 electrically connected, and the pixel circuits 11 are configured to drive the light emitting devices 12 to emit light. The pixel circuit 11 includes a driving transistor Td, a threshold compensation transistor M1, and a gate initialization transistor M2. The gate of the driving transistor Td is electrically connected to the threshold compensation transistor M1 and the gate initialization transistor M2 at a first node N1. The driving transistor Td is configured to generate a light emitting driving current. The threshold compensation transistor M1 is configured to compensate the threshold voltage of the driving transistor Td for the gate of the driving transistor Td. The gate initialization transistor M2 is configured to transmit an initialization signal to the gate of the driving transistor Td. The threshold compensation transistor M1 and the gate initialization transistor M2 can be double-gate transistors.

[0040] As shown in FIG. 3, the display panel 01 further includes a substrate 21, an array layer 22, and an organic light emitting layer 23. The array layer 22 is located between the substrate 21 and the organic light emitting layer 23. The transistors in the pixel circuit 11 are located in the array layer 22, and the light emitting device 12 is located in the organic light emitting layer 23. The light emitting device 12 can be an organic light emitting diode. It should be noted that only one transistor in the pixel circuit 11 is shown in FIG. 3.

[0041] The organic light emitting layer 23 includes a first electrode layer 231, an organic layer 232, and a second electrode layer 233. The organic layer 232 is located between the first electrode layer 231 and the second electrode layer 233, and the first electrode layer 231 is located on the side of the second electrode layer 233 facing the substrate 21. The first electrode layer 231 can be an anode layer of the light emitting device 12, the organic layer 232 can be a light emitting material layer of the light emitting device 12, and the second electrode layer 233 can be a cathode layer of the light emitting device 12.

[0042] The first electrode layer 231 includes a first electrode RE, which can be an anode of the light emitting device 12.

[0043] FIG. 4 is a layout schematic diagram of a display panel according to an embodiment of the present application. FIG. 5 is a layout schematic diagram of another display panel according to an embodiment of the present application. FIG. 6 is a layout schematic diagram of another display panel according to an embodiment of the present application. FIG. 7 is a layout schematic diagram of another display panel according to an embodiment of the present application. FIG. 8 is a layout schematic diagram of another display panel according to an embodiment of the present application. FIG. 9 is a layout schematic diagram of another display panel according to an embodiment of the present application. FIG. 10 is a layout schematic diagram of another display panel according to an embodiment of the present application.

[0044] In combination with Figs. 4-10, in a direction Z perpendicular to the plane in which the display panel 01 lies, the first electrode RE covers at least part of the threshold compensation transistor M1 and / or the gate initialization transistor M2. The array layer 22 comprises a first power supply signal line DL1, which can be used to transmit a voltage PVDD, which, in a direction Z perpendicular to the plane in which the display panel 01 lies, covers at least part of the threshold compensation transistor M1 and / or the gate initialization transistor M2.

[0045] Optionally, as shown in Fig. 4, in the same pixel circuit 11, in a direction perpendicular to the plane in which the display panel 01 lies, the first electrode RE covers the threshold compensation transistor M1, and the first power supply signal line DL1 covers the gate initialization transistor M2.

[0046] Optionally, as shown in Fig. 5, in the same pixel circuit 11, in a direction perpendicular to the plane in which the display panel 01 lies, the first power supply signal line DL1 covers the threshold compensation transistor M1, and the first electrode RE covers the gate initialization transistor M2.

[0047] Optionally, as shown in Fig. 6, in the same pixel circuit 11, in a direction perpendicular to the plane in which the display panel 01 lies, the first electrode RE and the first power supply signal line DL1 jointly cover the threshold compensation transistor M1.

[0048] Optionally, as shown in Fig. 7, in the same pixel circuit 11, in a direction perpendicular to the plane in which the display panel 01 lies, the first electrode RE and the first power supply signal line DL1 jointly cover the gate initialization transistor M2.

[0049] Optionally, as shown in Fig. 8, the display panel 01 comprises a plurality of pixel circuits 11, which comprise a first pixel circuit 11A and a second pixel circuit 11B, in which, in a direction perpendicular to the plane in which the display panel 01 lies, the first electrode RE covers the threshold compensation transistor M1 in the first pixel circuit 11A, and the first power supply signal line DL1 covers the gate initialization transistor M2 in the second pixel circuit 11B.

[0050] Optionally, as shown in Fig. 9, the display panel 01 comprises a plurality of pixel circuits 11, which comprise a first pixel circuit 11A and a second pixel circuit 11B, in which, in a direction perpendicular to the plane in which the display panel 01 lies, the first electrode RE covers the threshold compensation transistor M1 in the first pixel circuit 11A, and the first power supply signal line DL1 covers the threshold compensation transistor M1 in the second pixel circuit 11B.

[0051] Optionally, as shown in FIG. 10, the display panel 01 includes a plurality of pixel circuits 11, the plurality of pixel circuits 11 including a first pixel circuit 11A and a second pixel circuit 11B, and in a direction perpendicular to a plane on which the display panel 01 is located, the first electrode RE covers a gate initialization transistor M2 in the first pixel circuit 11A, and the first power signal line DL1 covers the gate initialization transistor M2 in the second pixel circuit 11B.

[0052] That is, in the direction perpendicular to the plane on which the display panel 01 is located, the first electrode RE and the first power signal line DL1 can cover transistors in the same pixel circuit 11, or can cover transistors in different pixel circuits 11 respectively.

[0053] Further, in the same pixel circuit 11, the first electrode RE and the first power signal line DL1 can cover different transistors respectively, or can cover the same transistor together.

[0054] It can be understood that the light-emitting driving current provided by the pixel circuit 11 to the light-emitting device 12 is related to the gate potential of the driving transistor Td. The present inventor has found through research that external light irradiation can cause the drain current of the transistor to become large, and since the threshold compensation transistor M1 and the gate initialization transistor M2 are electrically connected to the gate of the driving transistor Td, when external light irradiates on the threshold compensation transistor M1 or the gate initialization transistor M2, it is easy to cause the gate potential of the driving transistor Td to change and increase, thereby causing the light-emitting driving current provided by the pixel circuit 11 to the light-emitting device 12 to have poor stability, which can easily cause the display panel 01 to have a screen shaking problem and affect the display quality.

[0055] In the embodiment of the present application, the pixel circuit 11 includes a first transistor, the first transistor being electrically connected to the gate of the driving transistor Td, and in a direction Z perpendicular to a plane on which the display panel 01 is located, the first electrode RE covers at least part of the first transistor, and the first power signal line DL1 covers at least part of the first transistor. The first transistor is the aforementioned threshold compensation transistor M1 or gate initialization transistor M2.

[0056] From the above analysis, it can be seen that by arranging the first electrode RE and the first power signal line DL1 to cover at least part of the first transistor, the irradiation of the external environment light on the first transistor can be reduced, which is beneficial to improve the influence of the large drain current of the first transistor on the gate potential of the driving transistor Td, and further beneficial to improve the problem of poor brightness stability of the display panel 01 and improve the display effect.

[0057] Meanwhile, since the first electrode RE and the first power signal line DL1 are located in different film layers, the first electrode RE and the first power signal line DL1 can shield the first transistor together, which is beneficial to avoid the problem of spatial limitation of shielding the first transistor by using the same film layer, thereby being beneficial to avoid the external light of a large angle from entering the first transistor, and further being beneficial to further improve the leakage current problem of the first transistor.

[0058] Furthermore, the first electrode RE and the first power signal line DL1 can shield the first transistor in different pixel circuits 11, which is beneficial to synchronously shield the first transistor T1 in different pixel circuits 11, so that the brightness of sub-pixels of different colors can be consistent, and is beneficial to avoid the problem of color deviation at a large angle of the display panel 01. In addition, the shielding degree of the first electrode RE and the first power signal line DL1 on the first transistor T1 in different pixel circuits 11 can be flexibly adjusted as needed to meet different display requirements of the display panel 01.

[0059] In an embodiment of the present application, as shown in FIG. 1, the display panel 01 includes sub-pixels P of different colors, and each sub-pixel P includes a pixel circuit 11 and a light emitting device 12 as described above. Among the sub-pixels P of different colors, the light emitting devices 12 have different light emitting colors, but the structures of the pixel circuits 11 can be the same.

[0060] In the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE and the first power signal line DL1 cover different first transistors. Optionally, the first electrode RE and the first power signal line DL1 cover the first transistors in sub-pixels P of different colors.

[0061] For example, as shown in FIG. 9, taking the threshold compensation transistor M1 as an example, the first pixel circuit 11A and the second pixel circuit 11B belong to sub-pixels of different colors, the first electrode RE covers the threshold compensation transistor M1 in the first pixel circuit 11A, and the first power signal line DL1 covers the threshold compensation transistor M1 in the second pixel circuit 11B.

[0062] In the embodiment of the present application, the first transistors that are not covered by the first electrode RE can be covered by the first power signal line DL1, which is beneficial to avoid the situation that two first electrodes RE are too close to each other in order to cover different first transistors, and is beneficial to avoid the situation that the two adjacent first electrodes RE are too close to each other and drive abnormally while ensuring the shielding of the first transistor. Furthermore, avoiding the situation that the two adjacent first electrodes RE are too close to each other can also reduce the etching precision requirement for the two adjacent first electrodes RE, which is beneficial to reduce the process difficulty.

[0063] In addition, the film layer where the first power signal line DL1 is located usually has more wirings, and the first electrode RE and the first power signal line DL1 cover different first transistors respectively, so that the metal density of the film layer where the first power signal line DL1 is located can be avoided from being too large, and the process difficulty can be reduced, and the crosstalk and coupling of the same layer metal can be avoided.

[0064] FIG. 11 is a layout schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 12 is a layout schematic diagram of another display panel provided by an embodiment of the present application.

[0065] In an implementation manner of the embodiment of the present application, as shown in FIG. 11, the plurality of sub-pixels P include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3, and the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 can be sub-pixels of different colors. The sub-pixel P includes a pixel circuit PA, and the pixel circuit PA includes a driving transistor Td and a first transistor T1, and the first transistor T1 can be the threshold compensation transistor M1 in the above embodiment.

[0066] Among them, in the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE covers the first transistor T1 in the first sub-pixel P1 and the first transistor T1 in the second sub-pixel P2, and the first power signal line DL1 covers the first transistor T1 in the third sub-pixel P3.

[0067] Optionally, the first sub-pixel P1 is a blue sub-pixel, and the second sub-pixel P2 is any one of a green sub-pixel and a red sub-pixel.

[0068] In the implementation manner, the first electrode RE covers more first transistors T1, which is beneficial to reduce the number of the first transistors T1 blocked by the first power signal line DL1, thereby being beneficial to reduce the shape diversity of the first power signal line DL1, and further being beneficial to reduce the preparation difficulty of the first power signal line DL1.

[0069] Optionally, as shown in FIG. 11, the pixel circuit PA of the first sub-pixel P1 and the pixel circuit PA of the second sub-pixel P2 are arranged adjacently. At this time, the first transistors T1 of the first sub-pixel P1 and the second sub-pixel P2 can be covered by the same first electrode RE.

[0070] For example, the first sub-pixel P1 is a blue sub-pixel, the second sub-pixel P2 is a green sub-pixel, and the third sub-pixel P3 is a red sub-pixel, and the first electrode RE of the first sub-pixel P1 covers the first transistors T1 of the first sub-pixel P1 and the second sub-pixel P2.

[0071] In this way, the first electrode RE of the first sub-pixel P1 and the first electrode RE of the second sub-pixel P2 are not arranged too close to each other, and the driving abnormality caused by the first electrode RE of the first sub-pixel P1 being too close to the first electrode RE of the second sub-pixel P2 can be avoided.

[0072] In addition, the first electrode RE can have different areas according to the light-emitting efficiency of the sub-pixel. When the first sub-pixel P1 is a blue sub-pixel, the area of the first electrode RE of the first sub-pixel P1 is usually large. The first electrode RE of the first sub-pixel P1 can shield the first transistor T1 of the first sub-pixel P1. The first electrode RE of the first sub-pixel P1 can shield the first transistor T1 of the second sub-pixel P2 by being appropriately increased in size, and the first electrode RE of the second sub-pixel P2 does not need to be changed. In this way, the process difficulty can be reduced.

[0073] Optionally, as shown in FIG. 12, the pixel circuit PA of the third sub-pixel P3 is located between the pixel circuit PA of the first sub-pixel P1 and the pixel circuit PA of the second sub-pixel P2. In this case, the first transistors T1 of the first sub-pixel P1 and the second sub-pixel P2 can be covered by different first electrodes RE.

[0074] For example, the first sub-pixel P1 is a blue sub-pixel, the second sub-pixel P2 is a red sub-pixel, and the third sub-pixel P3 is a green sub-pixel. The first electrode RE of the first sub-pixel P1 covers the first transistor T1 of the first sub-pixel P1, and the first electrode RE of the second sub-pixel P2 covers the first transistor T1 of the second sub-pixel P2.

[0075] In this way, the first electrode of the first sub-pixel P1 and the first electrode of the second sub-pixel P2 are not arranged too close to each other, and the first electrode of the first sub-pixel P1 or the first electrode of the second sub-pixel P2 does not need to be prepared to be too large, which can save the preparation cost.

[0076] It should be noted that, for the convenience of showing the layout of the display panel, FIGS. 11 and 12 only show the channel layer, the gate layer, the first electrode RE, and the first power supply signal line DL1 of the transistor.

[0077] FIG. 13 is a layout schematic diagram of another display panel provided by an embodiment of the present application.

[0078] In another implementation manner of the embodiment of the present application, as shown in FIG. 13, a plurality of sub-pixels P include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be sub-pixels of different colors.

[0079] In a direction perpendicular to a plane on which the display panel 01 is located, the first electrode RE covers the first transistor T1 of the second sub-pixel P2, and the first power signal line DL1 covers the first transistors T1 of the first sub-pixel P1 and the third sub-pixel P3.

[0080] The first sub-pixel P1 is a blue sub-pixel, the second sub-pixel P2 is a green sub-pixel, and the third sub-pixel P3 is a red sub-pixel.

[0081] That is, in a direction perpendicular to a plane on which the display panel 01 is located, the first electrode RE covers the first transistor T1 of the green sub-pixel, and the first power signal line DL1 covers the first transistors T1 of the blue sub-pixel and the red sub-pixel.

[0082] In the present implementation, the first power signal line DL1 covers more first transistors T1, so that the number of first transistors T1 covered by the first electrode RE can be reduced, which is conducive to avoiding the case that the area of the first electrode RE in different sub-pixels P is large, thereby facilitating the improvement of the space utilization of the film layer where the first electrode RE is located, and avoiding the case that different first electrodes RE are too close to each other and cause driving abnormalities. Moreover, avoiding the proximity of adjacent first electrodes RE can also reduce the etching precision of the first electrode RE, which is conducive to reducing the preparation difficulty of the display panel 01. At the same time, without the need to set more first electrodes RE to be larger, the metal density of the first electrode layer 231 can be avoided to be too large, which is conducive to ensuring the light transmittance of the display panel 01, and when the light sensor is integrated inside the display panel 01, it is conducive to ensuring the normal work of the light sensor inside the display panel 01.

[0083] FIG. 14 is a layout schematic diagram of another display panel provided by an embodiment of the present application.

[0084] In an embodiment of the present application, as shown in FIG. 14, the first transistor T1 includes a first channel portion GD1, and in a direction perpendicular to a plane on which the display panel 01 is located, the distance between the edge of the first electrode RE and the projection of the first channel portion GD1 on the substrate 21 is J1, 5 μm≤J1≤10.5 μm. J1 can be the minimum distance between the edge of the first electrode RE and the projection of the first channel portion GD1 on the substrate 21.

[0085] In this way, the first electrode RE can block external light of different angles from entering the first channel portion GD1 of the first transistor T1 to meet the different brightness requirements of the sub-pixel P.

[0086] Optionally, 2.5 pm≤J1≤2.7 pm is set, and the first electrode RE can shield 30° external light from the outside into the first channel portion GD1 of the first transistor T1. 4.4 pm≤J1≤4.7 pm is set, and the first electrode RE can shield 45° external light from the outside into the first channel portion GD1 of the first transistor T1. 9.7 pm≤J1≤10.1 pm is set, and the first electrode RE can shield 60° external light from the outside into the first channel portion GD1 of the first transistor T1.

[0087] It should be noted that when the first transistor T1 is a double-gate transistor, the channels of the first transistor T1 are all the first channel portions GD1, and the first electrode RE can shield the same degree of the plurality of first channel portions GD1 of the same first transistor T1. For the convenience of showing the layout of the display panel, FIG. 14 only shows the film layers where the channel layer, the gate layer, the first electrode RE and the first power signal line DL1 of the transistor are located.

[0088] FIG. 15 is a layout schematic diagram of another display panel provided by an embodiment of the present application.

[0089] As shown in FIG. 15, in an embodiment of the present application, the first transistor T1 includes the first channel portion GD1, and the distance between the edge of the first power signal line DL1 and the projection of the first channel portion GD1 on the substrate 21 in the direction perpendicular to the plane where the display panel 01 is located is J2, 1 pm≤J2≤7 pm. J2 can be the minimum distance between the edge of the first power signal line DL1 and the projection of the first channel portion GD1 on the substrate 21.

[0090] In this way, the first power signal line DL1 can shield external light of different angles from the outside into the first channel portion GD1 of the first transistor T1 to meet the different brightness requirements of the sub-pixel P.

[0091] Optionally, 1 pm≤J2<2 pm, for example, J2 can be 1.4 pm, 1.6 pm, 1.8 pm, etc., and the first power signal line DL1 can shield 30° external light from the outside into the first channel portion GD1 of the first transistor T1.

[0092] Optionally, 2 pm≤J2≤3 pm, for example, J2 can be 2.4 pm, 2.6 pm, 2.8 pm, etc., and the first power signal line DL1 can shield 45° external light from the outside into the first channel portion GD1 of the first transistor T1.

[0093] Optionally, 6 pm≤J2≤7 pm, for example, J2 can be 6.2 pm, 6.6 pm, 6.8 pm, etc., and the first power signal line DL1 can shield 60° external light from the outside into the first channel portion GD1 of the first transistor T1.

[0094] It should be noted that when the first transistor T1 is a double-gate transistor, the channel of the first transistor T1 is the first channel portion GD1, and the first power supply signal line DL1 can shield the plurality of first channel portions GD1 of the same first transistor T1 to the same extent. For the convenience of showing the layout of the display panel, FIG. 15 only shows the film layers where the channel layer, the gate layer, the first electrode RE, and the first power supply signal line DL1 of the transistor are located.

[0095] FIG. 16 is a schematic diagram of an optical path related to an embodiment of the present application.

[0096] In the present application, the working principle of the first electrode RE shielding the first channel portion GD1 can be as shown in FIG. 16. The distance between the edge of the first electrode RE and the projection of the first channel portion GD1 on the substrate 21 is W, the angle of the incident light entering the edge of the first electrode RE is θ1, the refractive index of the insulating layer JY1 covering the edge of the first electrode RE is N0; the number of film layers between the first electrode RE and the first channel portion GD1 is n, and n≥2. From the first electrode RE to the first channel portion GD1, the refractive indices of the film layers are N1, N2, …, N(n) respectively, the thicknesses are H1, H2, …, H(n) respectively, the refraction angles are θ2, θ3, …, θ(n+1) respectively, and the offsets between adjacent two film layers are W1, W2, …, W(n-1).

[0097] N0*sinθ1=N1*sinθ2, W1=H1*tanθ2; N1*sinθ2=N2*sinθ3, W2=H2*tanθ3;

[0098] …; N(n-1)*sinθ(n)=N(n)*sinθ(n+1), W(n)=H(n)*tanθ(n+1); W=W1+W2+…+W(n).

[0099] In the present application, the size of θ1 can be controlled by controlling the size of W, so that the angle of the external light that can be shielded by the first electrode RE and enter the first transistor T1 can be controlled. Of course, this working principle is also applicable to the shielding of the first power supply signal line DL1 to the first transistor T1.

[0100] In an embodiment of the present application, the degree of shielding of the first transistor T1 in the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be set to be the same, that is, the first electrode RE and / or the first power supply signal line DL1 in the red sub-pixel, the green sub-pixel, and the blue sub-pixel can shield the external light entering the first channel portion of the first transistor T1 in the sub-pixels by the same angle.

[0101] In this way, the luminance of the red, green and blue sub-pixels can be made to change uniformly, thereby avoiding color cast of the display panel 01.

[0102] The first transistor T1 in the red, green and blue sub-pixels can also be arranged to be shielded to different degrees, i.e., the first electrode RE and / or the first power signal line DL1 in the red, green and blue sub-pixels can shield external light at different angles from entering the first channel portion of the first transistor T1 in the sub-pixels. In this way, the luminance of the red, green and blue sub-pixels can be made to change to different degrees, thereby facilitating different display requirements of the display panel 01.

[0103] For example, the first electrode RE can be arranged to shield 60° of external light from entering the first transistor in the red sub-pixel and the first transistor in the blue sub-pixel, and the first power signal line DL1 can be arranged to shield 30° of external light from entering the first transistor in the green sub-pixel. In this way, the leakage current of the first transistor T1 in the green sub-pixel can be made to be greater than that in the red sub-pixel and that in the blue sub-pixel, thereby making the luminance of the green sub-pixel change to a greater degree than that of the red sub-pixel and that of the blue sub-pixel. When the first transistor T1 is a gate initialization transistor, the display panel 01 can display a greenish effect. When the first transistor T1 is a threshold compensation transistor, the display panel 01 can display a yellowish effect.

[0104] For example, the first electrode RE can be arranged to shield 60° of external light from entering the first transistor in the green sub-pixel, and the first power signal line DL1 can be arranged to shield 30° of external light from entering the first transistor in the red sub-pixel and the first transistor in the blue sub-pixel. In this way, the leakage current of the first transistor T1 in the green sub-pixel can be made to be less than that in the red sub-pixel and that in the blue sub-pixel, thereby making the luminance of the green sub-pixel change to a smaller degree than that of the red sub-pixel and that of the blue sub-pixel. When the first transistor T1 is a gate initialization transistor, the display panel 01 can display a yellowish effect. When the first transistor T1 is a threshold compensation transistor, the display panel 01 can display a greenish effect.

[0105] It should be noted that, in the present embodiment, the angle of external light refers to the angle between the external light entering the display panel 01 and the direction perpendicular to the display panel.

[0106] FIG. 17 is a layout schematic diagram of another display panel provided by the present application.

[0107] In an embodiment of the present application, as shown in FIG. 1, the display panel 01 includes sub-pixels P of different colors, and each sub-pixel P includes a pixel circuit 11 and a light emitting device 12 as described above. Among the sub-pixels P of different colors, the light emitting colors of the light emitting devices 12 are different, but the structures of the pixel circuits 11 can be the same.

[0108] As shown in FIG. 17, in the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE and the first power signal line DL1 cover the same first transistor T1. It should be noted that FIG. 17 is a schematic diagram taking the first transistor T1 as an example, and for the convenience of showing the layout of the display panel, FIG. 17 only shows the channel layer and the gate layer of the transistor, the film layer where the first electrode RE and the first power signal line DL1 are located.

[0109] That is, the first transistor T1 in the same sub-pixel P can be covered by the whole formed by the first electrode RE and the first power signal line DL1.

[0110] From the above analysis, in order to achieve the same degree of shielding of the first transistor T1, in the direction perpendicular to the plane where the display panel 01 is located, the farther the projection edge of the shielding layer in the plane where the channel is located from the channel of the first transistor T1, the farther the channel of the first transistor T1 needs to be. That is, compared with shielding the first transistor T1 by the first power signal line DL1 alone, in the case of achieving the same degree of shielding of the first transistor T1, the distance between the projection edge of the first electrode RE in the plane where the channel is located and the channel of the first transistor T1 is greater than the distance between the projection edge of the first power signal line DL1 in the plane where the channel is located and the channel of the first transistor T1.

[0111] Therefore, in order to shield a larger angle of external light from entering the first transistor T1, such as shielding 60° of external light from entering the first transistor T1, if the first electrode RE is used alone to shield the first transistor T1, the area of the first electrode RE needs to be designed to be very large, which will make the distance between adjacent first electrodes RE too small, thereby causing the etching of the first electrode RE to be difficult, and it is difficult to realize the patterning of the first electrode RE in the process.

[0112] The inventors have also found that there are many metal traces in the film layer where the first power signal line DL1 is located, and if the first power signal line DL1 is used alone to shield the first transistor T1, the metal density of the film layer where the first power signal line DL1 is located will be large, which on the one hand will lead to a complex preparation process of the first power signal line DL1, and on the other hand will easily lead to an increase in coupling between metal traces in the same layer, affecting the signal transmission of the metal traces.

[0113] Therefore, in the embodiment of the present application, the first electrode RE and the first power signal line DL1 jointly shield the first transistor T1. In this way, the problem of too small distance between adjacent first electrodes RE is avoided, and the problem of too large metal trace density of the film layer where the first power signal line DL1 is located is also avoided.

[0114] FIG. 18 is an enlarged schematic view of the Q region in FIG. 17.

[0115] Please continue to refer to FIG. 17. In an embodiment of the present application, the first power signal line DL1 includes a first part DL11 and a second part DL12. The first part DL11 extends along a first direction Y, and the second part DL12 is located on one side of the first part DL11 and covers at least part of the first transistor T1 along a direction perpendicular to the plane where the display panel 01 is located. The first direction Y can be the column direction of the display panel 01.

[0116] In combination with FIG. 18, the first transistor T1 includes a first channel part GD1. The minimum distance between the edge of the second part DL12 and the projection of the first channel part GD1 on the substrate 21 is S1 along a direction perpendicular to the plane where the display panel 01 is located. Here, the second part DL12 refers to the second part DL12 covering the first channel part GD1. The minimum distance between the edge of the first electrode RE and the projection of the first channel part GD1 on the substrate 21 is S2. Here, the first electrode RE refers to the first electrode RE covering the first channel part GD1.

[0117] Here, S1 > S2.

[0118] In the embodiment of the present application, S1 > S2. Therefore, it is possible for the first power signal line DL1 to shield the large-angle incident light that cannot be shielded by the first electrode RE. This is conducive to avoiding the large-angle external light from irradiating the first channel part GD1 of the first transistor T1, and making it possible for the first transistors T1 in different color sub-pixels P to be shielded to the same extent. In this way, the brightness of different color sub-pixels changes uniformly, thereby facilitating the display panel 01 to have no obvious color cast.

[0119] Optionally, the first transistor T1 is from the green sub-pixel. Since the light-emitting efficiency of the organic light-emitting material in the green sub-pixel is high, a smaller light-emitting area can achieve higher light-emitting efficiency. The area of the first electrode RE in the green sub-pixel is usually small. By setting the first electrode RE to jointly cover the first transistor T1 in the green sub-pixel with the first power signal line DL1, the first electrode RE cannot block the large-angle incident light, which can be blocked by the first power signal line DL1. This is conducive to achieving the same degree of shielding of the first transistor T1 in the green sub-pixel, the red sub-pixel, and the blue sub-pixel under large-angle incident light, thereby facilitating the realization of the display panel 01 without obvious color cast.

[0120] In an embodiment of the present application, as shown in FIGS. 3 and 17, the array layer 22 includes the data line DL2, and the first power signal line DL1 is located in the same layer as the data line DL2. It should be noted that in FIG. 17, structures with the same filling pattern are located in the same layer.

[0121] That is, the first power signal line DL1 and the data line DL2 can be prepared by the same material and the same process.

[0122] In the embodiment of the present application, the first power signal line DL1 and the data line DL2 are set to be in the same layer, so that the first power signal line DL1 can be prepared at the same time as the data line DL2, which is conducive to simplifying the preparation process of the display panel 01 and reducing the preparation cost.

[0123] FIG. 19 is a plan view of another display panel provided in an embodiment of the present application, and FIG. 20 is a cross-sectional view of the display panel shown in FIG. 19.

[0124] In an embodiment of the present application, as shown in FIG. 19, the display panel 01 includes a display area AA and a non-display area NA arranged around the display area AA, the display area AA includes a first display area A1 and a second display area A2 arranged adjacent to each other, and the first display area A1 is located on a side of the second display area A2 close to the edge of the display panel 01.

[0125] The first display area A1 includes a first data line DL21, and the first data line DL21 extends along the first direction Y. The non-display area NA includes a fan-out line FL1, and the fan-out line FL1 can transmit a data voltage Vdata to the first data line DL21. The first data line DL21 is electrically connected to the fan-out line FL1 through a fan-out data line FIAA, and the fan-out data line FIAA can extend from the first display area A1 into the second display area A2.

[0126] The fan-out data line FIAA includes a first segment FA1 and a second segment FA2, and the second segment FA2 is in the same extension direction as the first data line DL21. As shown in FIG. 20, the second segment FA2 is in a different film layer from the first data line DL21, and the first power signal line DL1 and the second segment FA2 are in the same film layer. The first power signal line DL1 and the second segment FA2 can be made of the same material and by the same process.

[0127] Optionally, as shown in FIG. 20, the second segment FA2 is located on a side of the first data line DL21 away from the substrate 21. That is, the first power signal line DL1 is located on a side of the first data line DL1 away from the substrate 21.

[0128] The first segment FA1 can extend along a second direction X intersecting the first direction Y, and the second direction X can be a row direction (extension direction of the scan line) in the display panel 01. The first segment FA1 is in a different film layer from the first data line DL21.

[0129] Optionally, the first segment FA1 is located on a side of the first data line DL21 close to the substrate 21. In some other embodiments, the first segment FA1 can be in the same layer as the second segment FA2. In this case, the first power signal line DL1 can be disconnected at the first segment FA1. Since two adjacent first power signal lines DL1 can be connected by some connection lines, even if the first power signal line DL1 is disconnected at the first segment FA1, the signal transmission on the first power signal line DL1 will not be affected.

[0130] In the embodiments of the present application, the first data line DL21 is electrically connected to the fan-out line FL1 through the fan-out data line FIAA, so that the fan-out line FL1 does not need to be inclined to the first display area A1, which is beneficial to reduce the inclination of the fan-out line FL1 and reduce the frame width of the non-display area NA.

[0131] In addition, the extension length of the second segment FA2 is generally smaller than the extension length of the first data line DL21. The first power signal line DL1 is in the same layer as the second segment FA2 and in a different film layer from the first data line DL21, which is beneficial to reduce the wiring density of the film layer where the first power signal line DL1 is located and improve the space utilization of the film layer where the first power signal line DL1 is located.

[0132] It should be noted that, as shown in FIG. 19, the second display area A2 further includes a second data line DL22, which can be directly connected to the fan-out line FL1.

[0133] FIG. 21 is a layout schematic diagram of another display panel provided by the embodiments of the present application.

[0134] In an embodiment of the present application, as shown in FIGS. 11-13, the pixel circuit PA further includes a second transistor T2, the first transistor T1 can be the threshold compensation transistor M1 in FIG. 2, and the second transistor T2 can be the gate initialization transistor M2 in FIG. 2. The second transistor T2 is electrically connected with the driving transistor Td and the first transistor T1. The first transistor T1 and the second transistor T2 can both be electrically connected with the gate of the driving transistor Td at the first node N1. The second transistor T2 can be a double-gate transistor.

[0135] In combination with FIG. 21, in the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE and / or the first power signal line DL1 covers at least part of the second transistor T2.

[0136] That is, in the direction perpendicular to the plane where the display panel 01 is located, the second transistor T2 can be covered by the first electrode RE, can be covered by the first power signal line DL1, or can be covered by both the first electrode RE and the first power signal line DL1. It should be noted that FIG. 21 only shows the case where the first power signal line DL1 covers the second transistor T2. Moreover, for the convenience of showing the layout of the display panel, FIG. 21 only shows the channel layer, the gate layer of the transistor, and the film layers where the first electrode RE and the first power signal line DL1 are located.

[0137] From the above analysis, it can be known that after the second transistor T2 is irradiated by external light, the leakage current of the second transistor T2 will also increase. Since the second transistor T2 can be electrically connected with the gate of the driving transistor Td, it will also cause the change of the gate potential of the driving transistor Td to increase, thereby causing the light-emitting driving current provided by the pixel circuit 11 to the light-emitting device 12 to have poor stability.

[0138] In the embodiment of the present application, the first electrode RE and / or the first power signal line DL1 covers at least part of the second transistor T2, which can reduce the irradiation of the second transistor T2 by external ambient light, and is conducive to improving the influence of the increase of the leakage current of the second transistor T2 on the gate potential of the driving transistor Td, thereby being conducive to further improving the problem of poor brightness stability of the display panel 01 and improving the display effect.

[0139] In an embodiment of the present application, in combination with FIGS. 1 and 21, the display panel 01 includes a plurality of sub-pixels P of different colors. For the same sub-pixel P, in the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE covers the first transistor T1, and the first power signal line DL1 covers the second transistor T2.

[0140] In the embodiments of the present application, for the same sub-pixel P, the first electrode RE covers the first transistor T1, and the first power signal line DL1 covers the second transistor T2, so that the first transistor T1 and the second transistor T2 can be individually shielded by using the characteristic that the first electrode RE and the first power signal line DL1 are in different layers, which is beneficial to meet different needs of shielding the first transistor T1 and the second transistor T2.

[0141] In addition, since the film layer where the first power signal line DL1 is located is closer to the channel region of the transistor than the film layer where the first electrode RE is located, the first power signal line DL1 is more likely to shield external light of a larger angle from entering the second transistor T2, which is beneficial to improve the shielding ability of the second transistor T2.

[0142] Optionally, in the same sub-pixel P, the shielding degree of the first electrode RE on the first transistor T1 is the same as the shielding degree of the first power signal line DL1 on the second transistor T2.

[0143] For example, in the same sub-pixel P, the first electrode RE can shield 45° external light from entering the first transistor T1, and the first power signal line DL1 can shield 45° external light from entering the second transistor T2.

[0144] Optionally, in the same sub-pixel P, the shielding degree of the first electrode RE on the first transistor T1 is different from the shielding degree of the first power signal line DL1 on the second transistor T2.

[0145] For example, in the same sub-pixel P, the first electrode RE can only shield 30° external light from entering the first transistor T1, and the first power signal line DL1 can shield 60° external light from entering the second transistor T2.

[0146] It should be noted that in some other embodiments, for the same sub-pixel P, the first power signal line DL1 can also cover the first transistor T1, and the first electrode RE covers the second transistor T2.

[0147] Please continue to refer to FIG. 21. In an embodiment of the present application, the first transistor T1 includes a first channel portion GD1, the second transistor T2 includes a second channel portion GD2, and along the direction perpendicular to the plane where the display panel 01 is located, the first electrode RE covers the first channel portion GD1, and the minimum distance between the edge of the first electrode RE and the projection of the first channel portion GD1 on the substrate 21 is D1; the first power signal line DL1 covers the second channel portion GD2, and the minimum distance between the edge of the first power signal line DL1 and the projection of the second channel portion GD2 on the substrate 21 is D2.

[0148] Among them, D2 < D1.

[0149] As can be seen from the above embodiment, the distance between the first electrode RE and the first channel portion GD1 is greater than the distance between the first power signal line DL1 and the second channel portion GD2, so the ability of the first electrode RE to shield the first channel portion GD1 is less than the ability of the first power signal line DL1 to shield the second channel portion GD2.

[0150] In the embodiment of the present application, D2 < D1 is set, so the range of the first electrode RE shielding the first channel portion GD1 can be greater than the range of the first power signal line DL1 shielding the second channel portion GD2, so that it becomes possible for the first electrode RE to shield the external light entering the first channel portion GD1 at the same angle as the first power signal line DL1 to shield the external light entering the second channel portion GD2, and it further becomes possible for the first transistor T1 and the second transistor T2 to be shielded to the same degree, which is beneficial to realize the synchronous shielding of the first transistor T1 and the second transistor T2, and further beneficial to realize the same change in brightness of different color sub-pixels and realize no obvious color cast of the display panel.

[0151] FIG. 22 is a layout schematic diagram of another display panel provided by an embodiment of the present application.

[0152] In an embodiment of the present application, in combination with FIG. 1 and FIG. 22, the display panel 01 includes a plurality of sub-pixels P of different colors, and for the same sub-pixel P, the first power signal line DL1 covers the first transistor T1 and the second transistor T2 in the direction perpendicular to the plane where the display panel 01 is located.

[0153] Optionally, the first transistor T1 and the second transistor T2 in the same sub-pixel P are covered by the same first power signal line DL1.

[0154] It can be understood that in the pixel circuit 11 of the same sub-pixel P, the first transistor T1 and the second transistor T2 can be arranged closer.

[0155] In the embodiment of the present application, the first power signal line DL1 covers the first transistor T1 and the second transistor T2 of the same sub-pixel P, which is beneficial to reduce the difficulty of covering the first transistor T1 and the second transistor T2 in the process and reduce the preparation difficulty of the display panel 01.

[0156] Moreover, since the film layer where the first power signal line DL1 is located is closer to the channel region of the transistor, the first power signal line DL1 is more likely to shield the external light entering the first transistor T1 and the second transistor T2 at a larger angle, which is beneficial to improve the shielding ability of the first transistor T1 and the second transistor T2.

[0157] Please continue to refer to FIG. 22, in an embodiment of the present application, the first transistor T1 includes a first channel portion GD1, the second transistor T2 includes a second channel portion GD2, in the same sub-pixel P, along the direction perpendicular to the plane where the display panel 01 is located, the first power signal line DL1 covers the first channel portion GD1, the minimum distance between the edge of the first power signal line DL1 and the projection of the first channel portion GD1 on the substrate 21 is D3; the first power signal line DL1 covers the second channel portion GD2, the minimum distance between the edge of the first power signal line DL1 and the projection of the second channel portion GD2 on the substrate 21 is D4.

[0158] Wherein, D4 < D3.

[0159] Since the first transistor T1 can be the threshold compensation transistor M1 in FIG. 2, and the second transistor T2 can be the gate initialization transistor M2 in FIG. 2, in combination with FIG. 2, the first electrode of the second transistor T1 is electrically connected with the gate electrode of the driving transistor Td, the second electrode is electrically connected with the first reset signal line XL1, and the gate electrode is electrically connected with the first scan line SL1. Since the reset voltage Vref1 transmitted by the first reset signal line XL1 has a low potential, the drain current of the second transistor T1 will cause the potential of the gate electrode of the driving transistor to decrease. The first electrode of the first transistor T1 is electrically connected with the gate electrode of the driving transistor Td, the second electrode is electrically connected with the first electrode of the driving transistor Td, and the gate electrode is electrically connected with the second scan line SL2. Since the potential of the first electrode of the driving transistor Td is high in the light-emitting stage, the drain current of the first transistor T1 will cause the potential of the gate electrode of the driving transistor Td to increase.

[0160] In the embodiment of the present application, D4 < D3 is set, so that the range of the first power signal line DL1 shielding the first channel portion GD1 can be greater than the range of the first power signal line DL1 shielding the second channel portion GD2, so that the angle of the external light that can be shielded by the first power signal line DL1 and enter the first channel portion GD1 can be greater than the angle of the external light that can be shielded by the first power signal line DL1 and enter the second channel portion GD2, so that the drain current of the first transistor T1 is less than the drain current of the second transistor T2, which is conducive to reducing the potential of the gate electrode of the driving transistor Td, thereby being conducive to improving the brightness of the sub-pixel P.

[0161] It should be noted that, in order to facilitate the display of the layout of the display panel, FIG. 22 only shows the channel layer, the gate layer, the first electrode RE and the film layer where the first power signal line DL1 is located of the transistor.

[0162] Optionally, the same sub-pixel P is a green sub-pixel. That is, in the green sub-pixel, the angle of the external light that can be shielded by the first power signal line DL1 and enter the first channel portion GD1 can be greater than the angle of the external light that can be shielded by the first power signal line DL1 and enter the second channel portion GD2.

[0163] In this way, the brightness of the green sub-pixel can be improved, and since the green sub-pixel contributes more to the brightness of the display panel, the brightness of the display panel 01 can be improved.

[0164] Please continue to refer to FIG. 2. The pixel circuit 11 further includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. The first electrode of the third transistor T3 is electrically connected with the data line DL2, the second electrode is electrically connected with the second electrode of the driving transistor Td, and the gate electrode is electrically connected with the second scan line SL2. The third transistor T3 is configured to transmit the data voltage Vdata to the driving transistor Td.

[0165] The first electrode of the fourth transistor T4 is electrically connected with the first power signal line DL1, the second electrode is electrically connected with the second electrode of the driving transistor Td, and the gate electrode is electrically connected with the light-emitting control signal line EM. The fourth transistor T4 is configured to transmit the voltage PVDD on the first power signal line DL1 to the driving transistor Td.

[0166] The first electrode of the fifth transistor T5 is electrically connected with the first electrode of the driving transistor Td, the second electrode is electrically connected with the light-emitting device 12, and the gate electrode is electrically connected with the light-emitting control signal line EM. The fifth transistor T5 is configured to transmit the light-emitting driving current to the light-emitting device 12.

[0167] The first electrode of the sixth transistor T6 is electrically connected with the second reset signal line XL2, the second electrode is electrically connected with the light-emitting device 12, and the gate electrode is electrically connected with the second scan line SL2. The sixth transistor T6 is configured to transmit the reset voltage Vref2 on the second reset signal line XL2 to the light-emitting device 12, so as to complete the reset of the light-emitting device 12.

[0168] One plate of the storage capacitor Cst is electrically connected with the gate electrode of the driving transistor Td, and the other plate is electrically connected with the first power signal line DL1.

[0169] The working process of the pixel circuit 11 driving the light-emitting device 12 to emit light can be the same as the prior art, which will not be described here.

[0170] FIG. 23 is a schematic diagram of a display device provided in an embodiment of the present application.

[0171] The embodiment of the present application further provides a display device 02, as shown in FIG. 23, which includes the display panel 01 provided in the above embodiment. Exemplarily, the display device 02 is an electronic device such as a mobile phone, a computer, a television, a vehicle-mounted display, etc., which is not limited in the present application.

[0172] In the display device 02, the first electrode RE and the first power signal line DL1 cover at least part of the first transistor T1, so that the illumination of the first transistor T1 by ambient light can be reduced, which is beneficial to improve the influence of the large leakage current of the first transistor T1 on the gate potential of the driving transistor Td, and further beneficial to improve the poor brightness stability of the display panel 01 and improve the display effect.

[0173] Meanwhile, since the first electrode RE and the first power signal line DL1 are located in different film layers, they can cooperate to shield the first transistor T1, which is beneficial to avoid the spatial limitation problem of shielding the first transistor T1 by using the same film layer, thereby avoiding the problem of large-angle ambient light entering the first transistor, and further improving the leakage current problem of the first transistor.

[0174] Moreover, the first electrode RE and the first power signal line DL1 can shield the first transistor in different pixel circuits 11, which is beneficial to realize synchronous shielding of the first transistor T1 in different pixel circuits 11, so that the brightness of sub-pixels of different colors can change uniformly, and the large-angle color cast problem of the display panel 01 can be avoided. In addition, the shielding degree of the first electrode RE and the first power signal line DL1 on the first transistor T1 in different pixel circuits 11 can be flexibly adjusted according to the needs, so as to meet the different display requirements of the display panel 01.

[0175] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a driving transistor and a first transistor. The display panel further comprises a substrate, an array layer, and an organic light-emitting layer. The organic light-emitting layer comprises a first electrode layer, an organic layer, and a second electrode layer. The first electrode layer comprises a first electrode. The first electrode covers at least part of the first transistor in a direction perpendicular to a plane in which the display panel is located.

2. The display panel of claim 1, wherein, The array layer comprises a first power signal line, and the first power signal line covers at least part of the first transistor.

3. The display panel of claim 2, wherein, The display panel comprises sub-pixels of different colors, and the first electrode and the first power signal line cover different first transistors in a direction perpendicular to a plane in which the display panel is located.

4. The display panel of claim 3, wherein, The plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first electrode covers first transistors of the first sub-pixel and the second sub-pixel, and the first power signal line covers a first transistor of the third sub-pixel in a direction perpendicular to a plane in which the display panel is located.

5. The display panel of claim 4, wherein, The pixel circuits of the first sub-pixel and the second sub-pixel are arranged adjacently.

6. The display panel of claim 2, wherein, The first sub-pixel is a blue sub-pixel, and the second sub-pixel is any one of a green sub-pixel and a red sub-pixel.

7. The display panel of claim 1, wherein, The first electrode covers the first transistor of the green sub-pixel, and the first power signal line covers the first transistors of the blue sub-pixel and the red sub-pixel in a direction perpendicular to a plane in which the display panel is located.

8. The display panel of claim 7, wherein, The display panel comprises sub-pixels of different colors, and the first electrode and the first power signal line cover the same first transistor in a direction perpendicular to a plane in which the display panel is located. The first power signal line comprises a first portion and a second portion, and the second portion covers at least part of the first transistor in a direction perpendicular to a plane in which the display panel is located.

9. The display panel of claim 7, wherein, The first transistor comprises a first channel portion, and a minimum distance between a projection of an edge of the second portion on the substrate and a projection of the first channel portion on the substrate is S1, and a minimum distance between an edge of the first electrode and the projection of the first channel portion on the substrate is S2, and S1 > S2.

10. The display panel of claim 1, wherein, The first transistor is from a green sub-pixel.

11. The display panel of claim 1, wherein, The array layer comprises a data line, and the first power signal line and the data line are located in the same layer. The display panel comprises a display area and a non-display area arranged around the display area, the display area comprises a first display area and a second display area arranged adjacently, the first display area is located on a side of the second display area close to an edge of the display panel, the first display area comprises a first data line, the non-display area comprises a fan-out line, the first data line is electrically connected to the fan-out line through a fan-out data line, the fan-out data line comprises a first line segment and a second line segment, the second line segment has the same extension direction as the first data line, the first data line and the second line segment are located in different film layers, and the first power signal line and the second line segment are located in the same film layer.

12. The display panel of claim 1, wherein, The pixel circuit further comprises a second transistor, which is electrically connected with the driving transistor and the first transistor, and the first electrode and / or the first power signal line covers at least part of the second transistor in a direction perpendicular to a plane where the display panel is located.

13. The display panel of claim 12, wherein, The display panel comprises sub-pixels of different colors, and for the same sub-pixel, the first electrode covers the first transistor and the first power signal line covers the second transistor in a direction perpendicular to a plane where the display panel is located.

14. The display panel of claim 13, wherein, The first transistor comprises a first channel portion and the second transistor comprises a second channel portion, and a minimum distance between an edge of the first electrode and a projection of the first channel portion on the substrate in a direction perpendicular to a plane where the display panel is located is D1, and a minimum distance between an edge of the first power signal line and a projection of the second channel portion on the substrate in the direction is D2, wherein D2 < D1.

15. The display panel of claim 12, wherein, The display panel comprises sub-pixels of different colors, and for the same sub-pixel, the first power signal line covers the first transistor and the second transistor in a direction perpendicular to a plane where the display panel is located.

16. The display panel of claim 15, wherein, The first transistor comprises a first channel portion and the second transistor comprises a second channel portion, and a minimum distance between an edge of the first power signal line and a projection of the first channel portion on the substrate in a direction perpendicular to a plane where the display panel is located is D3, and a minimum distance between an edge of the first power signal line and a projection of the second channel portion on the substrate in the direction is D4, wherein D4 < D3.

17. The display panel of claim 16, wherein, The same sub-pixel is a green sub-pixel.

18. The display panel of claim 12, wherein, The first transistor is a threshold compensation transistor and the second transistor is a gate initialization transistor.

19. The display panel of claim 1, wherein, The first transistor comprises a first channel portion, and a distance between an edge of the first electrode and a projection of the first channel portion on the substrate in a direction perpendicular to a plane where the display panel is located is 2.5 μm-10.5 μm.

20. The display panel of claim 1, wherein, The first transistor comprises a first channel portion, and a distance between an edge of the first power signal line and a projection of the first channel portion on the substrate in a direction perpendicular to a plane where the display panel is located is 1 μm-7 μm.

21. The display panel of claim 20, wherein, The distance is 1-2 μm.

22. The display panel of claim 20, wherein, The distance is 2-3 μm.

23. The display panel of claim 20, wherein, The distance is 6-7 μm.

24. A display device comprising: The display panel comprises the pixel circuit as claimed in any one of claims 1-23.

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