Semiconductor structure and preparation method therefor, and storage array, memory, logic device and electronic device

Abstract

Provided in the embodiments of the present application are a semiconductor structure and a preparation method therefor, and a storage array, a memory, a logic device and an electronic device, which aim to increase the contact area of a gate electrode with respect to a gate dielectric layer, thereby improving the control capability of the gate electrode. In the semiconductor structure provided in the embodiments of the present application, a gate electrode comprises a first surface, which faces a side wall of a channel column, and a second surface, which is adjacent to the first surface; and a gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer, which are connected to each other, wherein the first gate dielectric layer is located between the channel column and the first surface, and the second gate dielectric layer covers the second surface, so as to increase the contact area of the gate electrode with respect to the gate dielectric layer, thereby improving the control capability of the gate electrode, and thus improving the performance of a transistor.

Description

Semiconductor structure, method of manufacturing the same, memory array, memory, logic device, and electronic device

[0001] This application claims priority to the Chinese patent application No. 202410650333.2, filed on May 23, 2024, and entitled “Semiconductor structure, method of manufacturing the same, memory array, memory, logic device, and electronic device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of storage devices, in particular to a semiconductor structure, a method of manufacturing the same, a memory array, a memory, a logic device, and an electronic device. BACKGROUND

[0003] In the manufacturing process of a dynamic random access memory (DRAM), a channel hole is etched on a gate, then a gate dielectric layer is formed on the inner wall of the channel hole, and then a channel pillar is formed to form a transistor. The surface of the gate of the transistor formed by the above steps faces the surface of the channel pillar and has a small contact with the gate dielectric layer, and the control ability of the gate is insufficient, which affects the performance of the transistor. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure, a method of manufacturing the same, a memory array, a memory, a logic device, and an electronic device, which aims to increase the contact area between the gate and the gate dielectric layer, thereby improving the control ability of the gate.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In one aspect, the present application provides a semiconductor structure, the semiconductor structure comprising a transistor, wherein the transistor comprises a channel pillar, a first insulating layer, a gate, and a gate dielectric layer, the channel pillar penetrating through the first insulating layer, the gate being disposed adjacent to the first insulating layer in the extension direction of the channel pillar, the gate comprising a first surface facing the sidewall of the channel pillar and a second surface facing the first insulating layer; the gate dielectric layer comprising a first gate dielectric layer and a second gate dielectric layer connected in series, the first gate dielectric layer being located between the channel pillar and the first surface, and the second gate dielectric layer being located on the side of the second surface facing the first insulating layer. Through the above arrangement, the second gate dielectric layer located on the side of the second surface facing the first insulating layer increases the dielectric constant between the gate and the first insulating layer, improves the equivalent capacitance between the gate and the end of the transistor close to the first insulating layer, reduces the leakage current between the end of the transistor close to the first insulating layer and the gate, improves the control ability of the gate on the transistor, and at the same time reduces the power consumption of the transistor and improves the performance of the transistor.

[0007] In some embodiments, the semiconductor structure further comprises a second insulating layer, the second insulating layer and the first insulating layer are arranged in a spaced manner along the extension direction of the channel column, and the gate electrode is located between the first insulating layer and the second insulating layer; the gate electrode further comprises a third surface, the third surface is arranged to face the second insulating layer; and the gate dielectric layer further comprises a third gate dielectric layer, the third gate dielectric layer is located on the side of the third surface facing the second insulating layer.

[0008] Through the above arrangement, on the basis of the second gate dielectric layer being located between the gate electrode and the first insulating layer, the third gate dielectric layer being located on the side of the third surface facing the second insulating layer, the second insulating layer and the first insulating layer being arranged in a spaced manner along the extension direction of the channel column, and the gate electrode being located between the first insulating layer and the second insulating layer, the third gate dielectric layer located on the side of the third surface facing the second insulating layer increases the dielectric constant between the gate electrode and the second insulating layer, improves the equivalent capacitance between the gate electrode and the transistor near the second insulating layer, reduces the leakage current between the transistor near the second insulating layer and the gate electrode, improves the control ability of the gate electrode on the transistor, and at the same time reduces the power consumption of the transistor and improves the performance of the transistor.

[0009] In some embodiments, the gate electrode comprises a first gate electrode layer and a second gate electrode layer, and the first gate electrode layer is located between the second gate electrode layer and the gate dielectric layer.

[0010] Through the above arrangement, the gate electrode formed by sequentially forming the first gate electrode layer and the second gate electrode layer can reduce damage to the gate dielectric layer when the gate electrode is formed.

[0011] In some embodiments, the channel column comprises a first channel layer and a filling column, the first channel layer is arranged on the sidewall of the filling column, and the first gate dielectric layer is located between the first channel layer and the first surface.

[0012] Through the above arrangement, the first channel layer is arranged on the sidewall of the filling column to form the channel column, and in other words, the filling column occupies the structure surrounded by the first channel layer. In an embodiment in which the two ends of the first channel layer are respectively connected to the first electrode and the second electrode, the filling column can limit the distance from the first electrode to the gate electrode and limit the distance from the second electrode to the gate electrode.

[0013] In some embodiments, the transistor further comprises a first electrode, the channel column further comprises a second channel layer, the second channel layer covers the first end surface of the filling column and is connected to the first channel layer, the first electrode is arranged to face the first end surface, and the second channel layer is in contact with the first electrode.

[0014] Through the above arrangement, the first electrode is arranged to face the first end surface, the first channel layer and the second channel layer jointly form a channel, the second channel layer is in contact with the first electrode, and the contact area of the channel in the channel column with the first electrode is increased, thereby improving the electrical properties of the transistor.

[0015] In some embodiments, the transistor further comprises a second electrode, the filling column further comprises a second end surface, the second end surface is arranged opposite to the first end surface, the second electrode is arranged facing the second end surface, and the second electrode is in contact with the first channel layer.

[0016] Through the above arrangement, the first electrode and the second electrode are respectively located at two ends of the channel column in the extending direction, the gate electrode is located between the first electrode and the second electrode, and the gate electrode is arranged on the side wall of the channel column. The conduction or cutoff of the channel column can be controlled by controlling the current of the gate electrode, so as to read data in the storage capacitor connected with the second electrode or write data into the storage capacitor.

[0017] In some embodiments, the first channel layer comprises a first contact surface parallel to the side wall of the filling column, and a second contact surface adjacent to the first contact surface, and the second electrode is in contact with the second contact surface and part of the first contact surface.

[0018] Through the above arrangement, the distance between the second electrode and the gate electrode is fixed through the second contact surface in contact with the second electrode, and the second electrode is also in contact with part of the first contact surface, so as to reduce the distance between the second electrode and the gate electrode and improve the electrical property of the transistor.

[0019] In some embodiments, the channel column further comprises a third channel layer, the third channel layer is located at one end of the first channel layer away from the second channel layer and connected with the first channel layer, and the third channel layer extends away from the filling column.

[0020] Through the above arrangement, the second electrode is arranged facing the second end surface, the first channel layer, the second channel layer and the third channel layer jointly form a channel, the third channel layer and the first channel layer jointly form a source electrode of the channel at the end close to the second electrode, and the third channel layer extends away from the filling column, so as to increase the contact area between the channel in the channel column and the second electrode and improve the electrical property of the transistor.

[0021] In some embodiments, the third channel layer and the second end surface form a groove, the second electrode is in contact with the third channel layer, and part of the second electrode is filled in the groove.

[0022] Through the above arrangement, the relative position between the third channel layer and the gate electrode is fixed, and part of the second electrode is located in the groove formed by the third channel layer and the second end surface of the filling column, so as to also reduce the distance between the second electrode and the gate electrode and improve the electrical property of the transistor.

[0023] In some embodiments, at least one of the first channel layer, the second channel layer and the third channel layer comprises an oxide semiconductor, so as to reduce the refresh frequency of the transistor by utilizing the low leakage characteristic of the oxide semiconductor, and further reduce the power consumption of the transistor.

[0024] In some embodiments, the semiconductor structure includes a plurality of transistors, and the center lines of the channel pillars in each transistor are arranged in parallel. The semiconductor structure further includes a first isolation layer, which covers the outer side of each transistor.

[0025] Through the above arrangement, the first isolation layer can isolate the two adjacent transistors, reduce the diffusion of hydrogen ions and oxygen ions between the internal and external structures of the transistor, and increase the electrical properties of the transistor. For example, in the embodiment in which the first channel layer, the second channel layer, and the third channel layer are oxide semiconductors, the diffusion of oxygen ions in the oxide semiconductor to the adjacent film layers can be prevented, thereby reducing the electrical properties of the transistor; at the same time, the diffusion of hydrogen ions in the adjacent film layers to the oxide semiconductor can be prevented, thereby reducing the electrical properties of the transistor.

[0026] In some embodiments, the semiconductor structure includes a plurality of transistors, and the center lines of the channel pillars in each transistor are arranged in parallel. The semiconductor structure further includes an insulating structure between the two adjacent transistors and a second isolation layer between the second electrode in the transistor and the insulating structure.

[0027] Through the above arrangement, the second isolation layer can isolate the second electrode and the insulating structure, and prevent the oxidation of the second electrode caused by the oxidation environment in the process of forming the insulating structure.

[0028] In some embodiments, the semiconductor structure includes a plurality of array regions and an isolation region arranged between two adjacent array regions. A plurality of transistors are arranged in an array in each array region, and an isolation structure is arranged in the isolation region.

[0029] Through the above arrangement, the isolation region is arranged between the two array regions, which facilitates the formation of the gate dielectric layer and the gate electrode layer of the plurality of transistors in the array region through one isolation region, and thus the storage density of the semiconductor structure can be increased by reducing the distance between the adjacent transistors in the same array region.

[0030] In some embodiments, the gate surrounds the channel pillar, which can increase the area of the gate covering the sidewall of the channel pillar, thereby improving the control ability of the gate over the channel pillar and further improving the performance of the transistor.

[0031] In some embodiments, the gate includes a first gate and a second gate, and the channel pillar is located between the first gate and the second gate, which can increase the area of the gate covering the sidewall of the channel pillar, thereby improving the control ability of the gate over the channel pillar and further improving the performance of the transistor.

[0032] On the other hand, the embodiments of the present application also provide a storage array, wherein the storage array includes the semiconductor structure described above and a storage capacitor connected to the transistor.

[0033] In the above embodiment, the storage capacitors are multiple, the transistors in the semiconductor structure are also multiple, the multiple storage capacitors are connected in correspondence with the multiple transistors, and the storage array further comprises a third isolation layer, which is arranged between two adjacent storage capacitors.

[0034] Through the above arrangement, the third isolation layer, together with the first and second isolation layers, isolates the adjacent transistors.

[0035] In another aspect, the embodiment of the present application further provides a preparation method of a semiconductor structure, comprising:

[0036] forming a stack structure, the stack structure comprising an initial first electrode, an initial first insulating layer, a dummy gate layer, an initial second insulating layer, and a mask layer arranged in layers;

[0037] forming multiple channel holes on the stack structure, and forming a dummy channel column in the channel holes, the dummy channel column penetrating through the mask layer, the first insulating layer, the dummy gate layer, and the second insulating layer;

[0038] removing the dummy gate layer to form a first gap layer, and forming a gate dielectric layer and a gate in the first gap layer, the gate comprising a first surface facing a sidewall of the channel column and a second surface adjacent to the first surface, the gate dielectric layer comprising a first gate dielectric layer and a second gate dielectric layer connected in series, the first gate dielectric layer being located between the channel column and the first surface, and the second gate dielectric layer covering the second surface;

[0039] removing the dummy channel column and forming a channel column in the channel hole.

[0040] In some embodiments, forming multiple channel holes on the stack structure comprises: forming multiple channel holes in each array region on the stack structure;

[0041] removing the dummy gate layer to form a first gap layer comprises: forming a replacement slit in an isolation region of the stack structure, the replacement slit being located between two adjacent array regions and penetrating through the mask layer, the second insulating layer, and the dummy gate layer; and removing the dummy gate layer through the replacement slit to form the first gap layer.

[0042] Through the above arrangement, the multiple dummy channel columns all penetrate through the dummy gate layer, which can also be said that the dummy gate layer surrounds the multiple dummy channel columns. The dummy gate layer surrounding the multiple dummy channel columns can be removed through the replacement slit between the adjacent array regions, so that the replacement of the dummy gate layer is realized at the same time, the number of replacement slits arranged on the semiconductor structure can be reduced, and thus the storage density of the semiconductor structure is increased.

[0043] In the above embodiments, forming the gate dielectric layer and the gate electrode in the first void layer includes: forming an initial gate dielectric layer and an initial gate electrode in the first void layer; forming an isolation structure in the replacement slit; forming a first slit between two adjacent pseudo-channel pillars, the first slit penetrating the second insulating layer, the initial gate dielectric layer and the initial gate electrode; and forming a first insulating structure in the first slit.

[0044] Through the above arrangement, the replacement slit is first formed in the isolation region between the adjacent array regions, and the pseudo-gate layer is removed through the replacement slit, and then the isolation structure is formed in the replacement slit, so as to realize the insulation between the transistors located in different array regions; and then the first slit is formed between the two adjacent pseudo-channel pillars, and the first insulating structure is formed in the first slit, so as to realize the isolation between the transistors in the same array region.

[0045] In some other embodiments, removing the pseudo-gate layer to form the first void layer includes: forming a first slit between two adjacent pseudo-channel pillars, the first slit penetrating the second insulating layer; removing the pseudo-gate layer through the first slit to form the first void layer; and after forming the gate dielectric layer and the gate electrode in the first void layer, forming a first insulating structure in the first slit.

[0046] Through the above arrangement, the pseudo-gate layer is removed through the first slit for forming the first insulating structure for isolating the adjacent transistors, compared with the previous embodiment, the semiconductor structure does not need to be provided with the isolation structure in the isolation region, thereby increasing the density of the transistors in the semiconductor structure and improving the performance of the semiconductor structure.

[0047] In some embodiments, forming the first slit includes: removing the mask layer to expose the sidewall of the pseudo-channel pillar and the second insulating layer; forming an initial shielding layer and removing a portion of the initial shielding layer between the two adjacent pseudo-channel pillars to form a second slit; the remaining portion of the initial shielding layer forms a shielding layer, and the shielding layer is located on the sidewall of the pseudo-channel pillar; and the first slit is formed through the second slit.

[0048] Through the above arrangement, the position of the second slit can be adjusted by setting the position of the initial shielding layer, so that the position of the first slit is formed between the two adjacent pseudo-channel pillars.

[0049] In some embodiments, before forming the first insulating structure in the first slit, the preparation method further includes: forming a first isolation layer in the first slit, so that the first isolation layer covers the second insulating layer, the gate electrode, the second gate dielectric layer and the first insulating layer, and isolates the two adjacent transistors.

[0050] In some embodiments, the removing the dummy channel pillars and forming channel pillars in the channel holes comprises: removing the dummy channel pillars; forming an initial channel layer in the channel holes and forming the fill pillars; forming an initial second electrode on the initial channel layer; forming a third slit through the initial second electrode; and removing part of the initial channel layer through the third slit.

[0051] Through the above arrangement, the third slit can expose the initial third channel layer between the two adjacent fill pillars. Part of the initial third channel layer is removed through the third slit to achieve isolation between the channel layers of the two adjacent transistors.

[0052] In some embodiments, before forming the second insulating structure in the third slit, the method further comprises forming a second isolation layer in the third slit, so that the second isolation layer covers the second electrode. After forming the above-mentioned insulating structure, the second isolation layer is located between the second electrode and the insulating structure, so as to isolate the second electrode and the insulating structure, and prevent the second electrode from being oxidized in the oxidation environment in the process of forming the insulating structure.

[0053] In some embodiments, before forming the initial second electrode, the preparation method further comprises: forming an initial fill pillar, and removing part of the initial fill pillar located in the channel hole to form the fill pillar; and forming the initial second electrode on the fill pillar.

[0054] Through the above arrangement, part of the final second electrode can be located in the groove formed by the third channel layer and the second end surface of the fill pillar, which can also reduce the distance between the second electrode and the gate, and improve the electrical properties of the transistor.

[0055] In some embodiments, the initial fill pillar can be formed in multiple times to avoid the generation of voids in the process of forming the initial fill pillar, thereby weakening the supporting effect of the fill pillar.

[0056] In another aspect, the embodiments of the present application also provide a memory, wherein the memory comprises the above-mentioned memory array and a controller, and the controller is connected with the memory array.

[0057] In another aspect, the embodiments of the present application also provide a logic device, wherein the logic circuit comprises the above-mentioned semiconductor structure and a gate circuit, and the semiconductor structure is connected with the gate circuit.

[0058] In another aspect, the embodiments of the present application also provide an electronic device, wherein the electronic device comprises the above-mentioned memory and a circuit board, and the memory is connected with the circuit board. And / or, the electronic device comprises the above-mentioned logic device and a circuit board, and the logic device is connected with the circuit board.

[0059] It can be understood that the semiconductor structure preparation method, the storage array, the memory, the logic device and the electronic device provided by the above-mentioned embodiments of the present application have the beneficial effects of the semiconductor structure, which are described above, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings described in the following are only some drawings of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following can be regarded as schematic diagrams, and are not limited to the actual size of the product, the actual process of the method, the actual time sequence of the signal, etc. involved in the embodiments of the present application.

[0061] Fig. 1 is a block diagram of an electronic device in an embodiment of the present application;

[0062] Fig. 2 is a block diagram of a memory in an embodiment of the present application;

[0063] Fig. 3 is a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0064] Fig. 4 is a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0065] Fig. 5 is a cross-sectional view of a gate of a semiconductor structure provided in an embodiment of the present application;

[0066] Fig. 6 is a cross-sectional view of a gate of a semiconductor structure provided in an embodiment of the present application;

[0067] Fig. 7 is a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0068] Fig. 8 is a structural schematic diagram of a storage array provided in an embodiment of the present application;

[0069] Fig. 9 is a flow chart of a semiconductor structure preparation method in an embodiment of the present application;

[0070] Fig. 10 is a structural schematic diagram after forming a laminated structure in an embodiment of the present application;

[0071] Fig. 11 is a structural schematic diagram after forming a channel hole in an embodiment of the present application;

[0072] Fig. 12 is a structural schematic diagram after forming a pseudo channel column in an embodiment of the present application;

[0073] Fig. 13 is a structural schematic diagram after forming a channel hole in an embodiment of the present application;

[0074] Fig. 14 is a structural schematic diagram after forming a replacement gap in an embodiment of the present application;

[0075] Figure 15 is a structure diagram for removing the dummy gate layer through the first gap in the embodiment of the present application;

[0076] Figure 16 is a structure diagram after forming the initial gate dielectric layer in the embodiment of the present application;

[0077] Figure 17 is a structure diagram after forming the initial gate in the embodiment of the present application;

[0078] Figure 18 is a structure diagram after forming the initial gate in the embodiment of the present application;

[0079] Figure 19 is a structure diagram after removing part of the initial gate in the embodiment of the present application;

[0080] Figure 20 is a structure diagram after forming the isolation structure in the embodiment of the present application;

[0081] Figure 21 is a structure diagram after removing the mask layer in the embodiment of the present application;

[0082] Figure 22 is a structure diagram after forming the initial shielding layer in the embodiment of the present application;

[0083] Figure 23 is a structure diagram after forming the shielding layer in the embodiment of the present application;

[0084] Figure 24 is a structure diagram after forming the first gap in the embodiment of the present application;

[0085] Figure 25 is a structure diagram after forming the first gap in the embodiment of the present application;

[0086] Figure 26 is a structure diagram after forming the first insulating structure in the embodiment of the present application;

[0087] Figure 27 is a structure diagram after forming the first insulating structure in the embodiment of the present application;

[0088] Figure 28 is a structure diagram after removing the mask layer in the embodiment of the present application;

[0089] Figure 29 is a structure diagram after forming the shielding layer in the embodiment of the present application;

[0090] Figure 30 is a structure diagram after forming the first gap in the embodiment of the present application;

[0091] Figure 31 is a structure diagram for removing the dummy gate layer through the first gap in the embodiment of the present application;

[0092] Figure 32 is a structure diagram after forming the gate dielectric layer and the gate in the embodiment of the present application;

[0093] Figure 33 is a structure diagram after forming the first insulating structure in the embodiment of the present application;

[0094] Figure 34 is a schematic view of a structure after removing dummy trench pillars in an embodiment of the present application;

[0095] Figure 35 is a schematic view of a structure after forming an initial channel layer in an embodiment of the present application;

[0096] Figure 36 is a schematic view of a structure after forming an initial filling layer in an embodiment of the present application;

[0097] Figure 37 is a schematic view of a structure after forming a filling layer in an embodiment of the present application;

[0098] Figure 38 is a schematic view of a structure after forming an initial second electrode in an embodiment of the present application;

[0099] Figure 39 is a schematic view of a structure after forming a second electrode in an embodiment of the present application;

[0100] Figure 40 is a schematic view of a structure after forming a second insulating structure in an embodiment of the present application;

[0101] Figure 41 is a schematic view of a structure after forming a second insulating structure in an embodiment of the present application;

[0102] Figure 42 is a schematic view of a structure after forming a second insulating structure in an embodiment of the present application;

[0103] Figure 43 is a schematic view of a structure after forming a second electrode in an embodiment of the present application;

[0104] Figure 44 is a schematic view of a structure after forming a third isolation layer in an embodiment of the present application;

[0105] Explanation of reference signs: 1, semiconductor structure; 2, transistor; 3, channel pillar; 4, gate; 5, first surface; 6, second surface; 7, gate dielectric layer; 8, first gate dielectric layer; 9, second gate dielectric layer; 10, third surface; 11, first gate layer; 12, second gate layer; 13, first gate; 14, second gate; 15, first channel layer; 16, fill pillar; 17, first electrode; 18, second electrode; 19, storage capacitor; 20, second channel layer; 21, first end surface; 22, second end surface; 23, first contact surface; 24, second contact surface; 25, third channel layer; 26, first insulating layer; 27, second insulating layer; 28, first electrode layer; 29, first contact layer; 30, first isolation layer; 31, insulating structure; 311, first insulating structure; 312, second insulating structure; 32, second isolation layer; 33, array region; 34, isolation region; 35, isolation structure; 36, storage array; 37, third isolation layer; 38, stack structure; 39, initial first electrode; 41, dummy gate layer; 43, mask layer; 44, initial first electrode layer; 45, initial first contact layer; 46, first mask layer; 47, second mask layer; 48, channel hole; 49, dummy channel pillar; 50, first void layer; 51, replacement slit; 52, initial gate dielectric layer; 53, initial gate; 54, initial second gate dielectric layer; 55, initial first gate layer; 56, initial second gate layer; 57, first slit; 58, initial blocking layer; 59, blocking layer; 60, second slit; 61, initial channel layer; 62, initial third channel layer; 63, initial fill pillar; 64, initial second electrode; 65, third slit; 66, third gate dielectric layer; 67, initial third gate dielectric layer. DETAILED DESCRIPTION

[0106] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will be used to clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0107] Hereinafter, the terms “first”, “second”, and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second”, and the like can explicitly or implicitly include one or more of the features.

[0108] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", "horizontal" and "vertical" are defined with respect to the orientation of the components shown in the drawings, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the orientation of the components shown in the drawings.

[0109] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood in a broad sense, for example, the "connection" can be a fixed connection, or a detachable connection, or an integral connection; can be directly connected, or indirectly connected through an intermediate medium.

[0110] It should be noted that in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or an integral connection; it can also be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate medium, or a communication inside two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0111] Please refer to FIG. 1, some embodiments of the present application provide an electronic device 1000. The electronic device 1000 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, and can also be a personal computer (PC), a server, a workstation, etc.

[0112] The electronic device 1000 can include a memory 100 and a circuit board, the memory 100 being connected with the circuit board; the electronic device 1000 can also include a logic device and a circuit board, the logic device being connected with the circuit board.

[0113] Please refer to FIG. 2, the embodiments of the present application also provide a memory 100. The memory 100 is used for the above-mentioned electronic device, which can include a controller 200 and a storage array 36, the controller 200 being connected with the storage array 36 to control the storage array 36 to store data.

[0114] The memory 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory 100 can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0115] In some embodiments, the memory 100 includes the controller 200 and a plurality of memory arrays 36, and the memory 100 is integrated into a Solid State Drive (SSD).

[0116] Referring to FIGS. 3 and 4, the embodiments of the present application also provide a memory array 36, wherein the memory array 36 includes the semiconductor structure 1 and a storage capacitor 19, and the semiconductor structure 1 includes the transistor 2, and the storage capacitor 19 is connected to the transistor 2 in the semiconductor structure 1.

[0117] The embodiments of the present application also provide a logic device, which includes the semiconductor structure 1 and a gate circuit, and the semiconductor structure 1 is used to form a logic circuit and is connected to the gate circuit. The logic device can include a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units can be independent devices or can be integrated into one or more processors. The gate circuit can include an AND gate, an OR gate, a NOT gate, an NAND gate, an NOR gate, an NAND gate, an XOR gate, etc.

[0118] Referring to FIG. 4, the semiconductor structure 1 provided by the embodiment of the present application is used in the storage array 36, and the transistor 2 in the semiconductor structure 1 can include a channel pillar 3, a first insulating layer 26, and a gate 4. The channel pillar 3 penetrates the first insulating layer 26, and the gate 4 is arranged adjacent to the first insulating layer 26 in the extension direction of the channel pillar 3. The gate 4 includes a first surface 5 facing the sidewall of the channel pillar 3 and a second surface 6 facing the first insulating layer 26. The transistor 2 can further include a gate dielectric layer 7, which includes a first gate dielectric layer 8 and a second gate dielectric layer 9 connected to each other. The first gate dielectric layer 8 is located between the channel pillar 3 and the first surface 5, and the second gate dielectric layer 9 is located on the side of the second surface 6 facing the first insulating layer 26.

[0119] In the above embodiment, the gate 4 can include a metal material, such as tungsten (W), ruthenium (Ru), nickel (Ni), molybdenum (Mo), etc., an alloy material, such as platinum alloy (NiPt), or a conductive oxide or a conductive nitride, such as indium tin oxide (InSnO), titanium nitride (TiN), tantalum nitride (TaN), etc. The gate dielectric layer 7 can include an insulating oxide, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), hafnium silicate (HfSiO4), etc., a nitride, such as silicon nitride (SiN), or a combination of the insulating oxide and the nitride, such as a combination of HfO2 / Al2O3 and SiN. The first gate dielectric layer 8 and the second gate dielectric layer 9 can be formed of the same material in the same step, and the first gate dielectric layer 8 and the second gate dielectric layer 9 can be an integrated structure.

[0120] In some embodiments, the gate dielectric layer 7 in the transistor 2 covers the sidewall of the entire channel pillar 3, and the gate 4 is arranged on the sidewall of the channel pillar 3, so that only the surface of the gate 4 facing the channel pillar 3 is in contact with the gate dielectric layer 7. Compared with the above embodiment, the semiconductor structure 1 provided by the embodiment of the present application includes the first gate dielectric layer 8 and the second gate dielectric layer 9 connected to each other. The first gate dielectric layer 8 is located between the channel pillar 3 and the first surface 5, and the second gate dielectric layer 9 is located on the side of the second surface 6 facing the first insulating layer 26. Through the above arrangement, the second gate dielectric layer 9 located on the side of the second surface 6 facing the first insulating layer 26 increases the dielectric constant between the gate 4 and the first insulating layer 26, improves the equivalent capacitance between the gate 4 and the end of the transistor 2 close to the first insulating layer 26, reduces the leakage current between the end of the transistor 2 close to the first insulating layer 26 and the gate 4, improves the control ability of the gate 4 on the transistor 2, reduces the power consumption of the transistor 2, and improves the performance of the transistor 2.

[0121] In some embodiments, the semiconductor structure 1 further comprises a second insulating layer 27, the second insulating layer 27 and the first insulating layer 26 are arranged in a spaced manner along the extension direction of the channel pillar 3, the gate 4 is located between the first insulating layer 26 and the second insulating layer 27, the gate 4 further comprises a third surface 10, the third surface 10 is arranged to face the second insulating layer 27, the gate dielectric layer 7 further comprises a third gate dielectric layer 66, the third gate dielectric layer 66 is located on the side of the third surface 10 facing the second insulating layer 27, as shown in FIG. 3, in some embodiments, the second surface 6 and the third surface 10 are arranged in a parallel and spaced manner along the vertical direction.

[0122] Through the above arrangement, on the basis that the second gate dielectric layer 9 is located between the gate 4 and the first insulating layer 26, the third gate dielectric layer 66 is located on the side of the third surface 10 facing the second insulating layer 27, the second insulating layer 27 and the first insulating layer 26 are arranged in a spaced manner along the extension direction of the channel pillar 3, the gate 4 is located between the first insulating layer 26 and the second insulating layer 27. The third gate dielectric layer 66 located on the side of the third surface 10 facing the second insulating layer 27 increases the dielectric constant between the gate 4 and the second insulating layer 27, improves the equivalent capacitance between the gate 4 and the end of the transistor 2 close to the second insulating layer 27, reduces the leakage current between the end of the transistor 2 close to the second insulating layer 27 and the gate 4, improves the control ability of the gate 4 on the transistor 2, while reducing the power consumption of the transistor 2 and improving the performance of the transistor.

[0123] In some embodiments, the gate 4 comprises a first gate layer 11 and a second gate layer 12, the first gate layer 11 is located between the second gate layer 12 and the gate dielectric layer 7; wherein part of the first gate layer 11 is located between the second gate layer 12 and the first gate dielectric layer 8, and part of the first gate layer 11 is located between the second gate layer 12 and the second gate dielectric layer 9. Wherein the first gate layer 11 comprises a conductive layer, and the second gate layer 12 comprises a metal layer. In combination with the above embodiments, the first gate layer 11 can comprise a conductive oxide or a conductive nitride, such as InSnO, TiN, TaN, etc.; the second gate layer 12 can comprise a metal material, such as W, Ru, Ni, Mo, etc., or an alloy material, such as NiPt.

[0124] By the above arrangement, the gate 4 formed by sequentially forming the first gate layer 11 and the second gate layer 12 can reduce damage to the gate dielectric layer 7 when forming the gate 4. For example, in an embodiment where the gate 4 only includes metal, the metal can cause some damage to the gate dielectric layer 7 during the process of forming the gate 4; and in an embodiment where the gate 4 includes the first gate layer 11 and the second gate layer 12, the first gate layer 11 includes conductive oxide and the second gate layer 12 includes metal, the conductive oxide between the gate dielectric layer 7 and the metal can reduce the damage to the gate dielectric layer 7. At the same time, since the first gate layer 11 and the second gate layer 12 are formed of different materials, the work function of the finally formed gate 4 can be adjusted.

[0125] Referring to FIG. 5, in some embodiments, the transistor 2 in the above embodiments can include a Gate All Around-FET (GAA-FET), in which the gate 4 can be arranged around the channel pillar 3, which can increase the area of the gate 4 covering the sidewall of the channel pillar 3 to improve the control ability of the gate 4 on the channel pillar 3, thereby improving the performance of the transistor 2. In an embodiment where the transistor 2 includes a Gate All Around-FET, the first surface 5 of the gate 4 is arranged around the sidewall of the channel pillar 3. If the channel pillar 3 is substantially a cylindrical body, the first surface 5 is substantially a sidewall surface of a cylinder; if the channel pillar 3 is substantially a square cylindrical body, the first surface 5 includes four mutually perpendicular surfaces arranged around the channel pillar 3.

[0126] Referring to FIG. 6, in other embodiments, the transistor 2 in the above embodiments can also be a double-gate transistor, in which the gate 4 can include a first gate 13 and a second gate 14, and the channel pillar 3 is located between the first gate 13 and the second gate 14. Similarly, the area of the gate 4 covering the sidewall of the channel pillar 3 can also be increased to improve the control ability of the gate 4 on the channel pillar 3, thereby improving the performance of the transistor 2. In an embodiment where the transistor 2 includes a double-gate transistor, the first surface 5 of the gate 4 is arranged close to the sidewall of the channel pillar 3. If the channel pillar 3 is substantially a cylindrical body, the first surface 5 is substantially a curved surface conforming to the sidewall of the cylinder; if the channel pillar 3 is substantially a square cylindrical body, the first surface 5 is a plane parallel to the sidewall of the channel pillar 3.

[0127] In the above embodiments, in combination with the embodiment where the gate 4 includes the first gate layer 11 and the second gate layer 12, the first gate 13 can include the first gate layer 11 and the second gate layer 12, and the second gate 14 can also include the first gate layer 11 and the second gate layer 12.

[0128] Referring to FIG. 7, in some embodiments, the channel pillar 3 comprises a first channel layer 15 disposed on the sidewall of the fill pillar 16 and a first gate dielectric layer 8 between the first channel layer 15 and the first surface 5. The first channel layer 15 can comprise poly-Si, a-Si, two-dimensional material, oxide semiconductor material (e.g. InGaZnO, InSnO, InGaO, InMgO, etc.). The fill pillar 16 can comprise insulating material, such as silicon oxide, silicon nitride, etc. In some embodiments, the transistor 2 further comprises a first electrode 17 and a second electrode 18 spaced apart along the center line direction of the channel pillar 3, wherein the first electrode 17 can be a bit line and the second electrode 18 is configured to connect with a storage capacitor 19. In combination with the above embodiments, the first channel layer 15 can form a drain at the end close to the first electrode 17 and a source at the end close to the second electrode 18. In combination with FIG. 3, the storage capacitor 19 in the storage array 36 can be connected with the transistor 2 through the second electrode 18 on the transistor 2. Since the semiconductor structure 1 increases the contact area of the gate 4 and the gate dielectric layer 7, the control ability of the gate 4 is improved, and thus the performance of the transistor 2 and the storage array 36 is improved. In combination with the above embodiments, by the above arrangement, the first channel layer 15 is disposed on the sidewall of the fill pillar 16 to form the channel pillar 3. In other words, the fill pillar 16 occupies the structure surrounded by the first channel layer 15. In the embodiment where the first channel layer 15 is connected with the first electrode 17 and the second electrode 18 at both ends respectively, the fill pillar 16 can limit the distance between the first electrode 17 and the gate 4, and limit the distance between the second electrode 18 and the gate 4.

[0129] In the above embodiments, the channel pillar 3 further comprises a second channel layer 20, the fill pillar 16 has a first end surface 21 close to the first electrode 17, and the second channel layer 20 covers the first end surface 21 of the fill pillar 16 and is connected with the first channel layer 15. The second channel layer 20 can also comprise poly-Si, a-Si, two-dimensional material, oxide semiconductor material (e.g. InGaZnO, InSnO, InGaO, InMgO, etc.), and in the embodiment where the second channel layer 20 and the first channel layer 15 have the same material, the second channel layer 20 and the first channel layer 15 are an integral structure. In combination with the above embodiments, the first electrode 17 is disposed facing the first end surface 21, the first channel layer 15 and the second channel layer 20 jointly form a channel, the second channel layer 20 and the first channel layer 15 jointly form a drain of the channel at the end close to the first electrode 17, and the second channel layer 20 is in contact with the first electrode 17, which increases the contact area of the channel and the first electrode 17 in the channel pillar 3 and improves the electrical properties of the transistor 2.

[0130] In the above embodiments, the filling pillar 16 further comprises a second end surface 22 close to the second electrode 18, the second end surface 22 is opposite to the first end surface 21, and the second electrode 18 is arranged to face the second end surface 22, and the second electrode 18 is in contact with the first channel layer 15. In the embodiments in which the second electrode 18 is used to connect the storage capacitor 19 (as shown in FIG. 3), the first electrode 17 and the second electrode 18 are respectively located at two ends of the channel pillar 3 in the extension direction, the gate 4 is located between the first electrode 17 and the second electrode 18, and the gate 4 is arranged on the sidewall of the channel pillar 3. The conduction or cutoff of the channel pillar 3 can be controlled by controlling the current of the gate 4, so as to read the data in the storage capacitor 19 connected with the second electrode 18, or write data into the storage capacitor 19.

[0131] Referring to FIG. 7, in combination with the embodiment in which the second electrode 18 is in contact with the first channel layer 15, in some embodiments, the first channel layer 15 comprises a first contact surface 23 parallel to the sidewall of the filling pillar 16, and a second contact surface 24 adjacent to the first contact surface 23, and the second electrode 18 is in contact with the second contact surface 24 and part of the first contact surface 23; that is, in the embodiment in which the relative position between the first channel layer 15 and the gate 4 is fixed, the distance between the second contact surface 24 in contact with the second electrode 18 and the gate 4 is fixed, and the second electrode 18 is also in contact with part of the first contact surface 23, so as to reduce the distance between the second electrode 18 and the gate 4, and improve the electrical property of the transistor 2.

[0132] In other embodiments, referring to FIG. 4, the channel pillar 3 further comprises a third channel layer 25, the third channel layer 25 is located at one end of the first channel layer 15 away from the second channel layer 20, and is connected with the first channel layer 15, wherein the third channel layer 25 can also comprise poly-Si, a-Si, two-dimensional material, oxide semiconductor material (such as InGaZnO, InSnO, InGaO, InMgO, etc.), and in the embodiment in which the material of the third channel layer 25 is the same as that of the first channel layer 15, the third channel layer 25 and the first channel layer 15 are integrated. In combination with the above embodiment, the second electrode 18 is arranged to face the second end surface 22, the first channel layer 15, the second channel layer 20 and the third channel layer 25 jointly form a channel, the third channel layer 25 and the first channel layer 15 jointly form a source electrode of the channel at one end close to the second electrode 18, and the third channel layer 25 extends away from the filling pillar 16, thereby increasing the contact area of the channel in the channel pillar 3 and the second electrode 18, and improving the electrical property of the transistor 2.

[0133] In the above embodiment, the third channel layer 25 and the second end surface 22 form a recess, the second electrode 18 contacts the third channel layer 25, and part of the second electrode 18 fills in the recess; that is, in the embodiment in which the relative position between the third channel layer 25 and the gate 4 is fixed, part of the second electrode 18 is located in the recess formed by the third channel layer 25 and the second end surface 22 of the filling column 16, which can also reduce the distance between the second electrode 18 and the gate 4, and improve the electrical properties of the transistor 2.

[0134] In the above embodiment, at least one of the first channel layer 15, the second channel layer 20, and the third channel layer 25 includes an oxide semiconductor, so as to reduce the refresh frequency of the transistor 2 by using the low leakage characteristics of the oxide semiconductor, thereby reducing the power consumption of the transistor 2.

[0135] Continuing to refer to FIG. 4, in some embodiments, the transistor 2 further includes a first insulating layer 26 and a second insulating layer 27, wherein the first insulating layer 26 is located between the gate 4 and the second electrode 18 in the center line direction of the channel column 3, and the second insulating layer 27 is located between the gate 4 and the first electrode 17 in the center line direction of the channel column 3. In combination with the above embodiment in which the second surface 6 is the upper surface of the gate 4 and the third surface 10 is the lower surface of the gate 4, the first insulating layer 26 is located between the second surface 6 and the second electrode 18, and the second insulating layer 27 is located between the third surface 10 and the first electrode 17. The second gate dielectric layer 9 can be located between the gate 4 and the first insulating layer 26, thereby increasing the dielectric constant between the gate 4 and the first insulating layer 26; at the same time, the third gate dielectric layer 66 can be located between the gate 4 and the second insulating layer 27, thereby increasing the dielectric constant between the gate 4 and the first insulating layer 26 and the dielectric constant between the gate 4 and the second insulating layer 27; both of which can increase the field effect of the gate 4 in the center line direction of the channel column 3, thereby improving the control ability of the gate 4. The first insulating layer 26 and the second insulating layer 27 can include insulating oxides, insulating nitrides, and carbon oxides, such as SiO, SiN, SiOC, AlO, or other insulating materials.

[0136] In the above embodiments, the first electrode 17 can include a first electrode layer 28 and a first contact layer 29, in some embodiments, the first electrode layer 28 and the first contact layer 29 can each include a metal or conductive oxide or alloy electrode such as W, Ni, Mo, Ru, InSnO, InGaO, InO, NiPt, TiN, and the first electrode layer 28 and the first contact layer 29 can be an integrated structure; in other embodiments, the first electrode layer 28 can include a metal or conductive nitride or alloy electrode such as W, Ni, Mo, Ru, NiPt, TiN, and the first contact layer 29 can include a conductive oxide such as InSnO, ITO, or the like, so that the first contact layer 29 can serve as a buffer layer between the channel pillar 3 and the first electrode layer 28. Similarly, the second electrode 18 can also include a second electrode layer 181 and a second contact layer 182, which will not be described here.

[0137] In some embodiments, referring to FIG. 4, the semiconductor structure 1 can include a plurality of transistors 2, and the plurality of transistors 2 can be arranged in an array, and the center lines of the channel pillars 3 in each transistor 2 are arranged in parallel; referring to FIG. 5 in combination with FIG. 4, in an embodiment in which the transistor 2 is a full-surrounding-gate transistor, the gates 4 in the plurality of transistors 2 are arranged in a row direction, and each gate 4 extends in a column direction, and the plurality of channel pillars 3 arranged in the column direction penetrate the same gate 4; referring to FIG. 6 in combination with FIG. 4, in an embodiment in which the transistor 2 is a double-gate transistor, each channel pillar 3 corresponds to a group of gates 4, and each group of gates 4 includes a first gate 13 and a second gate 14, the first gate 13 and the second gate 14 in the same group of gates 4 are located on both sides of the channel pillar 3 in the row direction, and the plurality of groups of gates 4 are arranged in the row direction, and the plurality of channel pillars 3 arranged in the column direction share the first gate 13 and the second gate 14 in the same group of gates 4. In the above two embodiments, the first electrodes 17 in the plurality of transistors 2 are arranged in the column direction, the plurality of first electrodes 17 extend in the row direction, and the plurality of channel pillars 3 arranged in the row direction are connected to the same first electrode 17.

[0138] Referring to FIG. 7, in some embodiments, the semiconductor structure 1 further comprises a first isolation layer 30 covering the outer side of each transistor 2. In combination with the above-mentioned embodiments in which the plurality of transistors 2 are arranged in an array, the first isolation layer 30 is arranged on both sides of the transistors 2 arranged in the row direction. The first isolation layer 30 is arranged in parallel along the center line of the channel column 3. In some embodiments, as shown in FIG. 4, the first isolation layer 30 can cover the first insulating layer 26, the gate 4, and the gate dielectric layer 7. In other embodiments, as shown in FIG. 7, the first isolation layer 30 can penetrate through the first insulating layer 26, the gate 4, the gate dielectric layer 7, and the second insulating layer 27 to isolate the two adjacent transistors 2, reduce the diffusion of hydrogen (H) and oxygen (O) between the internal and external structures of the transistor 2, and increase the electrical properties of the transistor 2, wherein H and O can include at least one of hydrogen ions and oxygen ions, related groups such as hydroxyl (-OH), molecules O2, and molecules H2. For example, in embodiments in which the first channel layer 15, the second channel layer 20, and the third channel layer 25 are oxide semiconductors, the diffusion of O in the oxide semiconductor to the adjacent film layers can be prevented, thereby reducing the electrical properties of the transistor 2. At the same time, the diffusion of H in the adjacent film layers to the oxide semiconductor can be prevented, thereby reducing the electrical properties of the transistor 2. In the above-mentioned embodiments, the first isolation layer 30 can include at least one of silicon nitride, hafnium oxide, and aluminum oxide.

[0139] In some embodiments, the semiconductor structure 1 further comprises an insulating structure 31 between two adjacent transistors 2, wherein the insulating structure 31 can comprise insulating oxide, insulating nitride, carbon oxide, such as SiO, SiN, SiOC, AIO, or other insulating materials. In combination with the above embodiments, the insulating structure 31 is between the first insulating layers 30 covering the two adjacent transistors 2. In the embodiments where the transistor 2 comprises the second electrode 18, the insulating structure 31 further comprises a second insulating layer 32 between the second electrode 18 of the transistor 2 and the insulating structure 31 to isolate the second electrode 18 and the insulating structure 31, preventing the second electrode 18 from being oxidized in the oxidizing environment during the process of forming the insulating structure 31. In the above embodiments, the second insulating layer 32 can comprise at least one of silicon nitride, hafnium oxide, and aluminum oxide. The second insulating layer 32 and the first insulating layer 30 can comprise the same material, so that the first insulating layer 30 and the second insulating layer 32 are formed in the same step. The second insulating layer 32 and the first insulating layer 30 can also comprise different materials, for example, the first insulating layer 30 covering the gate 4 comprises hafnium oxide, and the second insulating layer 32 covering the second electrode 18 comprises silicon nitride. In the embodiments where the second insulating layer 32 and the first insulating layer 30 comprise different materials, the first insulating layer 30 and the second insulating layer 32 are formed in different steps. In the above embodiments, forming gas annealing (FGA) can be performed during the process of forming the semiconductor structure 1, and the first insulating layer 30 and the second insulating layer 32 can avoid the reduction of the electrical properties of the semiconductor structure caused by H2 molecules in the forming gas annealing.

[0140] Referring to FIG. 8, in the above embodiment, the semiconductor structure 1 further comprises a plurality of array regions 33 and an isolation region 34, the plurality of array regions 33 are arranged at intervals, the isolation region 34 is arranged between two adjacent array regions 33, a plurality of transistors 2 are arranged in each array region 33, and correspondingly, no transistor 2 is arranged in the isolation region 34, and an isolation structure 35 is arranged in the isolation region 34, the isolation structure 35 can comprise insulating oxides, insulating nitrides and carbon oxides, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbon oxide (SiOC), aluminum oxide (AlO), or other insulating materials, etc. It can be understood that the distance between two transistors 2 arranged in two adjacent array regions 33 is greater than the distance between two adjacent transistors 2 arranged in the same array region 33 due to the isolation structure 35 arranged between the two transistors 2. Through the above arrangement, the isolation region 34 is arranged between two array regions 33, so as to facilitate forming the gate dielectric layer 7 and the gate electrode 4 of the plurality of transistors 2 in the array region 33 through one isolation region 34, and further, the storage density of the semiconductor structure 1 can be increased by reducing the distance between adjacent transistors 2 in the same array region 33.

[0141] Referring to FIG. 3 in combination with the above embodiment, in the implementation manner in which the semiconductor structure 1 comprises a plurality of transistors 2, the storage capacitor 19 in the storage array 36 can also be a plurality of storage capacitors 19, the plurality of storage capacitors 19 are connected in correspondence with the plurality of transistors 2, and the storage array 36 further comprises a third isolation layer 37, the third isolation layer 37 is arranged between two adjacent storage capacitors 19, and the third isolation layer 37 can comprise at least one of silicon nitride, hafnium oxide and aluminum oxide. In combination with the embodiment in which the semiconductor structure 1 comprises the first isolation layer 30 and the second isolation layer 32, the third isolation layer 37 together with the first isolation layer 30 and the second isolation layer 32 isolates the adjacent transistors 2.

[0142] In another aspect, the embodiment of the present application further provides a preparation method of a semiconductor structure, which can be used to manufacture the semiconductor structure 1 in the above embodiment. Referring to FIG. 9, the preparation method can comprise steps S100-S400:

[0143] S100: forming a laminated structure, the laminated structure comprises an initial first electrode, a first insulating layer, a dummy gate layer, a second insulating layer and a mask layer which are arranged in layers.

[0144] In S100, referring to FIG. 10 in combination with FIG. 4, the forming of the stack structure 38 includes sequentially forming the initial first electrode 39, the first insulating layer 26, the dummy gate layer 41, the second insulating layer 27, and the mask layer 43 by deposition. The initial first electrode 39 can include a stack structure of an initial first electrode layer 44 and an initial first contact layer 45. The initial first electrode layer 44 can include a metal or a conductive nitride or an alloy electrode such as W, Ni, Mo, Ru, NiPt, TiN. The initial first contact layer 45 can include a conductive oxide such as InSnO, ITO, etc. so that the first contact layer 29 formed later can serve as a buffer layer between the channel column 3 and the first electrode layer 28. In the subsequent process of preparing the semiconductor structure 1, part of the initial first electrode 39 can be removed along the column direction of the channel column 3 to form a plurality of first electrodes 17 arranged along the column direction and extending along the row direction. In the implementation where the initial first electrode 39 includes the initial first electrode layer 44 and the initial first contact layer 45, after part of the initial first electrode 39 is removed along the column direction, the first electrode 17 formed will include the first electrode layer 28 and the first contact layer 29 arranged in a stack, so that the first contact layer 29 can serve as a buffer layer between the channel column 3 and the first electrode layer 28.

[0145] The first insulating layer 26 and the second insulating layer 27 can include insulating oxides, insulating nitrides, and carbon oxides such as SiO, SiN, SiOC, AlO, or other insulating materials, etc. The dummy gate layer 41 can include polycrystalline silicon or monocrystalline silicon, etc. The mask layer 43 can include at least one of SiN, SiOC, TiN, a-Si, etc. For example, the mask layer 43 includes a first mask layer 46 and a second mask layer 47, the first mask layer 46 is SiN, and the second mask layer 47 is SiOC.

[0146] S200: Forming a plurality of channel holes on the stack structure, and forming a plurality of dummy channel columns in the channel holes, the dummy channel columns penetrating through the mask layer, the first insulating layer, the dummy gate layer, and the second insulating layer.

[0147] In S200, referring to FIG. 10 and FIG. 11 in combination, forming a plurality of channel holes 48 on the stack structure 38 includes arraying forming a plurality of channel holes 48 on the stack structure 38 by dry etching, the channel holes 48 penetrating through the mask layer 43, the first insulating layer 26, the dummy gate layer 41, and the second insulating layer 27. In the implementation where the initial first electrode 39 includes the initial first electrode layer 44 and the initial first contact layer 45, the initial first contact layer 45 can avoid excessive etching in the process of forming the channel holes 48 and damage the initial first electrode layer 44.

[0148] Referring to FIG. 12, forming the dummy channel pillars 49 in the channel holes 48 (as shown in FIG. 11) includes filling metal W in the channel holes 48 to form a columnar structure (i.e., the dummy channel pillars 49 described above), which serves as a temporary filling of the channel holes 48.

[0149] S300: removing the dummy gate layer to form a first gap layer, and forming a gate dielectric layer and a gate in the first gap layer, the gate includes a first surface facing a sidewall of the channel pillar and a second surface adjacent to the first surface, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer connected in series, the first gate dielectric layer is located between the channel pillar and the first surface, and the second gate dielectric layer covers the second surface.

[0150] In some embodiments of S300, referring to FIGS. 13, 14, and 15, before the dummy gate layer 41 is removed to form the first gap layer 50, the stack structure 38 is provided with a plurality of array regions 33 and isolation regions 34, and forming the plurality of channel holes 48 includes forming a plurality of channel holes 48 in each array region 33 of the stack structure 38 in a spaced manner, and correspondingly, no channel hole 48 is formed in the isolation regions 34. The edge of the array region 33 can be defined as the collection of edges of the transistors 2 formed by the channel holes 48 in the array region 33. The distance between two adjacent channel holes 48 located in two adjacent array regions 33 is greater than the distance between two adjacent channel holes 48 located in the same array region 33.

[0151] In the above embodiments, removing the dummy gate layer 41 to form the first gap layer 50 includes first forming a replacement slit 51 in the isolation region 34, the replacement slit 51 is located between two adjacent array regions 33, and the replacement slit 51 penetrates the mask layer 43, the second insulating layer 27 to expose part of the dummy gate layer 41, or penetrates the mask layer 43, the second insulating layer 27 and the dummy gate layer 41, and also can expose part of the dummy gate layer 41. After the plurality of dummy channel pillars 49 are formed, the plurality of dummy channel pillars 49 all penetrate the dummy gate layer 41, or in other words, the dummy gate layer 41 surrounds the plurality of dummy channel pillars 49, and the dummy gate layer 41 surrounding the plurality of dummy channel pillars 49 can be removed through the replacement slit 51 between the adjacent array regions 33, which achieves the replacement of the dummy gate layer 41 while reducing the number of replacement slits 51 provided on the semiconductor structure 1, thereby increasing the storage density of the semiconductor structure 1. After the dummy gate layer 41 is removed, the dummy channel pillars 49 can fix the relative positions between the first insulating layer 26 and the second insulating layer 27 to form the first gap layer 50 between the first insulating layer 26 and the second insulating layer 27.

[0152] In the above embodiments, referring to FIG. 16 and FIG. 17, after the first void layer 50 is formed, the gate dielectric layer 7 and the gate 4 are formed in the first void layer 50, which includes forming an initial gate dielectric layer 52 and an initial gate 53 in the first void layer 50; wherein after the initial gate dielectric layer 52 is formed, the initial gate dielectric layer 52 includes a first gate dielectric layer 8 covering the dummy channel pillar 49, an initial second gate dielectric layer 54 covering the first insulating layer 26, and an initial third gate dielectric layer 67 covering the second insulating layer 27; the initial gate 53 is formed such that the first gate dielectric layer 8 is between the initial gate 53 and the dummy channel pillar 49, the initial second gate dielectric layer 54 is between the initial gate 53 and the first insulating layer 26, and the initial third gate dielectric layer 67 is between the initial gate 53 and the second insulating layer 27. After the initial gate dielectric layer 52 is formed, part of the initial gate dielectric layer 52 can cover the sidewall of the replacement slit 51; similarly, after the initial gate 53 is formed, part of the initial gate 53 can also cover the sidewall of the replacement slit 51.

[0153] Referring to FIG. 18, in the implementation where the gate 4 includes the first gate layer 11 and the second gate layer 12, the initial gate 53 is formed by first forming an initial first gate layer 55 and then forming an initial second gate layer 56, such that the initial first gate layer 55 is between the initial second gate layer 56 and the initial gate dielectric layer 52. In combination with the above embodiments, the initial gate 53 is formed by the initial first gate layer 55 and the initial second gate layer 56, i.e. part of the initial first gate layer 55 and part of the initial second gate layer 56 can cover the sidewall of the replacement slit 51.

[0154] Referring to FIG. 17 and FIG. 19, then part of the initial gate 53 is removed along the previous replacement slit 51 until the initial third gate dielectric layer 67 covering the second insulating layer 27; or part of the initial gate 53, part of the initial second gate dielectric layer 54, and part of the initial third gate dielectric layer 67 are removed along the previous replacement slit 51 until the second insulating layer 27, to divide the initial gate 53, so as to disconnect the initial gate 53 located in different array regions 33. In the implementation where part of the initial gate dielectric layer 52 and part of the gate 53 cover the replacement slit 51, part of the initial gate dielectric layer 52 and part of the gate 53 covering the sidewall of the replacement slit 51 can be removed simultaneously in the process of removing part of the initial gate 53 along the previous replacement slit 51.

[0155] Referring to FIG. 19 and FIG. 20, at least one of insulating oxide, insulating nitride, and carbon oxide is filled in the replacement slit 51 to form an isolation structure 35, so as to realize insulation between the transistors 2 located in different array regions 33.

[0156] Referring to FIGS. 21-24, a first gap 57 is formed between two adjacent dummy channel pillars 49 in the same array region 33, and the forming of the first gap 57 includes removing the mask layer 43 on the first insulating layer 26 to expose one end of the dummy channel pillar 49 away from the initial first electrode 39 and the sidewall adjacent thereto, and to expose the first insulating layer 26. Referring to FIGS. 22 and 23, an initial shielding layer 58 is formed on the exposed dummy channel pillar 49 and the first insulating layer 26 by atomic layer deposition (ALD) or chemical vapor deposition (CVD), and the initial shielding layer 58 covers the one end of the dummy channel pillar 49 away from the initial first electrode 39 and the sidewall adjacent thereto, and covers the first insulating layer 26, and the initial shielding layer 58 can include SiN, and then part of the initial shielding layer 58 is removed along the thickness direction of the initial shielding layer 58. Since the extension direction of the part of the initial shielding layer 58 covering the sidewall of the dummy channel pillar 49 is different from the extension direction of the part of the initial shielding layer 58 covering the one end of the dummy channel pillar 49 away from the initial first electrode 39 and the initial shielding layer 58 covering the first insulating layer 26, when the part of the initial shielding layer 58 between the two adjacent dummy channel pillars 49 is removed, part of the initial shielding layer 58 covering the sidewall of the dummy channel pillar 49 remains, and this part of the initial shielding layer 58 forms a shielding layer 59. If the transistor 2 is a full-surrounding-gate transistor, when the array of channel holes 48 is formed, the distance between two adjacent channel holes 48 in the column direction is less than the distance between two adjacent channel holes 48 in the row direction, so that after the part of the initial shielding layer 58 is removed, the shielding layer 59 still covers between two adjacent dummy channel pillars 49 in the column direction, and a second gap 60 is formed between two adjacent dummy channel pillars 49 in the row direction, and the second gap 60 can expose the first insulating layer 26.

[0157] Referring to FIGS. 23 and 24, the first gap 57 is formed between the two adjacent dummy channel pillars 49 through the second gap 60, and the first gap 57 penetrates the first insulating layer 26, the initial gate dielectric layer 52, and the initial gate electrode 53, and in the process of forming the first gap 57, part of the initial second gate dielectric layer 54 can be removed, part of the initial third gate dielectric layer 67 can be removed, and part of the initial gate electrode 53 can be removed, the remaining part of the initial second gate dielectric layer 54 forms the second gate dielectric layer 9, the remaining part of the initial third gate dielectric layer 67 forms the third gate dielectric layer 66, and the second gate dielectric layer 9, the third gate dielectric layer 66, and the first gate dielectric layer 8 formed before form the final gate dielectric layer 7; and the remaining part of the initial gate electrode 53 forms the gate electrode 4, and the gate electrode 4 can be arranged to surround the dummy channel pillar 49.

[0158] If the transistor 2 is a double-gate transistor, under the premise that the gate 4 is arranged around the dummy channel pillar 49, the gate 4 between the two adjacent channel holes 48 in the column direction is removed by photolithography, and the remaining part of the gate 4 forms the first gate 13 and the second gate 14 located on both sides of the dummy channel pillar 49.

[0159] In combination with reference to FIGS. 18 and 25, in the embodiment in which the initial gate 53 includes an initial first gate layer 55 and an initial second gate layer 56, removing part of the initial gate 53 includes removing part of the initial first gate layer 55 and part of the initial second gate layer 56, and the remaining part of the initial first gate layer 55 forms the first gate layer 11, and the remaining initial second gate layer 56 forms the second gate layer 12, and the first gate layer 11 and the second gate layer 12 constitute the gate 4.

[0160] Through the above arrangement, the position of the second gap 60 can be adjusted by setting the position and width of the initial shielding layer 58, and then limiting the position of the shielding layer 59, so that the position of the first gap 57 is formed between the two adjacent dummy channel pillars 49.

[0161] In combination with reference to FIGS. 24 and 26, after the first gap 57 is formed, the preparation method further includes removing the shielding layer 59 and forming a first insulating structure 311 in the first gap 57, wherein the first insulating structure 311 can include insulating oxides, insulating nitrides, and carbon oxides such as SiO, SiN, SiOC, AlO, or other insulating materials.

[0162] Through the above arrangement, the replacement gap 51 is first formed in the isolation region 34 between the adjacent array regions 33, and the dummy gate layer 41 is removed through the replacement gap 51, and then the isolation structure 35 is formed in the replacement gap 51, so as to realize the insulation between the transistors 2 located in different array regions 33; and then the first gap 57 is formed between the two adjacent dummy channel pillars 49, and the first insulating structure 311 is formed in the first gap 57, so as to realize the isolation between the transistors 2 in the same array region 33.

[0163] In combination with reference to FIGS. 25 and 27, in the above embodiment, before the first insulating structure 311 is formed in the first gap 57, the preparation method further includes forming a first isolation layer 30 in the first gap 57, so that the first isolation layer 30 covers the first insulating layer 26, the gate 4, the second gate dielectric layer 9, and the second insulating layer 27, and isolates the two adjacent transistors 2.

[0164] In other embodiments of S300, referring to FIG. 28 to FIG. 33 in combination with FIG. 12, removing the dummy gate layer 41 to form the first void layer 50 includes directly removing the mask layer 43, and forming a first gap 57 between two adjacent dummy channel pillars 49, the first gap 57 penetrating the first insulating layer 26, wherein the process of forming the first gap 57 is the same as the previous embodiment, and is not described here. Then, the dummy gate layer 41 is removed through the first gap 57 to form the first void layer 50; after forming the gate dielectric layer 7 and the gate 4 in the first void layer 50, the first isolation layer 30 and the first insulating structure 311 are formed in the first gap 57.

[0165] Through the above arrangement, by removing the dummy gate layer 41 through the first gap 57 for forming the first insulating structure 311 for isolating the adjacent transistors 2, compared with the previous embodiment, the semiconductor structure 1 does not need to be provided with the isolation structure 35 in the isolation region 34, thereby increasing the density of the transistors 2 in the semiconductor structure 1 and improving the performance of the semiconductor structure 1.

[0166] In the embodiments of removing the dummy gate layer 41 to form the first void layer 50, and forming the gate dielectric layer 7 and the gate 4 in the first void layer 50, the dummy gate layer 41 in the stack structure 38 can be formed by deposition, that is, the thickness of the dummy gate layer 41 is easy to be controlled artificially, for example, the thickness of the dummy gate layer 41 can be 50 nm. That is, the thickness of the first void layer 50 formed after removing the dummy gate layer 41 can be determined. Since the gate dielectric layer 7 is also formed by deposition, the thickness of the gate dielectric layer 7 is also easy to be determined, thereby facilitating the control of the thickness of the gate 4, improving the consistency of the thickness of the gate 4, and further making the thickness of the gate 4 of each transistor 2 consistent, thereby improving the electrical stability of the semiconductor structure 1.

[0167] S400: removing the dummy channel pillar 49 and forming the channel pillar 3 in the channel hole 48.

[0168] In S400, referring to FIG. 34 and FIG. 35 in combination with FIG. 33, in the embodiments in which the dummy channel pillar 49 includes metal W, the dummy channel pillar 49 can be etched by hydrogen peroxide, thereby exposing the channel hole 48. Then, an oxide semiconductor is deposited in the channel hole 48 by ALD to form an initial channel layer 61, wherein the initial channel layer 61 can include a first channel layer 15 covering the sidewall of the channel hole 48, a second channel layer 20 covering the bottom of the channel hole 48, and an initial third channel layer 62 covering the first insulating layer 26. It can be understood that the first channel layer 15, the second channel layer 20 and the initial third channel layer 62 are integrated structures.

[0169] In the above embodiments, compared with forming the channel structure first and then forming the gate dielectric layer and the gate electrode layer corresponding to the channel structure, in the embodiments of the present application, since the gate electrode 4 and the gate dielectric layer 7 are both formed before the initial channel layer 61 is formed, the damage of the initial channel layer 61 caused by the etching step for forming the gate dielectric layer 7 and the gate electrode 4 is avoided, or the possibility of the initial channel layer 61 being doped by other parts of the semiconductor structure 1 is reduced, the influence of the initial channel layer 61 in the process of forming the semiconductor structure 1 is reduced, and thus the stability of the channel pillar 3 formed subsequently is improved, and thus the reliability of the semiconductor structure 1 is improved.

[0170] Referring to FIGS. 36 and 37 in combination with FIG. 35, the first channel layer 15 and the second channel layer 20 located in the channel hole 48 do not completely fill the channel hole 48, and after the initial channel layer 61 is formed, the filling pillar 16 is further formed to realize the support of the transistor 2. The forming of the filling pillar 16 can include forming an initial filling pillar 63 in the channel hole 48, and the forming of the initial filling pillar 63 can be performed in multiple times, for example, in the embodiment in which the filling pillar 16 includes silicon oxide, the forming of the initial filling pillar 63 can include depositing silicon oxide and etching part of the silicon oxide, and then continuing to deposit silicon oxide and etching part of the silicon oxide, and repeating the above process multiple times, so as to avoid the generation of a void in the process of forming the initial filling pillar 63, and thus the support effect of the filling pillar 16 is weakened.

[0171] In the process of forming the initial filling pillar 63, in order to ensure that the initial filling pillar 63 can completely fill the channel hole 48, after the initial filling pillar 63 is formed, part of the initial filling pillar 63 is located on the initial third channel layer 62 (i.e., the side of the initial third channel layer 62 away from the second insulating layer 27), and the preparation method further includes back-etching the initial filling pillar 63 to remove part of the initial filling pillar 63 located on the initial third channel layer 62, and thus exposing the initial third channel layer 62, and the remaining initial filling pillar 63 forms the filling pillar 16.

[0172] Please refer to FIGS. 38 and 39, the initial second electrode 64 is formed on the initial channel layer 61 and the filling pillar 16, and the initial second electrode 64 is patterned and etched to form a plurality of second electrodes 18, the plurality of second electrodes 18 are arranged at intervals in the row direction of the transistor 2, and the third gap 65 is formed between adjacent two second electrodes 18. The third gap 65 can expose the initial third channel layer 62 located between the adjacent two filling pillars 16. Part of the initial third channel layer 62 is removed through the third gap 65 to realize the isolation between the channel layers of the adjacent two transistors 2. The remaining part of the third channel layer 25 forms the third channel layer 25, and the third channel layer 25, the first channel layer 15 and the second channel layer 20 connected thereto form the final channel.

[0173] In some embodiments, during the process of etching back the initial filling pillars 63, part of the initial filling pillars 63 located in the channel holes 48 can be removed, and then the initial second electrodes 64 are formed, so that the final second electrodes 18 can be located in the recess formed by the third channel layer 25 and the second end surface 22 of the filling pillars 16, which can also reduce the distance between the second electrodes 18 and the gate 4, and improve the electrical properties of the transistor 2.

[0174] Referring to FIG. 40, in addition to removing the part of the third channel layer 62, the preparation method further includes forming a second insulating structure 312 in the third gap 65 to insulate the adjacent two second electrodes 18, wherein the second insulating structure 312 can include insulating oxides, insulating nitrides, and carbon oxides such as SiO, SiN, SiOC, AlO, or other insulating materials. In the above-mentioned embodiment of forming the first insulating structure 311, the first insulating structure 311 and the second insulating structure 312 can be formed of the same material, that is, there is no boundary between the first insulating structure 311 and the second insulating structure 312, and the first insulating structure 311 and the second insulating structure 312 can form an integrated structure of the insulating structure 31.

[0175] Referring to FIG. 41, in addition to forming the second insulating structure 312 in the third gap 65, the preparation method further includes forming a second isolation layer 32 in the third gap 65, so that the second isolation layer 32 covers the second electrode 18. After forming the above-mentioned insulating structure 31, the second isolation layer 32 is located between the second electrode 18 and the insulating structure 31, so as to isolate the second electrode 18 and the insulating structure 31, and prevent the second electrode 18 from being oxidized in the oxidation environment in the process of forming the insulating structure 31.

[0176] Referring to FIG. 42, in the above-mentioned embodiment, after forming the second isolation layer 32 in the third gap 65 (as shown in FIG. 39), part of the second isolation layer 32 can also cover the side of the second insulating layer 27 away from the gate 4. After forming the second insulating structure 312, part of the second isolation layer 32 is located between the second insulating structure 312 and the second insulating layer 27.

[0177] The preparation method of the semiconductor structure provided in the present application forms a first void layer 50 by removing the dummy gate layer 41, forms a gate dielectric layer 7 and a gate 4 in the first void layer 50, and then forms a channel pillar 3 in the channel hole 48, which increases the contact area of the gate 4 and the gate dielectric layer 7, thereby improving the control ability of the gate 4, and further improving the performance of the transistor 2.

[0178] Referring to Fig. 43, the application further provides a method for preparing a memory array, comprising connecting the memory capacitor 19 with the second electrode 18 after forming the second electrode 18, wherein the memory capacitor 19 can be formed independently from the semiconductor structure 1, or can be formed on the second electrode 18. The step of forming the second isolation layer 32 in the method for preparing the semiconductor structure is after forming the second electrode 18.

[0179] Referring to Fig. 44, after forming the memory array 36, the method further comprises forming a third isolation layer 37 between two adjacent memory capacitors 19.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the application, rather than limit them; although the application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a transistor, the transistor comprising: a channel column; a first insulating layer, the channel column penetrating through the first insulating layer; a gate, the gate being arranged adjacent to the first insulating layer in the extension direction of the channel column, the gate comprising a first surface facing the sidewall of the channel column and a second surface facing the first insulating layer; a gate dielectric layer, the gate dielectric layer comprising a first gate dielectric layer and a second gate dielectric layer connected in series, the first gate dielectric layer being located between the channel column and the first surface, the second gate dielectric layer being located on the side of the second surface facing the first insulating layer.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a second insulating layer, the second insulating layer and the first insulating layer being arranged spaced apart along the extension direction of the channel column, the gate being located between the first insulating layer and the second insulating layer; The gate further comprises a third surface, the third surface being arranged facing the second insulating layer; The gate dielectric layer further comprises a third gate dielectric layer, the third gate dielectric layer being located on the side of the third surface facing the second insulating layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that The gate comprises a first gate layer and a second gate layer, the first gate layer being located between the second gate layer and the gate dielectric layer.

4. The semiconductor structure according to any of claims 1 to 3, characterized in that The channel column comprises a first channel layer and a filling column, the first channel layer being arranged on the sidewall of the filling column, the first gate dielectric layer being located between the first channel layer and the first surface.

5. The semiconductor structure of claim 4, wherein, The transistor further comprises a first electrode, the channel column further comprises a second channel layer, the second channel layer covering a first end surface of the filling column and being connected with the first channel layer, the first electrode being arranged facing the first end surface, the second channel layer being in contact with the first electrode.

6. The semiconductor structure of claim 5, wherein, The transistor further comprises a second electrode, the filling column further comprises a second end surface, the second end surface being arranged opposite to the first end surface, the second electrode being arranged facing the second end surface, the second electrode being in contact with the first channel layer.

7. The semiconductor structure of claim 6, wherein, The first channel layer comprises a first contact surface parallel to the sidewall of the filling column and a second contact surface adjacent to the first contact surface, the second electrode being in contact with the second contact surface and part of the first contact surface.

8. The semiconductor structure of claim 6, wherein, The channel column further comprises a third channel layer, the third channel layer being located at one end of the first channel layer away from the second channel layer and being connected with the first channel layer, the third channel layer extending in a direction away from the filling column; the third channel layer and the second end surface form a groove, the second electrode being in contact with the third channel layer and part of the second electrode being filled in the groove.

9. The semiconductor structure of any of claims 1-8, wherein, The transistor is a plurality of transistors, the center lines of the channel columns in each of the transistors being arranged in parallel, the semiconductor structure further comprises a first isolation layer, the first isolation layer covering the outer side of each of the transistors.

10. The semiconductor structure of any of claims 1-9, wherein, The transistor is a plurality of transistors, the center lines of the channel columns in each of the transistors being arranged in parallel, the semiconductor structure further comprises an insulating structure and a second isolation layer, the insulating structure being located between two adjacent transistors, the second isolation layer being located between the second electrode in the transistor and the insulating structure.

11. The semiconductor structure of any of claims 1-10, wherein, The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

12. The semiconductor structure of any of claims 1-11, wherein, The gate surrounds the channel column.

13. The semiconductor structure of any of claims 1-11, wherein, The gate comprises a first gate and a second gate, and the channel column is located between the first gate and the second gate.

14. A memory array comprising: The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

15. A memory, comprising: The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

16. A logic device, comprising: The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

17. An electronic device, comprising: The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

18. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

19. The method of claim 18, wherein, The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

20. The method of claim 19, wherein, The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region.

21. The method of claim 18, wherein, The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region. The semiconductor structure comprises a plurality of array regions and isolation regions, the isolation regions are arranged between two adjacent array regions; a plurality of transistors are arranged in each array region; and an isolation structure is arranged in the isolation region After forming the gate dielectric layer and the gate electrode in the first gap layer, a first insulating structure is formed in the first gap.

22. The method of manufacturing according to claim 20 or 21, wherein, Forming the first gap comprises: removing the mask layer to expose the sidewall of the dummy channel pillar and the second insulating layer; forming an initial shielding layer and removing a portion of the initial shielding layer between two adjacent dummy channel pillars to form a second gap; the remaining portion of the initial shielding layer forms a shielding layer on the sidewall of the dummy channel pillar; the first gap is formed through the second gap.

23. The method of any one of claims 20-22, wherein, Before forming the first insulating structure in the first gap, the preparation method further comprises forming a first isolation layer in the first gap.

24. The method of any one of claims 18-23, wherein, The removing the dummy channel pillar and forming a channel pillar in the channel hole comprises: removing the dummy channel pillar; forming an initial channel layer in the channel hole and forming a filling pillar; forming an initial second electrode on the initial channel layer; forming a third gap through the initial second electrode; removing a portion of the initial channel layer through the third gap.

25. The method of claim 24, wherein, Before forming the initial second electrode, the preparation method further comprises: forming an initial filling pillar and removing a portion of the initial filling pillar in the channel hole to form the filling pillar; forming the initial second electrode on the filling pillar.

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