Packaging structure and manufacturing method therefor, and electronic device

Abstract

Provided are a packaging structure and a manufacturing method therefor, and an electronic device. The packaging structure comprises: a chip structure (10) having a first surface (12) and a second surface (13) which are opposite to each other, the chip structure (10) comprising a substrate and a chip functional layer arranged on the substrate, and the substrate being coherent and complete; a first bonding structure (40) arranged on the first surface (12); a first chiplet (20) arranged on the side of the first bonding structure (40) facing away from the chip structure (10), the size of the projection of the first chiplet (20) on the first surface (12) being smaller than the size of the first surface (12); a second bonding structure (50) arranged on the second surface (13); and a second chiplet (30) arranged on the side of the second bonding structure (50) facing away from the chip structure (10), the size of the projection of the second chiplet (20) on the second surface (13) being smaller than the size of the second surface (13). The solution can mitigate the warping of the packaging structure, thereby improving the manufacturability of the multi-layer stacked packaging structure, and reducing the occurrence of abnormal working of the corresponding packaging structure caused by uneven stress distribution.

Description

Package structure, manufacturing method thereof and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a package structure, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] With Moore's Law gradually reaching its limit, the demand for storage capacity and computing power of high-bandwidth storage and high-performance computing chips continues to grow. In order to achieve greater storage capacity, higher computing power and multiple bandwidths in a limited area, multi-layer stacked chip package structures have become a recent research hotspot. Such package structures usually include multiple layers of chips, but during the manufacturing process of the multi-layer stacked chips, wafer warping is prone to be too large, and the process is difficult to implement. After packaging, the multi-layer stacked devices are also prone to reliability problems such as abnormality and damage due to uneven stress distribution. SUMMARY

[0003] To solve the above technical problems, the present application provides a package structure, a manufacturing method thereof and an electronic device, which can balance the warping of the stress of the package structure during the stacking process, thereby improving the manufacturability of the mixed-bonding multi-layer stacked package structure and reducing the reliability problems such as abnormal operation and damage of the corresponding package structure due to uneven stress distribution.

[0004] In a first aspect, the present application provides a package structure, comprising: a chip structure, a first bonding structure, a first core particle, a second bonding structure and a second core particle. The chip structure comprises a substrate and a chip functional layer disposed on the substrate. The substrate is a continuous and complete substrate in a plane perpendicular to the thickness direction of the package structure. The chip structure has opposite first and second surfaces. A through-silicon via is disposed in the chip structure, and the through-silicon via penetrates from the first surface to the second surface. The first bonding structure is disposed on the first surface and comprises a dielectric structure and a metal structure. The first core particle is disposed on the side of the first bonding structure away from the chip structure, and the first core particle covers the metal structure of the first bonding structure, so that the first core particle can be electrically connected to the chip structure through the metal structure of the first bonding structure. The second bonding structure is disposed on the second surface and comprises a dielectric structure and a metal structure. The second core particle is disposed on the side of the second bonding structure away from the chip structure, and the second core particle covers the metal structure of the second bonding structure, so that the second core particle can be electrically connected to the chip structure through the metal structure of the second bonding structure. That is, the first and second core particles are fixed to the opposite first and second surfaces of the chip structure, respectively.

[0005] In the manufacturing of the packaging structure, the chip structure, the first core particle and the second core particle can be manufactured respectively, then the first core particle is bonded to the first surface of the chip structure, and the first surface is filled with medium, and the first bonding structure is formed between the first core particle and the chip structure; the second core particle is bonded to the second surface, and the second surface is filled with medium, and the second bonding structure is formed between the second core particle and the chip structure. In this way, the warping of the packaging structure caused by multiple and layer-by-layer bonding of the core particles on the same side of the chip structure and filling of the medium can be reduced. That is, the scheme of bonding the first core particle and the second core particle to the two side surfaces of the chip structure respectively can balance the stress on both sides of the chip structure, thereby relieving the warping of the packaging structure, and further improving the manufacturability of the mixed-bonding multi-layer stacked packaging structure and reducing the reliability problem of the packaging structure caused by uneven stress distribution.

[0006] In addition, the projection of the first core particle on the first surface is located within the range of the first surface and has a size smaller than that of the first surface. The first core particle is obtained after cutting. Therefore, in the manufacturing of the first core particle, the chip functional layer can be manufactured on the wafer first, then the wafer containing the functional layer is cut to obtain a plurality of core particles, and qualified core particles are selected as the first core particles. In this way, the yield of the first core particle can be guaranteed, and the stacking of the first core particle with poor function can be avoided, thereby improving the yield of the stacked packaging structure.

[0007] The projection of the second core particle on the second surface is located within the range of the second surface and has a size smaller than that of the second surface. The second core particle can also be obtained after cutting. Therefore, in the manufacturing of the second core particle, the chip functional layer can be manufactured on the wafer first, then the wafer containing the chip functional layer is cut to obtain a plurality of core particles, and qualified core particles are selected as the second core particles. In this way, the yield of the second core particle can be guaranteed, and the stacking of the second core particle with poor function can be avoided, thereby improving the yield of the stacked packaging structure.

[0008] For the number of the first core particles, in a possible implementation, the packaging structure can include one first core particle. In an example, the first core particle is a single-layer chip. In another example, the first core particle can be a multi-layer chip. The first core particle and the chip structure are connected in the way of mixed bonding of chip-wafer, and when the first core particle is a multi-layer chip, a plurality of wafers can be manufactured with chip functional layers respectively first, then the plurality of wafers and the chip functional layers are bonded into one whole body in the way of mixed bonding of wafer-wafer, and then function testing and cutting are performed to form the first core particle. The single-layer chip and the multi-layer chip can be used to realize different functions respectively, thereby making the function selection of the packaging structure more flexible.

[0009] In another possible implementation, the packaging structure can include at least two first core particles, the at least two first core particles being arranged on the first bonding structure at intervals respectively, and a part of the first core particles being single-layer chips and another part of the first core particles being multi-layer chips. For the functions of the single-layer chips and the multi-layer chips, in an example, the first core particles using the single-layer chips can implement computing functions with high heat dissipation requirements, and the first core particles using the multi-layer chips can implement high-bandwidth storage functions. In another example, the single-layer chips can be functional-free silicon dies, which are only used for adjusting the silicon proportion on both sides of the chip structure to balance stress and reduce warping. In this way, the packaging structure can implement both computing functions and high-bandwidth storage functions, so that the packaging structure can achieve the actual effect of near-memory computing.

[0010] For the number of the second core particles, in a possible implementation, the packaging structure can include one second core particle. In an example, the second core particle is a single-layer chip. In another example, the second core particle is a multi-layer chip. The second core particle and the chip structure are connected in a chip-die hybrid bonding manner. When the second core particle is a multi-layer chip, a plurality of functional layers can be respectively fabricated on a plurality of dies, then the plurality of dies with the functional layers are bonded into a whole in a die-die hybrid bonding manner, and then the second core particle is formed by cutting. The single-layer chips and the multi-layer chips can be respectively used to implement different functions, so that the function selection of the packaging structure is more flexible.

[0011] In another possible implementation, the packaging structure includes at least two second core particles, the at least two second core particles being arranged on the second bonding structure at intervals respectively, and a part of the second core particles being single-layer chips and another part of the second core particles being multi-layer chips. For the functions of the single-layer chips and the multi-layer chips, in an example, the second core particles using the single-layer chips can implement computing functions with high heat dissipation requirements, and the second core particles using the multi-layer chips can implement high-bandwidth storage functions. In another example, the single-layer chips can be functional-free silicon dies, which are only used for adjusting the silicon proportion on both sides of the chip structure to balance stress and reduce warping. In this way, the packaging structure can implement both computing functions and high-bandwidth storage functions, so that the packaging structure can be applied to electronic devices for near-memory computing.

[0012] In addition, when the number of the first core particles is at least two, the first core particles can be single-layer core particles and multi-layer core particles; when the number of the second core particles is at least two, the second core particles can be single-layer core particles and multi-layer core particles, that is, various combinations of the single-layer chips and the multi-layer chips can be arranged on the two side surfaces of the chip structure. The single-layer chips can also be functional-free structure silicon dies, which are only used for adjusting the silicon proportion on both sides of the chip structure to balance stress. By controlling the area proportion of the two side core particles and the dielectric layer on the chip structure, warping can be further relieved.

[0013] In some embodiments, the packaging structure includes at least two first die and at least two second die; the packaging structure further includes a third dielectric layer disposed on a side of the first bonding structure away from the chip structure, and the third dielectric layer includes a third dielectric structure disposed between two adjacent first die and a third dielectric structure located at the periphery of the at least two first die; the packaging structure includes a fourth dielectric layer disposed on a side of the second bonding structure away from the chip structure, and the fourth dielectric layer includes a fourth dielectric structure disposed between two adjacent second die and a fourth dielectric structure located at the periphery of the at least two second die, the fourth dielectric layer has a projected area on the chip structure equal to or approximately equal to that of the third dielectric layer, or in other words, the at least two first die and the at least two second die have a projected area on the chip structure equal to or approximately equal to that of each other, thereby further relieving the warpage generated during the fabrication of the packaging structure.

[0014] Further, the third dielectric layer and the fourth dielectric layer are both made of organic dielectric material or both made of inorganic dielectric material. In this way, the thermal expansion coefficients of the materials of the third dielectric layer and the fourth dielectric layer are relatively close, and the stress generated during fabrication is approximately equal, thereby further relieving the warpage generated during the stacking process and the warpage of the final packaging structure.

[0015] For the specific structure of the chip structure, in one possible embodiment, the chip structure is a single-layer chip structure. In another possible embodiment, the chip structure is a multi-layer chip structure. The multi-layer chip structure is connected by wafer-to-wafer hybrid bonding during fabrication. In some embodiments, the multi-layer chip structure can realize the function of high-bandwidth storage together with the multi-layer chip in the first die.

[0016] The second aspect of the present application also provides an electronic device including a circuit board and the packaging structure of any of the above embodiments, the packaging structure being disposed on the circuit board. The electronic device can realize all the effects of the packaging structure.

[0017] In a third aspect, the application also provides a method for manufacturing a package structure, the method comprising: providing a chip structure, the chip structure comprising a substrate and a chip functional layer disposed on the substrate, the substrate being continuous and complete along a plane perpendicular to a thickness direction, the chip structure having opposite first and second surfaces; bonding first dies to the first surface, the first dies and the chip structure forming first bonding structures therebetween, the first dies being electrically connected to the chip structure through the metal structures in the first bonding structures, a projection of the first dies on the first surface being within the range of the first surface and having a size smaller than that of the first surface; and bonding second dies to the second surface, the second dies and the chip structure forming second bonding structures therebetween, the second dies being electrically connected to the chip structure through the second bonding structures, a projection of the second dies on the second surface being within the range of the second surface and having a size smaller than that of the second surface. That is, in this embodiment, the first and second dies are bonded to the opposite first and second surfaces of the chip structure, respectively. In this way, the warping of the package structure caused by multiple and layer-by-layer bonding of the dies on the same side of the chip structure can be reduced. That is, the scheme of bonding the first and second dies to the opposite first and second surfaces of the chip structure, respectively, can balance the stress on both sides of the chip structure, thereby relieving the warping of the package structure, and further improving the manufacturability of the package structure and reducing the reliability problems such as abnormal operation or damage of the chip caused by uneven stress distribution.

[0018] In some embodiments, before the step of bonding the first dies to the first surface, the method further comprises: hybrid bonding a plurality of wafers each having a chip functional layer; and cutting the hybrid bonded wafers and selecting functional dies, i.e. qualified dies, from the hybrid bonded wafers as the first dies. In this way, the first dies with poor bonding function can be avoided, thereby improving the yield of the package structure.

[0019] In some embodiments, before the step of bonding the second dies to the second surface, the method further comprises: hybrid bonding a plurality of wafers each having a chip functional layer; and cutting the hybrid bonded wafers and selecting qualified dies from the hybrid bonded wafers as the second dies. In this way, the second dies with poor bonding function can be avoided, thereby improving the yield of the package structure.

[0020] In a possible embodiment, the step of bonding the first dies to the first surface comprises: bonding at least two first dies to the first surface, respectively; and filling a third dielectric structure between each pair of adjacent first dies and the periphery of the at least two first dies. This direct bonding method has better bonding position accuracy.

[0021] In another possible implementation, the step of bonding the first dielets to the first surface comprises: fabricating a first integral structure with at least two first dielets and a third dielectric structure between the at least two first dielets and the periphery of the at least two first dielets; and bonding the first integral structure to the first surface. This method has a simple bonding process, thereby improving the yield.

[0022] In another possible implementation, the step of bonding the second dielets to the second surface comprises: bonding at least two second dielets to the second surface respectively; and filling a fourth dielectric structure between each pair of adjacent second dielets and the periphery of the at least two second dielets. This method of directly bonding the dielets has a better bonding position accuracy.

[0023] In addition, the fourth dielectric structure between each pair of adjacent second dielets and the periphery of the at least two second dielets can form a fourth dielectric layer, and the third dielectric structure between each pair of adjacent first dielets and the periphery of the at least two first dielets can form a third dielectric layer, the fourth dielectric layer and the third dielectric layer being substantially symmetrical in scale with respect to the chip structure, thereby further relieving the warping generated during the fabrication of the package structure.

[0024] In another possible implementation, the step of bonding the second dielets to the second surface comprises: fabricating a second integral structure with at least two second dielets and a fourth dielectric structure between the at least two second dielets and the periphery of the at least two second dielets; and bonding the second integral structure to the second surface. This method has a simple bonding process, thereby improving the yield.

[0025] In some embodiments, before the step of bonding the second dielets to the second surface, the fabrication method further comprises: thinning the chip structure from the second surface. This can obtain the required thickness of the entire package structure.

[0026] In some embodiments, after the step of providing the chip structure, the fabrication method further comprises: thinning the chip structure from the second surface; fixing a carrier plate on the new second surface formed after the thinning; and before the step of bonding the second dielets to the second surface, the fabrication method further comprises: removing the carrier plate. In this way, the thickness required for bonding the first dielets to the chip structure can be ensured, thereby reducing the deformation of the chip structure during the bonding of the first dielets. In addition, the required thickness of the entire package structure can be ensured after the carrier plate is removed. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings described in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0028] FIG. 1 is a structural schematic diagram of a packaging structure in the related art;

[0029] FIG. 2 is a structural schematic diagram of a packaging structure in a first embodiment of the present application;

[0030] FIG. 3 is a structural schematic diagram of a packaging structure in a second embodiment of the present application;

[0031] FIG. 4 is a structural schematic diagram of a packaging structure in a third embodiment of the present application;

[0032] FIG. 5 is a structural schematic diagram of a packaging structure in a fourth embodiment of the present application;

[0033] FIG. 6 is a manufacturing flow schematic diagram of the packaging structure shown in FIG. 2;

[0034] FIG. 7 is a manufacturing process schematic diagram of a part of the packaging structure shown in FIG. 2;

[0035] FIG. 8 is a manufacturing process schematic diagram of another part of the packaging structure shown in FIG. 2.

[0036] FIG. 1 is a structural schematic diagram of a packaging structure in the related art; DETAILED DESCRIPTION

[0037] The technical solutions of the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0038] The term "and / or", merely used to describe associated objects, means that there can be three relationships, for example, A and / or B, can mean: A alone, A and B exist at the same time, B alone, three cases, where A, B can be singular or plural. The character " / " generally represents the "or" relationship between the associated objects before and after. "At least one" means one or more, and "multiple" means two or more. "At least one" or the like means any combination of these items, including single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0039] The terms "first" and "second" and the like in the description and claims of the present application are used to distinguish different objects, not to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, not to describe the specific order of the target objects.

[0040] The terms "connection", "connection" and the like are used to express the intercommunication or interaction between different components, which can include direct connection or indirect connection through other components. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, including a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the orientation of the components placed in the drawings.

[0041] In the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. On the contrary, the use of "exemplary" or "for example" and the like is intended to present the relevant concept in a specific manner.

[0042] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" is two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0043] With Moore's Law gradually approaching its limit, high-bandwidth storage and high-performance computing chips, such as high-bandwidth memory (HBM), continue to demand greater storage capacity and computing power. In order to achieve greater storage capacity, higher computing power and multiple bandwidths in a limited area, multi-layer stacked chip packaging structures have become a recent research hotspot. Such packaging structures generally include multiple layers of chips, and the vertical interconnection between different layers of chips is mainly achieved by using micro-bumps (μbumps). However, the packaging structure has a large warpage, which can easily lead to excessive warpage during the manufacturing process of the chip stack, making the process difficult to implement, and uneven stress distribution of the device after packaging, resulting in abnormal storage.

[0044] In a related technology, as shown in FIG. 1, a packaging structure 1 includes multiple layers of chips 11, and each two adjacent chips 11 are connected by wafer to wafer (W2W) hybrid bonding. In the process of manufacturing the packaging structure 1, the functional layers of the chips can be first manufactured on the wafer, and then each wafer with the functional layers of the chips is connected layer by layer in the W2W hybrid bonding manner to obtain the packaging structure 1. On the one hand, this structure and manufacturing method will cause the warpage of the packaging structure 1 to gradually increase during the multi-layer stacking process, which exceeds the allowable range of the processing equipment, thereby causing the stacking manufacturing process to be unable to continue. On the other hand, the size of each layer of chips 11 must be consistent at the beginning of the design, which leads to poor design flexibility of the packaging structure 1. On the other hand, after the functional layers of the chips are manufactured on each wafer, different positions on each wafer can have functional damage during the manufacturing process. If there is a functional damage in the thickness direction, it will cause the packaging structure 1 in the thickness direction to be unable to be normally used. That is, the yield of the packaging structure 1 is exponentially lower than that of a single wafer, which leads to the yield of the packaging structure 1 being too low to be mass-produced. Therefore, in this related technology, the number of stacked layers of chips 11 in the packaging structure 1 is greatly limited.

[0045] Based on this, as shown in FIG. 2, in the embodiment of the present application, a packaging structure 1 is provided. The packaging structure 1 can be applied to an electronic device. In addition to the packaging structure 1, the electronic device can also include a circuit board. The packaging structure 1 is arranged on the circuit board and is electrically connected with the circuit board. Here, the electronic device can be, for example, a server, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. The embodiment of the present application does not limit this. For example, the consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot, etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), an electronic device for self-service business, etc. The communication electronic product can be a server, a memory, a radar, a base station, etc.

[0046] In order to facilitate the description of the packaging structure 1 of the embodiment, two directions are defined, which are a first direction (X direction) and a third direction (Z direction). The X direction represents the length direction of the packaging structure 1, the Z direction represents the thickness direction of the packaging structure 1, and the X direction and the Z direction are perpendicular to each other.

[0047] As shown in FIG. 2, the packaging structure 1 comprises a chip structure 10, a first bonding structure 40, a first die 20, a second bonding structure 50 and a second die 30. The chip structure 10 comprises a substrate and a chip functional layer disposed on the substrate, the substrate is a continuous and complete substrate in a plane perpendicular to the Z direction, and the chip structure 10 has opposite first and second surfaces 12 and 13. The chip structure 10 is internally provided with a through-silicon via, and the through-silicon via penetrates from the first surface 12 to the second surface 13. The first bonding structure 40 is disposed on the first surface 12, and the first bonding structure 40 comprises a dielectric structure and a metal structure. The first die 20 is disposed on a side of the first bonding structure 40 away from the chip structure 10, and the first die 20 covers the metal structure of the first bonding structure 40, so that the first die 20 can be electrically connected to the chip structure 10 through the metal structure of the first bonding structure 40. The second bonding structure 50 is disposed on the second surface 13, and the second bonding structure 50 comprises a dielectric structure and a metal structure. The second die 30 is disposed on a side of the second bonding structure 50 away from the chip structure 10, and the second die 30 covers the metal structure of the second bonding structure 50, so that the second die 30 can be electrically connected to the chip structure 10 through the metal structure of the second bonding structure 50. That is, the first and second dies 20 and 30 are respectively fixed to the opposite first and second surfaces 12 and 13 of the chip structure 10.

[0048] In the manufacturing of the packaging structure 1, the chip structure 10, the first die 20 and the second die 30 can be manufactured respectively, then the first die 20 is bonded to the first surface 12 of the chip structure 10, and dielectric filling and covering are performed on the first surface 12, so that the first bonding structure 40 can be formed between the chip structure 10 and the first die 20; the second bonding structure 50 is manufactured on the second surface 13, and the second die 30 is bonded to the second surface 13 of the chip structure 10, and dielectric filling and covering are performed on the second surface 13, so that the second bonding structure 50 can be formed between the chip structure 10 and the second die 30. In this way, the problem of large warping of the packaging structure 1 caused by multiple and layer-by-layer bonding of the die on the same side of the chip structure 10 and dielectric filling and covering can be reduced. That is, the scheme of bonding the first and second dies 20 and 30 on the two side surfaces of the chip structure 10 respectively can balance the stress on the two sides of the chip structure 10, thereby relieving the warping of the packaging structure 1, and further improving the manufacturability of the hybrid bonding multi-layer stacked packaging structure 1 and reducing the reliability problem of abnormal operation or damage of the chip caused by uneven stress distribution.

[0049] In addition, the projection of the first core particle 20 on the first surface 12 is within the range of the first surface 12 and has a size smaller than that of the first surface 12. That is, the size of the first core particle 20 along the X direction is smaller than that of the first surface 12 along the X direction, and / or the size of the first core particle 20 along the Y direction is smaller than that of the first surface 12 along the Y direction. For example, the size of the first core particle 20 along the X direction is smaller than that of the first surface 12 along the X direction, and the size of the first core particle 20 along the Y direction is equal to that of the first surface 12 along the Y direction; or the size of the first core particle 20 along the X direction is equal to that of the first surface 12 along the X direction, and the size of the first core particle 20 along the Y direction is smaller than that of the first surface 12 along the Y direction; or the size of the first core particle 20 along the X direction is smaller than that of the first surface 12 along the X direction, and the size of the first core particle 20 along the Y direction is smaller than that of the first surface 12 along the Y direction. The Y direction is perpendicular to the X direction and the Z direction. In the embodiment, the first core particle 20 can be obtained by cutting. Therefore, when the first core particle 20 is manufactured, the functional layer of the chip can be manufactured on a wafer first, and then the wafer containing the functional layer of the chip is cut to obtain a plurality of core particles, and the qualified core particles are selected as the first core particle 20. In this way, the yield of the first core particle 20 can be ensured, and the core particles with poor bonding function can be avoided, thereby improving the yield of the packaging structure 1. In addition, as shown in FIG. 2, the total number of chips of the packaging structure 1 of the embodiment can reach 8 or more, which is much higher than the number of chips of the prior art shown in FIG. 1. Therefore, the number of chips that can be stacked in the packaging structure 1 of the embodiment is higher, thereby achieving a larger storage capacity, higher computing power, and multiple bandwidth in a limited area. In addition, since the first core particle 20 and the second core particle 30 are fixed to the chip structure 10 respectively in the embodiment, the embodiment can meet the heterogeneous integration.

[0050] The projection of the second die 30 on the second surface 13 is within the range of the second surface 13 and has a size smaller than the size of the second surface 13. That is, the size of the second die 30 along the X direction is smaller than the size of the second surface 13 along the X direction, and / or the size of the second die 30 along the Y direction is smaller than the size of the second surface 13 along the Y direction. For example, the size of the second die 30 along the X direction is smaller than the size of the second surface 13 along the X direction, and the size of the second die 30 along the Y direction is equal to the size of the second surface 13 along the Y direction; or, the size of the second die 30 along the X direction is equal to the size of the second surface 13 along the X direction, and the size of the second die 30 along the Y direction is smaller than the size of the second surface 13 along the Y direction; or, the size of the second die 30 along the X direction is smaller than the size of the second surface 13 along the X direction, and the size of the second die 30 along the Y direction is smaller than the size of the second surface 13 along the Y direction. In the embodiment, the second die 30 can also be a die obtained after cutting. Therefore, when the second die 30 is manufactured, the functional layer of the chip can be manufactured on a wafer first, then the wafer containing the functional layer of the chip is cut to obtain a plurality of dies, and then the qualified dies are selected as the second die 30. In this way, the yield of the second die 30 can be ensured, the dies with poor bonding function can be avoided, and thus the yield of the packaging structure 1 can be improved.

[0051] As shown in FIG. 3, the first bonding structure 40 can include a first metal wiring layer 43, a first hybrid bonding layer 44, a second hybrid bonding layer 45, and a second metal wiring layer 46 stacked in sequence along the Z direction. The first metal wiring layer 43, the first hybrid bonding layer 44, the second hybrid bonding layer 45, and the second metal wiring layer 46 can each include a metal structure and a dielectric structure, and the metal structures of the first metal wiring layer 43, the first hybrid bonding layer 44, the second hybrid bonding layer 45, and the second metal wiring layer 46 are connected and can each be copper. It can be understood that the specific structure of the second bonding structure 50 can be the same as that of the first bonding structure 40.

[0052] In addition, in the embodiment, the sizes of the chip structure 10, the first die 20, and the second die 30 along the X direction and / or along the Y direction are different, so that the number and size design of the first die 20 and the second die 30 are more flexible, and thus the size design of the packaging structure 1 is more flexible.

[0053] For the specific structure of the chip structure 10, in a possible implementation, as shown in FIG. 2, the chip structure 10 is a multi-layer chip 11. The bonding mode between the multi-layer chips 11 is W2W. A bonding structure is also formed between the multi-layer chips 11, and the specific structure of the bonding structure can be the same as that of the first bonding structure 40. Thus, in the embodiment, the chip structure 10 adopting the multi-layer chip 11 can realize the function of high-bandwidth storage.

[0054] In another possible implementation, as shown in FIG. 3, the chip structure 10 is a single-layer chip 11. In this embodiment, the chip structure 10 using the single-layer chip 11 can realize the computing function with high heat dissipation requirement.

[0055] As for the number of the first die 20, in one possible implementation, the packaging structure 1 can include one first die 20. In one example, as shown in FIG. 4, the first die 20 can be a multi-layer chip 21. In another example, as shown in FIG. 5, the first die 20 can be a single-layer chip 21.

[0056] The first die 20 and the chip structure 10 can be connected by die-to-wafer hybrid bonding. When the first die 20 is a multi-layer chip 21, the chip functional layers can be respectively fabricated on multiple wafers first, then the multiple wafers and the chip functional layers are bonded into one whole by wafer-to-wafer hybrid bonding, and then the first die 20 is formed by cutting. In the bonding process, a bonding structure can be formed between the wafers. The specific structure of the bonding structure can be the same as that of the first bonding structure 40. The single-layer chip 21 and the multi-layer chip 21 can be respectively used to realize different functions, thereby making the function selection of the packaging structure 1 more flexible.

[0057] In another possible implementation, as shown in FIG. 2, the packaging structure 1 can include at least two first dies 20, and the at least two first dies 20 are respectively arranged at intervals on the first bonding structure 40. A part of the first dies 20 are single-layer chips 21, and another part of the first dies 20 are multi-layer chips 21. The first dies 20 and the chip structure 10 can be connected by die-to-wafer hybrid bonding (D2W HB), and the multi-layer chips 21 are connected by wafer-to-wafer hybrid bonding (W2W HB).

[0058] As for the functions of the single-layer chip 21 and the multi-layer chip 21, in one example, the first die 20 using the single-layer chip 21 can realize the computing function with high heat dissipation requirement, and the first die 20 using the multi-layer chip 21 can realize the high-bandwidth storage function. In another example, the single-layer chip can be a silicon die without function, which is only used to adjust the silicon ratio on both sides of the chip structure 10 and balance the stress to reduce warping. In this way, on the one hand, the single-layer chip 21 and the multi-layer chip 21 can be respectively used to realize different functions, thereby making the function selection of the packaging structure 1 more flexible. On the other hand, the packaging structure 1 can realize the computing function and the high-bandwidth storage function, thereby making the packaging structure 1 applicable to the electronic device for near-memory computing.

[0059] As for the number of the second dies 30, in one possible implementation, the package structure 1 can include one second die 30. In one example, as shown in FIG. 4, the second die 30 is a single-layer chip 31. In another example, as shown in FIG. 5, the second die 30 is a multi-layer chip 31.

[0060] The second die 30 and the chip structure 10 can be connected by die-to-wafer hybrid bonding (D2W HB). When the second die 30 is a multi-layer chip 31, the chip functional layers can be respectively fabricated on multiple wafers first, then the multiple wafers containing the chip functional layers are bonded into one whole by wafer-to-wafer hybrid bonding (W2W HB), and then the second die 30 is cut. The single-layer chip 31 and the multi-layer chip 31 can be respectively used to realize different functions, thereby making the function selection of the package structure 1 more flexible.

[0061] In another possible implementation, the package structure 1 includes at least two second dies 30, and the at least two second dies 30 are respectively and spacedly arranged on the second bonding structure 50. A part of the second dies 30 are single-layer chips 31, and another part of the second dies 30 are multi-layer chips 31. The second dies 30 and the chip structure 10 are connected by D2W HB, and the multi-layer chips 31 can be connected by W2W HB.

[0062] As for the functions of the single-layer chip 31 and the multi-layer chip 31, in one example, the second die 30 using the single-layer chip 31 can realize the computing function with high heat dissipation requirement, and the second die 30 using the multi-layer chip 31 can realize the high-bandwidth storage function. In another example, the single-layer chip can be a non-functional silicon die, which is only used to adjust the silicon ratio on both sides of the chip structure 10 to balance the stress and reduce warping. In this way, on the one hand, the single-layer chip 31 and the multi-layer chip 31 can be respectively used to realize different functions, thereby making the function selection of the package structure 1 more flexible. On the other hand, the package structure 1 can realize the computing function and the high-bandwidth storage function, thereby making the package structure 1 applicable to the electronic device for near-memory computing.

[0063] In addition, since in the at least two first core particles 20, a part of the first core particles 20 are single-layer chips 21, and another part of the first core particles 20 are multi-layer chips 21; and in the at least two second core particles 30, a part of the second core particles 30 are single-layer chips 31, and another part of the second core particles 30 are multi-layer chips 31, that is to say, various combinations of single-layer chips and multi-layer chips can be arranged on both sides of the chip structure 10. The single-layer chips can also be non-functional structure silicon particles, which are only used to adjust the silicon ratio on both sides of the chip structure 10 to balance the stress. By controlling the area ratio of the core particles and the dielectric layer on the chip structure 10, the warping can be further relieved.

[0064] As shown in FIG. 2, the packaging structure 1 further comprises a third dielectric layer 60 arranged on the side of the first bonding structure 40 away from the chip structure 10, and the third dielectric layer 60 comprises a third dielectric structure 61 arranged between adjacent two first core particles 20 and at the periphery of the at least two first core particles 20.

[0065] As shown in FIG. 2, the packaging structure 1 comprises a fourth dielectric layer 70 arranged on the side of the second bonding structure 50 away from the chip structure 10, and the fourth dielectric layer 70 comprises a fourth dielectric structure 71 arranged between adjacent two second core particles 30 and at the periphery of the at least two second core particles 30. The projection area of the fourth dielectric layer 70 on the chip structure 10 is equal to or approximately equal to that of the third dielectric layer 60. In other words, the projection area of the at least two first core particles 20 on the chip structure 10 is equal to or approximately equal to that of the at least two second core particles 30, so that the warping generated in the stacking process and the warping of the final packaging structure 1 can be further relieved.

[0066] Further, as to the material of the third dielectric layer 60 and the fourth dielectric layer 70, in one possible implementation, the material of the third dielectric layer 60 and the fourth dielectric layer 70 is organic dielectric material. In this way, the cost can be reduced. In another possible implementation, the third dielectric layer 60 and the fourth dielectric layer 70 are both inorganic dielectric materials. In this way, the thermal expansion coefficients of the materials of the third dielectric layer 60 and the fourth dielectric layer 70 are relatively close, and the stress and warping generated in the manufacturing process are relatively close, so that the warping generated in the stacking process and the warping of the final packaging structure 1 can be further relieved.

[0067] Further, the materials of the third dielectric layer 60 and the fourth dielectric layer 70 are completely the same, so that the warping generated in the stacking process and the warping of the final packaging structure 1 can be further relieved.

[0068] As shown in FIG. 2, the packaging structure 1 can further include an under bump metallization (UBM) 81 at the bottom of the second die 30 and a controlled collapse chip connection (C4) bump 82 or μbump. It can be understood that the C4 bump 82 in FIG. 2 is only an example and is not necessarily a structure.

[0069] The embodiments of the present application further provide a manufacturing method of a packaging structure, which can be applied to the packaging structure 1 shown in FIG. 2. As shown in FIG. 6, the manufacturing method includes the following steps:

[0070] S601, providing a chip structure.

[0071] The chip structure 10 includes a substrate and a chip functional layer arranged on the substrate. The substrate is a continuous and complete substrate in a vertical plane along the thickness direction of the packaging structure 1. As shown in (a) of FIG. 7, the chip structure 10 has opposite first and second surfaces 12 and 13.

[0072] S602, manufacturing a first metal wiring layer and a hybrid bonding layer on the first surface.

[0073] In the embodiment, as shown in (b) of FIG. 7, the first metal wiring layer 43 is arranged between the chip structure 10 and the first hybrid bonding layer 44. The metal structure in the first metal wiring layer 43 is connected to the metal structure in the first hybrid bonding layer 44, and the metal structure in the first metal wiring layer 43 is connected to the through silicon via in the chip structure 10. After the first metal wiring layer 43 and the first hybrid bonding layer 44 are manufactured, a chemical-mechanical planarization (CMP) process can be performed on the first hybrid bonding layer 44, so that the surface topography of the first hybrid bonding layer 44 meets the requirements of the D2W hybrid bonding process.

[0074] S603, bonding a first die to the side of the first hybrid bonding layer away from the chip structure.

[0075] As shown in (c) of FIG. 7, the projection of the first die 20 on the first surface 12 is within the range of the first surface 12 and has a size smaller than that of the first surface 12. The number of the first die 20 can be at least two, and a part of the first die 20 is a single-layer die 21, and another part of the first die 20 is a multi-layer die 21. When the first die 20 is a multi-layer die 21, the following steps can be used for fabrication: first, a plurality of wafers on which chip functional layers are fabricated are bonded in sequence. The chip functional layers can be fabricated on the plurality of wafers respectively, and then the plurality of wafers on which the chip functional layers are fabricated are bonded in sequence in a W2W hybrid bonding manner. Second, the bonded wafers are cut to obtain the first die 20. The bonded wafers can be cut to obtain a plurality of die, and the qualified die can be selected as the first die 20. In this way, only the first die 20 with normal function can be used, so that the yield of the packaging structure 1 is improved.

[0076] The second metal wiring layer 46 and the second hybrid bonding layer 45 can be fabricated at the bottom of the first die 20, and the metal structure in the second metal wiring layer 46 is connected with the through silicon via inside the first die 20. The first die 20, the second metal wiring layer 46 and the second hybrid bonding layer 45 are fixed to the side of the first hybrid bonding layer 44 away from the chip structure 10, and the metal structure in the second hybrid bonding layer 45 is connected with the metal structure in the first hybrid bonding layer 44. The first metal wiring layer 43, the first hybrid bonding layer 44, the second hybrid bonding layer 45 and the second metal wiring layer 46 can form the first bonding structure 40, so that the first die 20 can be electrically connected with the through silicon via arranged in the chip structure 10 through the metal structure in the first bonding structure 40.

[0077] S604, as shown in (d) of FIG. 7, the third medium structure 61 is filled.

[0078] The third medium structure 61 can be filled between every two adjacent first die 20, and the third medium structure 61 can also be filled at the periphery of at least two first die 20. The first die 20 is connected to the side of the first hybrid bonding layer 44 away from the chip structure 10 in a hybrid bonding manner, and then the third medium structure 61 is filled. This method of directly bonding the first die 20 has better bonding position accuracy.

[0079] In another possible implementation, the step of bonding the first die 20 to the first surface 12 includes: fabricating the at least two first die 20 and the first medium structure as a first integral structure, and the first medium structure is between the two adjacent first die 20; and bonding the first integral structure to the first surface 12. This method can have a simpler bonding process, so that the yield is improved.

[0080] S605, as shown in (a) of FIG. 8, the chip structure 10 is thinned from the second surface 13.

[0081] Thus, the thickness required by the entire packaging structure 1 can be obtained.

[0082] S606, fabricating a first metal wiring layer and a first hybrid bonding layer on the second surface.

[0083] In the present embodiment, as shown in (b) of FIG. 8, the first metal wiring layer 43 is located between the first hybrid bonding layer 44 and the chip structure 10, the metal structures in the first metal wiring layer 43 are connected with the metal structures in the first hybrid bonding layer 44, and the metal structures in the first metal wiring layer 43 are connected with the through silicon vias in the chip structure 10. After the first metal wiring layer 43 and the first hybrid bonding layer 44 are fabricated, a chemical-mechanical planarization (CMP) process can be performed on the first hybrid bonding layer 44, so that the surface topography of the first hybrid bonding layer 44 meets the requirements of the D2W hybrid bonding process.

[0084] S607, bonding the second die to the side of the first hybrid bonding layer facing away from the chip structure.

[0085] As shown in (c) of FIG. 8, the number of the second dies 30 can be at least two, and a part of the second dies 30 are single-layer chips 31; and another part of the second dies 30 are multi-layer chips 31. When the second dies 30 are multi-layer chips 31, in the first step, a plurality of wafers on which chip functional layers are fabricated are bonded in sequence. The chip functional layers can be fabricated on the plurality of wafers respectively, and then the wafers on which the chip functional layers are fabricated are bonded in sequence in the manner of W2W hybrid bonding. In the second step, the bonded wafers are cut to obtain the second dies 30. After the bonded wafers are cut, a plurality of dies can be obtained, and the qualified dies can be selected as the second dies 30. Thus, it can be ensured that only the second dies 30 with normal functions are used, so as to improve the yield of the packaging structure 1.

[0086] It can be understood that the chip structure 10, the first die 20 and the second die 30 can be fabricated in parallel, that is, at the same time, so as to improve the yield and reduce the cost.

[0087] The second metal wiring layer 46 and the second hybrid bonding layer 45 can be fabricated on one side of the second die 30, and the metal structures in the second metal wiring layer 46 are connected to the through silicon vias inside the second die 30. The second die 30, the second metal wiring layer 46 and the second hybrid bonding layer 45 are fixed to the side of the first hybrid bonding layer 44 facing away from the chip structure 10, wherein the metal structures in the second hybrid bonding layer 45 are connected to the metal structures in the first hybrid bonding layer 44. The first metal wiring layer 43, the first hybrid bonding layer 44, the second hybrid bonding layer 45 and the second metal wiring layer 46 can form a second bonding structure 50, whereby the second die 30 can be electrically connected to the through silicon vias provided in the chip structure 10 through the metal structures in the second bonding structure 50. The projection of the second die 30 on the second surface 13 is smaller than the size of the second surface 13.

[0088] S608, as shown in (d) of FIG. 8, the fourth dielectric structure 71 is filled.

[0089] The fourth dielectric structure 71 can be filled between every two adjacent second dies 30, and the fourth dielectric structure 71 can also be filled around at least two second dies 30. The second dies 30 are first fixed to the side of the first hybrid bonding layer 44 facing away from the chip structure 10, and then the fourth dielectric structure 71 is filled, which directly bonds the second dies 30 and has better bonding position accuracy.

[0090] In addition, in the present embodiment, the fourth dielectric structure 71 between every two adjacent second dies 30 and around at least two second dies 30 can form a fourth dielectric layer 70, and the third dielectric structure 61 between every two adjacent first dies 20 and around at least two first dies 20 can form a third dielectric layer 60, the projection area of the fourth dielectric layer 70 and the third dielectric layer 60 on the chip structure 10 is equal or approximately equal, which can further relieve the warping generated during the fabrication of the package structure 1.

[0091] In other possible embodiments, the step of bonding the second dies 30 to the second surface 13 can include: fabricating the at least two second dies 30 and the fourth dielectric structure 71 as an integral structure, and the fourth dielectric structure 71 is between every two adjacent second dies 30 and around at least two second dies 30; and then bonding the integral structure to the second surface 13. This method can have a simpler bonding process, which can improve the yield.

[0092] After the fourth dielectric structure 71 is filled, an under bump metallization (UBM) 81, a controlled collapse chip connection (C4) bump 82 or μbump is formed on the bottom of the second die 30 in sequence, and a package structure 1 shown in Fig. 2 is obtained. Finally, the whole structure is cut and encapsulated to form a finished product. It can be understood that the C4 bump 82 in Fig. 2 is only an example and is not necessarily a structure.

[0093] It can be understood that in other embodiments, after the step of providing the chip structure 10, the manufacturing method further comprises: thinning the chip structure 10 from the second surface 13; fixing a carrier board on the new second surface 13 formed after the thinning; and before the step of bonding the second die 30 to the second surface 13, the manufacturing method further comprises: removing the carrier board. In this way, the thickness required when bonding the first die 20 to the chip structure 10 can be ensured, thereby reducing the case that the chip structure 10 is deformed too much during the bonding of the first die 20 due to the chip structure 10 being too thin, and the thickness required by the whole package structure 1 can be ensured after the carrier board is removed.

[0094] In the present embodiment, the first die 20 and the second die 30 are respectively located on the opposite first surface 12 and second surface 13 of the chip structure 10, thereby reducing the case that the wafer is warped too much during the manufacturing process and the finished package structure 1 is warped too much due to the multiple and layer-by-layer bonding of the dies on the same side of the chip structure 10, that is, the scheme of bonding the first die 20 and the second die 30 on the two side surfaces of the chip structure 10 respectively proposed in the present embodiment can balance the stress on the two sides of the chip structure 10, thereby relieving the warping of the package structure 1, and further improving the manufacturability of the mixed-bonding multi-layer stacked package structure 1 and reducing the reliability problems such as abnormal operation of the chip or damage of the structure of the package structure 1 due to uneven stress distribution.

[0095] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the specific embodiments described above, which are only illustrative and not restrictive, and those of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A package structure, characterized by, The package structure comprises: a chip structure, the chip structure comprising a substrate and a chip functional layer disposed on the substrate, the substrate being a continuous and complete substrate along a surface perpendicular to a thickness direction of the package structure, the chip structure having opposite first and second surfaces; a first bonding structure disposed on the first surface; a first core particle disposed on a side of the first bonding layer away from the chip structure, the first core particle being electrically connected to the chip structure through the first bonding structure, a projection of the first core particle on the first surface being located within the range of the first surface and having a size smaller than that of the first surface; a second bonding structure disposed on the second surface; a second core particle disposed on a side of the second bonding structure away from the chip structure, the second core particle being electrically connected to the chip structure through the second bonding structure, a projection of the second core particle on the second surface being located within the range of the second surface and having a size smaller than that of the second surface.

2. The package structure of claim 1, wherein, The first core particle is a single-layer chip or a multi-layer chip.

3. The package structure of claim 1, wherein, The package structure comprises at least two first core particles, the at least two first core particles being arranged on the first bonding structure at intervals, respectively, a part of the first core particles being single-layer chips and another part of the first core particles being multi-layer chips.

4. The package structure of any one of claims 1-3, wherein, The second core particle is a single-layer chip or a multi-layer chip.

5. The package structure of any one of claims 1-3, wherein, The package structure comprises at least two second core particles, the at least two second core particles being arranged on the second bonding structure at intervals, respectively, a part of the second core particles being single-layer chips and another part of the second core particles being multi-layer chips.

6. The package structure of any one of claims 1-5, wherein, The package structure comprises at least two first core particles and at least two second core particles. The package structure further comprises a third dielectric layer disposed on a side of the first bonding structure away from the chip structure, and the third dielectric layer comprises a third dielectric structure disposed between adjacent two first core particles and at the periphery of at least two first core particles. The package structure comprises a fourth dielectric layer disposed on a side of the second bonding structure away from the chip structure, and the fourth dielectric layer comprises a fourth dielectric structure disposed between adjacent two second core particles and at the periphery of at least two first core particles, the projection area of the fourth dielectric layer on the chip structure being equal to or approximately equal to that of the third dielectric layer.

7. The package structure of claim 6, wherein, The third dielectric layer and the fourth dielectric layer are both organic dielectric materials or both inorganic dielectric materials.

8. The package structure of any one of claims 1-7, wherein, The chip structure is a single-layer chip structure or a multi-layer chip structure.

9. An electronic device, comprising: The package structure is disposed on a circuit board.

10. A method for fabricating a package structure, the method comprising: The manufacturing method comprises: providing a chip structure, the chip structure comprising a substrate and a chip functional layer disposed on the substrate, the substrate being a continuous and complete substrate, the chip structure having opposite first and second surfaces; bonding a first core particle to the first surface, a first bonding structure being formed between the first core particle and the chip structure, the first core particle being electrically connected to the chip structure through the first bonding structure, a projection of the first core particle on the first surface being within the range of the first surface and having a size smaller than that of the first surface; bonding a second core particle to the second surface, a second bonding structure being formed between the second core particle and the chip structure, the second core particle being electrically connected to the chip structure through the second bonding structure, a projection of the second core particle on the second surface being within the range of the second surface and having a size smaller than that of the second surface.

11. The method of manufacturing according to claim 10, wherein, Before the step of bonding a first core particle to the first surface, the manufacturing method further comprises: bonding a plurality of wafers successively, each wafer being provided with a chip functional layer; cutting the bonded wafers and selecting core particles with normal functions to obtain the first core particle.

12. The production method according to claim 10 or 11, characterized by, The step of bonding a first core particle to the first surface comprises: bonding at least two first core particles to the first surface respectively; filling a third medium structure between each pair of adjacent first core particles and around the periphery of the at least two first core particles.

13. The production method according to claim 10 or 11, characterized by, The step of bonding a first core particle to the first surface comprises: manufacturing at least two first core particles and a third medium structure as a first integral structure, the third medium structure being located between each pair of adjacent first core particles and around the periphery of the at least two first core particles; bonding the first integral structure to the first surface.

14. The production method according to claim 12 or 13, characterized by, The step of bonding a second core particle to the second surface comprises: bonding at least two second core particles to the second surface respectively; filling a fourth medium structure between each pair of adjacent second core particles and around the periphery of the at least two second core particles, the fourth medium structure having a projection area on the chip structure equal to or approximately equal to that of the third medium structure.

15. The method of manufacturing according to claim 12 or 13, wherein, The step of bonding a second core particle to the second surface comprises: manufacturing at least two second core particles and a fourth medium structure as a second integral structure, the fourth medium structure being located between each pair of adjacent second core particles and around the periphery of the at least two second core particles; bonding the second integral structure to the second surface.

16. The method of making according to any one of claims 10-15, wherein, Before the step of bonding a second core particle to the second surface, the manufacturing method further comprises: thinning the chip structure from the second surface.

17. The method of making according to any one of claims 10-15, wherein, After the step of providing a chip structure, the manufacturing method further comprises: thinning the chip structure from the second surface; fixing a carrier plate on the newly formed second surface after thinning; Before the step of bonding a second core particle to the second surface, the manufacturing method further comprises: removing the carrier plate.

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