Pixel driving circuit, pixel driving circuit driving method and display panel

Abstract

The present disclosure relates to the technical field of display, and provides a pixel driving circuit, a pixel driving circuit driving method and a display panel. The pixel driving circuit comprises a driving transistor, a gate reset sub-circuit, a threshold compensation sub-circuit, a voltage stabilizing sub-circuit, a data writing sub-circuit, a first capacitor and a second capacitor, wherein the gate reset sub-circuit is used for loading a reference voltage to a first node in response to the gate level of a second reset control signal; the threshold compensation sub-circuit is used for, in response to the gate level of a fourth reset control signal, enabling a third node and the first node to be communicated with each other; the voltage stabilizing sub-circuit is used for loading a constant voltage to a fifth node in response to the gate level of a third reset control signal; and the data writing sub-circuit is used for loading a data voltage to the first node in response to the gate level of a data writing control signal. The present disclosure can improve the display quality of the display panel.

Description

Pixel driving circuit, driving method of pixel driving circuit and display panel

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410642997.4, filed May 22, 2024, entitled “Pixel driving circuit, driving method of pixel driving circuit and display panel,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a pixel driving circuit, a driving method of pixel driving circuit and a display panel. BACKGROUND

[0004] AMOLED (active matrix organic light emitting diode) is suitable for electronic products such as tablet computers and notebook computers. In the pixel driving circuit, threshold compensation and data voltage writing are usually performed simultaneously; however, when high-frequency refreshing is performed, the charging time of each row of pixel driving circuits is shortened, which easily leads to insufficient threshold compensation, so that the display panel appears uneven display, thereby affecting the display quality of the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a pixel driving circuit, a driving method of pixel driving circuit and a display panel, which can improve the display quality of the display panel.

[0007] According to one aspect of the present disclosure, a pixel driving circuit is provided, comprising a driving transistor, a gate reset sub-circuit, a threshold compensation sub-circuit, a voltage stabilizing sub-circuit, a data writing sub-circuit, a first capacitor and a second capacitor;

[0008] The first end of the gate reset sub-circuit is electrically connected with a reference voltage end, the second end of the gate reset sub-circuit, the second end of the threshold compensation sub-circuit, the control electrode of the driving transistor, the second end of the data writing sub-circuit, the second end of the second capacitor and the first node are mutually electrically connected, and the control end of the gate reset sub-circuit is electrically connected with a second reset control signal end; the gate reset sub-circuit is used to load the reference voltage to the first node in response to the gating level of the second reset control signal.

[0009] The first end of the threshold compensation sub-circuit, the second electrode of the driving transistor, and the third node are electrically connected to each other, and the control end of the threshold compensation sub-circuit is electrically connected to the fourth reset control signal end; the threshold compensation sub-circuit is used for making the third node and the first node communicate with each other in response to the gating level of the fourth reset control signal.

[0010] The first end of the voltage stabilizing sub-circuit is electrically connected to the constant voltage end, the second end of the voltage stabilizing sub-circuit, the second end of the first capacitor, the first end of the second capacitor, and the fifth node are electrically connected to each other, and the control end of the voltage stabilizing sub-circuit is electrically connected to the third reset control signal end; the voltage stabilizing sub-circuit is used for loading the constant voltage to the fifth node in response to the gating level of the third reset control signal.

[0011] The first end of the data writing sub-circuit is electrically connected to the data voltage end, and the control end of the data writing sub-circuit is electrically connected to the data writing control signal end; the data writing sub-circuit is used for loading the data voltage to the first node in response to the gating level of the data writing control signal.

[0012] The first electrode of the driving transistor, the first end of the first capacitor, and the second node are electrically connected to each other; the driving transistor is used for generating a driving current.

[0013] In an embodiment of the present disclosure, the second reset control signal and the fourth reset control signal are the same signal.

[0014] In an embodiment of the present disclosure, the gate reset sub-circuit comprises a gate reset transistor.

[0015] The first electrode of the gate reset transistor is electrically connected to the reference voltage end, the second electrode of the gate reset transistor is electrically connected to the first node, and the control electrode of the gate reset transistor is electrically connected to the second reset control signal end; the gate reset transistor is used for loading the reference voltage to the first node in response to the gating level of the second reset control signal.

[0016] The threshold compensation sub-circuit comprises a threshold compensation transistor.

[0017] The first electrode of the threshold compensation transistor is electrically connected to the third node, the second electrode of the threshold compensation transistor is electrically connected to the first node, and the control electrode of the threshold compensation transistor is electrically connected to the fourth reset control signal end; the threshold compensation transistor is used for making the third node and the first node communicate with each other in response to the gating level of the fourth reset control signal.

[0018] The voltage stabilizing sub-circuit comprises a voltage stabilizing transistor.

[0019] The first electrode of the voltage stabilizing transistor is electrically connected with the constant voltage terminal, the second electrode of the voltage stabilizing transistor is electrically connected with the fifth node, and the control electrode of the voltage stabilizing transistor is electrically connected with the third reset control signal terminal; the voltage stabilizing transistor is used for loading the constant voltage to the fifth node in response to the gating level of the third reset control signal.

[0020] The data writing sub-circuit comprises a data writing transistor.

[0021] The first electrode of the data writing transistor is electrically connected with the data voltage terminal, the second electrode of the data writing transistor is electrically connected with the first node, and the control electrode of the data writing transistor is electrically connected with the data writing control signal terminal; the data writing transistor is used for loading the data voltage to the first node in response to the gating level of the data writing control signal.

[0022] In an embodiment of the present disclosure, the pixel driving circuit further comprises a first light-emitting control sub-circuit and a second light-emitting control sub-circuit.

[0023] The first end of the first light-emitting control sub-circuit is electrically connected with the driving power voltage terminal, the second end of the first light-emitting control sub-circuit is electrically connected with the second node, and the control end of the first light-emitting control sub-circuit is electrically connected with the light-emitting control signal terminal; the first light-emitting control sub-circuit is used for loading the driving power voltage to the second node in response to the gating level of the light-emitting control signal.

[0024] The first end of the second light-emitting control sub-circuit is electrically connected with the third node, the second end of the second light-emitting control sub-circuit, the pixel electrode and the fourth node are electrically connected with each other, and the control end of the second light-emitting control sub-circuit is electrically connected with the light-emitting control signal terminal; the second light-emitting control sub-circuit is used for making the third node and the fourth node communicate with each other in response to the gating level of the light-emitting control signal.

[0025] In an embodiment of the present disclosure, the first light-emitting control sub-circuit comprises a first light-emitting control transistor.

[0026] The first electrode of the first light-emitting control transistor is electrically connected with the driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with the second node, and the control electrode of the first light-emitting control transistor is electrically connected with the light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the light-emitting control signal.

[0027] The second light-emitting control sub-circuit comprises a second light-emitting control transistor.

[0028] A first electrode of the second light-emitting control transistor is electrically connected with the third node, a second electrode of the second light-emitting control transistor is electrically connected with the fourth node, and a control electrode of the second light-emitting control transistor is electrically connected with a light-emitting control signal terminal; the second light-emitting control transistor is configured to make the third node and the fourth node communicate with each other in response to a gating level of the light-emitting control signal.

[0029] In an embodiment of the present disclosure, the pixel driving circuit further comprises an electrode reset sub-circuit and a switch reset sub-circuit.

[0030] The first end of the electrode reset sub-circuit is electrically connected with a first initialization voltage terminal, the second end of the electrode reset sub-circuit is electrically connected with the fourth node, and the control end of the electrode reset sub-circuit is electrically connected with a first reset control signal terminal; the electrode reset sub-circuit is configured to load the first initialization voltage to the fourth node in response to a gating level of the first reset control signal.

[0031] The first end of the switch reset sub-circuit is electrically connected with a second initialization voltage terminal, the second end of the switch reset sub-circuit is electrically connected with the second node, and the control end of the switch reset sub-circuit is electrically connected with the first reset control signal terminal; the switch reset sub-circuit is configured to load the second initialization voltage to the second node in response to a gating level of the first reset control signal.

[0032] In an embodiment of the present disclosure, the electrode reset sub-circuit comprises an electrode reset transistor.

[0033] The first electrode of the electrode reset transistor is electrically connected with the first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with the first reset control signal terminal; the electrode reset transistor is configured to load the first initialization voltage to the fourth node in response to a gating level of the first reset control signal.

[0034] The switch reset sub-circuit comprises a switch reset transistor.

[0035] The first electrode of the switch reset transistor is electrically connected with the second initialization voltage terminal, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal terminal; the switch reset transistor is configured to load the second initialization voltage to the second node in response to a gating level of the first reset control signal.

[0036] In an embodiment of the present disclosure, the pixel driving circuit further comprises a first light-emitting control transistor, a second light-emitting control transistor, an electrode reset transistor, and a switch reset transistor.

[0037] The first electrode of the first light-emitting control transistor is electrically connected with a driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with the second node, and the control electrode of the first light-emitting control transistor is electrically connected with a light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the light-emitting control signal;

[0038] The first electrode of the second light-emitting control transistor is electrically connected with the third node, the second electrode of the second light-emitting control transistor is electrically connected with the fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal terminal; the second light-emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the light-emitting control signal;

[0039] The first electrode of the electrode reset transistor is electrically connected with a first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with a first reset control signal terminal; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to the gating level of the first reset control signal;

[0040] The first electrode of the switch reset transistor is electrically connected with the second initialization voltage terminal, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal terminal; the switch reset transistor is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal.

[0041] In an embodiment of the present disclosure, the pixel driving circuit further comprises a first light-emitting control transistor, a second light-emitting control transistor, an electrode reset transistor, and a switch reset transistor.

[0042] The first electrode of the first light-emitting control transistor is electrically connected with a driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with the second node, and the control electrode of the first light-emitting control transistor is electrically connected with a first light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the first light-emitting control signal;

[0043] The first electrode of the second light-emitting control transistor is electrically connected with the third node, the second electrode of the second light-emitting control transistor is electrically connected with the fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with a second light-emitting control signal terminal; the second light-emitting control transistor is configured to make the third node and the fourth node communicate with each other in response to a gating level of the second light-emitting control signal.

[0044] The first electrode of the electrode reset transistor is electrically connected with a first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with a second reset control signal terminal; the electrode reset transistor is configured to load the first initialization voltage to the fourth node in response to a gating level of the second reset control signal.

[0045] In an embodiment of the present disclosure, the pixel driving circuit is configured to write the data voltage into the first node by the data writing sub-circuit after the reference voltage is written into the first node by the gate reset sub-circuit.

[0046] In an embodiment of the present disclosure, the material of the channel region of at least one transistor is metal oxide semiconductor material.

[0047] In an embodiment of the present disclosure, the constant voltage is any one of a driving power voltage, a first initialization voltage, a second initialization voltage, and a reference voltage.

[0048] According to another aspect of the present disclosure, a driving method of a pixel driving circuit is also provided, which is applied to the pixel driving circuit; wherein the driving method of the pixel driving circuit comprises:

[0049] In the reset phase, the pixel driving circuit is loaded with a gating level of a second reset control signal, a third reset control signal, and a fourth reset control signal.

[0050] In the compensation phase, the pixel driving circuit is loaded with a gating level of a second reset control signal, a third reset control signal, and a fourth reset control signal.

[0051] In the writing phase, the pixel driving circuit is loaded with a gating level of a third reset control signal and a data writing control signal.

[0052] In an embodiment of the present disclosure, the pixel driving circuit further comprises a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, an electrode reset sub-circuit, and a switch reset sub-circuit.

[0053] The first light-emitting control sub-circuit comprises a first light-emitting control transistor.

[0054] The first electrode of the first light-emitting control transistor is electrically connected with a driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with a second node, and the control electrode of the first light-emitting control transistor is electrically connected with a light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to a gating level of the light-emitting control signal.

[0055] The second light-emitting control sub-circuit comprises a second light-emitting control transistor.

[0056] The first electrode of the second light-emitting control transistor is electrically connected with a third node, the second electrode of the second light-emitting control transistor is electrically connected with a fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal terminal; the second light-emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the light-emitting control signal.

[0057] The electrode reset sub-circuit comprises an electrode reset transistor.

[0058] The first electrode of the electrode reset transistor is electrically connected with a first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with a first reset control signal terminal; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to a gating level of the first reset control signal.

[0059] The switch reset sub-circuit comprises a switch reset transistor.

[0060] The first electrode of the switch reset transistor is electrically connected with a second initialization voltage terminal, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal terminal; the switch reset transistor is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal.

[0061] The driving method of the pixel driving circuit comprises:

[0062] In the reset stage, the gating levels of the first reset control signal, the second reset control signal, the third reset control signal and the fourth reset control signal are loaded to the pixel driving circuit.

[0063] In the compensation stage, the gating levels of the second reset control signal, the third reset control signal and the fourth reset control signal are loaded to the pixel driving circuit.

[0064] In the writing stage, the gating levels of the third reset control signal and the data writing control signal are loaded to the pixel driving circuit.

[0065] In the light emitting stage, the pixel driving circuit is loaded with a gate level of the first light emitting control signal and a gate level of the second light emitting control signal.

[0066] According to a third aspect of the present disclosure, a driving method of a pixel driving circuit is also provided, applied to the pixel driving circuit; wherein the driving method of the pixel driving circuit comprises:

[0067] In the reset stage, the pixel driving circuit is loaded with a gate level of the first light emitting control signal, a gate level of the second reset control signal, and a gate level of the third reset control signal;

[0068] In the compensation stage, the pixel driving circuit is loaded with a gate level of the second reset control signal and a gate level of the third reset control signal;

[0069] In the write stage, the pixel driving circuit is loaded with a gate level of the third reset control signal and a gate level of the data write control signal;

[0070] In the light emitting stage, the pixel driving circuit is loaded with a gate level of the first light emitting control signal and a gate level of the second light emitting control signal.

[0071] According to a fourth aspect of the present disclosure, a display panel is also provided, comprising the pixel driving circuit arranged in an array.

[0072] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0073] The drawings herein are incorporated into the description and form part of the description, showing embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0074] FIG. 1 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0075] FIG. 2 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0076] FIG. 3 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0077] FIG. 4 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0078] FIG. 5 is a driving timing diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0079] FIG. 6-1 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0080] FIG. 6-2 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0081] FIG. 6-3 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0082] FIG. 6-4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0083] FIG. 7 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0084] FIG. 8 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0085] FIG. 9-1 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0086] FIG. 9-2 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0087] FIG. 9-3 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0088] FIG. 9-4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0089] FIG. 10 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0090] FIG. 11 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0091] FIG. 12 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0092] FIG. 13 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0093] FIG. 14 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0094] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be simplified or omitted. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0095] Although relative terms are used in this description, such as "upper," "lower," to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not intended to limit the scope of the disclosure to a particular orientation. It is to be understood that if the icon were turned over, such that the "upper" component became the "lower" component, then such would be within the scope of the disclosure. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0096] The terms "a," "an," "the" and "at least one" are used to mean one or more of something; the terms "comprises", "comprising", "has", "having" and "includes" are used to mean including, but not limited to; the term "first," "second," and "third," etc. are used to mean different or separate from one another and are not intended to imply an order or sequence unless otherwise specifically stated; and the term "one" is used to mean one, but also to mean greater than one unless otherwise indicated.

[0097] In this disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to a region in which current flows mainly.

[0098] In this specification, the "source" and "drain" of any one transistor are called a first electrode and a second electrode of the transistor, respectively, and the gate is called a control electrode of the transistor. The first electrode can be the drain electrode, and the second electrode can be the source electrode, or the first electrode can be the source electrode, and the second electrode can be the drain electrode. In this specification, at least part of a signal has a high level and a low level; one of the high level and the low level can be a selection level of the signal, which can cause a transistor controlled by the signal to be turned on; the other of the high level and the low level can be an off level of the signal, which can cause the transistor controlled by the signal to be turned off. For example, for a signal for controlling a P-type transistor, which can be input to a control terminal of the P-type transistor, the selection level of the signal is the low level, and the off level of the signal is the high level. For another example, for a signal for controlling an N-type transistor, which can be input to a control terminal of the N-type transistor, the selection level of the signal is the high level, and the off level of the signal is the low level.

[0099] The structure layer A is formed on the side of the structure layer B away from the substrate. It can be understood that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be at the same physical height as the structure layer B or lower than the physical height of the structure layer B, wherein the substrate is the height reference.

[0100] The display panel PNL provided by the embodiment of the present disclosure includes a display area AA and a peripheral area BB located at least one side of the display area AA. The display area AA of the display panel PNL includes an array of display units. The display unit includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL has a plurality of scan lines GL arranged along the row direction DH in the display area AA, each scan line GL is arranged one-to-one corresponding to each display unit row; the scan line GL is connected with each pixel driving circuit PDC of the corresponding display unit row. The display panel PNL has a plurality of data lines DL arranged along the column direction DV in the display area AA, each data line DL is arranged one-to-one corresponding to each display unit column; the data line DL is connected with each pixel driving circuit PDC of the corresponding display unit column. In this way, the pixel driving circuit PDC of each display unit is connected with one scan line GL and one data line DL. When the selection signal is loaded on the scan line GL, the data voltage loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0101] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, Mini LED and the like. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0102] In an embodiment of the present disclosure, referring to FIG. 2, the display panel PNL can include a substrate BP, a driving layer DRL and a pixel layer PIXL arranged in sequence. The pixel layer PIXL is provided with sub-pixels PIX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixel PIX; each sub-pixel PIX can emit light under the driving of the pixel driving circuit PDC to display a picture. Further, the display panel PNL further includes a thin film encapsulation layer TFE located away from the substrate BP on the side of the pixel layer PIXL, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0103] Optionally, the substrate BP can be a substrate of inorganic material, or a substrate of organic material, or a composite substrate of a substrate of inorganic material and a substrate of organic material. For example, in some embodiments of the present disclosure, the substrate BP can be made of glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the substrate BP can be made of poly(methyl methacrylate), polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate BP can be a flexible substrate, for example, the substrate BP can include polyimide.

[0104] Optionally, in the driving layer DRL, any one of the pixel driving circuits PDC can include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0105] It can be understood that in the pixel driving circuit PDC, the types of any two of the transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit PDC, some of the transistors can be N-type transistors and some of the transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit PDC, the material of the active layer of some of the transistors can be low-temperature polysilicon semiconductor material and the material of the active layer of some of the transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some of the thin film transistors are low-temperature polysilicon transistors and some of the thin film transistors are metal oxide transistors.

[0106] Optionally, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. which are stacked between the substrate base plate BP and the pixel layer PIXL. Each thin film transistor and storage capacitor can be located in the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form part of the wiring or conductive structure by being conductive if necessary. The gate layer GT can be used to form one or more of the gate layer GT wiring such as the write control wiring, the reset control wiring, the light-emitting control wiring, etc., and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer SD can be used to form the data wiring, the driving power voltage wiring, etc. of the source-drain metal layer wiring, and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a light shielding layer between the semiconductor layer SCL and the substrate base plate BP, etc. As needed, any one of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD, etc. film layer can also be multi-layered, for example, the driving layer DRL can include two different semiconductor layers SCL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) can be adaptively increased or reduced, or new insulating film layers can be added as needed.

[0107] Optionally, the driving layer DRL can also include a passivation layer, which can be arranged on the surface of the source-drain metal layer SD away from the substrate base plate BP, so as to protect the source-drain metal layer SD.

[0108] As an example, referring to FIG. 2, the driving layer DRL can include a buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD and a planarization layer PLN which are sequentially stacked, and the thin film transistor formed in this way is a top gate type thin film transistor.

[0109] In an embodiment of the present disclosure, the sub-pixel PIX in the pixel layer PIXL is a thin film light emitting element, which can include two electrodes and a light emitting functional unit arranged between the two electrodes. For example, referring to FIG. 2, the pixel layer PIXL can include a pixel electrode layer PEL, a light emitting functional layer EFL, and a common electrode layer COML arranged in sequence. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The light emitting functional layer EFL has a part connected with the pixel electrode PE as the light emitting functional unit of the sub-pixel PIX. The common electrode layer COML is electrically connected with the light emitting functional unit of each sub-pixel PIX as a common electrode.

[0110] Further, the pixel layer PIXL can further include a pixel definition layer PDL between the pixel electrode layer PEL and the light emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE. Any one pixel opening exposes at least a part of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a part of the inner area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected with the light emitting functional unit), and further define the light emitting area and the light emitting area of the sub-pixel PIX. The light emitting functional layer EFL covers at least the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light emitting functional layer EFL, so that the light emitting functional layer EFL emits light. The part of the light emitting functional layer EFL between the pixel electrode layer PEL and the common electrode layer COML can be used as a light emitting functional unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form the sub-pixel PIX. One of the pixel electrode PE and the common electrode layer COML is an anode of the sub-pixel PIX, and the other is a cathode of the sub-pixel PIX.

[0111] In an example, the pixel electrode PE is an anode of the sub-pixel PIX, and the common electrode layer COML is a cathode of the sub-pixel PIX.

[0112] It can be understood that the type of light emitting element is different, and the material and film layer of the light emitting functional unit are different. For example, when the light emitting element is an OLED, the light emitting functional unit can include an organic electroluminescent material layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0113] Referring to FIG. 2, a thin film encapsulation layer TFE can be disposed on a surface of the pixel layer PIXL away from the substrate BP, which can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layers can effectively block moisture and oxygen from the outside, avoiding the invasion of water and oxygen into the pixel layer PIXL and causing the material in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layers can be located in the peripheral region. The organic encapsulation layers are located between two adjacent inorganic encapsulation layers in order to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edges of the organic encapsulation layers can be located between the edges of the display region and the edges of the inorganic encapsulation layers. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 stacked in sequence on a side of the pixel layer PIXL away from the substrate BP. The first inorganic encapsulation layer CVD1 covers the display region and extends to the outside of the barrier wall; the organic encapsulation layer IJP covers the display region and extends to the inside of the barrier wall; and the second inorganic encapsulation layer CVD2 covers the organic encapsulation layer IJP and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer CVD2 is in contact with the first inorganic encapsulation layer CVD1. In this way, the organic encapsulation layer IJP is enclosed by the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and the stress on the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 is balanced. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 enclose the organic encapsulation layer IJP, isolating the organic encapsulation layer IJP from water and oxygen.

[0114] In some embodiments of the present disclosure, referring to FIG. 2, the display panel PNL can further include a touch function layer TSL, which can be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has a touch function.

[0115] Optionally, the pixel driving circuit PDC at least includes a data writing transistor, a driving transistor and a storage capacitor, a gate of the driving transistor can be electrically connected with one electrode plate of the storage capacitor. A source of the data writing transistor can be electrically connected with a data line DL, and a gate of the data writing transistor can be electrically connected with a scan line GL. The pixel driving circuit PDC is configured to, when a scan signal is loaded on the scan line GL, the data writing transistor is turned on, so that a driving voltage on the data line DL is written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on the gate thereof. It can be understood that the pixel driving circuit PDC of the embodiments of the present disclosure can also include other transistors or capacitors to make the pixel driving circuit PDC have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architecture of pixel driving circuit.

[0116] In the related art, the threshold compensation phase and the data writing phase of the pixel driving circuit PDC are carried out at the same time. In the high-frequency refresh process, due to the shortening of the time of the data writing phase of each row of sub-pixels, the threshold compensation is not sufficient, which affects the display quality of the display panel. For example, in the high-frequency refresh, the time length of the threshold compensation phase of each row of sub-pixels is greater than the time length of the data writing phase. If the threshold compensation phase and the data writing phase are carried out at the same time, the time of the threshold compensation will be correspondingly shortened, so that the threshold compensation is not sufficient, which causes the display panel to have display unevenness and the like.

[0117] In order to solve the above problems, the embodiments of the present disclosure provide a pixel driving circuit PDC applied to a display panel PNL. Referring to FIG. 3, the pixel driving circuit PDC includes a driving transistor T3, a gate reset sub-circuit SW1, a threshold compensation sub-circuit SW2, a voltage stabilizing sub-circuit SW3, a data writing sub-circuit SW4, a first capacitor C1 and a second capacitor C2. Wherein, a first end of the gate reset sub-circuit SW1 is electrically connected with a reference voltage end, a second end of the gate reset sub-circuit SW1, a second end of the threshold compensation sub-circuit SW2, a control electrode of the driving transistor T3, a second end of the data writing sub-circuit SW4, a second end of the second capacitor C2, a first node N1 are mutually electrically connected, and a control end of the gate reset sub-circuit SW1 is electrically connected with a second reset control signal end. The gate reset sub-circuit SW1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2.

[0118] The first end of the threshold compensation sub-circuit SW2, the second electrode of the driving transistor T3, and the third node N3 are electrically connected to each other, and the control end of the threshold compensation sub-circuit SW2 is electrically connected to the fourth reset control signal end. The threshold compensation sub-circuit SW2 is configured to make the third node N3 communicate with the first node N1 in response to the gating level of the fourth reset control signal RST4. The fourth reset control signal RST4 and the second reset control signal RST2 can be the same signal, so as to simultaneously turn on and turn off the gate reset sub-circuit SW1 and the threshold compensation sub-circuit SW2. In an example, the fourth reset control signal RST4 and the second reset control signal RST2 are loaded on the same wire. In another example, the fourth reset control signal RST4 and the second reset control signal RST2 are loaded on different wires.

[0119] The first end of the voltage stabilizing sub-circuit SW3 is electrically connected to the constant voltage end, the second end of the voltage stabilizing sub-circuit SW3, the second end of the first capacitor C1, the first end of the second capacitor C2, and the fifth node N5 are electrically connected to each other, and the control end of the voltage stabilizing sub-circuit SW3 is electrically connected to the third reset control signal end. The voltage stabilizing sub-circuit SW3 is configured to load the constant voltage Vx to the fifth node N5 in response to the gating level of the third reset control signal RST3.

[0120] The first end of the data writing sub-circuit SW4 is electrically connected to the data voltage end, and the control end of the data writing sub-circuit SW4 is electrically connected to the data writing control signal end. The data writing sub-circuit SW4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data writing control signal GS.

[0121] The first electrode of the driving transistor T3, the first end of the first capacitor C1, and the second node N2 are electrically connected to each other. The driving transistor T3 is configured to generate a driving current.

[0122] In this way, by electrically connecting the second end of the data writing sub-circuit SW4 to the first node N1, and electrically connecting the first end of the threshold compensation sub-circuit SW2 to the third node N3, and electrically connecting the second end of the threshold compensation sub-circuit SW2 to the first node N1, the threshold compensation stage and the data writing stage of the pixel driving circuit PDC can be independently performed in the high-frequency refresh process, and the threshold compensation stage is no longer limited by the time length of the data writing stage, so as to more fully compensate the threshold voltage of the pixel driving circuit PDC, reduce the possibility of display unevenness of the display panel PNL, and improve the display quality of the display panel PNL.

[0123] In one embodiment of the present disclosure, referring to FIG. 3, the gate reset sub-circuit SW1 includes a gate reset transistor T1. The first pole of the gate reset transistor T1 is electrically connected with a reference voltage terminal, the second pole of the gate reset transistor T1 is electrically connected with the first node N1, and the control pole of the gate reset transistor T1 is electrically connected with a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. In other embodiments of the present disclosure, the gate reset sub-circuit SW1 can include a plurality of gate reset transistors T1 connected in series or in parallel. Thus, the gate reset transistor T1 is turned on to load the reference voltage Vref to the first node N1, so as to reset the first node N1.

[0124] In one embodiment of the present disclosure, referring to FIG. 3, the threshold compensation sub-circuit SW2 includes a threshold compensation transistor T2. The first pole of the threshold compensation transistor T2 is electrically connected with the third node N3, the second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, and the control pole of the threshold compensation transistor T2 is electrically connected with a fourth reset control signal terminal. The threshold compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the fourth reset control signal RST4. In other embodiments of the present disclosure, the threshold compensation sub-circuit SW2 can include a plurality of threshold compensation transistors T2 connected in series or in parallel. Thus, the threshold compensation transistor T2 is turned on to make the first node N1 and the third node N3 communicate with each other, so as to write the subsequent threshold voltage to the first node N1.

[0125] In one embodiment of the present disclosure, referring to FIG. 3, the voltage stabilizing sub-circuit SW3 includes a voltage stabilizing transistor T9. The first pole of the voltage stabilizing transistor T9 is electrically connected with a constant voltage terminal, the second pole of the voltage stabilizing transistor T9 is electrically connected with the fifth node N5, and the control pole of the voltage stabilizing transistor T9 is electrically connected with a third reset control signal terminal. The voltage stabilizing transistor T9 is configured to load the constant voltage Vx to the fifth node N5 in response to the gating level of the third reset control signal RST3. In other embodiments of the present disclosure, the voltage stabilizing sub-circuit SW3 can include a plurality of voltage stabilizing transistors T9 connected in series or in parallel. Thus, the voltage stabilizing transistor T9 is turned on to load the driving power voltage VDD to the fifth node N5, so as to stabilize the second node N2.

[0126] In an embodiment of the present disclosure, referring to FIG. 3, the data writing sub-circuit SW4 comprises a data writing transistor T4. The first pole of the data writing transistor T4 is electrically connected with the data voltage terminal, the second pole of the data writing transistor T4 is electrically connected with the first node N1, and the control pole of the data writing transistor T4 is electrically connected with the data writing control signal terminal. The data writing transistor T4 is used to load the data voltage Data to the first node N1 in response to the gating level of the data writing control signal GS. In other embodiments of the present disclosure, the data writing sub-circuit SW4 can comprise a plurality of data writing transistors T4 connected in series or in parallel. Thus, the data writing transistor T4 is turned on to facilitate the writing of the data voltage Data to the first node N1.

[0127] It can be understood that, in the present disclosure, the gating level of each signal refers to the level at which the sub-circuit or transistor corresponding to the signal can be turned on. The cut-off level of each signal refers to the level at which the sub-circuit or transistor corresponding to the signal can be turned off. For example, in an embodiment of the present disclosure, the gating level of the data writing control signal GS refers to the level at which the data writing sub-circuit SW4 or the data writing transistor T4 can be turned on. The cut-off level of the data writing control signal GS refers to the level at which the data writing sub-circuit SW4 or the data writing transistor T4 can be turned off.

[0128] In an embodiment of the present disclosure, referring to FIG. 3, the pixel driving circuit PDC further comprises a first light emitting control sub-circuit SW5 and a second light emitting control sub-circuit SW6. The first terminal of the first light emitting control sub-circuit SW5 is electrically connected with the driving power voltage terminal, the second terminal of the first light emitting control sub-circuit SW5 is electrically connected with the second node N2, and the control terminal of the first light emitting control sub-circuit SW5 is electrically connected with the light emitting control signal terminal. The first light emitting control sub-circuit SW5 is used to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM.

[0129] In an embodiment of the present disclosure, referring to FIG. 3, the first terminal of the second light emitting control sub-circuit SW6 is electrically connected with the third node N3, the second terminal of the second light emitting control sub-circuit SW6, the pixel electrode, and the fourth node N4 are electrically connected with each other, and the control terminal of the second light emitting control sub-circuit SW6 is electrically connected with the light emitting control signal terminal. The second light emitting control sub-circuit SW6 is used to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light emitting control signal EM.

[0130] In an embodiment of the present disclosure, referring to FIG. 3, the first light-emitting control sub-circuit SW5 includes a first light-emitting control transistor T5. The first electrode of the first light-emitting control transistor T5 is electrically connected to the driving power supply voltage terminal, the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2, and the control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal. The first light-emitting control transistor T5 is configured to load the driving power supply voltage VDD to the second node N2 in response to the gating level of the light-emitting control signal EM. In other embodiments of the present disclosure, the first light-emitting control sub-circuit SW5 can include a plurality of first light-emitting control transistors T5 connected in series or in parallel.

[0131] In an embodiment of the present disclosure, referring to FIG. 3, the second light-emitting control sub-circuit SW6 includes a second light-emitting control transistor T6. The first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the control electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal. The second light-emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light-emitting control signal EM. In other embodiments of the present disclosure, the second light-emitting control sub-circuit SW6 can include a plurality of second light-emitting control transistors T6 connected in series or in parallel. In this way, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving current can be loaded to the pixel electrode of the light-emitting element to drive the light-emitting element to emit light.

[0132] In an embodiment of the present disclosure, referring to FIG. 3, the pixel driving circuit PDC further includes an electrode reset sub-circuit SW7 and a switch reset sub-circuit SW8. The first terminal of the electrode reset sub-circuit SW7 is electrically connected to the first initialization voltage terminal, the second terminal of the electrode reset sub-circuit SW7 is electrically connected to the fourth node N4, and the control terminal of the electrode reset sub-circuit SW7 is electrically connected to the first reset control signal terminal. The electrode reset sub-circuit SW7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1.

[0133] In an embodiment of the present disclosure, the first terminal of the switch reset sub-circuit SW8 is electrically connected to the second initialization voltage terminal, the second terminal of the switch reset sub-circuit SW8 is electrically connected to the second node N2, and the control terminal of the switch reset sub-circuit SW8 is electrically connected to the first reset control signal terminal. The switch reset sub-circuit SW8 is configured to load the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1.

[0134] In an embodiment of the present disclosure, referring to FIG. 3, the electrode reset sub-circuit SW7 includes an electrode reset transistor T7. The first electrode of the electrode reset transistor T7 is electrically connected with the first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected with the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected with the first reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1. In other embodiments of the present disclosure, the electrode reset sub-circuit SW7 can include a plurality of electrode reset transistors T7 connected in series or in parallel. In this way, the electrode reset transistor T7 is turned on, and the first initialization voltage Vinit1 is loaded to the fourth node N4, so as to reset the fourth node N4.

[0135] In an embodiment of the present disclosure, referring to FIG. 3, the switch reset sub-circuit SW8 includes a switch reset transistor T8. The first electrode of the switch reset transistor T8 is electrically connected with the second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected with the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected with the first reset control signal terminal. The switch reset transistor T8 is configured to load the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1. In other embodiments of the present disclosure, the switch reset sub-circuit SW8 can include a plurality of switch reset transistors T8 connected in series or in parallel. In this way, the switch reset transistor T8 is turned on, and the second initialization voltage Vinit2 is loaded to the second node N2, so as to reset the second node N2.

[0136] In an embodiment of the present disclosure, referring to FIG. 3, the pixel driving circuit PDC further includes a first light-emitting control transistor T5, a second light-emitting control transistor T6, an electrode reset transistor T7, and a switch reset transistor T8. The first electrode of the first light-emitting control transistor T5 is electrically connected with the driving power voltage terminal, the second electrode of the first light-emitting control transistor T5 is electrically connected with the second node N2, and the control electrode of the first light-emitting control transistor T5 is electrically connected with the light-emitting control signal terminal. The first light-emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the light-emitting control signal EM.

[0137] The first electrode of the second light-emitting control transistor T6 is electrically connected with the third node N3, the second electrode of the second light-emitting control transistor T6 is electrically connected with the fourth node N4, and the control electrode of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal terminal. The second light-emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light-emitting control signal EM.

[0138] The first electrode of the electrode reset transistor T7 is electrically connected with the first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected with the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected with the first reset control signal terminal. The electrode reset transistor T7 is used to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1.

[0139] The first electrode of the switch reset transistor T8 is electrically connected with the second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected with the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected with the first reset control signal terminal. The switch reset transistor T8 is used to load the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1.

[0140] In this way, the electrode reset transistor T7 and the switch reset transistor T8 are turned on, the first initialization voltage Vinit1 is loaded to the fourth node N4, and the second initialization voltage Vinit2 is loaded to the second node N2, so as to reset the second node N2 and the fourth node N4. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving current is loaded to the pixel electrode of the light-emitting element, so as to drive the light-emitting element to emit light.

[0141] In an embodiment of the present disclosure, referring to FIG. 7, the pixel driving circuit PDC further includes the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the electrode reset transistor T7. The first electrode of the first light-emitting control transistor T5 is electrically connected with the driving power voltage terminal, the second electrode of the first light-emitting control transistor T5 is electrically connected with the second node N2, and the control electrode of the first light-emitting control transistor T5 is electrically connected with the first light-emitting control signal terminal. The first light-emitting control transistor T5 is used to load the driving power voltage VDD to the second node N2 in response to the gating level of the first light-emitting control signal EM1.

[0142] The first electrode of the second light-emitting control transistor T6 is electrically connected with the third node N3, the second electrode of the second light-emitting control transistor T6 is electrically connected with the fourth node N4, and the control electrode of the second light-emitting control transistor T6 is electrically connected with the second light-emitting control signal terminal. The second light-emitting control transistor T6 is used to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the second light-emitting control signal EM2.

[0143] The first electrode of the electrode reset transistor T7 is electrically connected with the first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected with the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected with the second reset control signal terminal; the electrode reset transistor T7 is used to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the second reset control signal RST2.

[0144] In this way, the control electrode of the first light emitting control transistor T5 is loaded with the gating level of the first light emitting control signal EM1 to make the first light emitting control transistor T5 conductive, so as to load the driving power voltage VDD to the second node N2 to achieve the effect of resetting the second node N2 by the driving power voltage VDD.

[0145] In an embodiment of the present disclosure, the pixel driving circuit PDC is configured to write the data voltage Data to the first node N1 by the data writing sub-circuit SW4 after the gate reset sub-circuit SW1 writes the reference voltage Vref to the first node N1. For example, the control electrode of the gate reset transistor T1 is first loaded with the gating level of the second reset control signal RST2 to load the reference voltage Vref to the first node N1, and then the control electrode of the gate reset transistor T1 is loaded with the off level of the second reset control signal RST2 to lock the voltage of the first node N1. Then, the control electrode of the data writing transistor T4 is loaded with the gating level of the data writing control signal GS to load the data voltage Data to the first node N1. In this way, on the one hand, the crosstalk between the data writing control signal GS and the second reset control signal RST2 can be prevented, and on the other hand, when the data voltage Data is written to the first node N1, the data voltage Data can be prevented from leaking through the gate reset transistor T1.

[0146] In an embodiment of the present disclosure, the material of the channel region of at least one transistor is metal oxide semiconductor material. In an example, the material of the channel region of the driving transistor T3 can be metal oxide semiconductor material to reduce the electron mobility of the driving transistor T3 and improve the low gray scale quality of the display panel PNL. In another example, the materials of the channel regions of the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 can be metal oxide semiconductor material to prevent the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 from leaking and facilitate normal light emission of the light emitting element, thereby improving the display quality of the display panel PNL. In other examples, the materials of the channel regions of all transistors can be metal oxide semiconductor material.

[0147] In one embodiment of the present disclosure, the constant voltage Vx is any one of the driving power supply voltage VDD, the first initialization voltage Vinitl, the second initialization voltage Vinit2, and the reference voltage Vref. In one example, the constant voltage Vx can be the driving power supply voltage VDD. In another example, the constant voltage Vx is the first initialization voltage Vinitl. In other examples, the constant voltage Vx can be the second initialization voltage Vinit2 or the reference voltage Vref.

[0148] The pixel driving circuit PDC provided by the embodiments of the present disclosure is further described below in combination with specific equivalent circuit diagrams.

[0149] In the first example, referring to FIG. 4, the pixel driving circuit PDC includes a gate reset transistor T1, a voltage stabilizing transistor T9, and a first capacitor C1 and a second capacitor C2. The first electrode of the gate reset transistor T1 is electrically connected to a reference voltage terminal, the second electrode of the gate reset transistor T1 is electrically connected to a first node N1, and the control electrode of the gate reset transistor T1 is electrically connected to a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. The first electrode of a threshold compensation transistor T2 is electrically connected to a third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and the control electrode of the threshold compensation transistor T2 is electrically connected to the second reset control signal terminal. The threshold compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the second reset control signal RST2. The first electrode of a driving transistor T3 is electrically connected to a second node N2, the second electrode of the driving transistor T3 is electrically connected to the third node N3, and the control electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to generate a driving current. The first electrode of a data write transistor T4 is electrically connected to a data voltage terminal, the second electrode of the data write transistor T4 is electrically connected to the first node N1, and the control electrode of the data write transistor T4 is electrically connected to a data write control signal terminal. The data write transistor T4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data write control signal GS. The first electrode of a first light emitting control transistor T5 is electrically connected to a driving power voltage terminal, the second electrode of the first light emitting control transistor T5 is electrically connected to the second node N2, and the control electrode of the first light emitting control transistor T5 is electrically connected to a light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM. The first electrode of a second light emitting control transistor T6 is electrically connected to the third node N3, the second electrode of the second light emitting control transistor T6 is electrically connected to a fourth node N4, and the control electrode of the second light emitting control transistor T6 is electrically connected to the light emitting control signal terminal. The second light emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light emitting control signal EM. The first electrode of an electrode reset transistor T7 is electrically connected to a first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected to a first reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1. The first electrode of a switch reset transistor T8 is electrically connected to a second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected to the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected to the first reset control signal terminal.The switch reset transistor T8 is used for loading the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1. The first pole of the voltage stabilizing transistor T9 is electrically connected with the driving power voltage terminal, the second pole of the voltage stabilizing transistor T9 is electrically connected with the fifth node N5, and the control pole of the voltage stabilizing transistor T9 is electrically connected with the third reset control signal terminal. The voltage stabilizing transistor T9 is used for loading the driving power voltage VDD to the fifth node N5 in response to the gating level of the third reset control signal RST3. The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the fifth node N5. The first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the first node N1.

[0150] The driving method of the pixel driving circuit PDC of the example is exemplarily explained as follows, taking the pixel driving circuit PDC shown in Fig. 4 as an example, and referring to the timing diagram shown in Fig. 5.

[0151] In the P1 stage (reset stage), referring to Fig. 5 and Fig. 6-1, the gating levels of the first reset control signal RST1, the second reset control signal RST2, and the third reset control signal RST3 are loaded to the pixel driving circuit PDC, so that the gate reset transistor T1, the threshold compensation transistor T2, the electrode reset transistor T7, the switch reset transistor T8, and the voltage stabilizing transistor T9 are turned on. The off levels of the emission control signal EM and the data write control signal GS are loaded to the pixel driving circuit PDC, so that the data write transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are turned off. Then, the first initialization voltage Vinit1 is loaded to the fourth node N4; the second initialization voltage Vinit2 is loaded to the second node N2; the reference voltage Vref is loaded to the first node N1 and the third node N3; and the first node N1, the second node N2, the third node N3, and the fourth node N4 are reset. The driving power voltage VDD is loaded to the fifth node N5.

[0152] In the P2 stage (threshold compensation stage), referring to FIG. 5 and FIG. 6-2, the second reset control signal RST2 and the third reset control signal RST3 are loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1, the threshold compensation transistor T2 and the voltage stabilizing transistor T9 are turned on. The emission control signal EM, the first reset control signal RST1 and the data write control signal GS are loaded to the pixel driving circuit PDC at the off level, so that the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the third node N3, so that the driving transistor T3 is turned on. Since the switch reset transistor T8 is turned off in this stage, the second node N2 is discharged through the driving transistor T3, the threshold compensation transistor T2 and the gate reset transistor T1, until the voltage of the second node N2 is Vref-Vth, the driving transistor T3 is just turned off, at this time, the voltage of the second node N2 is locked to compensate the threshold voltage to the first node N1. Since the voltage stabilizing transistor T9 is turned on, the voltage of the fifth node N5 is the driving power voltage VDD, and the second node N2 is stabilized through the first capacitor C1.

[0153] In the P3 stage (data write stage), referring to FIG. 5 and FIG. 6-3, the data write control signal GS and the third reset control signal RST3 are loaded to the pixel driving circuit PDC at the gating level, so that the data write transistor T4 and the voltage stabilizing transistor T9 are turned on. The emission control signal EM, the first reset control signal RST1 and the second reset control signal RST2 are loaded to the pixel driving circuit PDC at the off level, so that the gate reset transistor T1, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the data voltage Data is written to the first node N1; since the driving power voltage VDD is continuously loaded to the fifth node N5, the second node N2 is stabilized, so that the voltage of the second node N2 is still Vref-Vth, and it is known that Vgs=Data-Vref+Vth.

[0154] It should be noted that, after the second reset control signal RST2 is loaded to the pixel driving circuit PDC at the off level in the P3 stage, the data write control signal GS is loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1 is turned off, and then the data write transistor T4 is turned on, to prevent the data voltage Data from leaking through the gate reset transistor T1, thereby reducing the power consumption of the system.

[0155] In the P4 stage (light emitting stage), referring to FIG. 5 and FIG. 6-4, the pixel driving circuit PDC is loaded with the gating level of the light emitting control signal EM, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. The pixel driving circuit PDC is loaded with the off level of the data writing control signal GS, the first reset control signal RST1, the second reset control signal RST2 and the third reset control signal RST3, so that the gate reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the electrode reset transistor T7, the switch reset transistor T8 and the voltage stabilizing transistor T9 are turned off. The driving transistor T3 is turned on due to the self-boosting of the second capacitor C2, and the driving current generated by the driving transistor T3 drives the light emitting element to emit light. The driving current wherein μ n ·C OX ·W / L are constants related to the process and the driving design. For example, μ n is the carrier mobility, C OX is the gate oxide layer capacitance, and W / L is the transistor width-length ratio. In the above formula, the driving current I OLED is irrelevant to the driving power supply voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power supply voltage VDD and the Vth drift of the driving transistor T3, so as to more fully compensate the threshold of the driving transistor T3 and improve the display quality of the display panel PNL.

[0156] It can be understood that, in the P4 stage, the pixel driving circuit PDC is first loaded with the off level of the data writing control signal GS, then loaded with the off level of the third reset control signal RST3, and finally loaded with the gating level of the light emitting control signal EM, so as to prevent crosstalk between the data writing control signal GS, the third reset control signal RST3 and the light emitting control signal EM.

[0157] In the present example, referring to FIG. 5, the gating level duration of the first reset control signal RST1 and the gating level duration of the data writing control signal GS can be set as the same duration. In this way, the data writing control signal GS can be obtained by shifting the first reset control signal RST1, so that the first reset control signal RST1 and the data writing control signal GS share one gate driving circuit, which can reduce the number of gate driving circuits and facilitate the narrow frame of the display panel PNL.

[0158] In this way, in the high-frequency refreshing process, the threshold compensation stage is separated from the data writing stage, so that the threshold compensation stage is no longer limited by the duration of the data writing stage, thereby more fully compensating the threshold voltage of the pixel driving circuit PDC, reducing the possibility of display unevenness of the display panel PNL, and improving the display quality of the display panel PNL.

[0159] Note that in this example, each transistor is a P-type transistor. The on voltage of each signal is a low voltage, and the off voltage of each signal is a high voltage. Vgs is a gate-source voltage difference of the drive transistor T3, and Vth is a threshold voltage of the drive transistor T3.

[0160] In the second example, referring to FIG. 7, the pixel driving circuit PDC includes a gate reset transistor T1, an electrode reset transistor T7, a voltage stabilizing transistor T9, and a first capacitor C1 and a second capacitor C2. The first electrode of the gate reset transistor T1 is electrically connected to a reference voltage terminal, the second electrode of the gate reset transistor T1 is electrically connected to a first node N1, and the control electrode of the gate reset transistor T1 is electrically connected to a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. The first electrode of the threshold value compensation transistor T2 is electrically connected to a third node N3, the second electrode of the threshold value compensation transistor T2 is electrically connected to the first node N1, and the control electrode of the threshold value compensation transistor T2 is electrically connected to the second reset control signal terminal. The threshold value compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the second reset control signal RST2. The first electrode of the driving transistor T3 is electrically connected to a second node N2, the second electrode of the driving transistor T3 is electrically connected to the third node N3, and the control electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to generate a driving current. The first electrode of the data write transistor T4 is electrically connected to a data voltage terminal, the second electrode of the data write transistor T4 is electrically connected to the first node N1, and the control electrode of the data write transistor T4 is electrically connected to a data write control signal terminal. The data write transistor T4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data write control signal GS. The first electrode of the first light-emitting control transistor T5 is electrically connected to a driving power voltage terminal, the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2, and the control electrode of the first light-emitting control transistor T5 is electrically connected to a first light-emitting control signal terminal. The first light-emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the first light-emitting control signal EM1. The first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second electrode of the second light-emitting control transistor T6 is electrically connected to a fourth node N4, and the control electrode of the second light-emitting control transistor T6 is electrically connected to a second light-emitting control signal terminal. The second light-emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the second light-emitting control signal EM2. The first electrode of the electrode reset transistor T7 is electrically connected to a first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected to the second reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the second reset control signal RST2. The first electrode of the voltage stabilizing transistor T9 is electrically connected to the driving power voltage terminal, the second electrode of the voltage stabilizing transistor T9 is electrically connected to a fifth node N5, and the control electrode of the voltage stabilizing transistor T9 is electrically connected to a third reset control signal terminal.The voltage stabilizing transistor T9 is used to load the driving power voltage VDD to the fifth node N5 in response to the gating level of the third reset control signal RST3. The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the fifth node N5. The first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the first node N1.

[0161] The driving method of the pixel driving circuit PDC of the example is exemplarily explained as follows, taking the pixel driving circuit PDC shown in FIG. 7 as an example, and referring to the timing diagram shown in FIG. 8.

[0162] In the P1 stage (reset stage), referring to FIG. 8 and FIG. 9-1, the pixel driving circuit PDC is loaded with the first emission control signal EM1, the second reset control signal RST2, and the gating level of the third reset control signal RST3, so that the gate reset transistor T1, the threshold compensation transistor T2, the first emission control transistor T5, the electrode reset transistor T7, and the voltage stabilizing transistor T9 are turned on. The pixel driving circuit PDC is loaded with the second emission control signal EM2 and the off level of the data writing control signal GS, so that the driving transistor T3, the data writing transistor T4, and the second emission control transistor T6 are turned off. Then, the first initialization voltage Vinit1 is loaded to the fourth node N4; the driving power voltage VDD is loaded to the second node N2 and the fifth node N5; the reference voltage Vref is loaded to the first node N1 and the third node N3; so as to reset the first node N1, the second node N2, the third node N3, and the fourth node N4.

[0163] In the P2 stage (threshold compensation stage), referring to FIG. 8 and FIG. 9-2, the pixel driving circuit PDC is loaded with the second reset control signal RST2 and the gating level of the third reset control signal RST3, so that the gate reset transistor T1, the threshold compensation transistor T2, the electrode reset transistor T7, and the voltage stabilizing transistor T9 are turned on. The pixel driving circuit PDC is loaded with the first emission control signal EM1, the second emission control signal EM2, and the off level of the data writing control signal GS, so that the data writing transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are turned off. Then, the reference voltage Vref is loaded to the first node N1 and the third node N3, so that the driving transistor T3 is turned on. Since the first emission control transistor T5 is turned off in this stage, the second node N2 is discharged through the driving transistor T3, the threshold compensation transistor T2, and the gate reset transistor T1, until the voltage of the second node N2 is Vref-Vth, and the driving transistor T3 is just turned off, at which time the voltage of the second node N2 is locked to compensate the threshold voltage to the first node N1. Since the voltage stabilizing transistor T9 is turned on, the voltage of the fifth node N5 is the driving power voltage VDD, and the second node N2 is stabilized through the first capacitor C1.

[0164] In the P3 stage (data writing stage), referring to FIG. 8 and FIG. 9-3, the gate-on level of the data writing control signal GS and the third reset control signal RST3 are loaded to the pixel driving circuit PDC, so that the data writing transistor T4 and the voltage stabilizing transistor T9 are turned on. The off level of the first emission control signal EM1, the second emission control signal EM2 and the second reset control signal RST2 are loaded to the pixel driving circuit PDC, so that the gate reset transistor T1, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6 and the electrode reset transistor T7 are turned off. Then the data voltage Data is written to the first node N1; since the driving power voltage VDD is continuously loaded to the fifth node N5, the second node N2 is voltage-stabilized, so the voltage of the second node N2 is still Vref-Vth, and it is known that Vgs=Data-Vref+Vth.

[0165] It should be noted that, in the P3 stage, after the off level of the second reset control signal RST2 is loaded to the pixel driving circuit PDC, the gate-on level of the data writing control signal GS is loaded to the pixel driving circuit PDC, so that the data writing transistor T4 is turned on after the gate reset transistor T1 is turned off, preventing the data voltage Data from leaking through the gate reset transistor T1, thereby reducing the power consumption of the system.

[0166] In the P4 stage (emission stage), referring to FIG. 8 and FIG. 9-4, the gate-on level of the first emission control signal EM1 and the second emission control signal EM2 are loaded to the pixel driving circuit PDC, so that the first emission control transistor T5 and the second emission control transistor T6 are turned on. The off level of the data writing control signal GS, the second reset control signal RST2 and the third reset control signal RST3 are loaded to the pixel driving circuit PDC, so that the gate reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the electrode reset transistor T7 and the voltage stabilizing transistor T9 are turned off. Since the second capacitor C2 is self-boosted, the driving transistor T3 is turned on, so that the driving current generated by the driving transistor T3 drives the light emitting element to emit light. Then the driving current wherein μ n ·C OX ·W / L are constants related to the process and driving design. For example, μ n is the carrier mobility, C OX is the gate oxide layer capacitance, and W / L is the transistor width-length ratio. In the above formula, the driving current I OLED is independent of the driving power voltage VDD and Vth, thereby solving the problems of the voltage drop of the driving power voltage VDD and the Vth drift of the driving transistor T3, so as to more fully compensate the threshold of the driving transistor T3, and to improve the display quality of the display panel PNL.

[0167] It can be understood that, in the P4 stage, the off level of the data write control signal GS is first loaded to the pixel driving circuit PDC, then the off level of the third reset control signal RST3 is loaded to the pixel driving circuit PDC, then the on level of the second emission control signal EM2 is loaded to the pixel driving circuit PDC, and finally the on level of the first emission control signal EM1 is loaded to the pixel driving circuit PDC, so as to prevent crosstalk between the data write control signal GS, the third reset control signal RST3, and the first and second emission control signals EM1 and EM2.

[0168] In this example, referring to FIG. 8, the on level duration of the first emission control signal EM1 and the on level duration of the second emission control signal EM2 can be set as the same duration. In this way, the first emission control signal EM1 can be shifted by the second emission control signal EM2, so that the first and second emission control signals EM1 and EM2 share one gate driving circuit, the number of gate driving circuits can be reduced, and the narrow frame of the display panel PNL can be facilitated.

[0169] In this way, compared with the pixel driving circuit PDC of the first example, the second initialization voltage Vinit2 can be removed by resetting the second node N2 by the driving power voltage VDD, the number of transistors can be reduced, and the layout design can be simplified.

[0170] It should be noted that in this example, each transistor is a P-type transistor. The on level of each signal is a low level, and the off level of each signal is a high level. Vgs is the gate-source voltage difference of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0171] In a third example, referring to FIG. 10, the pixel driving circuit PDC includes a gate reset transistor T1, a voltage stabilizing transistor T9, and a first capacitor C1 and a second capacitor C2. The first electrode of the gate reset transistor T1 is electrically connected to a reference voltage terminal, the second electrode of the gate reset transistor T1 is electrically connected to a first node N1, and the control electrode of the gate reset transistor T1 is electrically connected to a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. The first electrode of the threshold compensation transistor T2 is electrically connected to a third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and the control electrode of the threshold compensation transistor T2 is electrically connected to the second reset control signal terminal. The threshold compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the second reset control signal RST2. The first electrode of the driving transistor T3 is electrically connected to a second node N2, the second electrode of the driving transistor T3 is electrically connected to the third node N3, and the control electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to generate a driving current. The first electrode of the data write transistor T4 is electrically connected to a data voltage terminal, the second electrode of the data write transistor T4 is electrically connected to the first node N1, and the control electrode of the data write transistor T4 is electrically connected to a data write control signal terminal. The data write transistor T4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data write control signal GS. The first light emitting control transistor T5 has its first electrode electrically connected to a driving power voltage terminal, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to a light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM. The second light emitting control transistor T6 has its first electrode electrically connected to the third node N3, its second electrode electrically connected to a fourth node N4, and its control electrode electrically connected to the light emitting control signal terminal. The second light emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light emitting control signal EM. The first electrode of the electrode reset transistor T7 is electrically connected to a first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected to a first reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1. The first electrode of the switch reset transistor T8 is electrically connected to a second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected to the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected to the first reset control signal terminal.The switch reset transistor T8 is used for loading the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1. The first pole of the voltage stabilizing transistor T9 is electrically connected with the driving power voltage terminal, the second pole of the voltage stabilizing transistor T9 is electrically connected with the fifth node N5, and the control pole of the voltage stabilizing transistor T9 is electrically connected with the third reset control signal terminal. The voltage stabilizing transistor T9 is used for loading the driving power voltage VDD to the fifth node N5 in response to the gating level of the third reset control signal RST3. The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the fifth node N5. The first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the first node N1.

[0172] The driving method of the pixel driving circuit PDC of the example is exemplarily explained as follows, taking the pixel driving circuit PDC shown in FIG. 10 as an example, and referring to the timing diagram shown in FIG. 11.

[0173] In the P1 stage (reset stage), referring to FIG. 10 and FIG. 11, the gating levels of the first reset control signal RST1, the second reset control signal RST2, and the third reset control signal RST3 are loaded to the pixel driving circuit PDC, so that the gate reset transistor T1, the threshold compensation transistor T2, the electrode reset transistor T7, the switch reset transistor T8, and the voltage stabilizing transistor T9 are turned on. The off levels of the emission control signal EM and the data write control signal GS are loaded to the pixel driving circuit PDC, so that the data write transistor T4, the first emission control transistor T5, and the second emission control transistor T6 are turned off. It can be understood that in this stage, the gating level of the first reset control signal RST1 is loaded to the pixel driving circuit PDC first, and then the gating levels of the second reset control signal RST2 and the third reset control signal RST3 are loaded to the pixel driving circuit PDC. The electrode reset transistor T7 and the switch reset transistor T8 are turned on before the gate reset transistor T1, the threshold compensation transistor T2, and the driving transistor T3, so that the first initialization voltage Vinit1 is loaded to the fourth node N4, the second initialization voltage Vinit2 is loaded to the second node N2, and the reference voltage Vref is loaded to the first node N1 and the third node N3, so as to reset the first node N1, the second node N2, the third node N3, and the fourth node N4. The driving power voltage VDD is loaded to the fifth node N5.

[0174] In the P2 stage (threshold compensation stage), referring to FIG. 10 and FIG. 11, the second reset control signal RST2 and the third reset control signal RST3 are continuously loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1, the threshold compensation transistor T2 and the voltage stabilizing transistor T9 are turned on. The light emitting control signal EM, the first reset control signal RST1 and the data writing control signal GS are loaded to the pixel driving circuit PDC at the off level, so that the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the third node N3, so that the driving transistor T3 is turned on. Since the switch reset transistor T8 is turned off in this stage, the second node N2 is discharged through the driving transistor T3, the threshold compensation transistor T2 and the gate reset transistor T1, until the voltage of the second node N2 is Vref-Vth, the driving transistor T3 is just turned off, at this time, the voltage of the second node N2 is locked to compensate the threshold voltage to the first node N1. Since the voltage stabilizing transistor T9 is turned on, the voltage of the fifth node N5 is the driving power voltage VDD, and the second node N2 is stabilized through the first capacitor C1.

[0175] In the P3 stage (data writing stage), referring to FIG. 10 and FIG. 11, the data writing control signal GS and the third reset control signal RST3 are loaded to the pixel driving circuit PDC at the gating level, so that the data writing transistor T4 and the voltage stabilizing transistor T9 are turned on. The light emitting control signal EM, the first reset control signal RST1 and the second reset control signal RST2 are loaded to the pixel driving circuit PDC at the off level, so that the gate reset transistor T1, the threshold compensation transistor T2, the first light emitting control transistor T5, the second light emitting control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the data voltage Data is written to the first node N1; since the driving power voltage VDD is continuously loaded to the fifth node N5, the second node N2 is stabilized, so that the voltage of the second node N2 is still Vref-Vth, and it is known that Vgs=Data-Vref+Vth.

[0176] It should be noted that, in the P3 stage, after the second reset control signal RST2 is loaded to the pixel driving circuit PDC at the off level, the data writing control signal GS is loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1 is turned off, and then the data writing transistor T4 is turned on, to prevent the data voltage Data from leaking through the gate reset transistor T1, thereby reducing the power consumption of the system.

[0177] In the P4 stage (light emitting stage), referring to FIG. 10 and FIG. 11, the pixel driving circuit PDC is loaded with the gating level of the light emitting control signal EM, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. The pixel driving circuit PDC is loaded with the off level of the data writing control signal GS, the first reset control signal RST1, the second reset control signal RST2 and the third reset control signal RST3, so that the gate reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the electrode reset transistor T7, the switch reset transistor T8 and the voltage stabilizing transistor T9 are turned off. Due to the self-boosting of the second capacitor C2, the driving transistor T3 is turned on, and the driving current generated by the driving transistor T3 drives the light emitting element to emit light. The driving current wherein μ n ·C OX ·W / L are constants related to the process and driving design. For example, μ n is the carrier mobility, C OX is the gate oxide layer capacitance, and W / L is the transistor width-length ratio. In the above formula, the driving current I OLED is independent of the driving power supply voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power supply voltage VDD and the Vth drift of the driving transistor T3, so as to more fully compensate the threshold of the driving transistor T3 and improve the display quality of the display panel PNL.

[0178] It can be understood that, in the P4 stage, the pixel driving circuit PDC is first loaded with the off level of the data writing control signal GS, then loaded with the off level of the third reset control signal RST3, and finally loaded with the gating level of the light emitting control signal EM, so as to prevent crosstalk between the data writing control signal GS, the third reset control signal RST3 and the light emitting control signal EM.

[0179] In the present example, referring to FIG. 5, the gating level duration of the first reset control signal RST1 and the gating level duration of the second reset control signal RST2 are set to the same duration. In this way, the second reset control signal RST2 can be obtained by shifting the first reset control signal RST1, so that the first reset control signal RST1 and the second reset control signal RST2 share one gate driving circuit, which can reduce the number of gate driving circuits and facilitate the narrow frame of the display panel PNL.

[0180] In this way, in the high-frequency refreshing process, the threshold compensation stage is separated from the data writing stage, so that the threshold compensation stage is no longer limited by the duration of the data writing stage, thereby more fully compensating the threshold voltage of the pixel driving circuit PDC, reducing the possibility of display unevenness of the display panel PNL, and improving the display quality of the display panel PNL.

[0181] Note that in this example, each transistor is a P-type transistor. The on voltage of each signal is a low voltage, and the off voltage of each signal is a high voltage. Vgs is a gate-source voltage difference of the drive transistor T3, and Vth is a threshold voltage of the drive transistor T3.

[0182] In the fourth example, referring to FIG. 12, the pixel driving circuit PDC includes a gate reset transistor T1, a voltage stabilizing transistor T9, and a first capacitor C1 and a second capacitor C2. The first electrode of the gate reset transistor T1 is electrically connected to a reference voltage terminal, the second electrode of the gate reset transistor T1 is electrically connected to a first node N1, and the control electrode of the gate reset transistor T1 is electrically connected to a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. The first electrode of the threshold compensation transistor T2 is electrically connected to a third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and the control electrode of the threshold compensation transistor T2 is electrically connected to the second reset control signal terminal. The threshold compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the second reset control signal RST2. The first electrode of the driving transistor T3 is electrically connected to a second node N2, the second electrode of the driving transistor T3 is electrically connected to the third node N3, and the control electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to generate a driving current. The first electrode of the data write transistor T4 is electrically connected to a data voltage terminal, the second electrode of the data write transistor T4 is electrically connected to the first node N1, and the control electrode of the data write transistor T4 is electrically connected to a data write control signal terminal. The data write transistor T4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data write control signal GS. The first light emitting control transistor T5 has its first electrode electrically connected to a driving power voltage terminal, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to a light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM. The second light emitting control transistor T6 has its first electrode electrically connected to the third node N3, its second electrode electrically connected to a fourth node N4, and its control electrode electrically connected to the light emitting control signal terminal. The second light emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light emitting control signal EM. The first electrode of the electrode reset transistor T7 is electrically connected to a first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected to a first reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1. The first electrode of the switch reset transistor T8 is electrically connected to a second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected to the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected to the first reset control signal terminal.The switch reset transistor T8 is configured to load the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1. The first electrode of the voltage stabilizing transistor T9 is electrically connected with the first initialization voltage terminal or the second initialization voltage terminal, the second electrode of the voltage stabilizing transistor T9 is electrically connected with the fifth node N5, and the control electrode of the voltage stabilizing transistor T9 is electrically connected with the third reset control signal terminal. The voltage stabilizing transistor T9 is configured to load the first initialization voltage Vinit1 or the second initialization voltage Vinit2 to the fifth node N5 in response to the gating level of the third reset control signal RST3. The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the fifth node N5. The first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the first node N1.

[0183] In this way, the fifth node N5 can be stabilized by the first initialization voltage Vinit1 or the second initialization voltage Vinit2, and the second node N2 can be stabilized in turn. It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low, and the cutoff level of each signal is high.

[0184] In the fifth example, referring to FIG. 13, the pixel driving circuit PDC includes a gate reset transistor T1, a voltage stabilizing transistor T9, and a first capacitor C1 and a second capacitor C2. The first electrode of the gate reset transistor T1 is electrically connected to a reference voltage terminal, the second electrode of the gate reset transistor T1 is electrically connected to a first node N1, and the control electrode of the gate reset transistor T1 is electrically connected to a second reset control signal terminal. The gate reset transistor T1 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset control signal RST2. The first electrode of the threshold compensation transistor T2 is electrically connected to a third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and the control electrode of the threshold compensation transistor T2 is electrically connected to the second reset control signal terminal. The threshold compensation transistor T2 is configured to make the third node N3 and the first node N1 communicate with each other in response to the gating level of the second reset control signal RST2. The first electrode of the driving transistor T3 is electrically connected to a second node N2, the second electrode of the driving transistor T3 is electrically connected to the third node N3, and the control electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to generate a driving current. The first electrode of the data write transistor T4 is electrically connected to a data voltage terminal, the second electrode of the data write transistor T4 is electrically connected to the first node N1, and the control electrode of the data write transistor T4 is electrically connected to a data write control signal terminal. The data write transistor T4 is configured to load the data voltage Data to the first node N1 in response to the gating level of the data write control signal GS. The first light emitting control transistor T5 has its first electrode electrically connected to a driving power voltage terminal, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to a light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power voltage VDD to the second node N2 in response to the gating level of the light emitting control signal EM. The second light emitting control transistor T6 has its first electrode electrically connected to the third node N3, its second electrode electrically connected to a fourth node N4, and its control electrode electrically connected to the light emitting control signal terminal. The second light emitting control transistor T6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the light emitting control signal EM. The first electrode of the electrode reset transistor T7 is electrically connected to a first initialization voltage terminal, the second electrode of the electrode reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the electrode reset transistor T7 is electrically connected to a first reset control signal terminal. The electrode reset transistor T7 is configured to load the first initialization voltage Vinit1 to the fourth node N4 in response to the gating level of the first reset control signal RST1. The first electrode of the switch reset transistor T8 is electrically connected to a second initialization voltage terminal, the second electrode of the switch reset transistor T8 is electrically connected to the second node N2, and the control electrode of the switch reset transistor T8 is electrically connected to the first reset control signal terminal.The switch reset transistor T8 is used for loading the second initialization voltage Vinit2 to the second node N2 in response to the gating level of the first reset control signal RST1. The first pole of the voltage stabilizing transistor T9 is electrically connected with the driving power voltage terminal, the second pole of the voltage stabilizing transistor T9 is electrically connected with the fifth node N5, and the control pole of the voltage stabilizing transistor T9 is electrically connected with the third reset control signal terminal. The voltage stabilizing transistor T9 is used for loading the driving power voltage VDD to the fifth node N5 in response to the gating level of the third reset control signal RST3. The first end of the first capacitor C1 is electrically connected with the second node N2, and the second end of the first capacitor C1 is electrically connected with the fifth node N5. The first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the first node N1.

[0185] As follows, the driving method of the pixel driving circuit PDC of the example is exemplarily explained with the pixel driving circuit PDC shown in Fig. 13 as an example, referring to the timing diagram shown in Fig. 14.

[0186] In the P1 stage (reset stage), referring to Fig. 13 and Fig. 14, the gating levels of the first reset control signal RST1, the second reset control signal RST2, and the third reset control signal RST3 are loaded to the pixel driving circuit PDC, so that the gate reset transistor T1, the threshold compensation transistor T2, the electrode reset transistor T7, the switch reset transistor T8, and the voltage stabilizing transistor T9 are turned on. The off levels of the light emitting control signal EM and the data write control signal GS are loaded to the pixel driving circuit PDC, so that the data write transistor T4, the first light emitting control transistor T5, and the second light emitting control transistor T6 are turned off. Then, the first initialization voltage Vinit1 is loaded to the fourth node N4; the second initialization voltage Vinit2 is loaded to the second node N2; the reference voltage Vref is loaded to the first node N1 and the third node N3; and the first node N1, the second node N2, the third node N3, and the fourth node N4 are reset. The driving power voltage VDD is loaded to the fifth node N5.

[0187] In the P2 stage (threshold compensation stage), referring to FIG. 13 and FIG. 14, the second reset control signal RST2 and the third reset control signal RST3 are loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1, the threshold compensation transistor T2 and the voltage stabilizing transistor T9 are turned on. The emission control signal EM, the first reset control signal RST1 and the data write control signal GS are loaded to the pixel driving circuit PDC at the off level, so that the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the third node N3, so that the driving transistor T3 is turned on. Since the switch reset transistor T8 is turned off in this stage, the second node N2 is discharged through the driving transistor T3, the threshold compensation transistor T2 and the gate reset transistor T1, until the voltage of the second node N2 is Vref-Vth, the driving transistor T3 is just turned off, at this time, the voltage of the second node N2 is locked to compensate the threshold voltage to the first node N1. Since the voltage stabilizing transistor T9 is turned on, the voltage of the fifth node N5 is the driving power voltage VDD, and the second node N2 is stabilized through the first capacitor C1.

[0188] In the P3 stage (data write stage), referring to FIG. 13 and FIG. 14, the data write control signal GS and the third reset control signal RST3 are loaded to the pixel driving circuit PDC at the gating level, so that the data write transistor T4 and the voltage stabilizing transistor T9 are turned on. The emission control signal EM, the first reset control signal RST1 and the second reset control signal RST2 are loaded to the pixel driving circuit PDC at the off level, so that the gate reset transistor T1, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, the electrode reset transistor T7 and the switch reset transistor T8 are turned off. Then the data voltage Data is written to the first node N1; since the driving power voltage VDD is continuously loaded to the fifth node N5, the second node N2 is stabilized, so that the voltage of the second node N2 is still Vref-Vth, and it is known that Vgs=Data-Vref+Vth.

[0189] It should be noted that, in the P3 stage, after the second reset control signal RST2 is loaded to the pixel driving circuit PDC at the off level, the data write control signal GS is loaded to the pixel driving circuit PDC at the gating level, so that the gate reset transistor T1 is turned off, and then the data write transistor T4 is turned on, to prevent the data voltage Data from leaking through the gate reset transistor T1, thereby reducing the power consumption of the system.

[0190] In the P4 stage (light emitting stage), referring to FIG. 13 and FIG. 14, the pixel driving circuit PDC is loaded with the gating level of the light emitting control signal EM, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. The pixel driving circuit PDC is loaded with the off level of the data write control signal GS, the first reset control signal RST1, the second reset control signal RST2 and the third reset control signal RST3, so that the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the electrode reset transistor T7, the switch reset transistor T8 and the voltage stabilizing transistor T9 are turned off. The driving transistor T3 is turned on due to the self-boosting of the second capacitor C2, and the driving current generated by the driving transistor T3 drives the light emitting element to emit light. The driving current wherein μ n ·C OX ·W / L are constants related to the process and the driving design. For example, μ n is the carrier mobility, C OX is the gate oxide layer capacitance, and W / L is the transistor width-length ratio. In the above formula, the driving current I OLED is irrelevant to the driving power supply voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power supply voltage VDD and the Vth drift of the driving transistor T3, so as to more fully compensate the threshold of the driving transistor T3 and improve the display quality of the display panel PNL.

[0191] It can be understood that in the P4 stage, the pixel driving circuit PDC is first loaded with the off level of the data write control signal GS, then loaded with the off level of the third reset control signal RST3, and finally loaded with the gating level of the light emitting control signal EM, so as to prevent the crosstalk between the data write control signal GS, the third reset control signal RST3 and the light emitting control signal EM.

[0192] It should be noted that in this example, the drive transistor T3, the first light-emitting control transistor T5~the voltage stabilizing transistor T9 are all P-type transistors, the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 are all N-type transistors, and the materials of the channel regions of the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 are metal oxide materials. For example, the materials of the channel regions of the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 are IGZO (indium gallium zinc oxide). The gate-on voltages of the light-emitting control signal EM, the first reset control signal RST1, and the third reset control signal RST3 are low, the gate-off voltages of the second reset control signal RST2 and the data writing control signal GS are high, the gate-on voltages of the light-emitting control signal EM, the first reset control signal RST1, and the third reset control signal RST3 are high, and the gate-off voltages of the second reset control signal RST2 and the data writing control signal GS are low. Vgs is the gate-source voltage difference of the drive transistor T3, and Vth is the threshold voltage of the drive transistor T3.

[0193] In this way, by setting the materials of the channel regions of the gate reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 to be metal oxide materials, the leakage of the first node N1 can be prevented, and the possibility of screen flicker of the display panel PNL during low-frequency refresh can be reduced.

[0194] It should be noted that although the steps of the driving method of the pixel driving circuit in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all of the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0195] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present application is intended to cover any and all variations of the present disclosure comprising adaptations, modifications, equivalents, and alternatives following, within the scope of the present disclosure, and including those particularly pointed out in the appended claims. Both the foregoing description and the examples given are exemplary and explanatory only. The true scope of the present disclosure is indicated by the following claims.

Claims

1. A pixel driving circuit, comprising a driving transistor, a gate reset sub-circuit, a threshold compensation sub-circuit, a voltage stabilizing sub-circuit, a data writing sub-circuit, a first capacitor and a second capacitor; wherein a first end of the gate reset sub-circuit is electrically connected with a reference voltage terminal, a second end of the gate reset sub-circuit, a second end of the threshold compensation sub-circuit, a control electrode of the driving transistor, a second end of the data writing sub-circuit, a second end of the second capacitor and a first node are electrically connected with each other, and a control terminal of the gate reset sub-circuit is electrically connected with a second reset control signal terminal; the gate reset sub-circuit is configured to load the reference voltage to the first node in response to a gating level of the second reset control signal; a first end of the threshold compensation sub-circuit, a second electrode of the driving transistor and a third node are electrically connected with each other, and a control terminal of the threshold compensation sub-circuit is electrically connected with a fourth reset control signal terminal; the threshold compensation sub-circuit is configured to make the third node and the first node communicate with each other in response to a gating level of the fourth reset control signal; a first end of the voltage stabilizing sub-circuit is electrically connected with a constant voltage terminal, a second end of the voltage stabilizing sub-circuit, a second end of the first capacitor, a first end of the second capacitor and a fifth node are electrically connected with each other, and a control terminal of the voltage stabilizing sub-circuit is electrically connected with a third reset control signal terminal; the voltage stabilizing sub-circuit is configured to load the constant voltage to the fifth node in response to a gating level of the third reset control signal; a first end of the data writing sub-circuit is electrically connected with a data voltage terminal, and a control terminal of the data writing sub-circuit is electrically connected with a data writing control signal terminal; the data writing sub-circuit is configured to load the data voltage to the first node in response to a gating level of the data writing control signal; a first electrode of the driving transistor, a first end of the first capacitor and a second node are electrically connected with each other; the driving transistor is configured to generate a driving current.

2. The pixel driving circuit according to claim 1, wherein The second reset control signal and the fourth reset control signal are the same signal.

3. The pixel driving circuit of claim 1, wherein, The gate reset sub-circuit comprises a gate reset transistor; a first electrode of the gate reset transistor is electrically connected with the reference voltage terminal, a second electrode of the gate reset transistor is electrically connected with the first node, and a control electrode of the gate reset transistor is electrically connected with the second reset control signal terminal; the gate reset transistor is configured to load the reference voltage to the first node in response to a gating level of the second reset control signal; The threshold compensation sub-circuit comprises a threshold compensation transistor; a first electrode of the threshold compensation transistor is electrically connected with the third node, a second electrode of the threshold compensation transistor is electrically connected with the first node, and a control electrode of the threshold compensation transistor is electrically connected with the fourth reset control signal terminal; the threshold compensation transistor is configured to make the third node and the first node communicate with each other in response to a gating level of the fourth reset control signal; The voltage stabilizing sub-circuit comprises a voltage stabilizing transistor. The first electrode of the voltage stabilizing transistor is electrically connected with the constant voltage terminal, the second electrode of the voltage stabilizing transistor is electrically connected with the fifth node, and the control electrode of the voltage stabilizing transistor is electrically connected with the third reset control signal terminal; the voltage stabilizing transistor is used for loading the constant voltage to the fifth node in response to the gating level of the third reset control signal; The data writing sub-circuit comprises a data writing transistor; The first electrode of the data writing transistor is electrically connected with the data voltage terminal, the second electrode of the data writing transistor is electrically connected with the first node, and the control electrode of the data writing transistor is electrically connected with the data writing control signal terminal; the data writing transistor is used for loading the data voltage to the first node in response to the gating level of the data writing control signal.

4. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises a first light emitting control sub-circuit and a second light emitting control sub-circuit; The first end of the first light emitting control sub-circuit is electrically connected with the driving power voltage terminal, the second end of the first light emitting control sub-circuit is electrically connected with the second node, and the control end of the first light emitting control sub-circuit is electrically connected with the light emitting control signal terminal; the first light emitting control sub-circuit is used for loading the driving power voltage to the second node in response to the gating level of the light emitting control signal. The first end of the second light emitting control sub-circuit is electrically connected with the third node, the second end of the second light emitting control sub-circuit, the pixel electrode and the fourth node are electrically connected with each other, and the control end of the second light emitting control sub-circuit is electrically connected with the light emitting control signal terminal; the second light emitting control sub-circuit is used for making the third node and the fourth node communicate with each other in response to the gating level of the light emitting control signal.

5. The pixel driving circuit of claim 4, wherein, The first light emitting control sub-circuit comprises a first light emitting control transistor; The first electrode of the first light emitting control transistor is electrically connected with the driving power voltage terminal, the second electrode of the first light emitting control transistor is electrically connected with the second node, and the control electrode of the first light emitting control transistor is electrically connected with the light emitting control signal terminal; the first light emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the light emitting control signal. The second light emitting control sub-circuit comprises a second light emitting control transistor; The first electrode of the second light emitting control transistor is electrically connected with the third node, the second electrode of the second light emitting control transistor is electrically connected with the fourth node, and the control electrode of the second light emitting control transistor is electrically connected with the light emitting control signal terminal; the second light emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the light emitting control signal.

6. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises an electrode reset sub-circuit and a switch reset sub-circuit; The first end of the electrode reset sub-circuit is electrically connected with the first initialization voltage end, the second end of the electrode reset sub-circuit is electrically connected with the fourth node, and the control end of the electrode reset sub-circuit is electrically connected with the first reset control signal end; the electrode reset sub-circuit is used for loading the first initialization voltage to the fourth node in response to the gating level of the first reset control signal. The first end of the switch reset sub-circuit is electrically connected with the second initialization voltage end, the second end of the switch reset sub-circuit is electrically connected with the second node, and the control end of the switch reset sub-circuit is electrically connected with the first reset control signal end; the switch reset sub-circuit is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal.

7. The pixel driving circuit of claim 6, wherein, The electrode reset sub-circuit comprises an electrode reset transistor; The first electrode of the electrode reset transistor is electrically connected with the first initialization voltage end, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with the first reset control signal end; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to the gating level of the first reset control signal. The switch reset sub-circuit comprises a switch reset transistor; The first electrode of the switch reset transistor is electrically connected with the second initialization voltage end, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal end; the switch reset transistor is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal.

8. The pixel driving circuit of claim 3, wherein, The pixel driving circuit further comprises a first light-emitting control transistor, a second light-emitting control transistor, an electrode reset transistor and a switch reset transistor. The first electrode of the first light-emitting control transistor is electrically connected with the driving power voltage end, the second electrode of the first light-emitting control transistor is electrically connected with the second node, and the control electrode of the first light-emitting control transistor is electrically connected with the light-emitting control signal end; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the light-emitting control signal. The first electrode of the second light-emitting control transistor is electrically connected with the third node, the second electrode of the second light-emitting control transistor is electrically connected with the fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal end; the second light-emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the light-emitting control signal. The first electrode of the electrode reset transistor is electrically connected with the first initialization voltage end, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with the first reset control signal end; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to the gating level of the first reset control signal. The first electrode of the switch reset transistor is electrically connected with the second initialization voltage terminal, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal terminal; the switch reset transistor is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal.

9. The pixel driving circuit of claim 3, wherein, The pixel driving circuit further comprises a first light-emitting control transistor, a second light-emitting control transistor and an electrode reset transistor. The first electrode of the first light-emitting control transistor is electrically connected with the driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with the second node, and the control electrode of the first light-emitting control transistor is electrically connected with the first light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to the gating level of the first light-emitting control signal. The first electrode of the second light-emitting control transistor is electrically connected with the third node, the second electrode of the second light-emitting control transistor is electrically connected with the fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with the second light-emitting control signal terminal; the second light-emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the second light-emitting control signal. The first electrode of the electrode reset transistor is electrically connected with the first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with the second reset control signal terminal; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to the gating level of the second reset control signal.

10. The pixel driving circuit according to any one of claims 1 to 9, wherein The pixel driving circuit is configured to write the data voltage into the first node by the data writing sub-circuit after the gate reset sub-circuit writes the reference voltage into the first node.

11. The pixel driving circuit according to any one of claims 1 to 9, wherein The material of the channel region of at least one transistor is metal oxide semiconductor material.

12. The pixel driving circuit according to any one of claims 1 to 9, wherein The constant voltage is any one of the driving power voltage, the first initialization voltage, the second initialization voltage and the reference voltage.

13. A driving method of a pixel driving circuit, applied to the pixel driving circuit of claim 1; wherein, The driving method of the pixel driving circuit comprises: In the reset stage, the gating levels of the second reset control signal, the third reset control signal and the fourth reset control signal are loaded to the pixel driving circuit; In the compensation stage, the gating levels of the second reset control signal, the third reset control signal and the fourth reset control signal are loaded to the pixel driving circuit; In the writing stage, the gating levels of the third reset control signal and the data writing control signal are loaded to the pixel driving circuit.

14. The driving method of the pixel driving circuit according to claim 13, wherein The pixel driving circuit further comprises a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, an electrode reset sub-circuit and a switch reset sub-circuit. The first light-emitting control sub-circuit comprises a first light-emitting control transistor. The first electrode of the first light-emitting control transistor is electrically connected with a driving power voltage terminal, the second electrode of the first light-emitting control transistor is electrically connected with a second node, and the control electrode of the first light-emitting control transistor is electrically connected with a light-emitting control signal terminal; the first light-emitting control transistor is used for loading the driving power voltage to the second node in response to a gating level of the light-emitting control signal; The second light-emitting control sub-circuit comprises a second light-emitting control transistor; The first electrode of the second light-emitting control transistor is electrically connected with a third node, the second electrode of the second light-emitting control transistor is electrically connected with a fourth node, and the control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control signal terminal; the second light-emitting control transistor is used for making the third node and the fourth node communicate with each other in response to the gating level of the light-emitting control signal; The electrode reset sub-circuit comprises an electrode reset transistor; The first electrode of the electrode reset transistor is electrically connected with a first initialization voltage terminal, the second electrode of the electrode reset transistor is electrically connected with the fourth node, and the control electrode of the electrode reset transistor is electrically connected with a first reset control signal terminal; the electrode reset transistor is used for loading the first initialization voltage to the fourth node in response to a gating level of the first reset control signal; The switch reset sub-circuit comprises a switch reset transistor; The first electrode of the switch reset transistor is electrically connected with a second initialization voltage terminal, the second electrode of the switch reset transistor is electrically connected with the second node, and the control electrode of the switch reset transistor is electrically connected with the first reset control signal terminal; the switch reset transistor is used for loading the second initialization voltage to the second node in response to the gating level of the first reset control signal; The driving method of the pixel driving circuit comprises: In the reset stage, the pixel driving circuit is loaded with the gating levels of the first reset control signal, the second reset control signal, the third reset control signal and the fourth reset control signal; In the compensation stage, the pixel driving circuit is loaded with the gating levels of the second reset control signal, the third reset control signal and the fourth reset control signal; In the write-in stage, the pixel driving circuit is loaded with the gating levels of the third reset control signal and the data write-in control signal; In the light-emitting stage, the pixel driving circuit is loaded with the gating level of the light-emitting control signal.

15. A driving method of a pixel driving circuit, applied to the pixel driving circuit of claim 9; wherein, The driving method of the pixel driving circuit comprises: In the reset stage, the pixel driving circuit is loaded with the gating levels of the first light-emitting control signal, the second reset control signal and the third reset control signal; In the compensation stage, the pixel driving circuit is loaded with the gating levels of the second reset control signal and the third reset control signal; In the write-in stage, the pixel driving circuit is loaded with the gating levels of the third reset control signal and the data write-in control signal; In the light-emitting stage, the pixel driving circuit is loaded with the gating levels of the first light-emitting control signal and the second light-emitting control signal.

16. A display panel comprising an array of the pixel driving circuit according to any one of claims 1-12.

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