Method for configuring equalization parameters, chip, apparatus, and system

Abstract

Embodiments of the present application provide a method for configuring equalization parameters, a chip, an apparatus, and a system. In the method, a first PHY chip acquires a whole set of configuration information used for instructing to configure all parameters comprised in a parameter selection field, acquires, on the basis of the whole set of configuration information, a set of first configuration values corresponding to all parameters comprised in the parameter selection field, and applies the first configuration values to corresponding parameters. In this way, by means of the instruction of a whole set of configuration information, whole-set configuration is performed on equalization parameters to be configured in a communication system; compared with existing full traversal scanning modes for configuring equalization parameters to be configured one by one, the whole-set configuration mode allows for determination, for all equalization parameters to be configured and by means of a small number of parameter configurations, of a set of configuration values enabling the communication system to have good equalization performance in joint tuning, thereby making it possible to more quickly and accurately locate a tuning result of the communication system.

Description

A method, chip, device and system for configuring equalization parameters

[0001] The present application claims priority to the Chinese patent application No. 202410641983.0, filed on May 20, 2024, and entitled "A method, chip, device and system for configuring equalization parameters", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of data processing, in particular to a method, chip, device and system for configuring equalization parameters. BACKGROUND

[0003] For some high-speed interconnection scenarios, the communication system needs to configure equalization parameters to achieve better equalization effect in the communication system.

[0004] At present, for a communication system including a traditional optical module (may also be referred to as a retimed optical module), on the one hand, the configuration of the equalization parameters of the traditional optical module usually adopts a deconvolution manner, that is, the tap coefficients of a feed forward equalizer (FFE) are obtained by using an adaptive algorithm at a test point (TP) 2 of the traditional optical module, and then, based on the tap coefficients of the FFE and the equalization parameters of a transmitter finite impulse response (TX-FIR) of an optical digital signal processing (oDSP) chip in the traditional optical module, convolution is performed, and the result obtained by the convolution is configured to the TX-FIR in the oDSP chip of the traditional optical module. The TP2 point can refer to an optical output point of the optical module defined in Institute of Electrical and Electronics Engineers (IEEE) 802.3. On the other hand, if the equalization parameters of a physical layer (PHY) chip of a network device connected with the traditional optical module are configured by using the above-mentioned deconvolution manner, it will cause excessive pre-emphasis, poor signal-noise and distortion ratio (SNDR) of the signal, and affect the working performance of the communication system, that is, the above-mentioned deconvolution manner cannot be adapted to the configuration of the equalization parameters of the PHY chip of the network device connected with the traditional optical module; if the equalization parameters of the PHY chip of the network device connected with the traditional optical module are configured by using a full-amount traversal scanning (may also be referred to as a brute-force scanning) manner, since the number of the equalization parameters to be configured is increasing, more and more computing resources and processing time are required.

[0005] Therefore, it is urgent to provide a scheme capable of accurately and efficiently configuring the equalization parameters of a communication system, so as to guarantee the working performance of the communication system. SUMMARY

[0006] Therefore, the present application provides a configuration method, a chip, an apparatus and a system for equalization parameters, which can quickly and accurately optimize and configure the equalization parameters in a communication system.

[0007] In a first aspect, the present application provides a configuration method of equalization parameters. The method is applied to a first PHY chip. The method may, for example, comprise the following steps. First, the first PHY chip acquires a whole set of configuration information indicating configuration of all parameters included in a parameter selection field. Then, the first PHY chip acquires a first set of configuration values corresponding to all parameters included in the parameter selection field according to the whole set of configuration information. Next, the first PHY chip configures the first set of configuration values to the corresponding parameters. In this way, all equalization parameters to be configured (i.e., all parameters included in the parameter selection field) in the communication system are configured as a whole set according to the indication of the whole set of configuration information. Compared with the full traversal scanning method of configuring each equalization parameter to be configured one by one, the problem of low efficiency and high resource consumption in configuring the increasing equalization parameters to be configured independently is solved. The whole set configuration method can determine a set of configuration values of the equalization parameters to be configured in joint optimization, so that the equalization performance of the communication system is better, and it is possible to locate the optimization result of the communication system more quickly and accurately.

[0008] In some possible implementations, the first PHY chip acquires the whole set of configuration information may, for example, comprise that the first PHY chip receives the whole set of configuration information sent by the second PHY chip. This implementation may correspond to the link training scenario of the link from the first PHY chip to the second PHY chip in the communication system. The second PHY chip can be understood as the opposite end of the first PHY chip in the communication system. In this way, in the link training scenario, the first PHY chip can acquire the indication of the whole set of configuration from the opposite end, so that it is possible to realize the fast and accurate configuration of the equalization parameters by the whole set configuration.

[0009] As an example, the first PHY chip receiving the whole set of configuration information sent by the second PHY chip may, for example, comprise that the first PHY chip receives a first training frame sent by the second PHY chip, and a control field of the first training frame can be used to carry the whole set of configuration information. For the way of carrying the whole set of configuration information in the control field, for example, may comprise the following two ways. Way one: when an initial condition request field in the control field indicates separate parameter control and a format selection field is a first value, the control field indicates the whole set of configuration information, wherein the format selection field is any one reserved bit of the control field. Way two: when the initial condition request field in the control field indicates whole set parameter control through any one reserved value combination, the control field indicates the whole set of configuration information. In this way, in the link training scenario, the first PHY chip can acquire the whole set of configuration information from the training frame sent by the opposite end, so that it is possible to realize the fast and accurate configuration of the equalization parameters by the whole set configuration.

[0010] In some possible implementation manners, for the case that the whole set of configuration information is carried in the control field of the first training frame in the above-described manner one, the state machine related to the embodiments of the present application can include: case one, when the state machine of the first PHY chip is in the new index state, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control and the format selection field is the first value, the state machine of the first PHY chip jumps from the new index state to the new whole set state; case two, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control, the format selection field is the first value, and the parameter request field does not indicate keep, the state machine of the first PHY chip jumps from the new whole set state to the new request state; case three, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control, the format selection field is the first value, and the parameter request field does not indicate keep, the state machine of the first PHY chip jumps from the waiting state to the new request state; case four, when the state machine of the first PHY chip is in the new request state, in response to the fact that the parameter request field in the control field of the first training frame indicates keep, the state machine of the first PHY chip jumps from the new request state to the waiting state.

[0011] In some possible implementation manners, for the case that the whole set of configuration information is carried in the control field of the first training frame in the above-described manner one, the state machine related to the embodiments of the present application can include: case one, when the state machine of the first PHY chip is in the new index state, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control and the format selection field is the first value, the state machine of the first PHY chip jumps from the new index state to the new whole set state; case two, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control, the format selection field is the first value, and the parameter request field does not indicate keep, the state machine of the first PHY chip jumps from the new whole set state to the new request state; case three, in response to the fact that the initial condition request field in the control field of the first training frame indicates separate parameter control, the format selection field is the first value, and the parameter request field does not indicate keep, the state machine of the first PHY chip jumps from the waiting state to the new request state; case four, when the state machine of the first PHY chip is in the new request state, in response to the fact that the parameter request field in the control field of the first training frame indicates keep, the state machine of the first PHY chip jumps from the new request state to the waiting state.

[0012] In some possible implementation manners, after the first PHY chip configures the first configuration value to the corresponding parameter, the method can further include: the first PHY chip sends a second training frame to the second PHY chip, the second training frame being used by the second PHY chip to test a link performance from the first PHY chip to the second PHY chip to obtain first quality information. At this time, in a case where the second PHY chip determines that the first quality information does not satisfy a target condition, the second PHY chip can determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the corresponding parameter, and the second quality information being better than the first quality information. Therefore, the first PHY chip receives a third training frame sent by the second PHY chip, the third training frame including the adjustment information; the first PHY chip determines the second configuration value based on the adjustment information; and then, the first PHY chip configures the second configuration value to the corresponding parameter. In this way, when the first PHY chip configures a group of configuration values to the corresponding parameter, if the opposite end (that is, the second PHY chip) determines that the link quality at this time does not reach the expectation (that is, the target condition) of the whole group configuration at this stage, the first PHY chip can continue to configure another group of configuration values to the corresponding parameter based on the whole group configuration indication of the opposite end, until a group of configuration values that make the link quality satisfy the target condition are obtained as the configuration result of the whole group configuration at this stage.

[0013] In some possible implementation manners, the method is also applicable to a scenario of self-loop of a linear-drive pluggable optical module (LPO, which can also be referred to as a linear direct-drive optical module or a linear optical module), and the first PHY chip obtaining the whole group configuration information can include: the processor of the first PHY chip obtains the whole group configuration information of the TX when the LPO is in a self-loop state. In this way, without considering the opposite end, the processor of the first PHY chip can obtain the identifier of the whole group configuration information of the TX as the indication of the whole group configuration, so that it is possible to realize fast and accurate configuration of the balancing parameter in the LPO self-loop scenario by means of the whole group configuration.

[0014] As an example, in the scenario of the LPO self-loopback, after the first PHY chip configures the first configuration value to the corresponding parameter, the method can further include: the RX test of the first PHY chip tests the link performance from the first PHY chip to the second PHY chip to obtain first quality information. At this time, in one case, when the first PHY chip determines that the first quality information does not satisfy the target condition, the first PHY chip can determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate the corresponding link performance in the case of configuring the second configuration value to the corresponding parameter, and the second quality information being better than the first quality information. Thus, the first PHY chip determines the second configuration value based on the adjustment information, and then the first PHY chip configures the second configuration value to the corresponding parameter. In this way, when the first PHY chip configures a group of configuration values to the corresponding parameters, if the link quality based on the RX electrical signal quality in the loopback is determined to not reach the expectation (i.e., the target condition) of the whole group configuration stage, the first PHY chip can continue to configure another group of configuration values to the corresponding parameters based on the whole group configuration indication of the opposite end until a group of configuration values that make the link quality satisfy the target condition are obtained as the configuration result of the whole group configuration stage.

[0015] In some possible implementation manners, the configuration value in the whole group configuration process can come from a configuration table, and the configuration table can be obtained in the following manner: the first PHY chip obtains the configuration table according to the detail information of the first PHY chip and the LPO connected to the first PHY chip. The configuration table at least includes the first configuration value of all parameters included in the parameter selection field. The detail information can include at least one of the following information: the insertion loss of the connection interface of the first PHY chip and the LPO, the type of the LPO, the temperature of the LPO, the manufacturer of the LPO, and the number of tap coefficients of the TX-FIR in the first PHY chip. In this implementation manner, the first PHY chip obtains a group of first configuration values corresponding to all parameters included in the parameter selection field according to the whole group configuration information, which can include: the first PHY chip obtains the first configuration value from the configuration table according to the whole group configuration information. In this way, a configuration table including at least one group of configuration values is obtained through the architecture of the to-be-configured equalization parameter, so that a group of configuration values of the to-be-configured equalization parameter is obtained from the configuration table, thereby providing a data basis for the implementation of the whole group configuration, and making the whole group configuration scheme possible.

[0016] In some possible implementation manners, after the first PHY chip configures the entire set of configuration values to make the quality information satisfy the target condition, the first PHY chip can enter the independent configuration of the next stage. As an example, the method can further include: the first PHY chip obtaining independent configuration information, the independent configuration information indicating to respectively configure the parameters included in the parameter selection field; then, the first PHY chip recording the current set of configuration values of the parameters included in the parameter selection field as the first generation of tuning values according to the independent configuration information, and determining the target tuning values according to the first generation of tuning values. In this way, by defining the target condition, the progress of the configuration of the equalization parameters is grasped, after the entire set of configuration values is configured and it is determined that the corresponding quality information satisfies the target condition, the respective configuration of the parameters is performed based on the indication of the independent configuration, to obtain the target tuning values, so that the final optimization result of the configuration of the equalization parameters is more rapid and accurate.

[0017] The target condition can include any one of the following conditions: the quality information corresponding to the current set of configuration values of the parameters included in the parameter selection field satisfies a preset quality threshold; or the quality information corresponding to the current set of configuration values of the parameters included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table.

[0018] For the independent configuration manner, in some possible implementation manners, an evolutionary optimization manner can be adopted.

[0019] As an example, the first PHY chip can perform evolutionary optimization on only important parameters in the equalization parameters to be configured. For example, taking the first parameter set as a set of important parameters in all parameters included in the parameter selection field, and the first parameter set including a first parameter and a second parameter, the first PHY chip determining the target tuning values according to the first generation of tuning values can include: the first PHY chip obtaining first candidate data of the first parameter according to the first generation of tuning values of the first parameter and a first deviation range of the first parameter, the first candidate data being a value of the first parameter with a quantity corresponding to the first deviation range and taking the first generation of tuning values of the first parameter as a center; the first PHY chip determining a second generation of tuning values of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; the first PHY chip obtaining second candidate data of the second parameter according to the first generation of tuning values of the second parameter and a second deviation range of the second parameter, the second candidate data being a value of the second parameter with a quantity corresponding to the second deviation range and taking the first generation of tuning values of the second parameter as a center; and the first PHY chip determining a second generation of tuning values of the second parameter according to the second generation of tuning values of the first parameter, the second candidate data and fourth quality information corresponding to the second candidate data. In this way, in the case of obtaining the first generation of tuning values through the entire set of configuration, at least one evolutionary optimization is performed on the important parameters based on the first generation of tuning values with good effect, so that it is possible to quickly and accurately locate the target tuning values.

[0020] It should be noted that before the evolution optimization of the important parameters, the first PHY chip can also group the to-be-configured equalization parameters. That is, the method can also include: grouping all parameters included in the parameter selection field according to the influence of the parameters on the equalization performance in the communication system, obtaining a plurality of parameter sets, and the plurality of parameter sets include a first parameter set. In this way, since the important parameters usually have a greater influence on the equalization performance, during the evolution optimization process, the order of the evolution optimization is determined according to the importance of the parameters, which can accelerate the convergence speed of the evolution optimization to the target tuning value.

[0021] As another example, the first PHY chip can perform evolutionary optimization on both important parameters and non-important parameters in the to-be-configured equalization parameters. For example, taking the first parameter set as a set of important parameters among all parameters included in the parameter selection field, the first parameter set including the first parameter and the second parameter, the plurality of parameter sets further including a second parameter set, the second parameter set being a set of non-important parameters among all parameters included in the parameter selection field, the second parameter set including the third parameter, the first PHY chip determining the target tuning value according to the first generation tuning value can include: the first PHY chip obtaining first candidate data of the first parameter according to the first generation tuning value of the first parameter and a first deviation range of the first parameter, the first candidate data being a value of the first parameter corresponding to the number of the first deviation range and centered on the first generation tuning value of the first parameter; the first PHY chip determining the second generation tuning value of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; the first PHY chip obtaining second candidate data of the second parameter according to the first generation tuning value of the second parameter and a second deviation range of the second parameter, the second candidate data being a value of the second parameter corresponding to the number of the second deviation range and centered on the first generation tuning value of the second parameter; the first PHY chip determining the second generation tuning value of the second parameter according to the second generation tuning value of the first parameter, the second candidate data and fourth quality information corresponding to the second candidate data; then, the first PHY chip obtains third candidate data of the third parameter according to the first generation tuning value of the third parameter and a third deviation range of the third parameter, the third candidate data being a value of the third parameter corresponding to the number of the third deviation range and centered on the first generation tuning value of the third parameter; the first PHY chip determines the second generation tuning value of the third parameter according to the second generation tuning value of each parameter in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; if the sixth quality information corresponding to the second generation tuning value of each parameter in the first parameter set and the second parameter set satisfies the tuning stop condition, the first PHY chip determines the second generation tuning value as the target tuning value. In this way, in the case that the first generation tuning value is obtained in the whole set of configurations, at least one evolutionary optimization is performed on important parameters and non-important parameters based on the first generation tuning value with better effect, so that it is possible to quickly and accurately locate the target tuning value.

[0022] The tuning stop condition can include at least one of the following conditions: the tuning generation number is equal to a preset number of times; or, the difference between the quality information corresponding to the current generation tuning and the quality information corresponding to the previous generation tuning is less than a preset threshold; or, the tuning value corresponding to the current generation tuning is equal to the tuning value obtained in the previous generation tuning corresponding to the parameter.

[0023] For the independently configured manner, in some possible implementation manners, a preset algorithm can be adopted. As an example, the first PHY chip determining the target tuning value according to the first generation tuning value can include: the first PHY chip determining the target tuning value according to the first generation tuning value and a preset algorithm. The preset algorithm can include any one of the following algorithms: a genetic algorithm, a neural network algorithm or a particle swarm algorithm. In this way, through the preset algorithm, the effect of quickly and accurately positioning the target tuning value after the whole set of configurations can be achieved.

[0024] In a second aspect, the present application also provides a configuration method of equalization parameters. The method is applied to a second PHY chip. The method can include the following steps. First, the second PHY chip sends a first training frame to a first PHY chip. The first training frame includes whole set configuration information. The whole set configuration information indicates that all parameters included in a parameter selection field are configured. Then, the second PHY chip receives a second training frame sent by the first PHY chip. The second training frame is generated after the first PHY chip configures a set of first configuration values to parameters corresponding to the parameter selection field based on the whole set configuration information. Then, the second PHY chip tests the link performance of a link from the first PHY chip to the second PHY chip based on the second training frame, and obtains first quality information. The method can correspond to a link training scene of a link from the first PHY chip to the second PHY chip in a communication system. The second PHY chip can be understood as a peer of the first PHY chip in the communication system. In this way, in the link training scene, the second PHY chip can send the whole set configuration information to the first PHY chip. Through the indication of the whole set configuration information, the first PHY chip can configure all equalization parameters (i.e., all parameters included in the parameter selection field) to be configured in the communication system in a whole set. Compared with a full traversal scanning manner of configuring each equalization parameter to be configured one by one, the whole set configuration manner can solve the problems of low efficiency and high resource consumption in independently configuring the increasing equalization parameters to be configured. The whole set configuration manner can determine a set of configuration values with better equalization performance of the communication system in joint tuning of all equalization parameters to be configured, so that it is possible to quickly and accurately locate the tuning result of the communication system.

[0025] In some possible implementation manners, after the second PHY chip obtains the first quality information, the method can further include: if it is determined that the first quality information meets a target condition, the second PHY chip sends a third training frame to the first PHY chip. The control field of the third training frame indicates that the independent configuration information is carried. The independent configuration information indicates that the parameters included in the parameter selection field are configured respectively.

[0026] In some possible implementation manners, for the manner in which the control field carries independent configuration information, the manner can include: manner three, when the initial condition request field in the control field indicates separate parameter control, and the format selection field is the second value, the control field indicates independent configuration information, and the format selection field is any one of the reserved bits of the control field; and manner four, when the initial condition request field in the control field indicates separate parameter control, the control field indicates separate configuration information.

[0027] In some possible implementation manners, for the case in which the independent configuration information is carried in the control field of the third training frame by using the above-described manner three, the state machine related to the embodiments of the present application can include: case five, when the state machine of the first PHY chip is in the waiting state, in response to the initial condition request field in the control field of the third training frame indicating separate parameter control, and the format selection field being the second value, the state machine of the first PHY chip jumps from the waiting state to the new index state.

[0028] In some possible implementation manners, for the case in which the independent configuration information is carried in the control field of the third training frame by using the above-described manner four, the state machine related to the embodiments of the present application can include: case five, when the state machine of the first PHY chip is in the waiting state, in response to the initial condition request field in the control field of the third training frame indicating separate parameter control, the state machine of the first PHY chip jumps from the waiting state to the new index state.

[0029] In some possible implementation manners, after the second PHY chip obtains the first quality information, the method can further include: if it is determined that the first quality information does not satisfy the target condition, the second PHY chip determines adjustment information according to the first quality information, the adjustment information is used to indicate a second configuration value, the second configuration value corresponds to second quality information, the second quality information is used to indicate a corresponding link performance in a case in which the second configuration value is configured to the parameter corresponding to the parameter selection field, and the second quality information is better than the first quality information; then, the second PHY chip sends a fourth training frame to the first PHY chip, the fourth training frame includes the adjustment information; the second PHY chip receives a fifth training frame sent by the first PHY chip, the fifth training frame is generated after the first PHY chip configures the second configuration value to the parameter corresponding to the parameter selection field; and the second PHY chip tests the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtains the second quality information. In this way, at least one whole-group configuration can be performed through the judgment of the target condition, and the configuration efficiency of the equalization parameter is improved.

[0030] The target condition can include any one of the following conditions: quality information corresponding to the current set of configuration values of the parameter included in the parameter selection field satisfies a preset quality threshold; or, quality information corresponding to the current set of configuration values of the parameter included in the parameter selection field is better than quality information corresponding to other sets of configuration values in the configuration table.

[0031] It should be noted that the related description of the second aspect can refer to the corresponding description of the first aspect in the link training scenario.

[0032] In a third aspect, the present application further provides a chip applied to the first PHY chip. The chip includes an interface circuit and a processing circuit. The interface circuit is configured to obtain a complete set of configuration information, and the complete set of configuration information indicates configuration of all parameters included in the parameter selection field. The processing circuit is configured to obtain a set of first configuration values corresponding to all parameters included in the parameter selection field according to the complete set of configuration information. The processing circuit is further configured to configure the first configuration values to the corresponding parameters.

[0033] In some possible implementation manners, the interface circuit is specifically configured to: receive the complete set of configuration information sent by the second PHY chip.

[0034] As an example, the interface circuit is specifically configured to: receive the first training frame sent by the second PHY chip, and the control field of the first training frame carries the complete set of configuration information.

[0035] In some possible implementation manners, when the initial condition request field in the control field indicates separate parameter control and the format selection field is the first value, the control field indicates the complete set of configuration information, and the format selection field is any one reserved bit of the control field; or, when the initial condition request field in the control field indicates complete set parameter control through any one reserved value combination, the control field indicates the complete set of configuration information.

[0036] In some possible implementation manners, when the state machine of the first PHY chip is in the new index state, the state machine of the first PHY chip jumps from the new index state to the new complete set state in response to satisfaction of the following conditions: the initial condition request field in the control field of the first training frame indicates separate parameter control, and the format selection field is the first value; or, the initial condition request field in the control field of the first training frame indicates complete set parameter control.

[0037] In some possible implementations, the state machine of the first PHY chip transitions from a new set of states to a new request state in response to the following conditions: the initial condition request field in the control field of the first training frame indicates individual parameter control, the format selection field is a first value, and the parameter request field does not indicate hold; or, the initial condition request field in the control field of the first training frame indicates the entire set of parameter control, and the parameter request field does not indicate hold.

[0038] In some possible implementations, when the state machine of the first PHY chip is in the new request state, the state machine of the first PHY chip transitions from the new request state to the waiting state in response to the following condition: the parameter request field in the control field of the first training frame indicates that it is held.

[0039] In some possible implementations, the interface circuit is further configured to send a second training frame to the second PHY chip after configuring the first configuration value to the corresponding parameter. The second training frame is used by the second PHY chip to test the link performance from the first PHY chip to the second PHY chip to obtain first quality information, and to determine adjustment information based on the first quality information. The adjustment information is used to indicate a second configuration value, which corresponds to the second quality information. The second quality information is used to indicate the link performance when the second configuration value is configured to the corresponding parameter, and the second quality information is superior to the first quality information. The interface circuit is further configured to receive a third training frame sent by the second PHY chip, which includes the adjustment information. The processing circuit is further configured to determine the second configuration value based on the adjustment information.

[0040] In some possible implementations, the interface circuit is specifically used to: when the LPO connected to the first PHY chip is in a self-loopback state, the processor of the chip obtains the entire set of configuration information.

[0041] In some possible implementations, the processing circuit is further configured to, after configuring the first configuration value to the corresponding parameter, perform RX testing on the link performance from the TX of the first PHY chip back to the RX of the first PHY chip via the LPO, to obtain first quality information; the processing circuit is further configured to determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate the link performance when the second configuration value is configured to the corresponding parameter, the second quality information being superior to the first quality information; the processing circuit is further configured to determine the second configuration value based on the adjustment information.

[0042] In some possible implementations, the processing circuit is also used to configure the second configuration value to the corresponding parameter after configuring the first configuration value to the corresponding parameter.

[0043] In some possible implementation manners, the processing circuitry is further configured to obtain a configuration table according to the detail information of the first PHY chip and the LPO connected to the first PHY chip, the configuration table including at least the first configuration values of all parameters included in the parameter selection field, and the detail information including at least one of the following information: insertion loss of a connection interface of the first PHY chip and the LPO, type of the LPO, temperature of the LPO, manufacturer of the LPO, and number of tap coefficients of a transmitter finite impulse response (TX-FIR) in the first PHY chip; and the processing circuitry is specifically configured to obtain the first configuration values from the configuration table according to the entire set of configuration information.

[0044] In some possible implementation manners, the interface circuitry is further configured to obtain independent configuration information, the independent configuration information indicating that the parameters included in the parameter selection field are configured respectively; and the processing circuitry is further configured to record the current set of configuration values of the parameters included in the parameter selection field as the first generation of tuning values according to the independent configuration information, and determine the target tuning values according to the first generation of tuning values.

[0045] In some possible implementation manners, the processing circuitry is specifically configured to: obtain first candidate data of a first parameter according to the first generation of tuning values of the first parameter and a first deviation range of the first parameter, the first parameter belonging to a first parameter set, the first parameter set being a set of important parameters in all parameters included in the parameter selection field, the first candidate data being values of the first parameter corresponding to the first deviation range in number and centered on the first generation of tuning values of the first parameter; determine a second generation of tuning values of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; obtain second candidate data of a second parameter according to a first generation of tuning values of the second parameter in the first parameter set and a second deviation range of the second parameter, the second candidate data being values of the second parameter corresponding to the second deviation range in number and centered on the first generation of tuning values of the second parameter; and determine a second generation of tuning values of the second parameter according to the second generation of tuning values of the first parameter, the second candidate data, and fourth quality information corresponding to the second candidate data.

[0046] In some possible implementation manners, the processing circuitry is further configured to group all parameters included in the parameter selection field according to influences of the parameters on equalization performance in the communication system, to obtain a plurality of parameter sets, and the plurality of parameter sets include the first parameter set.

[0047] In some possible implementation manners, the plurality of parameter sets further includes a second parameter set, the second parameter set being a set of non-important parameters among all parameters included in the parameter selection field, and the second parameter set including a third parameter; the processing circuit is further configured to, after determining the second generation of optimized values of the parameters in the first parameter set, obtain third candidate data of the third parameter according to the first generation of optimized value of the third parameter and a third deviation range of the third parameter, the third candidate data being values of the third parameter corresponding to the third deviation range and centered on the first generation of optimized value of the third parameter; determine a second generation of optimized value of the third parameter according to the second generation of optimized values of the parameters in the first parameter set, the third candidate data, and fifth quality information corresponding to the third candidate data; and determine the target optimized value as the second generation of optimized values of the parameters in the first parameter set and the second parameter set if sixth quality information corresponding to the second generation of optimized values of the parameters meets an optimized stop condition.

[0048] The optimized stop condition can include at least one of the following conditions: the number of generations of optimization is equal to a preset number of generations; or a difference between quality information corresponding to the current generation of optimization and quality information corresponding to a previous generation of optimization is less than a preset threshold; or an optimized value corresponding to the current generation of optimization is equal to an optimized value obtained in the previous generation of optimization.

[0049] In some possible implementation manners, the processing circuit is specifically configured to: determine the target optimized value according to the first generation of optimized values and a preset algorithm, and the preset algorithm includes any one of the following algorithms: a genetic algorithm, a neural network algorithm, or a particle swarm algorithm.

[0050] It should be noted that the related description of the third aspect can be referred to the corresponding description of the first aspect.

[0051] In a fourth aspect, the present application further provides a chip applied to the second PHY chip. The chip includes an interface circuit and a processing circuit. The interface circuit is configured to send a first training frame to the first PHY chip, the first training frame including a complete set of configuration information, the complete set of configuration information indicating configuration of all parameters included in the parameter selection field; the interface circuit is further configured to receive a second training frame sent by the first PHY chip, the second training frame being generated by the first PHY chip after configuring a set of first configuration values to the parameters corresponding to the parameter selection field based on the complete set of configuration information; and the processing circuit is configured to test a link performance of a link from the first PHY chip to the second PHY chip based on the second training frame, and obtain first quality information.

[0052] In some possible implementation manners, the interface circuit is further configured to, after obtaining the first quality information, send, if it is determined that the first quality information satisfies the target condition, a third training frame to the first PHY chip, the control field of the third training frame indicating that the independent configuration information is carried, and the independent configuration information indicating that the parameters included in the parameter selection field are configured respectively.

[0053] As an example, when the initial condition request field in the control field indicates the separate parameter control and the format selection field is the second value, the control field indicates the independent configuration information, and the format selection field is any one of the reserved bits of the control field; or, when the initial condition request field in the control field indicates the separate parameter control, the control field indicates the separate configuration information.

[0054] In some possible implementation manners, when the state machine of the first PHY chip is in the waiting state, the state machine of the first PHY chip is switched from the waiting state to the new index state in response to the following condition being satisfied: the initial condition request field in the control field of the third training frame indicates the separate parameter control, and the format selection field is the second value; or, the initial condition request field in the control field of the third training frame indicates the separate parameter control.

[0055] In some possible implementation manners, the processing circuit is further configured to, after obtaining the first quality information, determine, if it is determined that the first quality information does not satisfy the target condition, adjustment information according to the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to the second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the parameters corresponding to the parameter selection field, and the second quality information being better than the first quality information; the interface circuit is further configured to send, to the first PHY chip, a fourth training frame including the adjustment information; the interface circuit is further configured to receive a fifth training frame sent by the first PHY chip, the fifth training frame being generated after the first PHY chip configures the second configuration value to the parameters corresponding to the parameter selection field; and the processing circuit is further configured to test the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtain the second quality information.

[0056] The target condition can include any one of the following conditions: the quality information corresponding to the current set of configuration values on the parameters included in the parameter selection field satisfies a preset quality threshold; or, the quality information corresponding to the current set of configuration values on the parameters included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table.

[0057] It should be noted that the related description of the fourth aspect can be referred to the corresponding description of the second aspect.

[0058] In a fifth aspect, the present application provides a configuration device for equalization parameters, which is applied to the first PHY chip. The device may, for example, comprise an obtaining unit and a processing unit. The obtaining unit is configured to obtain a complete set of configuration information, which indicates configuration of all parameters included in the parameter selection field; the processing unit is configured to obtain a first set of configuration values corresponding to all parameters included in the parameter selection field according to the complete set of configuration information; and the processing unit is further configured to configure the first set of configuration values to the corresponding parameters.

[0059] In some possible implementation manners, the obtaining unit is specifically configured to receive the complete set of configuration information sent by the second PHY chip.

[0060] As an example, the obtaining unit is specifically configured to receive the first training frame sent by the second PHY chip, and the control field of the first training frame carries the complete set of configuration information.

[0061] In some possible implementation manners, when the initial condition request field in the control field indicates individual parameter control and the format selection field is the first value, the control field indicates the complete set of configuration information, and the format selection field is any one reserved bit of the control field; or when the initial condition request field in the control field indicates complete set parameter control through any one reserved value combination, the control field indicates the complete set of configuration information.

[0062] In some possible implementation manners, when the state machine of the first PHY chip is in the new index state, the state machine of the first PHY chip jumps from the new index state to the new complete set state in response to satisfaction of the following conditions: the initial condition request field in the control field of the first training frame indicates individual parameter control, and the format selection field is the first value; or the initial condition request field in the control field of the first training frame indicates complete set parameter control.

[0063] In some possible implementation manners, the state machine of the first PHY chip jumps from the new complete set state to the new request state, or the state machine of the first PHY chip jumps from the waiting state to the new request state in response to satisfaction of the following conditions: the initial condition request field in the control field of the first training frame indicates individual parameter control, the format selection field is the first value, and the parameter request field does not indicate to keep; or the initial condition request field in the control field of the first training frame indicates complete set parameter control, and the parameter request field does not indicate to keep.

[0064] In some possible implementation manners, when the state machine of the first PHY chip is in the new request state, the state machine of the first PHY chip jumps from the new request state to the waiting state in response to satisfaction of the following condition: the parameter request field in the control field of the first training frame indicates to keep.

[0065] In some possible implementation manners, the apparatus can further include a sending unit and a receiving unit. The sending unit is configured to send, after the first configuration value is configured to the corresponding parameter, a second training frame to the second PHY chip, the second training frame being used by the second PHY chip to test a link performance from the first PHY chip to the second PHY chip to obtain first quality information, and determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate that the corresponding link performance under the condition that the second configuration value is configured to the corresponding parameter is better than the first quality information; the receiving unit is configured to receive a third training frame sent by the second PHY chip, the third training frame including the adjustment information; and the processing unit is further configured to determine the second configuration value based on the adjustment information.

[0066] In some possible implementation manners, the obtaining unit is specifically configured to: obtain, by the processor of the first PHY chip, the entire set of configuration information when the LPO connected to the first PHY chip is in a self-loopback state.

[0067] As an example, the processing unit is further configured to test, after the first configuration value is configured to the corresponding parameter, a link performance of RX of the first PHY chip from TX of the first PHY chip through the LPO and then looped back to the RX of the first PHY chip, to obtain first quality information; the processing unit is further configured to determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate that the corresponding link performance under the condition that the second configuration value is configured to the corresponding parameter is better than the first quality information; and the processing unit is further configured to determine the second configuration value based on the adjustment information.

[0068] In some possible implementation manners, the processing unit is further configured to configure the second configuration value to the corresponding parameter after the first configuration value is configured to the corresponding parameter.

[0069] In some possible implementation manners, the processing unit is further configured to obtain a configuration table according to detail information of the first PHY chip and the LPO connected to the first PHY chip, the configuration table including at least the first configuration value of all parameters included in the parameter selection field, and the detail information including at least one of the following information: an insertion loss of a connection interface of the first PHY chip and the LPO, a type of the LPO, a temperature of the LPO, a manufacturer of the LPO, and a number of tap coefficients of a transmitter finite impulse response (TX-FIR) in the first PHY chip; and the processing unit is specifically configured to obtain the first configuration value from the configuration table according to the entire set of configuration information.

[0070] In some possible implementation manners, the obtaining unit is further configured to obtain independent configuration information, the independent configuration information indicating that parameters included in the parameter selection field are configured respectively; and the processing unit is further configured to, according to the independent configuration information, record a current set of configuration values of the parameters included in the parameter selection field as first generation tuning values, and determine the target tuning values according to the first generation tuning values.

[0071] In some possible implementation manners, the processing unit is specifically configured to: obtain first candidate data of a first parameter according to the first generation tuning value of the first parameter and a first deviation range of the first parameter, the first parameter belonging to a first parameter set, the first parameter set being a set of important parameters in all parameters included in the parameter selection field, the first candidate data being a value of the first parameter corresponding in number to the first deviation range and centered on the first generation tuning value of the first parameter; determine a second generation tuning value of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; obtain second candidate data of a second parameter according to a first generation tuning value of the second parameter in the first parameter set and a second deviation range of the second parameter, the second candidate data being a value of the second parameter corresponding in number to the second deviation range and centered on the first generation tuning value of the second parameter; and determine a second generation tuning value of the second parameter according to the second generation tuning value of the first parameter, the second candidate data and fourth quality information corresponding to the second candidate data.

[0072] In some possible implementation manners, the processing unit is further configured to group all parameters included in the parameter selection field according to influences of the all parameters on the balance performance of the communication system, to obtain a plurality of parameter sets, and the plurality of parameter sets include the first parameter set.

[0073] In some possible implementation manners, the plurality of parameter sets further include a second parameter set, the second parameter set being a set of unimportant parameters in all parameters included in the parameter selection field, and the second parameter set including a third parameter. The processing unit is specifically configured to: after determining the second generation tuning values of the parameters in the first parameter set, obtain third candidate data of the third parameter according to a first generation tuning value of the third parameter and a third deviation range of the third parameter, the third candidate data being a value of the third parameter corresponding in number to the third deviation range and centered on the first generation tuning value of the third parameter; determine a second generation tuning value of the third parameter according to the second generation tuning values of the parameters in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; and if sixth quality information corresponding to the second generation tuning values of the parameters in the first parameter set and the second parameter set satisfies a tuning stop condition, determine the second generation tuning values as the target tuning values.

[0074] The tuning stop condition can include at least one of the following conditions: the tuning algebra is equal to a preset number of times; or, a difference between quality information corresponding to the current generation of tuning and quality information corresponding to a previous generation of tuning is less than a preset threshold; or, a tuning value corresponding to the current generation of tuning is equal to a tuning value obtained by the corresponding parameter in the previous generation of tuning.

[0075] In some possible implementation manners, the processing unit is specifically configured to: determine the target tuning value according to the first generation of tuning value and a preset algorithm, and the preset algorithm includes any one of the following algorithms: a genetic algorithm, a neural network algorithm, or a particle swarm algorithm.

[0076] It should be noted that the related description of the fifth aspect can refer to the corresponding description of the first aspect.

[0077] In the sixth aspect, the application further provides a configuration device for equalization parameters. The device is applied to a second PHY chip. The device can include a sending unit, a receiving unit, and a processing unit. The sending unit is configured to send a first training frame to a first PHY chip, and the first training frame includes a complete set of configuration information, and the complete set of configuration information indicates that all parameters included in a parameter selection field are configured. The receiving unit is configured to receive a second training frame sent by the first PHY chip, and the second training frame is generated after the first PHY chip configures a first set of configuration values to parameters corresponding to the parameter selection field based on the complete set of configuration information. The processing unit is configured to test a link performance of a link from the first PHY chip to the second PHY chip based on the second training frame, and obtain first quality information.

[0078] In some possible implementation manners, the sending unit is further configured to, after obtaining the first quality information, if it is determined that the first quality information meets a target condition, send a third training frame to the first PHY chip, and the control field of the third training frame indicates that independent configuration information is carried, and the independent configuration information indicates that the parameters included in the parameter selection field are configured respectively.

[0079] As an example, when the initial condition request field in the control field indicates separate parameter control, and the format selection field is the second value, the control field indicates independent configuration information, and the format selection field is any one of the reserved bits of the control field; or, when the initial condition request field in the control field indicates separate parameter control, the control field indicates separate configuration information.

[0080] In some possible implementation manners, when the state machine of the first PHY chip is in the waiting state, the state machine of the first PHY chip jumps from the waiting state to the new index state in response to the following conditions being met: the initial condition request field in the control field of the third training frame indicates separate parameter control, and the format selection field is the second value; or the initial condition request field in the control field of the third training frame indicates separate parameter control.

[0081] In some possible implementation manners, the processing unit is further configured to, after obtaining the first quality information, determine adjustment information according to the first quality information if it is determined that the first quality information does not meet the target condition, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the parameter corresponding to the parameter selection field, and the second quality information being better than the first quality information; the sending unit is further configured to send, to the first PHY chip, a fourth training frame, the fourth training frame including the adjustment information; the receiving unit is further configured to receive a fifth training frame sent by the first PHY chip, the fifth training frame being generated by the first PHY chip after the second configuration value is configured to the parameter corresponding to the parameter selection field; and the processing unit is further configured to test the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtain the second quality information.

[0082] The target condition can include any one of the following conditions: the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field meets a preset quality threshold; or the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table.

[0083] It should be noted that the related description of the sixth aspect can be referred to the description corresponding to the second aspect.

[0084] In a seventh aspect, the present application provides a communication device, the communication device including an interface and a processor. The interface is configured to receive instructions and transmit the instructions to the processor. The processor is configured to execute the method corresponding to the first aspect, the second aspect, and possible implementation manners thereof.

[0085] In an eighth aspect, the present application provides a communication system, the communication system including a first PHY chip and a second PHY chip. The first PHY chip is configured to execute the method corresponding to the first aspect and possible implementation manners thereof. The second PHY chip is configured to execute the method corresponding to the second aspect and possible implementation manners thereof.

[0086] In a ninth aspect, the present application provides a storage medium, wherein the storage medium stores instructions, and the instructions, when executed on a processor, implement the method of the first aspect, the second aspect, and possible implementation manners thereof.

[0087] In a tenth aspect, the present application provides a program product, wherein the program product comprises a program, and the program, when executed on a processor, implements the method of the first aspect, the second aspect, and possible implementation manners thereof. BRIEF DESCRIPTION OF DRAWINGS

[0088] FIG. 1 is a schematic diagram of a conventional optical module according to an embodiment of the present application;

[0089] FIG. 2 is a schematic diagram of an LPO according to an embodiment of the present application;

[0090] FIG. 3 is a schematic diagram of a scenario of an end-to-end communication link according to an embodiment of the present application;

[0091] FIG. 4 is a schematic diagram of a method 100 for configuring an equalization parameter according to an embodiment of the present application;

[0092] FIG. 5 is a schematic diagram of a method 200 corresponding to the method 100 when the method 100 is applied to the scenario shown in FIG. 3 according to an embodiment of the present application;

[0093] FIG. 6 is a schematic diagram of a state machine of the method provided according to an embodiment of the present application;

[0094] FIG. 7 is a schematic diagram of a scenario of a self-loop to which the method provided according to an embodiment of the present application is applicable;

[0095] FIG. 8 is a schematic diagram of a scenario of a multi-tap TX-FFE to which the method provided according to an embodiment of the present application is applicable;

[0096] FIG. 9 is a schematic diagram of an example of the method according to an embodiment of the present application;

[0097] FIG. 10 is a schematic diagram of a structure of a chip 1000 according to an embodiment of the present application;

[0098] FIG. 11 is a schematic diagram of a structure of a communication apparatus 1100 according to an embodiment of the present application;

[0099] FIG. 12 is a schematic diagram of a structure of a communication apparatus 1200 according to an embodiment of the present application;

[0100] FIG. 13 is a schematic diagram of a structure of a communication apparatus 1300 according to an embodiment of the present application;

[0101] FIG. 14 is a schematic diagram of a structure of a communication system 1400 according to an embodiment of the present application. DETAILED DESCRIPTION

[0102] At present, for a communication system including a traditional optical module, the configuration of equalization parameters is performed in two parts respectively: for the configuration of equalization parameters in the traditional optical module, a deconvolution method is usually adopted; for the configuration of equalization parameters of a PHY chip of a network device connected with the traditional optical module, a full-amount traversal scanning method is adopted. Since the deconvolution method is used to configure the equalization parameters of the PHY chip of the network device, it will cause excessive pre-emphasis, that is, the signal in the communication system is increased but the noise is unchanged, so that the SNDR of the signal is deteriorated, and the working performance of the communication system is affected, therefore, the above-mentioned deconvolution method cannot be adapted to the configuration of the equalization parameters of the PHY chip of the network device connected with the traditional optical module. For the configuration of the equalization parameters of the PHY chip of the network device connected with the traditional optical module, since the number of equalization parameters to be configured is increasing, more and more computing resources and processing time are required. It can be seen that, although the deconvolution method can realize the configuration of the equalization parameters of the oDSP chip in the traditional optical module, it needs to be separately configured for the network device connected with the traditional optical module, and still needs to be configured by full-amount traversal scanning, therefore, the current configuration method for the communication system including the traditional optical module not only has the problem of inaccurate configuration, but also needs to consume more computing resources and processing time.

[0103] With the continuous improvement of network user demand and the continuous increase of data traffic, in the high-speed interconnected communication system, the cost, bandwidth density and energy consumption are also rapidly rising, and saving cost, bandwidth density and reducing power consumption have become the goal to be pursued in the next step of development of the communication system.

[0104] For example, a conventional optical module is shown in FIG. 1, which can at least include an optical Digital Signal Processing (oDSP) chip, a Laser Driver (Laser DRV), a Laser, a Photo-Diode (PD) and a Trans-impedance Amplifier (TIA), wherein the oDSP chip has a large power consumption, which accounts for more than 50% of the power consumption of the conventional optical module, and the oDSP chip also has a high cost. Therefore, the LPO is born. Since the LPO adopts a linear optical engine interface to connect with a network device, and the linear optical engine interface has significant advantages in power consumption, cost, latency and the like, the LPO is likely to be widely used in future high-speed interconnected communication systems. The LPO is shown in FIG. 2, which can at least include a Laser DRV (which can also be understood as a DRV), a Laser, a PD and a TIA, compared with the conventional optical module, the oDSP chip included in the conventional optical module is removed, and the equalization capability of the oDSP chip is offloaded to a continuous time linear equalizer (CTLE) integrated in the Laser DRV of the LPO and a forward feedback equalizer (FFE) included in a serializer / deserializer (SerDes) on an application-specific integrated circuit (ASIC) side of the network device connected with the LPO. Specifically, as shown in FIG. 2, the Laser DRV of the LPO can integrate the CTLE to compensate for channel impairment, and the FFE can be included in the SerDes on the ASIC side of the network device connected with the LPO, so as to reduce the bit error rate (BER) of the link through stronger equalization performance. There are many equalization parameters to be configured and coupled with each other, and the influence of each equalization parameter on the end-to-end communication link needs to be considered.

[0105] For a communication system including an LPO, using the above deconvolution method to configure the equalization parameters of the PHY chip of the network device connected to the LPO can cause excessive pre-emphasis, poor SNDR of the signal, and affect the working performance of the communication system. Moreover, since the oDSP chip is no longer included in the LPO, the above deconvolution method cannot be adapted to the configuration of the equalization parameters in the LPO. It can be seen that the above deconvolution method cannot be applied to the configuration of the communication system including the LPO. If the full-amount traversal scanning method is used to configure the communication system including the LPO, since the number of equalization parameters to be configured is increasing, more computing resources and processing time are required.

[0106] For example, in the future 224G+ optoelectronic interconnection technology, whether a traditional optical module or an LPO is used to connect with a network device, the equalization capability of the communication system must be greatly improved, and the equalization parameters involved will greatly increase. For example, the FFE included in the SerDes on the ASIC side of the network device needs more tap coefficients to overcome the inter-symbol interference (ISI) caused by bandwidth limitation, for example, the FFE selects an equalizer with more than or equal to 15 taps (i.e., 15 tap coefficients). The more tap coefficients the FFE has, the more equalization parameters with a coupling relationship the FFE needs to jointly optimize and configure, and the influence of multiple equalization parameters on the equalization performance of the equalizer needs to be considered.

[0107] It can be seen that in many scenarios including the above two examples, the equalization parameters that need to be jointly optimized are increasing, and each equalization parameter is coupled with each other, and the configuration solution space is very large. At present, the optimal values of the multiple equalization parameters to be configured are determined by full-quantity traversal scanning of the multiple equalization parameters to be configured. However, with the increase of the equalization parameters to be configured, the traversal scanning method has a huge solution space, which brings problems of long optimization time and difficulty in finding a global optimal solution, and the calculation and storage resources consumed are huge, which cannot meet the demand of quickly optimizing the equalization parameters. Taking the end-to-end communication link of the LPO-LPO architecture shown in FIG. 3 as an example, the modules related to the equalization function of the sending side can include TX-FFE on the SerDes transmitter (TX) of the network device 1 and DRV_CTLE on the LPO 1, and the modules related to the equalization function of the receiving side can include PD+TIA on the LPO 2 and RX-CTLE, Clock Data Recovery FFE (CDR_FFE) and RX_Volterra equalizer (RX_Vol) on the SerDes receiver (RX) of the network device 2. Taking the joint optimization and configuration of the equalization parameters of the sending side as an example, assuming that the FEE is a 3tap FFE, the equalization parameters to be configured can include 3 tap coefficients of TX-FFE and 3 equalization parameters of DRV_CTLE, and the corresponding solution space is shown in Table 1 as follows. The solution space can be represented as: Q1*Q2*Q3*M1*M2*M3. The number of solution spaces is large, and therefore, it takes a long time to jointly optimize the equalization parameters on the communication link. Therefore, it is an urgent problem to be solved in the development process of high-speed interconnection communication scenarios to quickly and conveniently jointly optimize multiple equalization parameters to be configured.

[0108] Table 1

[0109] Based on this, the embodiment of the present application provides a configuration scheme of equalization parameters, which can realize accurate and efficient configuration of equalization parameters for the scenario of more equalization parameters to be jointly configured in a communication system, and guarantee the working performance of the communication system. The configuration method of equalization parameters may, for example, include the following steps. First, a first PHY chip acquires a complete set of configuration information, which indicates that all parameters included in a parameter selection (coef_sel) field are configured. Then, the first PHY chip acquires a first set of configuration values corresponding to all parameters included in the parameter selection field according to the complete set of configuration information. Then, the first PHY chip configures the first configuration values to the corresponding parameters. In this way, through the indication of the complete set of configuration information, the equalization parameters to be configured in the communication system (i.e., all parameters included in the parameter selection field) are configured as a complete set. Compared with the full-amount traversal scanning mode of configuring each equalization parameter to be configured one by one, the problem of low efficiency and high resource consumption in independently configuring the gradually increasing equalization parameters to be configured is solved. The complete set configuration method can determine a set of configuration values with better equalization performance of the communication system in the joint optimization of all equalization parameters to be configured through a small number of parameter configurations, so as to more quickly and accurately locate the optimization result of the communication system.

[0110] It should be noted that in the embodiments of the present application, the network device (which can also be referred to as a communication apparatus) where the PHY chip is located can be a general term for devices that can exist in a network, and can be a conventional network device such as a switch, a router, or a firewall, or a terminal device such as a user host or a vehicle host. For the scenario of configuring the equalization parameters on the end-to-end communication link, the first PHY chip executing the method provided in the embodiments of the present application can be a PHY chip on the sending device, and the second PHY chip can be a PHY chip on the receiving device. Taking the communication link from the network device 1 to the network device 2 through the LPO 1 and the LPO 2 in sequence as shown in FIG. 3 as an example, the first PHY chip can be the PHY chip 1 in the network device 1 for connecting the LPO 1, and the second PHY chip can be the PHY chip 2 in the network device 2 for the LPO 2. Specifically, the PHY chip can include firmware or mainboard control software. The firmware can be understood as an operating system of the SerDes, and the firmware is a control software in the PHY chip, which can be deployed in a microcontroller unit (MCU) of the SerDes, and the functions include controlling a register in the equalizer of the SerDes, and the firmware can execute the corresponding method provided in the embodiments of the present application. The network device where the PHY chip is located includes a mainboard and a plurality of line cards, and the mainboard is used to control each line card, and the mainboard control software can execute the corresponding method provided in the embodiments of the present application, and the obtained configuration value (or tuning value) is issued through the mainboard, and the PMD layer (i.e., the register of the SerDes) is controlled through a protocol or other channels, so as to realize the downward configuration of the configuration value (or the tuning value).

[0111] It should be noted that the PHY chip can be implemented by an ASIC chip, and can also be referred to as an electrical chip. The SerDes on the ASIC side in the above can be integrated with the ASIC chip, or can be set independently of the ASIC chip.

[0112] The embodiments of the present application can be applicable to a link training (LT) scenario, that is, before the communication system is running, the optimization and configuration of the to-be-configured parameters including the equalization parameters can be completed through link training, and the preparation work for the running of the communication system is prepared. The method provided by the embodiments of the present application can belong to the Link training stage. For the communication system, the end-to-end link training can be performed in two directions at the same time, and when the link training in both directions is completed, the link training of the bidirectional link of the communication system is completed. When the link training in a certain direction fails, it is considered that the link training for the bidirectional link of the communication system fails, and the link training in two directions needs to be restarted. For the entire link training process, a maximum allowed time (such as max-timer) or a maximum training number can be set. Then, the link training failure can mean that the link training is not completed within the max-timer, and once the duration of the link training exceeds the limit of the max-timer, it is considered that the link training fails, and the entire link training process can be restarted by resetting the link training. Alternatively, the link training failure can mean that the number of link training reaches the maximum training number, and the link training is still not completed, at this time, it can be considered that the link training fails, and the entire link training process can be restarted by resetting the link training. For details, reference can be made to the related description of the method 100 applied to the scenario shown in FIG. 3 or the related description of the method 200.

[0113] The embodiments of the present application can also be applicable to the scenario that after the LPO is connected to the network device, the end of the LPO away from the network device is looped back, for details, reference can be made to the related description of the method 100 applied to the scenario shown in FIG. 7.

[0114] It should be noted that the to-be-configured equalization parameters in the embodiments of the present application can be equalization parameters on the end-to-end communication link, such as the related description of the scenario shown in FIG. 3; can be equalization parameters on the network device and the LPO, such as the related description of the scenario shown in FIG. 7; and can also be equalization parameters on the network device or the optical module, such as the related description of the scenario shown in FIG. 8.

[0115] It should be noted that the method provided by the embodiments of the present application can be applied to the case of jointly optimizing and configuring a plurality of to-be-configured equalization parameters in various data transmission scenarios, including but not limited to: data center, supercomputing node, artificial intelligence data center network (AIDCN) and the like.

[0116] It should be noted that the optical module in the embodiments of the present application can also be replaced with an active copper cable linear (ACC-Linear) module. The ACC-Linear module is different from the LPO in that there is no device (such as a laser and a PD) for converting an electrical signal into an optical signal, and the ACC-Linear module can include, for example, a linear equalization chip for improving the equalization performance of a signal. In the following, the ACC-Linear module is used instead of the optical module in the description of the configuration process of the equalization parameters, without affecting the description of the configuration process of the equalization parameters.

[0117] In order to more clearly introduce the embodiments of the present application, the method provided by the embodiments of the present application is described below with reference to the accompanying drawings.

[0118] FIG. 4 is a flowchart of a configuration method 100 of equalization parameters provided by the embodiments of the present application. In the method 100, a first PHY chip is taken as an execution subject, and the embodiments of the present application are introduced. The first PHY chip can be, for example, the PHY chip 1 in the network device 1 or the PHY chip 2 in the network device 2 shown in FIG. 3; or the first PHY chip can be, for example, the PHY chip 1 in the network device 1 shown in FIG. 7; or the first PHY chip can be, for example, the PHY chip 1 in the network device 1 shown in FIG. 8. The method 100 is implemented by the first PHY chip, and can be implemented by, for example, Firmware or host board control software in the first PHY chip.

[0119] As shown in FIG. 4, the method 100 can include, for example, the following S101-S103:

[0120] S101, the first PHY chip obtains a complete set of configuration information, and the complete set of configuration information indicates configuration of all parameters included in a parameter selection field.

[0121] The complete set of configuration information can be information indicating that a complete set of configuration values is configured on corresponding parameters. In the embodiments of the present application, all parameters participating in configuration can have corresponding embodiments in the parameter selection field, and therefore the complete set of configuration information can be understood as information indicating configuration of all parameters included in the parameter selection field. For example, in the configuration process of the equalization parameters of the sender (i.e., the network device 1 and the LPO 1) in the scenario shown in FIG. 3, the complete set of configuration information can indicate simultaneous configuration of pre1, main and post1 of the 3tap coefficient TX-FFE and dc_gain, boost0 and boost1 of the DRV_CTLE.

[0122] The parameter selection field can be one field in the training frame. The training frame can include a frame marker field, a control field, a status field, and a training pattern field. Among them, the bit in the control field and the status field in the training frame can be encoded in a differential Manchester encoding (DME) manner. The link training can be divided into three steps: first, frame locking, which can be understood as the identification of the training frame, which is implemented through the frame marker field in the training frame. Second, the training process is used to complete the interaction and negotiation of parameters. Among them, the control field in the training frame is used to indicate how the TX side of the party receiving the training frame adjusts the equalization parameters, such as which preset is used for initialization configuration, which parameter is selected for adjustment, etc. The status field in the training frame is fed back by the TX side of the party adjusting the equalization parameters, such as whether the parameter has been adjusted to the limit, whether the receiving end is in the ready state, etc. Third, the update of the parameter. It should be noted that the above three steps involved in the link training are not improved in the embodiments of the present application, so the three steps are not described, and the specific can be referred to the definition in the related communication standard.

[0123] The parameter selection field can be one of the control fields of the training frame. The control field of the training frame can include 16 bits from the 0th bit to the 15th bit, which is described below as an example of the definition of the control field in the training frame in IEEE 802.3 CL162. The 9 known value combinations of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit of the control field of the training frame can be used to indicate the parameters that can be involved in the configuration, respectively. The 6th bit, the 7th bit, the 10th bit, the 11th bit, the 14th bit and the 15th bit are reserved (Reserved) bits. It should be noted that in the configuration process of the 6 equalization parameters of the sender (i.e., network device 1 and LPO 1) in the scenario shown in FIG. 3, only any 6 known value combinations of the 9 known value combinations of the parameter selection field can take effect, and each known value combination corresponds to a unique parameter to be configured. For example, when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 0011, it can be used to indicate the configuration of pre1 of TX-FFE; when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 1011, it can be used to indicate the configuration of main of TX-FFE; when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 0111, it can be used to indicate the configuration of post1 of TX-FFE; when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 1111, it can be used to indicate the configuration of dc_gain of DRV_CTLE; when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 0000, it can be used to indicate the configuration of boost0 of DRV_CTLE; and when the known value combination of the 2nd bit, the 3rd bit, the 4th bit and the 5th bit is 1000, it can be used to indicate the configuration of boost1 of DRV_CTLE.

[0124] In some possible implementation, the embodiment of the present application is applicable to the scenario shown in FIG. 3, for example, the equalization parameters are configured when the link training is performed on the communication system shown in FIG. 3. In the following example for this scenario, the link training is performed on the link from the network device 1 to the network device 2 in FIG. 3, and the equalization parameters in the sender (i.e., the network device 1 and the LPO 1) are configured in the link training process. In this implementation, the first PHY chip can correspond to the PHY chip 1 in the network device 1, and the second PHY chip corresponds to the PHY chip 2 in the network device 2.

[0125] As an example, S101 can include that the first PHY chip receives the whole set of configuration information sent by the second PHY chip. For example, the whole set of configuration information can be carried in the control field of the first training frame sent by the second PHY chip to the first PHY chip, that is, S101 can include that the first PHY chip receives the first training frame sent by the second PHY chip, and the control field of the first training frame carries the whole set of configuration information.

[0126] For the manner that the control field of the first training frame carries the whole set of configuration information, the following manners can be included but are not limited to:

[0127] Manner one, when the initial condition request (ic_req) field in the control field indicates individual coefficient control (ind_ctl) and the format select (format_sel) field is the first value, the control field can indicate the whole set of configuration information. The format select field can be any reserved bit of the control field. Compared with the definition of the training frame in the current IEEE 802.3, one reserved bit is used in the embodiment of the present application, which is defined as the format select field, and is used to indicate whether the whole set of configuration or independent configuration is used for the parameter. The initial condition request field can be the 12th and 13th bits of the control field. For example, the 6th bit of the control field is used as the format select field, and the first value is 1. When the initial condition request field = 00 and the format select field = 1, the first training frame includes the whole set of configuration information. In the state machine description below, the whole set of configuration information corresponding to this manner can be represented as: ic_req = ind_ctl * format_sel = 1.

[0128] Manner two, when the initial condition request field in the control field indicates group coefficient control (group_ctl) through any reserved value combination, the control field can indicate the whole set of configuration information. The initial condition request field can be the 11th, 12th and 13th bits of the control field. For example, the reserved value combination of the 11th, 12th and 13th bits in the first training frame can include 101. When the initial condition request field = 101, the first training frame includes the whole set of configuration information. In the state machine description below, the whole set of configuration information corresponding to this manner can be represented as: ic_req = group_ctl.

[0129] It should be noted that the related description in this implementation manner can refer to the related description of the method 200 corresponding to FIG. 5, which will not be described here.

[0130] In some possible implementation manners, the embodiments of the present application can also be applied to the scenario of the self-loop shown in FIG. 7, for example, configuring the equalization parameters in the TX-FFE in the network device 1 and the DRV_CTLE in the LPO 1 shown in FIG. 7. In the following example for this scenario, the first PHY chip can correspond to the PHY chip 1 in the network device 1.

[0131] As an example, S101 can include: when the LPO is in the self-loop state, the processor of the first PHY chip obtains a complete set of configuration information of the TX. The complete set of configuration information can be an identifier corresponding to the self-loop state configured in the processor of the first PHY chip of the network device. When the LPO is inserted into the network device and the LPO is in the self-loop state, the network device confirms that the LPO enters the self-loop state, and the processor of the first PHY chip of the network device selects a set of configuration parameters from the configuration table according to the complete set of configuration information and configures the TX of the first PHY chip of the network device. The equalization parameters of the TX of the first PHY chip are embodied by registers, and the processor (such as Firmware) of the first PHY chip issues an instruction to the register to configure the corresponding equalization parameters on the TX of the first PHY chip. In specific implementation, after the processor of the first PHY chip obtains the complete set of configuration information, it can select a set of configuration values from the configuration table and configure them into the registers corresponding to the equalizer of the TX. It should be noted that the processor of the first PHY chip may, for example, be a microcontroller unit (MCU) of a SerDes, and in this example, the processor of the first PHY chip can also be implemented through a controller of the first PHY chip.

[0132] It should be noted that other descriptions in this implementation manner can refer to the related description of FIG. 7 below, which will not be expanded here.

[0133] It can be seen that through S101, the first PHY chip obtains the complete set of configuration information, which provides an indication for subsequent configuration of all parameters to be configured, making it possible to quickly and accurately configure the equalization parameters based on the embodiments of the present application.

[0134] S102, the first PHY chip obtains a set of first configuration values corresponding to all parameters included in the parameter selection field according to the complete set of configuration information.

[0135] For S102, for example, the first PHY chip can obtain the first configuration value corresponding to all parameters included in the parameter selection field in response to the indication of the complete set of configuration information.

[0136] As an example, before S102, the method 100 can further include: the first PHY chip obtaining a configuration table, the configuration table can include a plurality of groups of configuration values corresponding to all parameters included in the parameter selection field, and the plurality of groups of configuration values can include at least a first group of configuration values. Then, S102 can include: the first PHY chip obtaining the first group of configuration values from the configuration table in response to the indication of the entire group of configuration information.

[0137] For the first PHY chip obtaining the configuration table, for example, the first PHY chip can obtain the configuration table 2 from the entire configuration table 1 according to the detail information of the first PHY chip and the LPO, the configuration table 2 being the basis for the entire group configuration in the embodiments of the present application, and the configuration table 2 can include at least the first configuration values of all parameters included in the parameter selection field. The detail information can include at least one of the following information: the insertion loss of the connection interface of the first PHY chip and the LPO, the type of the LPO, the temperature of the LPO, the manufacturer of the LPO, and the number of tap coefficients of the TX-FIR in the first PHY chip. The insertion loss of the connection interface of the first PHY chip and the LPO can refer to the loss of energy or gain on the connection interface when the LPO is inserted into the network device where the first PHY chip is located. The type of the LPO can refer to whether the LPO is a single-mode or multi-mode LPO. The temperature of the LPO can refer to the temperature of the working environment of the LPO or the LPO itself. The manufacturer of the LPO can refer to the enterprise that produces the LPO. The number of tap coefficients of the TX-FIR in the first PHY chip can refer to the number of tap coefficients of the TX-FFE in the first PHY chip, for example, if the first PHY chip includes a 3-tap TX-FFE, then the number of tap coefficients of the TX-FIR in the first PHY chip is 3. The configuration table 1 is a whole table maintained by the first PHY chip or the network device where the first PHY chip is located. For different values of each information included in the above detailed information, at least one group of configuration values can be obtained from the configuration table 1, that is, for a group of values of each information included in the above detailed information, at least one group of configuration values corresponding to all parameters included in the parameter selection field can be obtained from the configuration table 1. The configuration table 1 can be stored in the Firmware of the first PHY chip, for example.

[0138] For example, for the case that the insertion loss of the connection interface of the first PHY chip and the LPO is 6 dB, the type of the LPO is a single-mode LPO, the temperature of the LPO is 15 degrees Celsius, the manufacturer of the LPO is A, and the number of tap coefficients of the TX-FIR in the first PHY chip is 3, the configuration table 2 shown in Table 2 can be obtained.

[0139] For example, for the case that the type of LPO is single-mode LPO, the temperature of LPO is 15 degrees Celsius, the manufacturer of LPO is A, and the number of tap coefficients of TX-FIR in the first PHY chip is 3, and the insertion loss of the connection interface between the first PHY chip and the LPO is 6dB-15dB, the configuration table 2 shown in Table 3 can be obtained.

[0140] Table 2

[0141] Table 3

[0142] In the configuration table 2, nonlinear coefficients and output swing can also be included. The nonlinear coefficients are used to overcome the nonlinear effects caused by optoelectronic devices, and the output swing is used to compensate the signal transmitted from the sender to the receiver. In the embodiments of the present application, the equalization parameters to be configured shown in Table 2 are taken as an example for description.

[0143] Based on the first set of configuration values determined in S102, any set of values corresponding to pre1, main, post1, dc_gain, boost0 and boost1 in Table 2 or Table 3 can be used, for example, A1, B1, C1, D1, E1 and F1.

[0144] For the link training scenario, the link training process before S102 can include the following steps. S11, the first PHY chip and the second PHY chip can simultaneously send a training frame to complete frame locking. S12, the second PHY chip sends a training frame 1 to the first PHY chip. The control field in the training frame 1 is used to indicate which preset is selected for initialization configuration. For example, the control field of the training frame 1 can indicate the corresponding preset through the value combination of the initial condition request field, for example, initial condition request field = 10 indicates using preset1 for initialization configuration, initial condition request field = 01 indicates using preset2 for initialization configuration, and initial condition request field = 11 indicates using preset3 for initialization configuration. S13, after the first PHY chip completes the initialization configuration based on the training frame 1, the first PHY chip feeds back a training frame 2 to the second PHY chip. S14, the second PHY chip sends a training frame 3 to the first PHY chip. The training frame 3 includes a complete set of configuration information. S14 can be understood as a possible implementation of S101. The training frame 3 corresponds to the first training frame described above.

[0145] It should be noted that the preset of the initialization configuration can be a set of initialization configuration values corresponding to all parameters included in the parameter selection field, and the initialization configuration values can be included in the configuration table. The preset of the initialization configuration can be used as an actual configuration value of all parameters included in the parameter selection field before the first configuration value is obtained, or can be used as a reference for obtaining the first configuration value from the configuration table. For example, in addition to including the entire set of configuration information, the first training frame can also include adjustment information for indicating the relationship between the preset of the initialization configuration and the first configuration value. For example, the adjustment information indicates that the first configuration value takes the next set of configuration values of the preset of the initialization configuration. For another example, the adjustment information indicates that the first configuration value takes the previous set of configuration values of the preset of the initialization configuration. The adjustment information can be carried by, for example, a value combination of a Coefficient Request field in the first training frame.

[0146] It can be seen that a set of first configuration values are obtained through S102, and preparation work is completed for the execution of configuring the first configuration values to corresponding parameters (that is, S103).

[0147] S103, the first PHY chip configures the first configuration values to corresponding parameters.

[0148] As an example, S103 can include, for example, the first PHY chip configures the configuration values corresponding to the equalization parameters on the first PHY chip (such as the equalization parameters of TX-FFE) in the first configuration values to the equalization parameters corresponding to the first PHY chip; and the first PHY chip configures the configuration values corresponding to the equalization parameters on the LPO (such as the equalization parameters of DRV_CTLE) in the first configuration values to the LPO through an Inter-Integrated Circuit (IIC or I2C) bus, other management register channels or data channels.

[0149] It should be noted that for the case that there are many equalization parameters to be configured, the equalization parameters to be configured can also be carried in multiple different configuration sub-tables, and each configuration sub-table corresponds to a part of the equalization parameters to be configured. Then, in the embodiment of the present application, any one parameter set can be configured as a whole first, and when the equalization parameters of the parameter set are configured, the configuration of another parameter set can be started. As an example, weights can be set for the configuration sub-tables corresponding to the multiple parameter sets, and the order of configuration of the parameter sets is determined based on the size of the weights. The weights can be flexibly set based on actual conditions (such as the size of the influence of the parameters in the parameter set on the equalization performance or the importance of the parameters, etc.).

[0150] For example, the equalization parameters to be configured include: a third parameter set and a fourth parameter set, the first configuration value of the third parameter set belongs to the first configuration sub-table, and the first configuration value of the fourth parameter set belongs to the second configuration sub-table. S103 can include: the first PHY chip configures the first configuration value in the first configuration sub-table to each parameter in the third parameter set respectively; if it is determined that the quality information 1 corresponding to the first configuration value of the third parameter set satisfies condition 1, the first configuration value in the second configuration sub-table is configured to each parameter in the fourth parameter set respectively. Condition 1 can be used to indicate whether the expected effect has been achieved for the whole group configuration of the parameters in the current parameter set. Condition 1 may, for example, include that the gap between the quality information 1 and the quality information 2 corresponding to the previous group of configuration values in the first configuration sub-table is less than a preset threshold 1.

[0151] After S103, the method 100 can further include: obtaining the link performance of the link including the first PHY chip and the LPO (corresponding to the scenario of link training, the link is from the first PHY chip to the second PHY chip; corresponding to the scenario of LPO self-loopback, the link is from the TX of the first PHY chip to the RX of the first PHY chip through the LPO), to obtain the first quality information; determining whether the first quality information satisfies a target condition. If it satisfies, it can be considered that the expected effect has been achieved for the whole group configuration of all the parameters included in the parameter selection field, and it is not necessary to continue to improve the link quality by adjusting all the parameters included in the parameter selection field as a whole. If it does not satisfy, it can be considered that it is necessary to continue to configure all the parameters included in the parameter selection field as a whole to improve the link quality. The target condition can be used to indicate whether the expected effect has been achieved for the whole group configuration of all the parameters included in the parameter selection field. The target condition may, for example, include any one of the following conditions: the quality information corresponding to the current group of configuration values on the parameters included in the parameter selection field satisfies a preset quality threshold; or, the quality information corresponding to the current group of configuration values on the parameters included in the parameter selection field is better than the quality information corresponding to other groups of configuration values in the configuration table. Taking the quality information represented by the BER as an example, the target condition can include: the BER corresponding to the current group of configuration values is less than or equal to a BER threshold, or the BER corresponding to the current group of configuration values is the minimum value among the BERs corresponding to each group of configuration values in the configuration table; taking the quality information represented by the signal-to-noise ratio (SNR) as an example, the target condition can include: the SNR corresponding to the current group of configuration values is greater than or equal to an SNR threshold, or the SNR corresponding to the current group of configuration values is the minimum value among the SNRs corresponding to each group of configuration values in the configuration table.

[0152] As an example, if it is determined that the first quality information satisfies the target condition, the first PHY chip can obtain independent configuration information indicating that the parameters included in the parameter selection field are configured respectively; the first PHY chip records the current set of configuration values (i.e., the first configuration values) of the parameters included in the parameter selection field as the first generation of tuning values based on the independent configuration information, and determines the target tuning values according to the first generation of tuning values. In this way, the phase of the whole set of configurations in the configuration process of the equalization parameters is completed, and the configuration result of this phase, i.e., the first generation of tuning values, is obtained, and this is used as the basis to enter the phase of independent configuration of the equalization parameters.

[0153] As another example, if it is determined that the first quality information does not satisfy the target condition, adjustment information can be determined based on the first quality information, and the second configuration values indicated by the adjustment information are configured to the corresponding parameters. In this way, the best set of configuration values in terms of link performance can be obtained from a plurality of sets of configuration values through multiple whole set configurations, as the starting point of the next phase of independent configuration, so as to improve the configuration efficiency of the equalization parameters. In this example, it is necessary to constantly search for a set of configuration values that satisfies the target condition, and the configuration value that satisfies the target condition is taken as the first generation of tuning values, so that the first PHY chip determines the target tuning values according to the first generation of tuning values.

[0154] Among the adjustment information indicating the second configuration values, in one case, a specific set of configuration values among all the parameters included in the parameter selection field can be directly indicated. For example, the first configuration values are A2, B2, C2, D2, E2 and F2 in Table 3 above, and the adjustment information can directly indicate that the second configuration values are A1, B1, C1, D1, E1 and F1 in Table 3. In another case, the relationship between the second configuration values and the first configuration values can be indicated, for example, the adjustment information indicates that the second configuration values take the next set of configuration values of the first configuration values, and for another example, the adjustment information indicates that the second configuration values take the previous set of configuration values of the first configuration values, and in this way, the second configuration values can be determined based on the first configuration values and the adjustment information.

[0155] For the scenario of link training, after S103, the method 100 can further include that the first PHY chip sends a second training frame to the second PHY chip, the second training frame including, in addition to the state information after the first configuration values are configured to the corresponding parameters, test information; the second PHY chip tests the link performance of the link from the first PHY chip to the second PHY chip based on the test information in the second training frame to obtain the first quality information.

[0156] For example, the status field of the second training frame is used to indicate the status information after the first configuration value is configured to the corresponding parameter, and the status information can include but is not limited to: the adjustment result corresponding to the link training, the specific parameter adjusted, and the state of the specific parameter adjusted. For the case where the status information corresponds to the training frame, the adjustment result corresponding to the link training can indicate whether the parameter corresponding to a certain link training request needs to be adjusted, the specific parameter adjusted can indicate the parameter actually adjusted in the process of responding to a certain link training request to perform link training, and the state of the specific parameter adjusted can indicate whether the parameter of each adjusted parameter is adjusted to the limit (i.e. the boundary or boundary range of the value that the parameter can take).

[0157] For example, the training mode field of the second training frame is used to carry test information, and the training mode field can be understood as a test sequence, which is used by the second PHY chip to test the link quality of the link transmitting the second training frame. Since the link is in the state after being configured based on the first configuration value, the first link quality obtained by testing the link quality of the link can represent the effect of the configuration, and can provide reliable data basis for the next decision of configuring the link.

[0158] In some possible implementations, after the second PHY chip obtains the first quality information, the method 100 can further include: determining, by the second PHY chip, whether the first quality information satisfies a target condition. If the second PHY chip determines that the first quality information satisfies the target condition, the second PHY chip can generate and send, to the first PHY chip, a third training frame, and the third training frame can include independent configuration information indicating that the parameters included in the parameter selection field are configured respectively. The first PHY chip can record, based on the independent configuration information, a current set of configuration values (i.e., the first configuration values) of the parameters included in the parameter selection field as the first generation of tuning values, and determine the target tuning values according to the first generation of tuning values. If the second PHY chip determines that the first quality information does not satisfy the target condition, the second PHY chip can continue to instruct the first PHY chip to perform the whole set of configurations, and instruct the adjustment information of the whole set of configurations. For example, the second PHY chip can determine, according to the first quality information, the adjustment information for indicating the second configuration values corresponding to the second quality information, the second quality information being used to indicate the corresponding link performance in the case that the second configuration values are configured to the parameters corresponding to the parameter selection field, and the second quality information being better than the first quality information. Then, the second PHY chip sends a fourth training frame (also corresponding to the third training frame) to the first PHY chip, and the fourth training frame includes the adjustment information. After receiving the fourth training frame, the first PHY chip can determine the second configuration values based on the adjustment information, and configure the second configuration values to the corresponding parameters. Thus, the first PHY chip can generate and send a fifth training frame to the second PHY chip, so that the second PHY chip tests the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtains the second quality information. In this example, it is necessary to continuously search for a set of configuration values satisfying the target condition, and the configuration values satisfying the target condition are used as the first generation of tuning values, so that the first PHY chip determines the target tuning values according to the first generation of tuning values.

[0159] In this scenario, the adjustment information can be carried, for example, by the value combination of the parameter request (Coefficient Request) field in the fourth training frame. For example, the first configuration values are A2, B2, C2, D2, E2 and F2 in Table 3, if the adjustment information indicates that the second configuration values take the previous set of configuration values of the first configuration values, then the second configuration values determined according to the adjustment information can be A1, B1, C1, D1, E1 and F1 in Table 3; if the adjustment information indicates that the second configuration values take the next set of configuration values of the first configuration values, then the second configuration values determined according to the adjustment information can be A3, B3, C3, D3, E3 and F3 in Table 3.

[0160] In this scenario, the way of carrying the independent configuration information in the control field of the sixth training frame can include but is not limited to:

[0161] In the first way, when the initial condition request field in the control field indicates individual coefficient control (ind ctl) and the format selection field is the second value, the control field can indicate independent configuration information. For example, the 6th bit of the control field is the format selection field, and the second value is 0. When the initial condition request field = 00 and the format selection field = 0, the sixth training frame includes independent configuration information. In the state machine description below, the independent configuration information corresponding to this way can be represented as: ic req = ind ctl * format sel = 0.

[0162] In the second way, when the initial condition request field in the control field indicates individual coefficient control (ind ctl), the control field can indicate independent configuration information. The initial condition request field can be the 11th, 12th and 13th bits of the control field. For example, when the initial condition request field = 000, it indicates individual coefficient control, that is, the sixth training frame includes independent configuration information. In the state machine description below, the independent configuration information corresponding to this way can be represented as: ic req = ind ctl.

[0163] For the scenario of LPO self-loopback, after S103, the method 100 can further include: the RX test of the first PHY chip tests the link performance of the RX of the first PHY chip after the LPO from the TX of the first PHY chip to the RX of the first PHY chip, to obtain first quality information, and transmits the first quality information to the processor of the first PHY chip.

[0164] In some possible implementations, after the processor of the first PHY chip obtains the first quality information, the method 100 can further include: the processor of the first PHY chip determining whether the first quality information satisfies a target condition. If the processor of the first PHY chip determines that the first quality information satisfies the target condition, the processor of the first PHY chip obtains independent configuration information corresponding to the target condition, records a current set of configuration values (i.e., first configuration values) of parameters included in the parameter selection field as first generation tuning values, and determines a target tuning value according to the first generation tuning values. If the processor of the first PHY chip determines that the first quality information does not satisfy the target condition, the processor of the first PHY chip can continue to instruct the TX of the first PHY chip to perform the whole set of configurations, and instruct adjustment information of the whole set of configurations. For example, the processor of the first PHY chip can determine the adjustment information according to the first quality information, the adjustment information being used to instruct second configuration values corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration values are configured to the parameters corresponding to the parameter selection field, and the second quality information being better than the first quality information. Then, the processor of the first PHY chip sends the adjustment information to the TX of the first PHY chip. The processor of the first PHY chip determines the second configuration values based on the adjustment information, and configures the second configuration values to the parameters corresponding to the TX. In this example, a set of configuration values satisfying the target condition needs to be searched constantly, and the configuration values satisfying the target condition are taken as the first generation tuning values, so that the first PHY chip determines the target tuning value according to the first generation tuning values.

[0165] In this scenario, the independent configuration information can be, for example, an identifier corresponding to the target condition and maintained by the processor of the first PHY chip, which is different from the whole set of configuration information. When the processor of the first PHY chip determines that the LPO is in the self-looping state and the current quality information does not satisfy the target condition, the identifier corresponding to the whole set of configuration information takes effect, and the whole set of configurations enters the stage. When the processor of the first PHY chip determines that the LPO is in the self-looping state and the current quality information satisfies the target condition, the identifier corresponding to the independent configuration information takes effect, and the independent configuration enters the stage.

[0166] After the first generation tuning values are determined, the method 100 enters the stage of independent configuration, and the first PHY chip can determine the target tuning value according to the first generation tuning values.

[0167] As an example, the first PHY chip can determine the target tuning value according to the first generation tuning value in an evolutionary optimization manner. Before evolutionary tuning, the first PHY chip can group all parameters included in the parameter selection field according to the influence of the parameters on the equalization performance of the communication system, obtain a plurality of parameter sets, and the plurality of parameter sets can include at least a first parameter set and a second parameter set. For grouping, in one case, the grouping can be implemented according to the physical characteristics of the communication system. Taking a 5-tap FFE as an example, according to the impulse response (IPR) curve and the principle of the FFE, it can be determined that the influence of pre1 and post1 on the equalization performance of the communication system is greater than the influence of pre2 and post2 on the equalization performance of the communication system, and therefore, pre1 and post1 of the TX-FFE can be divided into the first parameter set, and pre2 and post2 of the TX-FFE can be divided into the second parameter set. In addition, the value of main of the TX-FFE can be equal to n-|pre1|-|pre2|-|post1|-|post2|, and n is an integer, so the value of main can be determined based on the other four tap coefficients. In this embodiment, the main is divided into the second parameter set, and in other scenarios, the main can also be flexibly divided according to needs. For DRV_CTLE, boost1 can be divided into the first parameter set and dc_gain and boost0 can be divided into the second parameter set according to the response curve of the CTLE, because boost1 dominates the boost capability of the CTLE at high frequencies. In another case, the grouping can also be implemented through simulation and actual measurement of the communication system. The grouping process can include, for example, first, traversing and scanning each equalization parameter with a large step, observing the quality information (such as BER or SER) of the electrical signal at the RX side under each scan combination; then, defining the quality threshold of the electrical signal at the RX side, and dividing each equalization parameter into the first parameter set or the second parameter set according to the quality threshold; in this way, through multiple simulations, the quality information of the electrical signal at the RX side corresponding to each equalization parameter scan is sorted, and the corresponding quality threshold of the electrical signal is found, so that the importance of the equalization parameter can be determined, and the final first parameter set and second parameter set can be obtained.

[0168] In the first case in the example, the first PHY chip can perform several times of independent optimization on the important parameters in the important parameter set among the equalization parameters to be configured, and obtain the optimization result when the optimization stop condition is met, and configure the equalization parameters in the communication system according to the optimization result. In this way, since the non-important parameters have less impact on the equalization performance of the communication system, the important parameters can be optimized, which greatly reduces the number of solution spaces and makes it possible to quickly converge to the optimal parameter combination.

[0169] In the second case in the example, the first PHY chip can perform several times of independent optimization on the important parameters in the important parameter set among the equalization parameters to be configured and perform several times of independent optimization on the non-important parameters in the non-important parameter set, and obtain the optimization result when the optimization stop condition is met, and configure the equalization parameters in the communication system according to the optimization result. In this way, the number of iterations can be accelerated, and the efficiency of configuring the equalization parameters can be improved.

[0170] Hereinafter, the case in which the plurality of parameter sets include a first parameter set, the first parameter set is an important parameter set, and a second parameter set is a non-important parameter set is described.

[0171] For the first case, the first PHY chip determines the target optimization value according to the first generation optimization value, and the process of one-time independent configuration may, for example, include: the first PHY chip obtains first candidate data of the first parameter according to the first generation optimization value of the first parameter and a first deviation range of the first parameter, the first parameter belongs to the first parameter set, the first parameter set is an important parameter set in all parameters included in the parameter selection field, and the first candidate data is a value of the first parameter corresponding to the number of the first deviation range centered on the first generation optimization value of the first parameter; the first PHY chip determines the second generation optimization value of the first parameter according to the first candidate data and the third quality information corresponding to the first candidate data; the first PHY chip obtains second candidate data of the second parameter according to the first generation optimization value of the second parameter in the first parameter set and a second deviation range of the second parameter, the second candidate data is a value of the second parameter corresponding to the number of the second deviation range centered on the first generation optimization value of the second parameter; and the first PHY chip determines the second generation optimization value of the second parameter according to the second generation optimization value of the first parameter, the second candidate data, and the fourth quality information corresponding to the second candidate data. In this way, by scanning each parameter in the first parameter set one by one, the further optimization value of each parameter is determined, and the final optimization result of the equalization parameter is quickly obtained through less scanning. In the process of scanning each parameter in the important parameter set, the scanning order can be determined based on the importance of each parameter in the first parameter set or other sorting strategies.

[0172] In the process of the second generation tuning of the first parameter, the first candidate data can be determined according to the first generation tuning value of the first parameter and the first deviation range. Taking the first generation tuning value of pre1 of TX-FFE as -15 for example, if the first deviation value is 1, then the number of the first candidate data can be 3 (the value of -15 itself and the values of the first deviation value before and after it), if the value interval of pre1 is 1, then the first candidate data can include -16, -15 and -14; if the value interval of pre1 is 2, then the first candidate data can include -17, -15 and -13; if the first deviation value is 2, then the number of the first candidate data can be 5 (the value of -15 itself and the values of the first deviation value before and after it), if the value interval of pre1 is 1, then the first candidate data can include -17, -16, -15, -14 and -13; if the value interval of pre1 is 2, then the first candidate data can include -19, -17, -15, -13 and -11. Similarly, the second candidate data can be determined according to the first generation tuning value of the second parameter and the second deviation range. It should be noted that the first deviation range and the second deviation range can be flexibly set according to the protocol or actual needs, which can be the same or different. Moreover, the deviation range of the parameter can be a preset value, or a value obtained by simply adjusting the preset value based on the quality information.

[0173] For "the first PHY chip determines the second generation tuning value of the first parameter according to the first candidate data and the third quality information corresponding to the first candidate data", for example, it can include: when the value of each parameter in the second parameter set is the default value and the value of the second parameter is the first generation tuning value, the value of the first parameter is set to each first candidate data respectively, the third quality information of the electrical signal in the PHY chip corresponding to each first candidate data is obtained, and the first candidate data corresponding to the best quality in the third quality information is determined as the second generation tuning value of the first parameter. For example, the first parameter is pre1 of TX-FFE, and the first candidate data is -16, -15 and -14 respectively. Then, the third quality information of the electrical signal in the PHY chip corresponding to the first candidate data -16, -15 and -14 can be obtained respectively, and the first candidate data corresponding to the best quality in the three third quality signals is selected as the second generation tuning value of pre1, such as -14. For the implementation mode of "the first PHY chip determines the second generation tuning value of the second parameter according to the second generation tuning value of the first parameter, the second candidate data and the fourth quality information corresponding to the second candidate data", please refer to the implementation mode of "the first PHY chip determines the second generation tuning value of the first parameter according to the first candidate data and the third quality information corresponding to the first candidate data". For example, assuming that the second parameter is post1 of TX-FFE, the second candidate data is -4, -3, -2, -1 and 0 respectively, the first parameter is pre1 of TX-FFE, and the pre1 is configured as the second generation tuning value -14 of pre1. Then, the fourth quality information of the electrical signal in the PHY chip corresponding to the second candidate data -4, -3, -2, -1 and 0 can be obtained respectively, and the second candidate data corresponding to the best quality in the five fourth quality signals is selected as the second generation tuning value of post1, such as -1.

[0174] It can be seen that the second generation tuning value of each parameter in the first parameter set is obtained through the above steps. At this time, it can be judged whether the tuning stop condition is met. If it is met, the tuning result (i.e. the target tuning value) is determined based on the second generation tuning value of each parameter in the first parameter set, and the equalizer is configured based on the tuning result. If the tuning stop condition is not met, more generations of tuning can be continued for each parameter in the first parameter set, and the implementation mode of each subsequent generation of tuning is the same as that of the second generation of tuning. In this way, the tuning stop condition is met after a certain generation of tuning value of the first parameter set is obtained.

[0175] The tuning stop condition can include at least one of the following conditions: condition one, the tuning generation number is equal to a preset number; condition two, the difference between the quality of the electrical signal corresponding to the current generation of tuning and the quality of the electrical signal corresponding to the previous generation of tuning is less than a preset threshold; and condition three, the tuning value corresponding to the current generation of tuning is equal to the tuning value obtained in the previous generation of tuning.

[0176] When the tuning stop condition includes only one of the above conditions, the tuning stop condition is considered to be met only when the condition is met, for example, the tuning stop condition is that the tuning generation number is equal to 5, then when the fifth generation tuning value of each parameter in the first parameter set is obtained, the tuning stop condition is considered to be met; for another example, the tuning stop condition is that the difference between the quality of the electrical signal corresponding to the current generation tuning and the quality of the electrical signal corresponding to the previous generation tuning is less than 1, then when the fifth generation tuning value of each parameter in the first parameter set is obtained, and the difference between the quality of the electrical signal corresponding to the fourth generation tuning value and the quality of the electrical signal corresponding to the third generation tuning value is less than 1, the fourth generation tuning value of each parameter in the first parameter set is considered to meet the tuning stop condition; for another example, the tuning stop condition is that the tuning value corresponding to the current generation tuning is equal to the tuning value obtained in the previous generation tuning of the corresponding parameter, then when the sixth generation tuning value of each parameter in the first parameter set is obtained and the sixth generation tuning value of each parameter in the first parameter set or the fifth generation tuning value of each parameter in the first parameter set is considered to meet the tuning stop condition.

[0177] When the tuning stop condition includes at least two of the above conditions, the tuning stop condition is considered to be met only when each condition included in the tuning stop condition is met, for example, the tuning stop condition includes that the tuning generation number is equal to 5 and the difference between the quality of the electrical signal corresponding to the current generation tuning and the quality of the electrical signal corresponding to the previous generation tuning is less than 1, then starting from the fifth generation tuning, attention is paid to the current generation tuning value of each parameter in the first parameter set obtained in each generation tuning, the difference between the quality of the electrical signal corresponding to the current generation tuning value and the quality of the electrical signal corresponding to the previous generation tuning value is calculated, and it is judged whether the difference is less than the difference threshold (such as 1), if it is met, the current generation tuning value of each parameter in the first parameter set is considered to meet the tuning stop condition.

[0178] In order to make the evolutionary optimization in the first case more clear, the following is an exemplary brief description.

[0179] Suppose that the equalization parameters to be configured in the communication system include: a, b, c, d, e, f, g, h, i and j, a total of 10, according to the influence of each parameter on the equalization performance in the communication system, the 10 parameters are divided into an important parameter set and a non-important parameter set, wherein the important parameter set includes: a, b, f, g and i, and the non-important parameter set includes: c, d, e, h and j. Through the whole set configuration of the method 100, the first generation tuning value of each parameter is obtained, which can be represented by opt_1, for example, the first generation tuning value of a can be represented as a opt_1Suppose that the order of performing the subsequent generation tuning according to the importance for the parameters in the important parameter set is: a, b, f, g and i. Then, in the independent configuration, the evolution optimization process of the 10 parameters can include:

[0180] S21, second generation tuning is performed on a to obtain a second generation tuning value a of a opt_2 .

[0181] S22, second generation tuning is performed on b to obtain a second generation tuning value b of b opt_2 .

[0182] S23, second generation tuning is performed on f to obtain a second generation tuning value f of f opt_2 .

[0183] S24, second generation tuning is performed on g to obtain a second generation tuning value g of g opt_2 .

[0184] S25, second generation tuning is performed on i to obtain a second generation tuning value i of i opt_2 .

[0185] S26, it is judged whether the tuning stop condition is met. If the tuning stop condition is met, S27 is executed, otherwise, k=k+1, the k-th generation tuning shown in S28-S32 is executed (k is initially 2) and S26 is returned to be executed.

[0186] When it is determined that the tuning stop condition is not met after S26, k=3, and the third generation tuning of each parameter in the important parameter set is executed according to S28-S32. When the third generation tuning is completed, it is determined that the tuning stop condition is still not met, k=4, and the fourth generation tuning of each parameter in the important parameter set is executed according to S28-S32. Similarly, the process is repeated.

[0187] S27, the tuning result is obtained based on the current generation tuning value of each parameter in the important parameter set, and the equalizer of the communication system is configured based on the tuning result.

[0188] S28, k-th generation tuning is performed on a to obtain a k-th generation tuning value a of a opt_k .

[0189] S29, k-th generation tuning is performed on b to obtain a k-th generation tuning value b of b opt_k .

[0190] S30, k-th generation tuning is performed on f to obtain a k-th generation tuning value f of f opt_k .

[0191] S31, k-th generation tuning is performed on g to obtain a k-th generation tuning value g of g opt_k .

[0192] S32, the kth generation of i is optimized to obtain the kth generation of i optimized value i opt_k .

[0193] It can be seen that, after the whole set of configurations, the parameters in the important parameter set are optimized for at least one generation, and the effect of quickly converging to the global optimum of the multiple balanced parameters to be configured with the coupling relationship can be achieved by fewer scanning times, and the optimization efficiency of the balanced parameters is improved.

[0194] For the second case, taking the third parameter as an example, the second parameter set includes the third parameter, and the target optimization value is determined by the first PHY chip according to the first generation of optimization value, and the process of one-time independent configuration may include: after the first PHY chip determines the second generation of optimization value of each parameter in the first parameter set, the first PHY chip can also obtain the third candidate data of the third parameter according to the first generation of optimization value of the third parameter and the third deviation range of the third parameter. The third candidate data is the value of the third parameter centered on the first generation of optimization value of the third parameter, and the number corresponds to the third deviation range; then, the first PHY chip determines the second generation of optimization value of the third parameter according to the second generation of optimization value of each parameter in the first parameter set, the third candidate data and the fifth quality information corresponding to the third candidate data. In this way, by determining the further optimization value of each parameter in the first parameter set through the scanning of each parameter, and determining the further optimization value of each parameter in the second parameter set through the scanning of each parameter, the final optimization result of the balanced parameter is quickly obtained through fewer scans. Wherein, in the process of scanning each parameter in the non-important parameter, the scanning order can be determined based on the importance of each parameter in the second parameter set or other sorting strategies.

[0195] It can be seen that, by the above steps, the second generation of optimization value of each parameter in the first parameter set and the second parameter set is obtained, at this time, it can be judged whether the optimization stop condition is met, if it is met, the optimization result (i.e. the target optimization value) is determined based on the second generation of optimization value of each parameter in the first parameter set and the second parameter set, and the equalizer is configured based on the optimization result. For example, if it is determined that the sixth quality information corresponding to the second generation of optimization value of each parameter in the first parameter set and the second parameter set meets the optimization stop condition, the second generation of optimization value is determined as the target optimization value; if the optimization stop condition is not met, more generations of optimization can be continued for each parameter in the first parameter set, and after each generation of optimization or a preset interval of generations of optimization, the optimization of each parameter in the second parameter set is performed, and so on, until the optimization stop condition is met after the certain generation of optimization value of the first parameter set and the second parameter set is obtained.

[0196] In order to make the evolution optimization in the second case more clear, the following is an exemplary brief description.

[0197] Assume that the equalization parameters to be configured in the communication system include: a, b, c, d, e, f, g, h, i and j, a total of 10, according to the influence of each parameter on the equalization performance in the communication system, the 10 parameters are divided into an important parameter set and a non-important parameter set, wherein the important parameter set includes: a, b, f, g and i, and the non-important parameter set includes: c, d, e, h and j. Through the whole set configuration of the method 100, the first generation of tuning values of each parameter is obtained, which can be represented by opt_1, for example, the first generation of tuning values of a can be represented as a opt_1 . Assume that for the parameters in the important parameter set, the order of performing subsequent generations of tuning according to importance is: a, b, f, g and i; for the parameters in the non-important parameter set, the order of performing subsequent generations of tuning according to importance is: c, d, e, h and j. Then, in the independent configuration, the evolution optimization process of the 10 parameters can include:

[0198] S41, the second generation of tuning is performed on a to obtain the second generation of tuning value a opt_2 .

[0199] S42, the second generation of tuning is performed on b to obtain the second generation of tuning value b opt_2 .

[0200] S43, the second generation of tuning is performed on f to obtain the second generation of tuning value f opt_2 .

[0201] S44, the second generation of tuning is performed on g to obtain the second generation of tuning value g opt_2 .

[0202] S45, the second generation of tuning is performed on i to obtain the second generation of tuning value i opt_2 .

[0203] S46, the second generation of tuning is performed on c to obtain the second generation of tuning value c opt_2 .

[0204] S47, the second generation of tuning is performed on d to obtain the second generation of tuning value d opt_2 .

[0205] S48, the second generation of tuning is performed on e to obtain the second generation of tuning value e opt_2 .

[0206] S49, the second generation of tuning is performed on h to obtain the second generation of tuning value h opt_2 .

[0207] S50, the second generation of tuning is performed on j to obtain the second generation of tuning value j opt_2 .

[0208] S51, it is judged whether the optimization stop condition is satisfied, if yes, S52 is executed, otherwise, k=k+1, the kth generation optimization shown in S53-S62 is executed, and S51 is returned.

[0209] When S51 is determined not to satisfy the optimization stop condition, k=3, the third generation optimization of each parameter is executed in S53-S62; when the third generation optimization is completed, it is determined that the optimization stop condition is still not satisfied, k=4, the fourth generation optimization of each parameter is executed in S53-S62, and so on.

[0210] S52, the optimization result is obtained based on the current generation optimization value of each parameter in the non-important parameter set and the current generation optimization value of each parameter in the important parameter set, and the equalizer of the communication system is configured based on the optimization result.

[0211] S53, the kth generation optimization of a is performed to obtain the kth generation optimization value a opt_k .

[0212] S54, the kth generation optimization of b is performed to obtain the kth generation optimization value b opt_k .

[0213] S55, the kth generation optimization of f is performed to obtain the kth generation optimization value f opt_k .

[0214] S56, the kth generation optimization of g is performed to obtain the kth generation optimization value g opt_k .

[0215] S57, the kth generation optimization of i is performed to obtain the kth generation optimization value i opt_k .

[0216] S58, the kth generation optimization of c is performed to obtain the kth generation optimization value c opt_k .

[0217] S59, the kth generation optimization of d is performed to obtain the kth generation optimization value d opt_k .

[0218] S60, the kth generation optimization of e is performed to obtain the kth generation optimization value e opt_k .

[0219] S61, the kth generation optimization of h is performed to obtain the kth generation optimization value h opt_k .

[0220] S62, the kth generation optimization of j is performed to obtain the kth generation optimization value j opt_k .

[0221] It can be seen that, after the whole set of configurations, at least one generation of one-by-one optimization is performed on the important parameter set and the parameters in the non-important parameter, which can realize fast convergence to the global optimum through fewer scanning times for the multiple balanced parameters to be configured with coupling relationship, and improve the optimization efficiency of the balanced parameters.

[0222] It should be noted that in the evolutionary optimization, the deviation range of the same parameter in different generations of optimization process can be the same or different, and can be flexibly set according to requirements or experience.

[0223] As another example, the first PHY chip can adopt a full-quantity traversal scanning manner to determine the target optimization value according to the first generation of optimization values. For example, based on the importance of the parameters, the parameters can be scanned in full quantity from important parameters to non-important parameters until the target optimization value meeting the optimization stop condition is obtained. It should be noted that in this example, it can not be necessary to scan all parameters, for example, through scanning of part of the important parameters, the link quality of the link can meet the optimization stop condition. The optimization stop condition can refer to the description in the previous example.

[0224] As another example, the first PHY chip can adopt a preset algorithm to determine the target optimization value according to the first generation of optimization values. The preset algorithm can include any one of the following algorithms: genetic algorithm, neural network algorithm or particle swarm algorithm. For example, the first generation of optimization values are input into the genetic algorithm, neural network algorithm or particle swarm algorithm, and the corresponding algorithm outputs the target optimization value. These algorithms can be models trained by a large amount of training data, and the training data can refer to multiple groups of data including the first generation of optimization values and the target optimization values.

[0225] It can be seen that, in the method 100, by performing whole set configuration on the balanced parameters to be configured and then performing independent configuration, compared with the full-quantity traversal scanning manner of configuring each balanced parameter to be configured one by one, the problem of low efficiency and high resource consumption in independent configuration of gradually increasing balanced parameters to be configured is solved, and the joint optimization of all balanced parameters to be configured can be determined through a small number of whole configurations, so that the balanced performance of the communication system is better, and thus, based on the set of configuration values, the evolutionary optimization and other manners of independent configuration can be used to more quickly and accurately locate the optimization result of the communication system.

[0226] For the scenario shown in FIG. 3, the link training process of the link from the first PHY chip to the second PHY chip can refer to FIG. 5. FIG. 5 is a flow diagram of a method 200 for configuring a complete set of equalization parameters, which is introduced by the interaction between the first PHY chip and the second PHY chip. The first PHY chip can be the PHY chip 1 of the network device 1 or the PHY chip 2 of the network device 2 shown in FIG. 3. The steps of the method 200 implemented by the first PHY chip can be implemented by the Firmware or the mainboard control software in the first PHY chip. The steps of the method 200 implemented by the second PHY chip can be implemented by the Firmware or the mainboard control software in the second PHY chip. As shown in FIG. 5, the method 200 can include the following steps, for example:

[0227] S201. The second PHY chip sends a first training frame to the first PHY chip, and the first training frame can include complete set configuration information indicating that all parameters included in the parameter selection field are configured.

[0228] S202. The first PHY chip receives the first training frame sent by the second PHY chip.

[0229] S203. The first PHY chip obtains a first set of configuration values corresponding to all parameters included in the parameter selection field according to the complete set configuration information.

[0230] S204. The first PHY chip configures the first configuration values to the corresponding parameters.

[0231] S205. The first PHY chip sends a second training frame to the second PHY chip, and the second training frame is generated by the first PHY chip after configuring the first set of configuration values to the parameters corresponding to the parameter selection field based on the complete set configuration information.

[0232] S206. The second PHY chip receives the second training frame sent by the first PHY chip.

[0233] S207. The second PHY chip tests the link performance of the link from the first PHY chip to the second PHY chip based on the second training frame, and obtains first quality information.

[0234] Then, the second PHY chip can determine adjustment information based on the first quality information, the adjustment information being used to indicate the second configuration value. The second PHY chip sends the adjustment information to the first PHY chip. The first PHY chip determines the second configuration value based on the adjustment information, and configures the second configuration value to the corresponding parameter. After the quality information corresponding to any one set of configuration values satisfies the target condition, the second PHY chip sends a third training frame to the first PHY chip, the third training frame including independent configuration information, indicating entering the stage of independent configuration.

[0235] Compared with the current state machine, the embodiment of the application adds a state machine branch of a set of configurations, as shown in FIG. 6. In the state machine branch of the set of configurations:

[0236] When the state machine of the first PHY chip is in a new index state (NEW_INDEX), in response to satisfying the following condition, the state machine of the first PHY chip jumps from the NEW_INDEX to a new group (NEW_GROUP) state: the initial condition request field in the control field of the first training frame indicates individual parameter control, and the format selection field is the first value, that is, ic_req = ind_ctl * format_sel = 1 in FIG. 6; or the initial condition request field in the control field of the first training frame indicates set of parameter control, that is, ic_req = group_ctl in FIG. 6.

[0237] When the state machine of the first PHY chip jumps from the NEW_GROUP state to a new request (NEW_REQUEST) state, or the state machine of the first PHY chip jumps from a waiting (WAIT) state to the NEW_REQUEST state: the initial condition request field in the control field of the first training frame indicates individual parameter control, the format selection field is the first value, and the parameter request field does not indicate holding, that is, ic_req = ind_ctl * format_sel = 1 * coef_req ≠ hold in FIG. 6; or the initial condition request field in the control field of the first training frame indicates set of parameter control, and the parameter request field does not indicate holding, that is, ic_req = group_ctl * coef_req ≠ hold in FIG. 6.

[0238] When the state machine of the first PHY chip is in the NEW_REQUEST state, in response to satisfying the following condition, the state machine of the first PHY chip jumps from the NEW_REQUEST state to the WAIT state: the parameter request field in the control field of the first training frame indicates holding, that is, coef_req = hold in FIG. 6.

[0239] When the state machine of the first PHY chip is in the WAIT state, the state machine of the first PHY chip jumps from the WAIT state to the NEW_INDEX state in response to the following conditions being met: the initial condition request field in the control field of the third training frame indicates individual parameter control, and the format selection field is the second value, i.e., ic_req = ind_ctl * format_sel = 0 in FIG. 6; or the initial condition request field in the control field of the first training frame indicates individual parameter control, i.e., ic_req = ind_ctl in FIG. 6.

[0240] In this way, by the method 200, the communication system can be configured as a whole, a better configuration basis of link performance is provided for the configuration process of the equalization parameters, and fast and accurate configuration of the equalization parameters is possible.

[0241] Compared with the equalization parameters to be configured shown in Table 1, if the number of whole-group configuration is 10 times, the independent configuration adopts the evolutionary optimization manner, the three-generation tuning meets the tuning stop condition, each equalization parameter corresponds to three candidate data for each-generation tuning, and the number of scanning can be: 10 + 6 * 3 * 3 = 64, which is much less than the corresponding scanning number in Table 1. It can be seen that the embodiment of the present application can greatly reduce the solution space of the equalization parameters in this scenario and shorten the configuration time.

[0242] FIG. 7 shows a structure schematic diagram of an LPO self-loop-back scenario to which the method provided by the embodiment of the present application is applicable. As shown in FIG. 7, the scenario may, for example, include a network device 1, an LPO 2, and a fiber loopback device 3. The network device 1 may, for example, include a PHY chip 1, and the PHY chip 1 may, for example, include a processor and a TX-FFE. Taking the case that the TX and RX in the PHY chip 1 are both 4 channels as an example, the PHY chip 1 may, for example, connect the signals output by the TX 10-TX 13 of the LPO 2 through the TX 0-TX 3 of the PHY chip 1, and may, for example, connect the signals output by the RX 10-RX 13 of the LPO 2 through the RX 0-RX 3 of the PHY chip 1. The LPO 2 may, for example, include a laser drive array 21, a laser array 22, a detector array 23, and a TIA array 24. The signals output by the TX 10-TX 13 of the LPO 2 may, for example, pass through the laser drive array 21 and the laser array 22 in sequence and be output to the TX 20-TX 23 of the LPO 2. The signals received by the RX 20-RX 23 of the LPO 2 may, for example, pass through the detector array 23 and the TIA array 24 in sequence and be output to the RX 10-RX 13 of the LPO 2. The fiber loopback device 3 may, for example, connect the TX 20-TX 23 of the LPO 2 with the RX 20-RX 23 of the LPO 2, for example, connect the TX 20 to the RX 20, connect the TX 21 to the RX 21, connect the TX 22 to the RX 22, and connect the TX 23 to the RX 23.

[0243] It should be noted that the LPO is usually equipped with a dustproof cap at the factory, and the optical fiber loopback device 3 in the embodiment of the present application can be used as an optical fiber loopback cap or other optical fiber loopback device with a dustproof cap function, and is equipped on the LPO at the factory. When the LPO is connected with the network device of the user, the configuration method of the equalization parameters provided in the embodiment of the present application can be implemented by using the optical fiber loopback device of the LPO, for example, the joint optimization of the equalization parameters of the network device and the LPO is realized by using the feedback information of the RX side of the PHY chip.

[0244] In this way, the equalization parameters of the network device 1 and the LPO 2 can be jointly optimized by using the method provided in the embodiment of the present application through the LPO self-loopback mode without relying on the opposite end device and the opposite end optical module in the communication system, which realizes the convenient, fast and accurate optimization of the equalization parameters in the communication system.

[0245] It should be noted that the method provided in the embodiment of the present application can also be applied to other high-reliability scenarios of joint configuration of multiple equalization parameters to be configured, and the applicable communication system architecture can include but is not limited to the architecture where the LPO is located and the architecture where the traditional optical module is located, and can be applied to high-speed interconnection interfaces and high-speed interface modules, wherein the high-speed interface module includes but is not limited to QSFP-DD, OSFP, COBO, CFP2, CFP8, etc., and the high-speed interconnection interface includes but is not limited to a transceiver module line card point-to-point interconnection interface, a router line card dense wavelength division multiplexing (DWDM) interconnection interface, a transceiver module line card DWDM interconnection interface, etc.

[0246] As an example, the embodiment of the present application can also be applied to the joint configuration of the tap coefficients of the multi-tap TX-FFE in the 224G and above high-speed interconnection scenarios. As shown in FIG. 8, for the 224G+SerDes high-speed interconnection scenario, the TX-FFE of the SerDes of the network device 1 is a multi-tap FFE, the SerDes of the network device 1 can be connected with the LPO, and the LPO can include the DRV_CTLE; the SerDes of the network device 1 can also be connected with the traditional optical module, and the network device 1 connected with the LPO is taken as an example in FIG. 8. The TX-FFE of the SerDes of the network device 1 is a multi-tap FFE, and the TP2 point index (such as the extinction ratio (ER) or the transmitter dispersion eye closure quaternary (TDECQ)) of the LPO or the linear direct-drive optical module can be used as the optimization basis.

[0247] Taking the FFE with 11 taps as an example, the value range of the 11 tap coefficients is shown in Table 4 below:

[0248] Table 4

[0249] The PHY chip 1 in FIG. 8 can correspond to the first PHY chip in the present disclosure, and the method provided in the embodiments of the present application is implemented to configure the 11 tap coefficients, and the specific process is not described again.

[0250] If the global traversal scanning mode is used, 7x7x9x13x16x8x13x8x7x7=4.2e9 times of scanning are required; if the method provided in the embodiments of the present application is used, assuming that the number of times of the whole group configuration is 5 times, the independent configuration uses the evolutionary optimization mode, the three generations of optimization meet the optimization cutoff condition, each equalization parameter corresponds to three candidate data in each generation of optimization, and the number of times of scanning can be: 5+10x3x3=95, and the solution space is much smaller than 4.2e9. It can be seen that the embodiments of the present application can greatly reduce the solution space of the equalization parameter configuration in this scenario and shorten the configuration time.

[0251] In order to make the method provided in the embodiments of the present application more easily understood, a possible configuration process of the equalization parameter is described below in combination with FIG. 9.

[0252] As shown in FIG. 9, this embodiment takes the link training process of the link from the first PHY chip to the second PHY chip as an example, which can include, for example:

[0253] S301, the first PHY chip and the second PHY chip send training frame 1 to each other, and complete frame locking.

[0254] S302, the second PHY chip sends training frame 2 to the first PHY chip, and the value of the initial condition request field in the control field of the training frame 2 indicates that the initialization configuration is based on preset1.

[0255] S303, the first PHY chip performs initialization configuration based on preset1 according to the indication of the training frame 2.

[0256] It should be noted that the first PHY chip can obtain a configuration table based on the detail information of the first PHY chip and the LPO connected to the first PHY chip, and the configuration table can include at least preset1 and subsequent configuration value 1 and configuration value 2. The detail information can include at least one of the following information: insertion loss of the connection interface of the first PHY chip and the LPO, type of the LPO, temperature of the LPO, manufacturer of the LPO, and number of tap coefficients of the TX-FIR in the first PHY chip.

[0257] S304, after the second PHY chip is initialized and configured, it is determined that the link quality of the link from the first PHY chip to the second PHY chip does not satisfy the target condition, and the second PHY chip sends a training frame 3 to the first PHY chip, the value of the initial condition request field of the control field in the training frame 3 indicates separate parameter control, the format selection field of the control field is the first value, indicating the whole set of configuration values; and the parameter request field in the control field of the training frame 3 indicates the next set of configuration values.

[0258] For example, the next set of configuration values of preset1 in the configuration table is configuration value 1, and the next set of configuration values of configuration value 1 is configuration value 2.

[0259] S305, the first PHY chip obtains configuration value 1 based on the training frame 3, and configures configuration value 1 to the corresponding parameters.

[0260] S306, the first PHY chip sends a training frame 4 to the second PHY chip, the state field of the training frame 4 indicates that the step of configuring configuration value 1 to the corresponding parameters is completed, and the training frame 4 includes training mode field 1.

[0261] S307, the second PHY chip performs link testing on the link from the first PHY chip to the second PHY chip based on the training mode field 1, and obtains quality information 1; the second PHY chip determines that the quality information 1 does not satisfy the target condition, generates a training frame 5 based on the quality information 1, the value of the initial condition request field of the control field in the training frame 5 indicates separate parameter control, the format selection field of the control field is the first value, indicating the whole set of configuration values; and the parameter request field in the control field of the training frame 5 indicates the next set of configuration values.

[0262] S308, the second PHY chip sends a training frame 5 to the first PHY chip, the value of the initial condition request field of the control field in the training frame 5 indicates separate parameter control, the format selection field of the control field is the first value, indicating the whole set of configuration values; and the parameter request field in the control field of the training frame 5 indicates the next set of configuration values.

[0263] S309, the first PHY chip obtains configuration value 2 based on the training frame 5, and configures configuration value 2 to the corresponding parameters.

[0264] S310, the first PHY chip sends a training frame 6 to the second PHY chip, the state field of the training frame 6 indicates that the step of configuring configuration value 2 to the corresponding parameters is completed, and the training frame 6 includes training mode field 2.

[0265] S311, the second PHY chip performs link test on the link from the first PHY chip to the second PHY chip based on the training mode field 2 to obtain quality information 2; the second PHY chip determines that the quality information 2 meets a target condition, generates a training frame 7 based on the quality information 2, and sends the training frame 7 to the first PHY chip, wherein a value of an initial condition request field in a control field in the training frame 7 indicates separate parameter control, a format selection field in the control field is the second value, indicating independent configuration, and a parameter selection field in the control field in the training frame 7 indicates a specific parameter 1 configured.

[0266] S312, the first PHY chip performs evolutionary optimization 1 on each parameter 1 to be configured based on the training frame 7 to obtain a configuration value 3 of the parameter 1, and configures the configuration value 3 to the parameter 1.

[0267] The evolutionary optimization of each parameter 1 can refer to the related description of the method 100. The evolutionary optimization 1 and the evolutionary optimization 2 can respectively indicate a generation of optimization process. The parameter 1 is a general indication of the equalization parameter to be configured, and the evolutionary optimization 1 of each parameter 1 means that a generation of evolutionary optimization is performed on each equalization parameter to be configured, and the specific generation of evolutionary optimization is evolutionary optimization 1.

[0268] S313, the first PHY chip sends a training frame 8 to the second PHY chip, a state field in the training frame 8 indicates that the step of configuring the configuration value 3 to the corresponding parameter 1 is completed, and the training frame 8 includes a training mode field 3.

[0269] S314, the second PHY chip performs link test on the link from the first PHY chip to the second PHY chip based on the training mode field 3 to obtain quality information 3; the second PHY chip determines that the quality information 3 does not meet an optimization cutoff condition, generates a training frame 9 based on the quality information 3, and sends the training frame 9 to the first PHY chip, wherein a value of an initial condition request field in a control field in the training frame 9 indicates separate parameter control, a format selection field in the control field is the second value, indicating independent configuration, and a parameter selection field in the control field in the training frame 9 indicates a specific parameter 1 configured.

[0270] S315, the first PHY chip performs evolutionary optimization 2 on each parameter 1 to be configured based on the training frame 9 to obtain a configuration value 4 of the parameter 1, and configures the configuration value 4 to the parameter 1.

[0271] S316, the first PHY chip sends a training frame 10 to the second PHY chip, a state field in the training frame 10 indicates that the step of configuring the configuration value 4 to the corresponding parameter 1 is completed, and the training frame 10 includes a training mode field 4.

[0272] S317, the second PHY chip performs link test on the link from the first PHY chip to the second PHY chip based on the training mode field 4 to obtain quality information 4; and the second PHY chip determines that the quality information 4 meets the tuning cutoff condition, and considers that the tuning of the link from the first PHY chip to the second PHY chip is completed.

[0273] It can be seen that, through the above S301-S317, the two generations of tuning in the whole set of configuration and evolution optimization mode of the two sets of configuration values obtains the final result of tuning and configuration. For the demand of joint tuning of multiple coupled equalization parameters, the configuration of the equalization parameters is realized quickly and accurately.

[0274] Correspondingly, the embodiment of the application further provides a chip 1000, as shown in FIG. 10. The chip 1000 can include an interface circuit 1001 and a processing circuit 1002.

[0275] If the chip 1000 corresponds to the first PHY chip, the functions of each structure in the chip 1000 are as follows:

[0276] The interface circuit 1001 is configured to obtain the whole set of configuration information, and the whole set of configuration information indicates that all parameters included in the parameter selection field are configured. The function of the interface circuit 1001 can correspond to S101 in FIG. 4.

[0277] The processing circuit 1002 is configured to obtain a first set of configuration values corresponding to all parameters included in the parameter selection field according to the whole set of configuration information. The function of the processing circuit 1002 can correspond to S102 in FIG. 4.

[0278] The processing circuit 1002 is further configured to configure the first set of configuration values to the corresponding parameters. The function of the processing circuit 1002 can correspond to S103 in FIG. 4.

[0279] In some possible implementation ways, the interface circuit 1001 is specifically configured to receive the whole set of configuration information sent by the second PHY chip.

[0280] As an example, the interface circuit 1001 is specifically configured to receive the first training frame sent by the second PHY chip, and the control field of the first training frame carries the whole set of configuration information.

[0281] In some possible implementation ways, when the initial condition request field in the control field indicates separate parameter control and the format selection field is the first value, the control field indicates the whole set of configuration information, and the format selection field is any one reserved bit of the control field; or when the initial condition request field in the control field indicates whole set parameter control through any one reserved value combination, the control field indicates the whole set of configuration information.

[0282] In some possible implementation manners, when the state machine of the first PHY chip is in the new index state, the state machine of the first PHY chip jumps from the new index state to a new full set state in response to the following condition being met: the initial condition request field in the control field of the first training frame indicates individual parameter control, and the format selection field is the first value; or, the initial condition request field in the control field of the first training frame indicates full set parameter control.

[0283] In some possible implementation manners, the state machine of the first PHY chip jumps from the new full set state to a new request state, or the state machine of the first PHY chip jumps from the waiting state to the new request state in response to the following condition being met: the initial condition request field in the control field of the first training frame indicates individual parameter control, the format selection field is the first value, and the parameter request field does not indicate to keep; or, the initial condition request field in the control field of the first training frame indicates full set parameter control, and the parameter request field does not indicate to keep.

[0284] In some possible implementation manners, when the state machine of the first PHY chip is in the new request state, the state machine of the first PHY chip jumps from the new request state to the waiting state in response to the following condition being met: the parameter request field in the control field of the first training frame indicates to keep.

[0285] In some possible implementation manners, the interface circuit 1001 is further configured to, after the first configuration value is configured to the corresponding parameter, send a second training frame to the second PHY chip, the second training frame being used by the second PHY chip to test a link performance from the first PHY chip to the second PHY chip to obtain first quality information, and determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value corresponding to the second quality information, the second quality information being used to indicate that the corresponding link performance is better than the first quality information when the second configuration value is configured to the corresponding parameter; the interface circuit 1001 is further configured to receive a third training frame sent by the second PHY chip, the third training frame including the adjustment information; and the processing circuit 1002 is further configured to determine the second configuration value based on the adjustment information.

[0286] In some possible implementation manners, the interface circuit 1001 is specifically configured to: when the LPO connected to the first PHY chip is in a self-loopback state, the processor of the chip 1000 obtains full set configuration information.

[0287] In some possible implementation manners, the processing circuit 1002 is further configured to, after the first configuration value is configured to the corresponding parameter, perform RX testing on a link performance of the RX of the first PHY chip from the TX of the first PHY chip through the LPO and back to the RX of the first PHY chip, to obtain first quality information; the processing circuit 1002 is further configured to determine adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the corresponding parameter, the second quality information being better than the first quality information; and the processing circuit 1002 is further configured to determine the second configuration value based on the adjustment information.

[0288] In some possible implementation manners, the processing circuit 1002 is further configured to, after the first configuration value is configured to the corresponding parameter, configure a second configuration value to the corresponding parameter.

[0289] In some possible implementation manners, the processing circuit 1002 is further configured to obtain a configuration table according to details of the first PHY chip and the LPO connected to the first PHY chip, the configuration table including at least the first configuration value of all parameters included in the parameter selection field, the details including at least one of the following information: insertion loss of a connection interface of the first PHY chip and the LPO, type of the LPO, temperature of the LPO, manufacturer of the LPO, and number of tap coefficients of a transmitter finite-length unit impulse response TX-FIR in the first PHY chip; and the processing circuit 1002 is specifically configured to obtain the first configuration value from the configuration table according to the entire set of configuration information.

[0290] In some possible implementation manners, the interface circuit 1001 is further configured to obtain independent configuration information, the independent configuration information being used to indicate that the parameters included in the parameter selection field are configured respectively; and the processing circuit 1002 is further configured to record a current set of configuration values of the parameters included in the parameter selection field as first generation tuning values according to the independent configuration information, and determine target tuning values according to the first generation tuning values.

[0291] In some possible implementation manners, the processing circuit 1002 is specifically configured to: obtain first candidate data of a first parameter according to a first generation tuning value of the first parameter and a first deviation range of the first parameter, the first parameter belonging to a first parameter set, the first parameter set being a set of important parameters in all parameters included in the parameter selection field, the first candidate data being values of the first parameter corresponding to a quantity of the first deviation range and centered on the first generation tuning value of the first parameter; determine a second generation tuning value of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; obtain second candidate data of a second parameter according to a first generation tuning value of the second parameter and a second deviation range of the second parameter, the second candidate data being values of the second parameter corresponding to a quantity of the second deviation range and centered on the first generation tuning value of the second parameter; and determine a second generation tuning value of the second parameter according to the second generation tuning value of the first parameter, the second candidate data and fourth quality information corresponding to the second candidate data.

[0292] In some possible implementation manners, the processing circuit 1002 is further configured to group all parameters included in the parameter selection field according to influences of the all parameters on the balance performance in the communication system, to obtain a plurality of parameter sets, and to obtain the plurality of parameter sets including the first parameter set.

[0293] In some possible implementation manners, the plurality of parameter sets further include a second parameter set, the second parameter set being a set of non-important parameters in all parameters included in the parameter selection field, and the second parameter set including a third parameter. After determining the second generation tuning values of the parameters in the first parameter set, the processing circuit 1002 is further configured to obtain third candidate data of the third parameter according to a first generation tuning value of the third parameter and a third deviation range of the third parameter, the third candidate data being values of the third parameter corresponding to a quantity of the third deviation range and centered on the first generation tuning value of the third parameter; determine a second generation tuning value of the third parameter according to the second generation tuning values of the parameters in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; and determine the second generation tuning values as target tuning values if sixth quality information corresponding to the second generation tuning values of the parameters in the first parameter set and the second parameter set satisfies a tuning stop condition.

[0294] The tuning stop condition can include at least one of the following conditions: a tuning generation number is equal to a preset number of times; or a difference between quality information corresponding to a current generation tuning and quality information corresponding to a previous generation tuning is less than a preset threshold; or a tuning value corresponding to the current generation tuning is equal to a tuning value of a corresponding parameter obtained in the previous generation tuning.

[0295] In some possible implementation manners, the processing circuit 1002 is specifically configured to determine the target tuning value according to the first tuning value and a preset algorithm, and the preset algorithm includes any one of the following algorithms: a genetic algorithm, a neural network algorithm, or a particle swarm algorithm.

[0296] It should be noted that the related description of the chip 1000 can refer to the description of the related operations performed by the first PHY chip in the method 100 or the method 200.

[0297] If the chip 1000 corresponds to the second PHY chip, the functions of the structures in the chip 1000 are as follows.

[0298] The interface circuit 1001 is configured to send a first training frame to the first PHY chip, and the first training frame includes a complete set of configuration information, and the complete set of configuration information indicates to configure all parameters included in the parameter selection field. The function of the interface circuit 1001 can correspond to S201 in FIG. 5.

[0299] The interface circuit 1001 is further configured to receive a second training frame sent by the first PHY chip, and the second training frame is generated after the first PHY chip configures a set of first configuration values to the parameters corresponding to the parameter selection field based on the complete set of configuration information. The function of the interface circuit 1001 can correspond to S205 in FIG. 5.

[0300] The processing circuit 1002 is configured to test the link performance of the link from the first PHY chip to the second PHY chip based on the second training frame, and obtain first quality information. The function of the processing circuit 1002 can correspond to S207 in FIG. 5.

[0301] In some possible implementation manners, the interface circuit 1001 is further configured to, after obtaining the first quality information, if it is determined that the first quality information satisfies a target condition, send a third training frame to the first PHY chip, and the control field of the third training frame indicates to carry independent configuration information, and the independent configuration information indicates to configure the parameters included in the parameter selection field respectively.

[0302] As an example, when the initial condition request field in the control field indicates separate parameter control, and the format selection field is the second value, the control field indicates independent configuration information, and the format selection field is any one of the reserved bits of the control field; or when the initial condition request field in the control field indicates separate parameter control, the control field indicates separate configuration information.

[0303] In some possible implementation manners, when the state machine of the first PHY chip is in the waiting state, the state machine of the first PHY chip jumps from the waiting state to the new index state in response to the following conditions being met: the initial condition request field in the control field of the third training frame indicates separate parameter control, and the format selection field is the second value; or, the initial condition request field in the control field of the third training frame indicates separate parameter control.

[0304] In some possible implementation manners, the processing circuit 1002 is further configured to, after obtaining the first quality information, determine adjustment information according to the first quality information if it is determined that the first quality information does not satisfy the target condition, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the parameter corresponding to the parameter selection field, and the second quality information being better than the first quality information; the interface circuit 1001 is further configured to send, to the first PHY chip, a fourth training frame including the adjustment information; the interface circuit 1001 is further configured to receive a fifth training frame sent by the first PHY chip, the fifth training frame being generated after the first PHY chip configures the second configuration value to the parameter corresponding to the parameter selection field; and the processing circuit 1002 is further configured to test the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtain the second quality information.

[0305] The target condition can include any one of the following conditions: the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field satisfies a preset quality threshold; or the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table.

[0306] It should be noted that the related description of the chip 1000 can refer to the description of the related operations performed by the second PHY chip in the method 200.

[0307] Correspondingly, the embodiment of the present application further provides a communication device 1100, as shown in FIG. 11, the device 1100 is applied to a first PHY chip, and the device 1100 can include an acquisition unit 1101 and a processing unit 1102. The acquisition unit 1101 can correspond to the interface circuit 1001 in the chip 1000 or the interface 1301 in the communication device 1300 described below; and the processing unit 1102 can correspond to the processing circuit 1002 in the chip 1000 or the processor 1302 in the communication device 1300 described below.

[0308] The acquisition unit 1101 is configured to acquire a complete set of configuration information, the complete set of configuration information being used to indicate configuration of all parameters included in the parameter selection field.

[0309] The processing unit 1102 is configured to obtain a first set of configuration values corresponding to all parameters included in the parameter selection field according to the entire set of configuration information.

[0310] The processing unit 1102 is further configured to configure the first set of configuration values to corresponding parameters.

[0311] In some possible implementation manners, the obtaining unit 1101 is specifically configured to receive the entire set of configuration information sent by the second PHY chip.

[0312] As an example, the obtaining unit 1101 is specifically configured to receive the first training frame sent by the second PHY chip, and the control field of the first training frame carries the entire set of configuration information.

[0313] In some possible implementation manners, when the initial condition request field in the control field indicates separate parameter control and the format selection field is the first value, the control field indicates the entire set of configuration information, and the format selection field is any one reserved bit of the control field; or, when the initial condition request field in the control field indicates the entire set of parameter control by any one reserved value combination, the control field indicates the entire set of configuration information.

[0314] In some possible implementation manners, when the state machine of the first PHY chip is in the new index state, in response to the following condition being met, the state machine of the first PHY chip jumps from the new index state to the new entire set state: the initial condition request field in the control field of the first training frame indicates separate parameter control, and the format selection field is the first value; or, the initial condition request field in the control field of the first training frame indicates the entire set of parameter control.

[0315] In some possible implementation manners, in response to the following condition being met, the state machine of the first PHY chip jumps from the new entire set state to the new request state, or the state machine of the first PHY chip jumps from the waiting state to the new request state: the initial condition request field in the control field of the first training frame indicates separate parameter control, the format selection field is the first value, and the parameter request field does not indicate to keep; or, the initial condition request field in the control field of the first training frame indicates the entire set of parameter control, and the parameter request field does not indicate to keep.

[0316] In some possible implementation manners, when the state machine of the first PHY chip is in the new request state, in response to the following condition being met, the state machine of the first PHY chip jumps from the new request state to the waiting state: the parameter request field in the control field of the first training frame indicates to keep.

[0317] In some possible implementation manners, the apparatus 1100 can further include a sending unit and a receiving unit. The sending unit is configured to, after the first configuration value is configured to the corresponding parameter, send a second training frame to the second PHY chip, the second training frame being used by the second PHY chip to test a link performance from the first PHY chip to the second PHY chip to obtain first quality information, and determine adjustment information based on the first quality information, the adjustment information being used to indicate the second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate that the corresponding link performance under the condition that the second configuration value is configured to the corresponding parameter, the second quality information being better than the first quality information. The receiving unit is configured to receive a third training frame sent by the second PHY chip, the third training frame including the adjustment information. The processing unit 1102 is further configured to determine the second configuration value based on the adjustment information.

[0318] In some possible implementation manners, the obtaining unit 1101 is specifically configured to: when the LPO connected with the first PHY chip is in a self-loopback state, the processor of the first PHY chip obtains the whole set of configuration information.

[0319] As an example, the processing unit 1102 is further configured to, after the first configuration value is configured to the corresponding parameter, test a link performance of RX of the first PHY chip from TX of the first PHY chip through the LPO and then looped back to the RX of the first PHY chip, to obtain first quality information. The processing unit 1102 is further configured to determine adjustment information based on the first quality information, the adjustment information being used to indicate the second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate that the corresponding link performance under the condition that the second configuration value is configured to the corresponding parameter, the second quality information being better than the first quality information. The processing unit 1102 is further configured to determine the second configuration value based on the adjustment information.

[0320] In some possible implementation manners, the processing unit 1102 is further configured to, after the first configuration value is configured to the corresponding parameter, configure the second configuration value to the corresponding parameter.

[0321] In some possible implementation manners, the processing unit 1102 is further configured to obtain a configuration table according to detail information of the first PHY chip and the LPO connected with the first PHY chip, the configuration table including at least the first configuration value of all parameters included in the parameter selection field. The detail information includes at least one of the following information: an insertion loss of a connection interface of the first PHY chip and the LPO, a type of the LPO, a temperature of the LPO, a manufacturer of the LPO, and a number of tap coefficients of a transmitter finite impulse response (TX-FIR) in the first PHY chip. Then, the processing unit 1102 is specifically configured to obtain the first configuration value from the configuration table according to the whole set of configuration information.

[0322] In some possible implementation, the obtaining unit 1101 is further configured to obtain independent configuration information, the independent configuration information indicating that parameters included in the parameter selection field are configured respectively; and the processing unit 1102 is further configured to record a current set of configuration values of the parameters included in the parameter selection field as first generation tuning values according to the independent configuration information, and determine the target tuning values according to the first generation tuning values.

[0323] In some possible implementation, the processing unit 1102 is specifically configured to: obtain first candidate data of the first parameter according to the first generation tuning value of the first parameter and the first deviation range of the first parameter, the first parameter belonging to the first parameter set, the first parameter set being a set of important parameters in all parameters included in the parameter selection field, the first candidate data being a value of the first parameter with the first generation tuning value of the first parameter as a center and a quantity corresponding to the first deviation range; determine the second generation tuning value of the first parameter according to the first candidate data and third quality information corresponding to the first candidate data; obtain second candidate data of the second parameter according to the first generation tuning value of the second parameter in the first parameter set and a second deviation range of the second parameter, the second candidate data being a value of the second parameter with the first generation tuning value of the second parameter as a center and a quantity corresponding to the second deviation range; and determine the second generation tuning value of the second parameter according to the second generation tuning value of the first parameter, the second candidate data and fourth quality information corresponding to the second candidate data.

[0324] In some possible implementation, the processing unit 1102 is further configured to group all parameters included in the parameter selection field according to influences of the all parameters on the balance performance of the communication system, to obtain a plurality of parameter sets, and the plurality of parameter sets include the first parameter set.

[0325] In some possible implementation, the plurality of parameter sets further include a second parameter set, the second parameter set being a set of unimportant parameters in all parameters included in the parameter selection field, and the second parameter set including a third parameter. The processing unit 1102 is specifically configured to: after determining the second generation tuning values of the parameters in the first parameter set, obtain third candidate data of the third parameter according to the first generation tuning value of the third parameter and a third deviation range of the third parameter, the third candidate data being a value of the third parameter with the first generation tuning value of the third parameter as a center and a quantity corresponding to the third deviation range; determine the second generation tuning value of the third parameter according to the second generation tuning values of the parameters in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; and determine the second generation tuning values as the target tuning values if sixth quality information corresponding to the second generation tuning values of the parameters in the first parameter set and the second parameter set satisfies a tuning stop condition.

[0326] The tuning stop condition can include at least one of the following conditions: the tuning generation number is equal to a preset number; or, a difference between quality information corresponding to the current generation tuning and quality information corresponding to a previous generation tuning is less than a preset threshold; or, a tuning value corresponding to the current generation tuning is equal to a tuning value obtained by the corresponding parameter in the previous generation tuning.

[0327] In some possible implementation manners, the processing unit 1102 is specifically configured to: determine the target tuning value according to the first generation tuning value and a preset algorithm, the preset algorithm including any one of the following algorithms: a genetic algorithm, a neural network algorithm, or a particle swarm algorithm.

[0328] It should be noted that the related description of the communication apparatus 1100 can be referred to the description of the related operations performed by the first PHY chip in the method 100 or the method 200.

[0329] Correspondingly, the embodiment of the present application further provides a communication apparatus 1200, as shown in FIG. 12, which is applied to a second PHY chip, and the apparatus 1200 can include a sending unit 1201, a receiving unit 1202, and a processing unit 1203. The receiving unit 1202 and the sending unit 1201 can correspond to the interface circuit 1001 in the chip 1000 or the interface 1301 in the communication apparatus 1300 described below; and the processing unit 1203 can correspond to the processing circuit 1002 in the chip 1000 or the processor 1302 in the communication apparatus 1300 described below.

[0330] The sending unit 1201 is configured to send a first training frame to the first PHY chip, the first training frame including whole set configuration information, the whole set configuration information indicating configuration of all parameters included in the parameter selection field.

[0331] The receiving unit 1202 is configured to receive a second training frame sent by the first PHY chip, the second training frame being generated by the first PHY chip after configuring a set of first configuration values to the parameters corresponding to the parameter selection field based on the whole set configuration information.

[0332] The processing unit 1203 is configured to test a link performance of a link from the first PHY chip to the second PHY chip based on the second training frame, and obtain first quality information.

[0333] In some possible implementation manners, the sending unit 1201 is further configured to, after obtaining the first quality information, if it is determined that the first quality information satisfies a target condition, send a third training frame to the first PHY chip, the control field of the third training frame indicating that the independent configuration information is carried, and the independent configuration information indicating separate configuration of the parameters included in the parameter selection field.

[0334] As an example, when the initial condition request field in the control field indicates separate parameter control, and the format selection field is the second value, the control field indicates independent configuration information, and the format selection field is any one of the reserved bits of the control field; or, when the initial condition request field in the control field indicates separate parameter control, the control field indicates separate configuration information.

[0335] In some possible implementation manners, when the state machine of the first PHY chip is in the waiting state, the state machine of the first PHY chip jumps from the waiting state to the new index state in response to the following conditions being met: the initial condition request field in the control field of the third training frame indicates separate parameter control, and the format selection field is the second value; or, the initial condition request field in the control field of the third training frame indicates separate parameter control.

[0336] In some possible implementation manners, the processing unit 1203 is further configured to, after obtaining the first quality information, determine adjustment information according to the first quality information if it is determined that the first quality information does not meet the target condition, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate a corresponding link performance in a case where the second configuration value is configured to the parameter corresponding to the parameter selection field, and the second quality information being better than the first quality information; the sending unit 1201 is further configured to send, to the first PHY chip, a fourth training frame including the adjustment information; the receiving unit 1202 is further configured to receive a fifth training frame sent by the first PHY chip, the fifth training frame being generated after the first PHY chip configures the second configuration value to the parameter corresponding to the parameter selection field; and the processing unit 1203 is further configured to test the link performance of the link from the first PHY chip to the second PHY chip based on the fifth training frame, and obtain the second quality information.

[0337] The target condition can include any one of the following conditions: the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field meets a preset quality threshold; or, the quality information corresponding to the current set of configuration values on the parameter included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table.

[0338] It should be noted that the related description of the communication apparatus 1200 can be referred to the description of the related operations performed by the second PHY chip in the method 200.

[0339] Correspondingly, the embodiment of the present application further provides a communication device 1300, as shown in FIG. 13. The communication device 1300 can include an interface 1301 and a processor 1302. Wherein, the interface 1301 can correspond to the interface circuit 1001 in the chip 1000, the acquisition unit 1101 in the communication device 1100 or the sending unit 1201 and the receiving unit 1202 in the communication device 1200; the processor 1302 can correspond to the processing circuit 1002 in the chip 1000, the processing unit 1102 in the communication device 1100 or the processing unit 1203 in the communication device 1200.

[0340] The interface 1301 is configured to receive instructions and transmit to the processor 1302.

[0341] The processor 1302 is configured to execute the embodiments shown in the above method 100 or method 200.

[0342] In addition, the embodiment of the present application further provides a communication system 1400, as shown in FIG. 14. The communication system 1400 can include a first PHY chip 1401 and a second PHY chip 1402.

[0343] Wherein, the first PHY chip 1401 is configured to execute the steps performed by the first PHY chip in the embodiments of the above method 100 or method 200.

[0344] The second PHY chip 1402 is configured to execute the steps performed by the second PHY chip in the embodiments of the above method 100 or method 200.

[0345] In addition, the embodiment of the present application further provides a storage medium, which stores program codes or instructions, and when the program codes or instructions are run on a processor, the processor executes the method in any one of the implementation manners of the above embodiments.

[0346] In addition, the embodiment of the present application further provides a program product, and when the program product is run on a processor, the processor executes the method in any one of the implementation manners of the above embodiments.

[0347] It should be understood that the "determining B according to A" mentioned in the embodiments of the present application does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0348] It should be understood that the network architecture and business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It is known to those skilled in the art that with the evolution of network architecture and the appearance of new business scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0349] The ordinal numbers "1", "2", "3", "first", "second", "third" and the like in the present application are used to distinguish a plurality of objects, and are not used to limit the order of the plurality of objects.

[0350] The "A and / or B" mentioned in the present application should be understood as including the following cases: only A, only B, or both A and B.

[0351] From the description of the above embodiments, a person skilled in the art can clearly understand that all or part of the steps of the above-mentioned embodiment methods can be implemented by means of software plus a general hardware platform. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a read-only memory (English: read-only memory, ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network communication device such as a router) execute the methods described in various embodiments or some parts of the embodiments.

[0352] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for system embodiments and device embodiments, since they are basically similar to method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments. The above-described device and system embodiments are only schematic, and the modules shown as separate components can or can not be physically separated, and the components shown as modules can or can not be physical modules, i.e. they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment according to actual needs. A person of ordinary skill in the art can understand and implement it without creative labor.

[0353] The above is only the preferred embodiment of the present application, and is not used to limit the protection scope of the present application. It should be pointed out that, for those skilled in the art, without departing from the present application, a number of improvements and refinements can be made, which should also be regarded as the protection scope of the present application.

Claims

A method for configuring equalization parameters, characterized in that The method is applied to a first PHY chip, and the method comprises: obtaining a whole set of configuration information, the whole set of configuration information indicating configuration of all parameters included in a parameter selection field; obtaining a first set of configuration values corresponding to all parameters included in the parameter selection field according to the whole set of configuration information; configuring the first configuration values to corresponding parameters. The method according to claim 1, wherein the obtaining a whole set of configuration information comprises: receiving the whole set of configuration information sent by a second PHY chip. The method according to claim 2, characterized in that The receiving the whole set of configuration information sent by the second PHY chip comprises: receiving a first training frame sent by the second PHY chip, a control field of the first training frame carrying the whole set of configuration information. The method according to claim 3, wherein: when an initial condition request field in the control field indicates individual parameter control and a format selection field is a first value, the control field indicates the whole set of configuration information, and the format selection field is any one reserved bit of the control field; or, when the initial condition request field in the control field indicates whole set parameter control through any one reserved value combination, the control field indicates the whole set of configuration information. The method according to claim 4, characterized in that When a state machine of the first PHY chip is in a new index state, in response to satisfying the following condition, the state machine of the first PHY chip jumps from the new index state to a new whole set state: the initial condition request field in the control field of the first training frame indicates individual parameter control, and the format selection field is the first value; or, the initial condition request field in the control field of the first training frame indicates whole set parameter control. The method according to claim 5, characterized in that In response to satisfying the following condition, the state machine of the first PHY chip jumps from the new whole set state to a new request state, or the state machine of the first PHY chip jumps from a waiting state to a new request state: the initial condition request field in the control field of the first training frame indicates individual parameter control, the format selection field is the first value, and the parameter request field does not indicate keep; or, the initial condition request field in the control field of the first training frame indicates whole set parameter control, and the parameter request field does not indicate keep. The method according to claim 6, characterized in that When the state machine of the first PHY chip is in the new request state, in response to satisfying the following condition, the state machine of the first PHY chip jumps from the new request state to the waiting state: the parameter request field in the control field of the first training frame indicates keep. The method according to any one of claims 2-7, characterized in that After the configuring the first configuration values to corresponding parameters, the method further comprises: sending a second training frame to the second PHY chip, the second training frame being used by the second PHY chip to test link performance from the first PHY chip to the second PHY chip to obtain the first quality information, and determining adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate corresponding link performance in case that the second configuration value is configured to corresponding parameters, the second quality information being superior to the first quality information; receiving a third training frame sent by the second PHY chip, the third training frame including the adjustment information; determining the second configuration value based on the adjustment information. The method according to claim 1, wherein the obtaining the whole set of configuration information comprises: obtaining, by a processor of the first PHY chip, the whole set of configuration information when a linearly driven pluggable optical module (LPO) connected to the first PHY chip is in a self-loopback state. The method of claim 9, wherein After the first configuration value is configured to the corresponding parameters, the method further comprises: testing, by a receiver (RX) in the first PHY chip, link performance of a signal from a transmitter (TX) in the first PHY chip through the LPO and back to the RX in the first PHY chip to obtain the first quality information; determining adjustment information based on the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate corresponding link performance in case that the second configuration value is configured to corresponding parameters, the second quality information being superior to the first quality information; determining the second configuration value based on the adjustment information. The method according to claim 8 or 10, characterized in that After the first configuration value is configured to the corresponding parameters, the method further comprises: configuring the second configuration value to the corresponding parameters. The method according to any one of claims 1 to 11, characterized in that The method further comprises: obtaining a configuration table according to details of the first PHY chip and an LPO connected to the first PHY chip, the configuration table including at least the first configuration values of all parameters included in the parameter selection field, the details including at least one of the following: insertion loss of a connection interface of the first PHY chip and the LPO, type of the LPO, temperature of the LPO, manufacturer of the LPO, and number of tap coefficients of a finite impulse response (FIR) of a transmitter in the first PHY chip; The obtaining a set of first configuration values corresponding to all parameters included in the parameter selection field according to the whole set of configuration information comprises: obtaining the first configuration values from the configuration table according to the whole set of configuration information. The method according to any one of claims 1 to 12, characterized in that The method further comprises: obtaining independent configuration information, the independent configuration information being used to indicate separate configuration of parameters included in the parameter selection field; recording a current set of configuration values of the parameters included in the parameter selection field as first generation tuning values according to the independent configuration information, and determining a target tuning value according to the first generation tuning values. The method of claim 13, wherein The method further comprises: grouping all parameters included in the parameter selection field according to influences of the parameters on the equalization performance of the communication system, to obtain a plurality of parameter sets, wherein the plurality of parameter sets comprise the first parameter set. The plurality of parameter sets further comprise a second parameter set, wherein the second parameter set is a non-important parameter set among all parameters included in the parameter selection field, and the second parameter set comprises a third parameter. The method further comprises: obtaining third candidate data of the third parameter according to the first generation tuning value of the third parameter and a third deviation range of the third parameter, wherein the third candidate data is a value of the third parameter corresponding to a quantity of the third deviation range and centered on the first generation tuning value of the third parameter; The method of claim 14, wherein determining the second generation tuning value of the third parameter according to the second generation tuning value of each parameter in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; if it is determined that sixth quality information corresponding to the second generation tuning value of each parameter in the first parameter set and the second parameter set satisfies a tuning stop condition, determining the second generation tuning value as the target tuning value. The method of claim 15, wherein The tuning stop condition comprises at least one of the following conditions: a tuning generation number is equal to a preset number of times; or, a difference between quality information corresponding to a current generation tuning and quality information corresponding to a previous generation tuning is less than a preset threshold; or, a tuning value corresponding to the current generation tuning is equal to a tuning value of a corresponding parameter obtained in the previous generation tuning. The method of claim 16, wherein The method further comprises: grouping all parameters included in the parameter selection field according to influences of the parameters on the equalization performance of the communication system, to obtain a plurality of parameter sets, wherein the plurality of parameter sets comprise the first parameter set. The plurality of parameter sets further comprise a second parameter set, wherein the second parameter set is a non-important parameter set among all parameters included in the parameter selection field, and the second parameter set comprises a third parameter. The method further comprises: The method of claim 13, wherein obtaining third candidate data of the third parameter according to the first generation tuning value of the third parameter and a third deviation range of the third parameter, wherein the third candidate data is a value of the third parameter corresponding to a quantity of the third deviation range and centered on the first generation tuning value of the third parameter; determining the second generation tuning value of the third parameter according to the second generation tuning value of each parameter in the first parameter set, the third candidate data and fifth quality information corresponding to the third candidate data; if it is determined that sixth quality information corresponding to the second generation tuning value of each parameter in the first parameter set and the second parameter set satisfies a tuning stop condition, determining the second generation tuning value as the target tuning value. The tuning stop condition comprises at least one of the following conditions: a tuning generation number is equal to a preset number of times; or, a difference between quality information corresponding to a current generation tuning and quality information corresponding to a previous generation tuning is less than a preset threshold; or, a tuning value corresponding to the current generation tuning is equal to a tuning value of a corresponding parameter obtained in the previous generation tuning. The method further comprises: grouping all parameters included in the parameter selection field according to influences of the parameters on the equalization performance of the communication system, to obtain a plurality of parameter sets, wherein the plurality of parameter sets comprise the first parameter set. The target tuning value is determined according to the first generation tuning value and a preset algorithm, and the preset algorithm includes any one of the following algorithms: a genetic algorithm, a neural network algorithm, or a particle swarm algorithm. A method of configuring equalization parameters, characterized by The method is applied to a second PHY chip, and the method includes: sending a first training frame to a first PHY chip, the first training frame including a complete set of configuration information, the complete set of configuration information indicating configuration of all parameters included in a parameter selection field; receiving a second training frame sent by the first PHY chip, the second training frame being generated by the first PHY chip after a set of first configuration values are configured to parameters corresponding to the parameter selection field based on the complete set of configuration information; testing link performance of a link from the first PHY chip to the second PHY chip based on the second training frame to obtain first quality information. The method of claim 19, wherein After the first quality information is obtained, the method further includes: if it is determined that the first quality information satisfies a target condition, sending a third training frame to the first PHY chip, a control field of the third training frame indicating that independent configuration information is carried, the independent configuration information indicating separate configuration of parameters included in the parameter selection field. The method of claim 20, wherein when an initial condition request field in the control field indicates separate parameter control and a format selection field is a second value, the control field indicates the independent configuration information, and the format selection field is any one of reserved bits of the control field; or when the initial condition request field in the control field indicates the separate parameter control, the control field indicates the separate configuration information. The method of claim 21, wherein When a state machine of the first PHY chip is in a waiting state, the state machine of the first PHY chip jumps from the waiting state to a new index state in response to satisfaction of the following condition: the initial condition request field in the control field of the third training frame indicates the separate parameter control, and the format selection field is the second value; or the initial condition request field in the control field of the third training frame indicates the separate parameter control. The method of claim 19, wherein After the first quality information is obtained, the method further includes: if it is determined that the first quality information does not satisfy a target condition, determining adjustment information according to the first quality information, the adjustment information being used to indicate a second configuration value, the second configuration value corresponding to second quality information, the second quality information being used to indicate corresponding link performance in a case where the second configuration value is configured to parameters corresponding to the parameter selection field, and the second quality information being better than the first quality information; sending a fourth training frame to the first PHY chip, the fourth training frame including the adjustment information; receiving a fifth training frame sent by the first PHY chip, the fifth training frame being generated by the first PHY chip after the second configuration value is configured to the parameters corresponding to the parameter selection field; testing link performance of a link from the first PHY chip to the second PHY chip based on the fifth training frame to obtain the second quality information. The method according to any one of claims 20-23, characterized in that The target condition comprises any one of the following conditions: The quality information corresponding to the current set of configuration values of the parameters included in the parameter selection field satisfies a preset quality threshold; Or, the quality information corresponding to the current set of configuration values of the parameters included in the parameter selection field is better than the quality information corresponding to other sets of configuration values in the configuration table. A communication device, characterized by The communication device comprises an interface and a processor; The interface is configured to receive an instruction and transmit the instruction to the processor; The processor is configured to execute the method according to any one of claims 1-24. A chip characterized by The communication device comprises an interface circuit and a processing circuit; The interface circuit is configured to execute the receiving operation and the sending operation in the method according to any one of claims 1-24; The processing circuit is configured to execute other operations in the method according to any one of claims 1-24, except the receiving operation and the sending operation. A communication system characterized by The communication system comprises a first PHY chip and a second PHY chip; The first PHY chip is configured to execute the method according to any one of claims 1-18; The second PHY chip is configured to execute the method according to any one of claims 19-24.

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