Data processing method, device, and system

Abstract

Disclosed in embodiments of the present application is a data processing method, which can be applied to a concatenated FEC scheme under a high-speed transmission scenario such as 200G, 400G, and 800G. The scheme comprises: performing p:q symbol demultiplexing and alignment marker locking on p first data streams having undergone Reed-Solomon (RS) encoding, so as to obtain a symbol pair boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q=8×p; and on the basis of the obtained symbol pair boundary, performing second data processing, comprising inner code encoding and modulation, on the p first data streams, so as to obtain p modulated data streams. In the present scheme, before inner code encoding, a symbol pair boundary is provided, improving the error correction performance of a concatenated FEC scheme.

Description

A data processing method, device and system

[0001] The present application claims priority to the Chinese patent application No. 202410658716.4, filed on May 24, 2024, and entitled "A data processing method, device and system", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, in particular to a data processing method, device and system. BACKGROUND

[0003] Under the continuous promotion of 5G, cloud computing, big data, artificial intelligence and other technologies, high-speed optical transmission networks are developing towards large capacity, packetization and intelligentization. Optical communication systems use the amplitude, phase, polarization or frequency of light waves to carry information, and use forward error correction (FEC) coding to perform error correction coding on the transmitted data, which can solve transmission errors and the receiving end can recover the original data sent by the sending end from the received data. A cascaded FEC transmission scheme is currently proposed, in which a sending device and a sending processing module are connected through a connection unit interface. The sending device performs first FEC encoding on the data to be transmitted, and sends the first FEC encoded data to the sending processing module. The sending processing module performs second FEC encoding on the first FEC encoded data, and generates a corresponding modulation symbol sequence by modulation mapping of the second FEC encoded bit sequence, and finally generates an optical signal according to the modulation symbol sequence and transmits it to the receiving end through an optical fiber. The first FEC encoding is also called outer code encoding, and the second FEC encoding is also called inner code encoding. The modulation mapping is also called symbol mapping.

[0004] Generally, the sending processing module also performs interleaving before the second FEC encoding to disrupt the data order, thereby enhancing the error correction performance of the cascaded FEC scheme. For the first FEC encoded data received by the sending processing module, the symbol boundary of the first FEC encoding in the received data needs to be obtained, and the interleaving can be processed based on multiple symbols of the first FEC encoding as granularity, so that the cascaded FEC scheme has good error correction performance.

[0005] In the prior art, for 200GBASE-R inner code encoding, the client sublayer is 200GBASE-R 1:1 SM-PMA (symbol-multiplexing, SM) based physical media attachment (PMA), and the PMA layer (also referred to as 200GBASE-R 1:1 SM-PMA) does not provide a symbol boundary. Similarly, for 400GBASE-R inner code encoding and its client sublayer is 400GBASE-R 2:2 SM-PMA, for 800GBASE-R inner code encoding and its client sublayer is 800GBASE-R 4:4 SM-PMA, the PMA layer does not provide a symbol boundary. The PMA layer does not provide a symbol boundary, which affects the error correction performance of the overall concatenated FEC scheme, and is a problem that needs to be solved. SUMMARY

[0006] Embodiments of the present application provide a data processing method, device and system, so that the outer code symbol boundary can be obtained before inner code encoding, to realize better concatenated FEC error correction performance, and can be applied to more transmission scenarios.

[0007] In a first aspect, embodiments of the present application provide a data processing method, comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data stream subjected to Reed-Solomon RS encoding, to obtain a symbol pair boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8xp; performing data processing including inner code encoding and modulation on the p pieces of first data stream according to the obtained symbol pair boundary, to obtain p pieces of modulated data stream.

[0008] In a second aspect, embodiments of the present application provide another data processing method, comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data stream subjected to Reed-Solomon RS encoding, to obtain a symbol pair boundary and q pieces of second data stream, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8xp; performing q:p symbol multiplexing on the q pieces of second data stream, to obtain p pieces of third data stream; performing data processing including inner code encoding and modulation on the p pieces of third data stream according to the obtained symbol pair boundary, to obtain p pieces of modulated data stream.

[0009] In the above embodiments of the present application, the symbol pair boundary is obtained before inner code encoding, and the symbol pair boundary is used to ensure that the information bits in the inner code encoding contain an integer number of RS symbols, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0010] In a first possible implementation manner of the above aspect, the p:q symbol demultiplexing and alignment identification locking on the p first data streams subjected to Reed-Solomon RS encoding specifically comprises: p:q symbol demultiplexing on the p first data streams subjected to Reed-Solomon RS encoding to obtain q second data streams; and alignment identification locking on the q second data streams respectively to obtain a symbol pair boundary.

[0011] In a second possible implementation manner of the above aspect, the p:q symbol demultiplexing comprises p 1:8 symbol demultiplexing, where the p 1:8 symbol demultiplexing corresponds to the p first data streams one by one. This embodiment provides a specific implementation manner of demultiplexing, which is simple to implement.

[0012] In a third possible implementation manner of the above aspect, the 1:8 symbol demultiplexing adopts a round-robin manner of distributing 20 bits each time to demultiplex the corresponding first data stream to obtain eight second data streams. It should be understood that the round-robin manner of 20 bits can match the symbol pair boundary, and is used for alignment identification locking on each second data stream to obtain the symbol pair boundary of the corresponding first data stream.

[0013] In a fourth possible implementation manner of the above aspect, the symbol pair boundary is p, which corresponds to the p first data streams one by one.

[0014] In a fifth possible implementation manner of the above aspect, the eight second data streams all achieve alignment identification locking, and the 20-bit boundary distributed is a symbol pair boundary.

[0015] In a sixth possible implementation manner of the above aspect, within a threshold time interval, at least one of the eight second data streams does not achieve alignment identification locking, the 20-bit boundary distributed in the 1:8 symbol demultiplexing is shifted, 1:8 symbol demultiplexing is performed again to obtain eight second data streams again, and alignment identification locking is performed on the eight second data streams obtained again respectively to obtain a symbol pair boundary. This embodiment provides a complete flow of obtaining a symbol pair boundary. Only when all the second data streams achieve alignment identification locking, a correct symbol pair boundary can be obtained.

[0016] In a seventh possible implementation of the above aspect, in combination with the sixth possible implementation of the above aspect, a granularity of shifting the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is 1 bit; or a granularity of shifting the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is 20*m+1 bits, where m is an integer greater than 0. The embodiments of the present application provide multiple shifting granularities, which can match the processing bit width of specific hardware, are relatively simple to implement, and have low complexity.

[0017] In an eighth possible implementation of the above aspect, in combination with the above aspect and possible implementations of the above aspect, p=1, 2, or 4.

[0018] In a ninth possible implementation of the above aspect, in combination with the above aspect and possible implementations of the above aspect, a code word length of the inner code is 128 bits, where the information bits are 120 bits and the check bits are 8 bits; or a code word length of the inner code is 126 bits, where the information bits are 110 bits and the check bits are 16 bits.

[0019] In a tenth possible implementation of the above aspect, in combination with the above aspect and possible implementations of the above aspect, a code word length of the RS is 544 symbols, where the information length is 514 symbols, and each symbol contains 10 bits. The symbol pair includes 20 bits.

[0020] In an eleventh possible implementation of the above aspect, in combination with the tenth possible implementation of the above aspect, the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line including the smallest number of storage units includes 0 storage units, the difference in the number of storage units between each adjacent two delay lines is Q, each storage unit is configured to store 40 bits, and Q is an integer greater than or equal to 1.

[0021] In a twelfth possible implementation of the above aspect, in combination with the eleventh possible implementation of the above aspect, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and r*40 bits of the data stream output after the convolution interleaving include the 40 bits output by each delay line.

[0022] In a thirteenth possible implementation of the above aspect, in combination with the eleventh possible implementation of the above aspect, the 40 bits stored in each storage unit in the convolution interleaving are 4 RS symbols. At this time, it can be ensured that the 12 consecutive RS symbols output by the convolution interleaver come from 12 different RS code words, so that the concatenated FEC has better decoding performance.

[0023] In a fourteenth possible implementation of the above aspect, in combination with the above aspect and possible implementations of the above aspect, the modulation adopts four-level pulse amplitude PAM4 modulation.

[0024] In a third aspect, an embodiment of the present application provides a data processing apparatus, comprising: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identification locking on p first data streams that have been Reed-Solomon (RS) encoded, to obtain a symbol pair boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8xp; and the second processing unit is configured to perform data processing including inner code encoding and modulation on the p first data streams according to the obtained symbol pair boundary, to obtain p modulated data streams.

[0025] In a fourth aspect, an embodiment of the present application provides a data processing apparatus, comprising: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identification locking on p first data streams that have been Reed-Solomon (RS) encoded, to obtain a symbol pair boundary and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8xp; the second processing unit is configured to perform q:p symbol multiplexing on the q second data streams, to obtain p third data streams; and perform data processing including inner code encoding and modulation on the p third data streams according to the obtained symbol pair boundary, to obtain p modulated data streams.

[0026] In the above embodiments of the present application, the data processing apparatus obtains the symbol pair boundary before performing inner code encoding, and uses the symbol pair boundary to ensure that the information bits in the inner code encoding contain an integer number of RS symbols, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0027] In a first possible implementation of the above aspect, in combination with the above aspect, the first processing unit is specifically configured to: perform p:q symbol demultiplexing on p first data streams that have been Reed-Solomon (RS) encoded, to obtain q second data streams; and perform alignment identification locking on the q second data streams respectively, to obtain a symbol pair boundary.

[0028] In a second possible implementation form of the above aspect, the p:q symbol demultiplexing comprises p 1:8 symbol demultiplexings, wherein the p 1:8 symbol demultiplexings correspond to the p first data streams one by one. This embodiment provides a specific implementation of the demultiplexing, which is simple to implement.

[0029] In a third possible implementation form of the above aspect, in combination with the second possible implementation form of the above aspect, the 1:8 symbol demultiplexing is configured to demultiplex the corresponding first data stream by polling 20 bits each time to obtain 8 second data streams. It should be understood that polling 20 bits can match the symbol pair boundary, which is used to align and lock each second data stream, so as to obtain the symbol pair boundary of the corresponding first data stream.

[0030] In a fourth possible implementation form of the above aspect, in combination with the above aspect and possible implementation forms of the above aspect, the symbol pair boundary is p, which corresponds to the p first data streams one by one.

[0031] In a fifth possible implementation form of the above aspect, in combination with the fourth possible implementation form of the above aspect, the 8 second data streams are all aligned and locked, and the 20 bits of the boundary are a symbol pair boundary.

[0032] In a sixth possible implementation form of the above aspect, in combination with the fourth possible implementation form of the above aspect, within a threshold time interval, at least one of the 8 second data streams is not aligned and locked, and the first processing unit is further configured to shift the 20 bits of the boundary in the 1:8 symbol demultiplexing, re-perform 1:8 symbol demultiplexing to obtain 8 second data streams again, and align and lock the 8 second data streams obtained again respectively to obtain a symbol pair boundary. This embodiment provides a complete process of obtaining a symbol pair boundary. Only when all the second data streams are aligned and locked, can a correct symbol pair boundary be obtained.

[0033] In a seventh possible implementation form of the above aspect, in combination with the sixth possible implementation form of the above aspect, a granularity of shifting the 20 bits of the boundary in the 1:8 symbol demultiplexing is 1 bit, or a granularity of shifting the 20 bits of the boundary in the 1:8 symbol demultiplexing is 20xm+1 bits, where m is an integer greater than 0. The embodiments of the present application provide multiple shifting granularities, which can match the processing bit width of specific hardware, are relatively simple to implement, and have relatively low complexity.

[0034] In an eighth possible implementation form of the above aspect and possible implementation forms thereof, p = 1, 2 or 4.

[0035] In a ninth possible implementation form of the above aspect and possible implementation forms thereof, the code word length of the inner code is 128 bits, wherein the information bits are 120 bits and the check bits are 8 bits; or the code word length of the inner code is 126 bits, wherein the information bits are 110 bits and the check bits are 16 bits.

[0036] In a tenth possible implementation form of the above aspect and possible implementation forms thereof, the code word length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The symbol pair includes 20 bits.

[0037] In an eleventh possible implementation form of the above aspect and possible implementation forms thereof, the second processing unit is further configured to perform convolution interleaving on the received data stream, the convolution interleaving comprising delaying the input data stream according to r delay lines, the r being an integer greater than 1, each delay line including a different number of storage units, the delay line including the least number of storage units including 0 storage units, the difference in the number of storage units between each adjacent two delay lines being Q, each storage unit being configured to store 40 bits, the Q being an integer greater than or equal to 1.

[0038] In a twelfth possible implementation form of the above aspect and possible implementation forms thereof, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the r x 40 bits in the output data stream after the convolution interleaving include the 40 bits output by each delay line.

[0039] In a thirteenth possible implementation form of the above aspect and possible implementation forms thereof, the 40 bits stored in each storage unit in the convolution interleaving are 4 RS symbols. In this case, it can be ensured that the 12 consecutive RS symbols output by the convolution interleaver come from 12 different RS code words, so that the concatenated FEC has better decoding performance.

[0040] In a fourteenth possible implementation form of the above aspect and possible implementation forms thereof, the modulation adopts four-level pulse amplitude modulation (PAM4) modulation.

[0041] In some possible implementation forms, the data processing apparatus provided by the embodiments of the present application is applied to scenarios including Ethernet, optical transport network and space optical communication, etc.

[0042] In a fifth aspect, an embodiment of the present application provides a chip, which is configured to execute the method according to any one of the embodiments of the first aspect or the second aspect.

[0043] In a sixth aspect, an embodiment of the present application provides an optical module. The optical module comprises a processor and an interface. The processor is configured to execute the method according to any one of the embodiments of the first aspect or the second aspect, and the processor is configured to send a signal via the interface. For example, the interface is configured to send the signal from the processor or transmit a received signal to the processor.

[0044] In a seventh aspect, an embodiment of the present application provides a communication device. The communication device comprises a host device and an optical module according to any one of the embodiments of the sixth aspect. The optical module is connected to the host device.

[0045] In an eighth aspect, an embodiment of the present application provides another device. The device comprises a processor and an interface. The processor is configured to execute the method according to any one of the embodiments of the first aspect or the second aspect, and the processor is configured to send a signal via the interface. For example, the interface is configured to send the signal from the processor or transmit a received signal to the processor. The device can be a router, a switch, a server, an optical transport network device, or the like.

[0046] In a ninth aspect, an embodiment of the present application provides a communication system. The communication system comprises a first communication device and a second communication device. At least one of the first communication device and the second communication device is the communication device according to any one of the embodiments of the seventh aspect. The first communication device and the second communication device are connected.

[0047] In a tenth aspect, an embodiment of the present application provides a computer readable storage medium. The computer readable storage medium stores instructions. When the instructions are executed by a computer, the method according to any one of the embodiments of the first aspect or the second aspect is implemented.

[0048] In an eleventh aspect, an embodiment of the present application provides a computer program product. The computer program product comprises program instructions. When the computer program product is executed, the method according to any one of the embodiments of the first aspect or the second aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1 is a schematic diagram of a communication system to which an embodiment of the present application is applied;

[0050] FIG. 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1;

[0051] FIG. 3 is a schematic diagram of another communication system to which an embodiment of the present application is applied;

[0052] FIG. 4 is a flowchart of a data processing method according to an embodiment of the present application;

[0053] Figure 5(a) is a flow chart of acquiring symbol pair boundary according to an embodiment of the present application;

[0054] Figure 5(b) is a flow chart of acquiring symbol pair boundary according to an embodiment of the present application;

[0055] Figure 6(a) is a structure diagram of convolution interleaving processing according to an embodiment of the present application;

[0056] Figure 6(b) is a structure diagram of another convolution interleaving processing according to an embodiment of the present application;

[0057] Figure 7 is a diagram of data processing architecture according to an embodiment of the present application;

[0058] Figure 8 is a diagram of another data processing architecture according to an embodiment of the present application;

[0059] Figure 9 is a diagram of yet another data processing architecture according to an embodiment of the present application;

[0060] Figure 10 is a diagram of yet another data processing architecture according to an embodiment of the present application;

[0061] Figure 11 is a diagram of yet another data processing architecture according to an embodiment of the present application;

[0062] Figure 12 is a diagram of yet another data processing architecture according to an embodiment of the present application;

[0063] Figure 13 is a structure diagram of a data processing apparatus according to an embodiment of the present application;

[0064] Figure 14 is a structure diagram of an optical module according to an embodiment of the present application;

[0065] Figure 15 is a structure diagram of a communication device according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] The embodiments of the present application provide a data processing method, apparatus and system, which can acquire outer code symbol boundary before inner code encoding, so as to realize better cascade FEC error correction performance and can be applied to more transmission scenarios.

[0067] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and the above-described drawings are used to distinguish similar objects, and are not intended to indicate a specific order or sequence. It should be understood that the above terms can be interchanged, as appropriate, so that the embodiments described in the present application can be implemented in an order other than that described in the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units need not be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products, or apparatuses.

[0068] FIG. 1 is a schematic diagram of a communication system to which embodiments of the present application are applied. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be devices such as switches, routers, or servers, and the sending device 01 is also referred to as a client-side device located at the sending end, and the receiving device 05 is also referred to as a client-side device located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device is also referred to as a host-side device. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host-side chip. The connection interface between the sending device 01 and the sending processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The sending processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a DR optical module or a FR optical module or a LR optical module, such as an 800G FR4 optical module, an 800G LR4 optical module, an 800G DR4-2 optical module, a 400G FR2 optical module, a 400G LR2 optical module, a 400G DR2-2 optical module, a 200G LR1 optical module, a 200G DR1-2 optical module, a 200G FR1 optical module, etc. Moreover, the sending device 01, the sending processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system can support bidirectional transmission, or can support unidirectional transmission, which is not limited here.

[0069] Figure 2 is a schematic diagram of a process of data transmission in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from the sending device 01 to the receiving device 05, the sending device 01 is configured to perform outer code encoding on the data, and then transmit the outer code encoded data to the sending processing module 02. The sending processing module 02 is configured to perform inner code encoding on the outer code encoded data, to obtain outer code encoded and inner code encoded data, and transmit the outer code encoded and inner code encoded data to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer code encoded and inner code encoded data to the receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the outer code encoded and inner code encoded data, and transmit the inner code decoded data to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the inner code decoded data.

[0070] It should be understood that the "inner" in the inner code and the "outer" in the outer code are only distinguished based on the distance of the execution subject operating on the data relative to the channel transmission medium 03. The execution subject operating on the inner code is closer to the channel transmission medium, and the execution subject operating on the outer code is farther away from the channel transmission medium. In the embodiments of the present application, since the data is transmitted from the sending end device 01 to the channel transmission medium 03 through the sending end processing module 02, and then transmitted from the channel transmission medium 03 to the receiving end device 05 through the receiving end processing module 04. The data encoded by the sending end device 01 is farther away from the channel transmission medium 03 than the data encoded by the sending end processing module 02, and the data decoded by the receiving end device 05 is farther away from the channel transmission medium 03 than the data decoded by the receiving end processing module 04. Therefore, the data encoded by the sending end device 01 is called data encoded by the outer code, the data encoded by the sending end processing module 02 is called data encoded by the inner code, the data decoded by the receiving end device 05 is called data decoded by the outer code, and the data decoded by the receiving end processing module 04 is called data decoded by the inner code. In a possible implementation, the inner code encoding and the outer code encoding described above are both in the form of FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the sending end device 01 can perform outer code encoding using Reed-solomon (RS) code, and the sending end processing module 02 can perform inner code encoding using Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can perform inner code encoding using Bose-Chaudhuri-Hocquenghem (BCH) code. The BCH code that can correct a single error is equivalent to Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can also perform inner code encoding using Polar code. In some specific application scenarios, the sending end device 01 can perform outer code encoding using RS (544, 514) code, also known as KP4 code.

[0071] FIG. 3 is a schematic diagram of another communication system to which embodiments of the present application are applied. As shown in FIG. 3, the communication system includes a sending device 01, a channel transmission medium 03, and a receiving device 05. The sending device 01 performs outer code encoding and inner code encoding on data, and the data after outer code encoding and inner code encoding is sent to the channel transmission medium 03. The receiving device 05 performs inner code decoding and outer code decoding on the data received from the channel transmission medium 03. Taking the communication system as an example of a data center network, the sending device 01 and the receiving device 05 can be switches, routers, servers, or other devices, and the sending device 01 is also referred to as a client-side device or a host device at the sending end, and the receiving device 05 is also referred to as a client-side chip at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host chip. The sending device 01, the channel transmission medium 03, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not limited here. That is, the sending device 01 shown in FIG. 3 also integrates the functions of the sending processing module 02 shown in FIG. 2, and the receiving device 05 shown in FIG. 3 also integrates the functions of the receiving processing module 04 shown in FIG. 2. At this time, the sending device 01 can also use linear-drive pluggable optics (LPO) technology, co-packaged optics (CPO) technology, or near packaged optics (NPO) technology.

[0072] It should also be noted that the above is an exemplary description of the application scenarios of the data processing method provided by the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. Those skilled in the art can know that the application scenarios can be adjusted according to application requirements as the business requirements change, and the embodiments of the present application do not enumerate them one by one.

[0073] FIG. 4 is a flowchart of a data processing method provided by an embodiment of the present application. It should be understood that the data processing method is applied to a sending end, for example, can be implemented by the sending processing module 02 shown in FIG. 2, or can be implemented by the sending device 01 shown in FIG. 3.

[0074] 101. Perform p:q symbol demultiplexing and alignment identification locking on the p pieces of first data stream after RS encoding to obtain a symbol pair boundary (also referred to as a two-symbol boundary), where p is an integer greater than or equal to 1, q is an integer, and q = 8xp.

[0075] In the embodiments of the present application, the p first data streams are all data streams encoded by outer codes. For the convenience of introduction, the following will be described by taking RS encoding as an example, and in actual application, other encoding modes can also be used for outer code encoding. The data stream encoded by RS can include multiple RS code words, and in the embodiments of the present application, the code length of RS code is counted in units of symbols. The symbol in RS code can be referred to as RS symbol, also referred to as outer code RS symbol. For example, RS code adopts RS(544, 514) code, also referred to as KP4 code, the code length of the RS code is 544 RS symbols, that is, the code word of RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a RS adjacent RS symbols in each of the first data streams come from a RS RS code word, wherein a RS is greater than or equal to 4 and is an integer power of 2.

[0076] For 200G transmission scenarios, for example, 200GBASE-R inner code encoding, the p = 1. In some specific applications, the p = 1 first data stream is obtained by processing 1 AUI data stream of 200GAUI-1 by 200GBASE-R 1:1 SM-PMA. The 1 AUI data stream of 200GAUI-1 is obtained by processing 8 PCSL data streams by 200GBASE-R 8:1 SM-PMA. Every 2 adjacent RS symbols in the 8 PCSL data streams come from 2 different RS code words.

[0077] For 400G transmission scenarios, for example, 400GBASE-R inner code encoding, the p = 2. In some specific applications, the p = 2 first data streams are obtained by processing 2 AUI data streams of 400GAUI-2 by 400GBASE-R 2:2 SM-PMA. The 2 AUI data streams of 400GAUI-2 are obtained by processing 16 PCSL data streams by 400GBASE-R 16:2 SM-PMA. Every 2 adjacent RS symbols in the 16 PCSL data streams come from 2 different RS code words.

[0078] For 800G transmission scenario, for example, 800GBASE-R inner code encoding, the p = 4. In some specific applications, the p = 4 first data streams are obtained by 800GBASE-R 4:4 SM-PMA processing of 4 AUI data streams of 800GAUI-4. The 4 AUI data streams of 800GAUI-4 are obtained by 800GBASE-R 32:4 SM-PMA processing of 32 PCSL data streams. Every 2 adjacent RS symbols in the 32 PCSL data streams come from 2 different RS code words.

[0079] It should be noted that for the above 200GBASE-R inner code encoding, 400GBASE-R inner code encoding, 800GBASE-R inner code encoding, the nominal rate of each data stream in the p first data streams is 212.5G bits per second (b / s). Moreover, every a RS = 4 adjacent RS symbols come from a RS = 4 different RS code words.

[0080] It should be noted that in some specific applications, the p first data streams are also called p PMA data streams.

[0081] As shown in FIG. 5(a), p:q symbol demultiplexing processing is performed on the p first data streams to obtain q second data streams, where q = 8xp. As shown in FIG. 5(b), the p:q symbol demultiplexing includes p 1:8 symbol demultiplexings, and each 1:8 symbol demultiplexing corresponds to one of the p first data streams. Each 1:8 symbol demultiplexing adopts a round-robin manner of distributing 20 bits at a time to demultiplex the input 1 first data stream to obtain 8 output second data streams.

[0082] Alignment marker lock processing is performed on the q second data streams respectively. Here, the alignment marker lock is also referred to as alignment lock. The alignment marker lock performs a locking operation using the known alignment marker (AM) in the PCSL data stream.

[0083] It is noted that the 8 output second data streams achieve alignment marker lock only when the 20-bit boundary corresponds to the 2-symbol boundary in the 1:8 symbol demultiplexing. Here, achieving alignment marker lock means that the alignment marker is correctly locked. At this time, the 20-bit boundary is a symbol pair boundary. It is understood that the number of symbol pair boundaries is equal to the number of first data streams, i.e., p symbol pair boundaries correspond to p first data streams.

[0084] It is noted that when the 8 output second data streams do not achieve alignment marker lock in a certain time interval, which can also be referred to as a threshold time interval, or a certain bit interval (e.g., 222,822,400 bits), which can also be referred to as a threshold bit interval, the 20-bit boundary in the 1:8 symbol demultiplexing is shifted, which is also referred to as slipping. In some specific applications, the 20-bit boundary in the 1:8 symbol demultiplexing slips by 1 bit. In other specific applications, the 20-bit boundary in the 1:8 symbol demultiplexing slips by more than 1 bit, in which case it is necessary to ensure that all possible boundaries are evaluated, which can slip by 20xm+1 bits, m being an integer greater than 0, for example, slipping by 21 bits or 41 bits. When the shift interval matches the processing bit width of the specific hardware implementation, the implementation is relatively simple and has low complexity. The above shift operation is performed until all 8 output second data streams achieve alignment marker lock.

[0085] When the 8 output second data streams of the 1:8 symbol demultiplexing achieve alignment marker lock, symbol pair lock is achieved, and the symbol pair boundary corresponding to the first data stream is also obtained. The symbol pair boundary is also referred to as a two-symbol boundary, which can be referred to as a symbol boundary. When q second data streams achieve alignment marker lock, p symbol pair boundaries are achieved. At this time, the q second data streams are q PCSL data streams. The adjacent 2 RS symbols in the q second data streams come from 2 different RS codewords. More specifically, for a second data stream, the symbols in the data stream are represented in the form of A, B, A, B, etc. starting from the alignment marker, where A represents an RS symbol in one codeword and B represents an RS symbol in another codeword.

[0086] It is noted that each of the first data streams has a symbol pair boundaryRS = 4 adjacent RS symbols from a RS = 4 different RS codewords, obtaining the symbol pair boundary corresponding to a first data stream, and thus obtaining 4 adjacent RS symbols in the first data stream.

[0087] 102. According to the obtained symbol pair boundary, the p first data streams are subjected to data processing including inner code encoding and modulation to obtain p modulated data streams.

[0088] According to the obtained symbol pair boundary, 40 bits adjacent (also referred to as continuous) in each first data stream can be obtained, corresponding to 4 RS symbols. More specifically, the 4 RS symbols are from 4 different RS codewords. The 4 RS symbols are also referred to as RS FEC quartet (RS-FEC-symbol-quartet).

[0089] The following describes the inner code encoding mode by taking one first data stream as an example. Specifically, K information bits in the first data stream are subjected to inner code encoding to generate N-K check bits, thereby obtaining an inner code codeword including N bits, where 1 < K < N. In this application, K is considered to be a multiple of 10. In combination with the obtained symbol pair boundary, the K information bits in each inner code codeword can correspond to K / 10 outer code RS symbols.

[0090] In some specific applications, the K information bits in each inner code codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols are from K / 10 different outer code RS codewords, so that the FEC cascading scheme including RS encoding and inner code encoding has optimal performance. For example, the inner code encoding adopts BCH (126, 110), K = 110 information bits in each inner code codeword correspond to K / 10 = 11 outer code symbols, and the corresponding K / 10 = 11 outer code symbols are from K / 10 = 11 different outer code RS codewords. For another example, the inner code encoding adopts a linear block code with N = 128 and K = 120, K = 120 information bits in each inner code codeword correspond to K / 10 = 12 outer code symbols, and the corresponding K / 10 = 12 outer code symbols are from K / 10 = 12 different outer code RS codewords. In order to make the K information bits in each inner code codeword correspond to K / 10 different outer code RS codewords, the first data stream is subjected to convolution interleaving processing before inner code encoding. The convolution interleaving processing is described in detail below.

[0091] Specifically, the convolution interleaver performing the convolution interleaving process includes r delay lines, each of which includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage unit, and the difference in the number of storage units between each two adjacent delay lines is Q, where r is an integer greater than 1, and Q is an integer greater than or equal to 1. Each storage unit is used to store d bits, where d is an integer greater than or equal to 1. The bits in the input data stream of the convolution interleaver are sequentially input to the r delay lines according to the sequence number of the r delay lines, d bits are input from each delay line at a time, and d bits are output from each delay line at a time. In some specific applications, the convolution interleaver outputs d bits at a time. In other specific applications, the convolution interleaver outputs rxd bits at a time, the rxd bits come from the r delay lines, and include the d bits output from each delay line. The rxd bits in the data stream output by the convolution interleaver in succession include the d bits output from each delay line.

[0092] It should be understood that the r delay lines respectively include 0 storage units, Q storage units, 2Q storage units, …, (r-1)Q storage units, and each storage unit is used to store d bits. The r delay lines respectively correspond to r delay values, and the delay values include 0 bits, Qxd bits, 2Qxd bits, …, (r-1)Qxd bits. The more bits included in the delay value of the delay line, the longer the delay (also referred to as the time delay) of the data stream by the delay line. It should be understood that when the delay line does not include storage units, the delay of the delay line is 0 bits, i.e., no delay transmission. It should be understood that the storage unit described above is also referred to as a delay element.

[0093] FIG. 6(a) is a schematic diagram of a first structure of the convolution interleaving process in the embodiments of the present application. As shown in FIG. 6(a), the number of storage units in the r delay lines decreases in turn according to the sequence number of the r delay lines. That is, the delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units in turn, and the delay line r-1 has 0 storage unit. FIG. 6(b) is a schematic diagram of a second structure of the convolution interleaving process in the embodiments of the present application. As shown in FIG. 6(b), the number of storage units in the r delay lines increases in turn according to the sequence number of the r delay lines. That is, the delay line 0 has 0 storage unit, each delay line increases by Q storage units in turn, and the delay line r-1 has (r-1)Q storage units.

[0094] It should be noted that at the same time, the switch of the convolution interleaver input and output is located on the same delay line, and after the current delay line is input d bits and output d bits, the switch is switched to the next delay line to ensure that the bits in the input data stream are sequentially input to the r delay lines according to the sequence number of the r delay lines, and the continuous rxd bits in the output data stream include the d bits output by each delay line. The specific data read and write operation is as follows: reading d bits from the storage unit closest to the output port of the current delay line; transferring the d bits stored in each storage unit in the current delay line to the next storage unit. Then, write d bits to the storage unit closest to the input port of the current delay line. Then, switch to the next delay line and repeat the above operation, and the same applies.

[0095] It should be understood that when the same parameters r, Q and d are used, the convolution interleaving process of FIG. 6(a) and the convolution interleaving process of FIG. 6(b) are inverse operations of each other. That is, when the sending processing module adopts the convolution interleaving structure shown in FIG. 6(a), the corresponding convolution deinterleaving of the receiving processing module adopts the structure shown in FIG. 6(b). Similarly, when the sending processing module adopts the convolution interleaving structure shown in FIG. 6(b), the corresponding convolution deinterleaving of the receiving processing module adopts the structure shown in FIG. 6(a).

[0096] Typically, the number of bits d stored in each storage unit = a RS × 10 = 40. According to the obtained symbol boundary, the 40 bits stored in each storage unit come from 40 consecutive bits in a first data stream, corresponding to 4 RS symbols. The 4 RS symbols come from 4 different RS code words.

[0097] After the p first data streams are subjected to inner code encoding, they are modulated to obtain p modulated data streams. In some specific applications, the modulation adopts 4-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM4).

[0098] In the embodiments of the present application, the data processing flow can be divided into two parts, the first data processing can include p:q symbol demultiplexing and alignment identification locking, and the second data processing can include at least one of 1:8 K-bit distribution, cyclic shift, 8:1 bit-pair interleaving, pad insertion, and precoder in addition to inner code encoding and modulation.

[0099] It should be noted that in some specific applications, the convolution interleaving operation can be bypassed so that the overall cascaded FEC scheme has a lower latency and can be applied in application scenarios requiring low latency.

[0100] The following provides several embodiments to introduce the possible values of p by taking a linear block code with N=128 and K=120 as an example.

[0101] Embodiment 1: Considering 200GBASE-R inner code encoding, p=1 and q=8xp=8.

[0102] As shown in FIG. 7, one AUI data stream of 200GAUI-1 is subjected to 200GBASE-R 1:1 SM-PMA processing to obtain p=1 first data stream. The p=1 first data stream is subjected to 1:8 symbol demultiplexing and alignment identification locking to obtain the symbol boundary (also referred to as 2-symbol boundary or symbol pair boundary) of the first data stream. The 1:8 symbol demultiplexing adopts a round-robin manner of distributing 20 bits at a time to demultiplex the input 1 first data stream to obtain 8 output second data streams.

[0103] According to the obtained symbol pair boundary, the p=1 first data stream is subjected to second data processing including inner code encoding and PAM4 modulation to obtain p=1 PAM4 modulation data stream. The second data processing can include convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0104] The convolution interleaver includes r=3 delay lines, the difference between the number of storage units of each adjacent two delay lines is Q=192, and each storage unit is used to store d=40 bits. According to the obtained symbol pair boundary, the d=40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundary, the cyclic shift is a cyclic shift operation on 12 symbols in the 120 information bits with symbol as granularity.

[0105] It should be noted that in this embodiment, as shown in FIG. 7, the 1024-bit padding insertion in the second data processing is performed after the inner code encoding operation, and 120-bit padding insertion can also be performed before the inner code encoding. At this time, 8 inner code pre-encoding data streams are respectively periodically inserted with 120-bit padding, each group of 120 bits is subjected to inner code encoding to obtain 128-bit padding after encoding, and after 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0106] In this embodiment, the symbol pair boundary is obtained before the inner code encoding is performed, and the 120 information bits in the inner code (128, 120) encoding are from 12 different RS code words by using the symbol pair boundary, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0107] Embodiment 2: Considering 400GBASE-R inner code encoding, p = 2 and q = 8xp = 16.

[0108] As shown in FIG. 8, 2 AUI data streams of 400GAUI-2 are processed by 400GBASE-R 2:2 SM-PMA to obtain p = 2 first data streams. The p = 2 first data streams are subjected to 2:16 symbol demultiplexing and alignment mark lock to obtain the respective symbol boundaries (also referred to as 2-symbol boundaries, or symbol pair boundaries) of the p = 2 first data streams. The 2:16 symbol demultiplexing includes p = 2 1:8 symbol demultiplexing, as shown in FIG. 5(b). Each 1:8 symbol demultiplexing uses a round-robin method of distributing 20 bits at a time to demultiplex the input 1 first data stream to obtain 8 output second data streams.

[0109] According to the obtained symbol pair boundary, the p = 2 first data streams are subjected to second data processing including inner code encoding and PAM4 modulation to obtain p = 2 PAM4 modulation data streams. The second data processing can include convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0110] The convolution interleaver includes r = 3 delay lines, and the difference between the number of storage units of each adjacent two delay lines is Q = 96, and each storage unit is used to store d = 40 bits. According to the obtained symbol pair boundary, the d = 40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundary, the cyclic shift is a cyclic shift operation on 12 symbols in the 120 information bits with symbol as granularity.

[0111] It should be noted that in the embodiment, as shown in FIG. 8, after the second data processing, the p=2 first data streams obtain p=2 PAM4 data streams. In the data processing of each first data stream, the 1024-bit padding insertion is performed after the inner code encoding operation, or the 120-bit padding insertion can be performed before the inner code encoding. At this time, 8 inner code pre-encoding data streams are periodically inserted with 120-bit padding, and each group of 120 bits is encoded to obtain 128-bit padding after the inner code encoding, and after the 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0112] In the embodiment, the symbol pair boundary is obtained before the inner code encoding, and the 120 information bits in the inner code (128, 120) encoding are from 12 different RS code words by using the symbol pair boundary, so that the concatenated FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0113] Embodiment 3: Considering 800GBASE-R inner code encoding, p=4 and q=8xp=32.

[0114] As shown in FIG. 9, the 4 AUI data streams of 800GAUI-4 are processed by 800GBASE-R 4:4 SM-PMA to obtain p=4 first data streams. The p=4 first data streams are subjected to 4:32 symbol demultiplexing and alignment mark locking to obtain the respective symbol boundaries (also referred to as 2-symbol boundaries, or symbol pair boundaries) of the p=4 first data streams. The 4:32 symbol demultiplexing includes p=4 1:8 symbol demultiplexing, as shown in FIG. 5(b). Each 1:8 symbol demultiplexing adopts a round-robin method of distributing 20 bits at a time to demultiplex the input 1 first data stream to obtain 8 output second data streams.

[0115] According to the obtained symbol pair boundary, the p=4 first data streams are subjected to second data processing including inner code encoding and PAM4 modulation to obtain p=4 PAM4 modulation data streams. The second data processing can include convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0116] The convolution interleaver includes r=3 delay lines, the difference between the number of storage units of each adjacent two delay lines is Q=48, and each storage unit is used to store d=40 bits. According to the obtained symbol pair boundary, the d=40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundary, the cyclic shift is a cyclic shift operation on 12 symbols in 120 information bits with symbol as granularity.

[0117] It should be noted that in the embodiment, as shown in FIG. 9, the p=4 first data streams are obtained after the second data processing. For the data processing of each first data stream, the 1024-bit padding insertion is performed after the inner code encoding operation, or the 120-bit padding insertion can be performed before the inner code encoding. At this time, the 8 inner code pre-encoding data streams are periodically inserted with 120-bit padding, and the 128-bit padding is obtained after the inner code encoding of each group of 120 bits. After the 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0118] In the embodiment, the symbol pair boundary is obtained before the inner code encoding, and the 120 information bits in the inner code (128, 120) encoding come from 12 different RS code words by using the symbol pair boundary, so that the concatenated FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0119] In the above embodiment, the input of the second data processing including the inner code encoding is the p first data streams. In some specific applications, the input of the second data processing can be p data streams obtained by q:p symbol multiplexing of the data stream implementing the alignment mark lock. At this time, another flow of the data processing method is as follows:

[0120] 201, performing p:q symbol demultiplexing and alignment mark locking on the p first data streams encoded by the RS to obtain a symbol pair boundary and q second data streams, wherein p is an integer greater than or equal to 1, and q is an integer and q=8xp.

[0121] 202, performing q:p symbol multiplexing on the q second data streams to obtain p third data streams;

[0122] The q:p symbol multiplexing includes p 8:1 symbol multiplexings, and the p 8:1 symbol multiplexings correspond to the p first data streams one by one. More specifically, the 1 8:1 symbol multiplexing multiplexes 8 second data streams obtained by 1:8 symbol demultiplexing of 1 first data stream. The 1 8:1 symbol multiplexing uses a round-robin mode of 2 symbols (i.e., a symbol pair, a total of 20 bits) to multiplex the 8 second data streams inputted to obtain 1 third data stream. The p 8:1 symbol multiplexings multiplex the q=8×p second data streams inputted to obtain p third data streams.

[0123] 203. The p third data streams are subjected to data processing including inner code encoding and modulation according to the symbol pair boundary obtained.

[0124] It should be noted that in some specific applications, the q second data streams are subjected to deskewing before the q:p symbol multiplexing is performed, so that there is no offset between the q second data streams after the deskewing, to support accurate calculation of path data delay, and the deskewing is also referred to as full deskewing. In other specific applications, the deskewing is based on 20-bit deskewing, i.e., an offset of d skew bits is allowed between the q second data streams, where d skew is an integer multiple of 20, and the deskewing is also referred to as 20-bit deskewing.

[0125] The following provides several embodiments to introduce another flow of the data processing method, taking a linear block code with N=128 and K=120 as an example.

[0126] Embodiment 4: Considering 200GBASE-R inner code encoding, p=1 and q=8×p=8.

[0127] As shown in FIG. 10, 1 AUI data stream of 200GAUI-1 is subjected to 200GBASE-R 1:1 SM-PMA processing to obtain p=1 first data stream. The p=1 first data stream is subjected to 1:8 symbol demultiplexing and alignment identification locking to obtain a symbol boundary (also referred to as 2-symbol boundary, or symbol pair boundary) of the first data stream and obtain q=8 second data streams. The 1:8 symbol demultiplexing uses a round-robin mode of distributing 20 bits at a time to demultiplex 1 first data stream inputted to obtain 8 second data streams outputted.

[0128] The second data stream of q=8 aligned alignment identification lock is 8:1 symbol multiplexed to obtain p=1 third data stream, and the p=1 third data stream is subjected to second data processing of containing inner code encoding and PAM4 modulation according to the obtained symbol pair boundary, to obtain p=1 PAM4 modulation data stream. The second data processing can contain convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0129] The convolution interleaver contains r=3 delay lines, the difference in the number of storage units of each adjacent two delay lines is Q=192, and each storage unit is used to store d=40 bits. According to the obtained symbol pair boundary, d=40 bits stored in each storage unit in convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundary, the cyclic shift is a cyclic shift operation on 12 symbols in 120 information bits with symbol as granularity.

[0130] It should be noted that in the embodiment, as shown in FIG. 10, the 1024-bit padding insertion in the second data processing is performed after the inner code encoding operation, and 120-bit padding insertion can also be performed before the inner code encoding. At this time, the 8 inner code encoding pre-data streams are respectively periodically inserted with 120-bit padding, and each group of 120 bits is subjected to inner code encoding to obtain 128-bit padding after encoding, and after 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0131] In the embodiment, the symbol pair boundary is obtained before the inner code encoding, and the symbol pair boundary is used to make the 120 information bits in the inner code (128, 120) encoding come from 12 different RS code words, so that the concatenated FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0132] Embodiment 5: Considering 400GBASE-R inner code encoding, p=2 and q=8xp=16.

[0133] As shown in FIG. 11, the 2 AUI data streams of the 400GAUI-2 are processed by the 400GBASE-R 2:2 SM-PMA to obtain p=2 first data streams. The p=2 first data streams are subjected to 2:16 symbol demultiplexing and alignment-locked to obtain the respective symbol boundaries (also referred to as 2-symbol boundaries, or symbol pair boundaries) of the p=2 first data streams and to obtain q=16 second data streams. The 2:16 symbol demultiplexing includes p=2 1:8 symbol demultiplexing, as shown in FIG. 5(b). Each 1:8 symbol demultiplexing demultiplexes the input first data stream to obtain 8 output second data streams by round-robin distribution of 20 bits at a time.

[0134] The q=16 second data streams, which are subjected to alignment-locked, are subjected to 16:2 symbol multiplexing to obtain p=2 third data streams, which are subjected to second data processing including inner code encoding and PAM4 modulation according to the obtained symbol pair boundaries to obtain p=2 PAM4 modulated data streams. The second data processing includes convolution interleaving, 1:8 120-bit distribution, cyclic shifting, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0135] The convolution interleaver includes r=3 delay lines, and the number of storage units of each adjacent two delay lines differs by Q=96, and each storage unit is used to store d=40 bits. According to the obtained symbol pair boundaries, the d=40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundaries, the cyclic shifting is a cyclic shifting operation on 12 symbols in the 120 information bits with symbol as granularity.

[0136] It should be noted that, in the embodiment, as shown in FIG. 11, the p=2 first data streams in the second data processing obtain p=2 PAM4 data streams after being subjected to the second data processing. In the data processing performed for each first data stream, the 1024-bit padding insertion is performed after the inner code encoding operation, or 120-bit padding insertion can be performed before the inner code encoding. At this time, 8 inner code pre-encoding data streams are respectively periodically inserted with 120-bit padding, and each set of 120 bits is subjected to inner code encoding to obtain 128-bit padding after encoding, and is subjected to 8:1 bit pair interleaving to obtain a total of 128*8=1024-bit padding.

[0137] In the embodiment, the symbol pair boundary is obtained before the inner code encoding is performed, and the 120 information bits in the inner code (128, 120) encoding are from 12 different RS code words by using the symbol pair boundary, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0138] Embodiment 6: Considering 800GBASE-R inner code encoding, p = 4 and q = 8xp = 32.

[0139] As shown in FIG. 12, the 4 AUI data streams of 800GAUI-4 are processed by 800GBASE-R 4:4 SM-PMA to obtain p = 4 first data streams. The p = 4 first data streams are subjected to 4:32 symbol demultiplexing and alignment mark locking to obtain the symbol pair boundary (also referred to as 2-symbol boundary, or symbol pair boundary) of each of the p = 4 first data streams and obtain q = 32 second data streams. The 4:32 symbol demultiplexing includes p = 4 1:8 symbol demultiplexing, as shown in FIG. 5(b). Each 1:8 symbol demultiplexing uses a round-robin method of distributing 20 bits at a time to demultiplex the 1 first data stream inputted thereby to obtain 8 second data streams outputted.

[0140] The q = 32 second data streams subjected to the alignment mark locking are subjected to 32:4 symbol multiplexing to obtain p = 4 third data streams, and the p = 4 first data streams are subjected to second data processing including inner code encoding and PAM4 modulation according to the obtained symbol pair boundary to obtain p = 4 PAM4 modulation data streams. The second data processing includes convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, 1024-bit padding insertion, and PAM4 modulation.

[0141] The convolution interleaver includes r = 3 delay lines, the difference between the number of storage units of each adjacent two delay lines is Q = 48, and each storage unit is used to store d = 40 bits. According to the obtained symbol pair boundary, the d = 40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained symbol pair boundary, the cyclic shift is a cyclic shift operation on 12 symbols in the 120 information bits with symbol as granularity.

[0142] It should be noted that in the embodiment, as shown in FIG. 12, after the second data processing, the p=4 first data streams are obtained after the second data processing. For each first data stream, the 1024-bit padding insertion is performed after the inner code encoding operation, or the 120-bit padding insertion can be performed before the inner code encoding. At this time, 8 inner code pre-encoding data streams are periodically inserted with 120-bit padding, and each group of 120 bits is encoded to obtain 128-bit padding after the inner code encoding. After 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0143] In the embodiment, the symbol pair boundary is obtained before the inner code encoding, and the 120 information bits in the inner code (128, 120) encoding are from 12 different RS code words by using the symbol pair boundary, so that the concatenated FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0144] FIG. 13 is a structural schematic diagram of a data processing apparatus in an embodiment of the present application. As shown in FIG. 13, the data processing apparatus includes a first processing unit 1301 and a second processing unit 1302. The first processing unit 1301 is configured to perform the first data processing described in the foregoing embodiments, and the second processing unit 1302 is configured to perform the second data processing described in the foregoing embodiments. The specific data processing manner has been described in detail in the foregoing embodiments, and will not be described here.

[0145] It should be understood that the data processing apparatus provided by the present application can also be implemented in other manners. For example, the division of the units in the apparatus is merely a logical function division, and actual implementation can be in another manner, for example, a plurality of units or components can be combined or integrated into another system. In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each can be a separate physical unit, or two or more functional units can be integrated in a processing unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0146] Figure 14 is a schematic diagram of a structure of an optical module according to an embodiment of the present application. As shown in Figure 14, the optical module includes a processor 1401 and an interface 1402. The processor 1401 is configured to perform the operations of the data processing apparatus described in the above embodiments. The interface 1402 can be a transceiver or an input / output interface. The interface 1402 is configured to receive a signal from another apparatus and transmit the signal to the processor 1401 or transmit a signal from the processor 1401 to another apparatus. As an example, the processor 1401 performs the inner code encoding process to obtain an encoded data stream, and transmits the encoded data stream through the interface 1402. In this example, the interface 1402 can be an electrical interface. As another example, the processor 1401 performs the inner code encoding process to obtain an encoded data stream and performs symbol mapping (also referred to as modulation mapping) to obtain a symbol stream to be transmitted. A modulator in the optical module performs signal processing such as electro-optical conversion on the symbol stream to be transmitted to obtain an optical signal, and transmits the optical signal through the interface 1402. In this example, the interface 1402 can be an optical interface. Optionally, the optical module can further include a memory 1403. The memory 1403 is configured to store program instructions and / or data.

[0147] Generally, an optical module includes optoelectronic devices, a processor, and an interface. The optoelectronic devices include a transmitter device and a receiver device. The transmitter of the optical module converts an electrical signal into an optical signal and transmits the optical signal through an optical fiber. The receiver of the optical module receives an optical signal and converts the optical signal into an electrical signal.

[0148] It should be noted that the types of the optical module in the embodiments of the present application include, but are not limited to, normal optical module, near package optics (NPO) module, co-packaged optics (CPO) module, and the like. The functions that can be implemented by the normal optical module include, but are not limited to, digital signal processor (DSP) and clock data recovery (CDR), and the like. For example, the normal optical module converts an analog signal into a digital signal, performs DSP on the digital signal, and then converts the digital signal into an analog signal to be sent to a host-side device. Since the DSP needs to be retimed, the normal optical module can also be referred to as a retimed module. The normal optical module is connected to the host-side device through an attachment unit interface (AUI). The NPO module and the CPO module do not have a pluggable optical module physical package form, and are closer to the host-side device. The NPO module and the CPO module can also be referred to as an optical engine. The NPO technology or the CPO technology is a technology of "packaging" the host-side device (or the host-side chip) and the optical engine. When the host-side device and the optical engine are packaged by using the NPO technology, the optical engine can be referred to as an NPO module. When the host-side device and the optical engine are packaged by using the CPO technology, the optical engine can be referred to as a CPO module.

[0149] FIG. 15 is a schematic structural diagram of a communication device according to an embodiment of the present application. As shown in FIG. 15, the communication device includes a host-side device 1501 and an optical module 1502. The host-side device 1501 is configured to send data to the optical module 1502, and the optical module 1502 generates an optical signal according to the data sent by the host-side device 1501 and sends the optical signal through a channel. For example, the host-side device can be a switch, a router, a server, or the like. The communication device can be a communication device including the host-side device 1501 and the optical module 1502.

[0150] The embodiments of the present application also provide an optical transport network (OTN) device, which comprises a line side device and a client side device. The client side device can also be referred to as a tributary side device in some scenarios. The line side device comprises a processor and an interface. The processor is configured to execute the data processing method described in the above embodiments. The interface can be a transceiver or an input / output interface. The interface is configured to receive a signal from another device outside the line side device and transmit the signal to the processor, or transmit a signal from the processor to another device outside the line side device.

[0151] The embodiments of the present application also provide a chip. The chip integrates a circuit for implementing the functions of the processor described above and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, the chip can be connected to an external memory through the interface. The chip can complete the method steps of any one or more of the above embodiments. Alternatively, the chip implements the actions performed by the data processing device in the above embodiments according to program codes stored in the memory.

[0152] As an example, the chip in the embodiments of the present application can be a central processing unit (CPU), and can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a transistor logic device, a hardware component or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor, and can also be a processing circuit implementing specific functions.

[0153] The embodiments of the present application also provide a computer readable storage medium, which comprises a program or instructions. When the program or instructions are executed on a computer, the data processing method described in the above embodiments is implemented.

[0154] It should be understood that the processor mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit or the like. When implemented by software, the processor can be a general-purpose processor, which reads software codes stored in a memory to implement the functions. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0155] As an example, the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor, and can also be a processing circuit that implements specific functions.

[0156] The memory in the embodiments of the present application can be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can be a component of the processor. The processor and the storage medium can be located in an ASIC. The ASIC can be located in a network device or a terminal device. Of course, the processor and the storage medium can also exist as discrete components in the network device or the terminal device.

[0157] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof.

[0158] When implemented by using hardware, the data processing method provided by the embodiments of the present application can be implemented without reading software codes or instructions, for example, by using a CPU, a DSP, an ASIC, an FPGA, other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0159] When implemented using software, the functions can be implemented using one or more computer programs or instructions stored or executed in at least one computer-readable medium. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a computer-readable signal. The computer-readable medium can include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, DVDs, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any other suitable type of machine-readable medium. Suitable machine-readable media for storing or transmitting software include hardware- or software-readable media that store data which can be accessed by one or more computer systems. A computer-readable medium stores computer-executable instructions or data that, in combination with the computer system, cause the computer system to operate. For example, a non-transitory computer-readable medium comprising a computer-readable medium that does not undergo a transformation during transmission is any medium that stores data that is not transmitted but is accessed by the computer system. Examples of non-transitory computer-readable media include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. The term "computer-readable medium" includes, but is not limited to, portable or fixed computer-readable media that store data for use by or in connection with one or more computer systems or devices.

[0160] Finally, it should be noted that the above merely illustrates the embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises the following steps: p:q symbol demultiplexing and alignment mark locking are performed on p first data streams subjected to Reed-Solomon (RS) coding to obtain symbol pair boundaries, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8 * p; convolution interleaving is performed on the p first data streams according to the obtained symbol pair boundaries.

2. A data processing method, characterized by, The method comprises the following steps: p:q symbol demultiplexing and alignment mark locking are performed on p first data streams subjected to Reed-Solomon (RS) coding to obtain symbol pair boundaries and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8 * p; q:p symbol multiplexing is performed on the q second data streams to obtain p third data streams; convolution interleaving is performed on the p third data streams according to the obtained symbol pair boundaries.

3. The method according to claim 1 or 2, characterized in that, The p:q symbol demultiplexing and alignment mark locking performed on the p first data streams subjected to Reed-Solomon (RS) coding comprises the following steps: p:q symbol demultiplexing is performed on the p first data streams subjected to Reed-Solomon (RS) coding to obtain q second data streams; alignment mark locking is performed on the q second data streams respectively to obtain symbol pair boundaries.

4. The method according to any one of claims 1 to 3, characterized in that, The p:q symbol demultiplexing comprises p 1:8 symbol demultiplexings, wherein the p 1:8 symbol demultiplexings correspond to the p first data streams one by one.

5. The method of claim 4, wherein, The 1:8 symbol demultiplexing adopts a round-robin manner of distributing 20 bits each time to demultiplex the corresponding first data stream to obtain eight second data streams.

6. The method of claim 5, wherein, The symbol pair boundaries are p, which correspond to the p first data streams one by one.

7. The method of claim 6, wherein, The eight second data streams all achieve alignment mark locking, and the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is the symbol pair boundary.

8. The method of claim 6, wherein, Within a threshold time interval, at least one of the eight second data streams does not achieve alignment mark locking, the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is shifted, 1:8 symbol demultiplexing is performed again to obtain eight second data streams again; alignment mark locking is performed on the eight second data streams obtained again respectively to obtain one symbol pair boundary.

9. The method of claim 8, wherein, The granularity of shifting the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is one bit; or The granularity of shifting the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is 20 * m + 1 bits, wherein m is an integer greater than 0.

10. The method according to any one of claims 1-9, characterized in that, p = 1, 2 or 4.

11. The method according to any one of claims 1-10, characterized in that, The method further comprises the following steps: 1:8 120-bit distribution is performed on the P data streams subjected to convolution interleaving respectively to obtain eight fourth data streams; inner code coding is performed on the eight fourth data streams respectively.

12. The method of claim 11, wherein, The inner code has a code word length of 128 bits, wherein the information bits are 120 bits and the check bits are 8 bits; or the inner code has a code word length of 126 bits, wherein the information bits are 110 bits and the check bits are 16 bits.

13. The method according to any one of claims 1-12, characterized in that, The RS code has a code word length of 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits.

14. The method of claim 13, wherein, The convolution interleaving comprises delaying an input data stream according to r delay lines, the r being an integer greater than 1, each delay line comprising a different number of storage units, the delay line comprising the least number of storage units comprising 0 storage units, the difference between the number of storage units of each adjacent two delay lines being Q, each storage unit being used for storing 40 bits, the Q being an integer greater than or equal to 1.

15. The method of claim 14, wherein, Each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r*40 bits in the data stream output after the convolution interleaving comprises the 40 bits output by each delay line, wherein the 40 bits stored in the storage unit are 4 RS symbols.

16. A data processing apparatus, characterized by: Comprise: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identification locking on p first data streams subjected to Reed-Solomon RS encoding, to obtain symbol pair boundaries, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8*p; the second processing unit is configured to perform convolution interleaving processing on the p first data streams respectively according to the obtained symbol pair boundaries.

17. A data processing apparatus, characterized in that, Comprise: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identification locking on p first data streams subjected to Reed-Solomon RS encoding, to obtain symbol pair boundaries and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8*p; the second processing unit is configured to perform q:p symbol multiplexing on the q second data streams to obtain p third data streams, and perform convolution interleaving processing on the p third data streams respectively according to the obtained symbol pair boundaries.

18. The apparatus of claim 16 or 17, wherein, The first processing unit is specifically configured to: perform p:q symbol demultiplexing on p first data streams subjected to Reed-Solomon RS encoding to obtain q second data streams; perform alignment identification locking on the q second data streams respectively to obtain symbol pair boundaries.

19. The apparatus of any one of claims 16-18, wherein, The p:q symbol demultiplexing comprises p 1:8 symbol demultiplexings, wherein the p 1:8 symbol demultiplexings correspond to the p first data streams one by one.

20. The apparatus of claim 19, wherein, The 1:8 symbol demultiplexing adopts a round-robin manner of distributing 20 bits at a time to demultiplex the corresponding 1 first data stream to obtain 8 second data streams.

21. The apparatus of claim 20, wherein, The symbol pair boundaries are p, which correspond to the p first data streams one by one.

22. The apparatus of claim 21, wherein, The 8 second data streams all achieve alignment identification locking, and the boundary of the 20 bits distributed is the symbol pair boundary.

23. The apparatus of claim 21, wherein, Within a threshold time interval, at least one of the 8 second data streams does not achieve alignment identification locking, and the first processing unit is further configured to shift the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing, re-perform 1:8 symbol demultiplexing to re-obtain 8 second data streams, and perform alignment identification locking on the re-obtained 8 second data streams respectively to obtain 1 symbol pair boundary.

24. The apparatus of claim 23, wherein, The granularity of shifting the boundary of the 20 bits distributed in the 1:8 symbol demultiplexing is 1 bit; or A granularity of shifting a boundary of 20 bits distributed in the 1:8 symbol demultiplexing is 20xm+1 bits, where m is an integer greater than 0.

25. The apparatus of any one of claims 16-24, wherein, P = 1, 2, or 4.

26. The apparatus of any one of claims 16-25, wherein, The second processing unit is further configured to: perform 1:8 K-bit distribution on the p pieces of first data streams respectively according to the obtained symbol pair boundaries to obtain 8×P pieces of fourth data streams, K being an integer greater than 1; perform inner code encoding on the 8×P pieces of fourth data streams respectively.

27. The apparatus of claim 26, wherein, The inner code has a code word length of 128 bits, where information bits are 120 bits and check bits are 8 bits, or the inner code has a code word length of 126 bits, where information bits are 110 bits and check bits are 16 bits.

28. The apparatus of any one of claims 16-27, wherein, The RS has a code word length of 544 symbols, where an information length is 514 symbols, and each symbol contains 10 bits.

29. The apparatus of claim 28, wherein, The convolution interleaving includes delaying input data streams according to r delay lines, r being an integer greater than 1, each delay line including a different number of storage units, the delay line including the least number of storage units including 0 storage units, a difference in the number of storage units between each adjacent two delay lines being Q, each storage unit being configured to store 40 bits, and Q being an integer greater than or equal to 1.

30. The apparatus of claim 29, wherein, Each delay line inputs 40 bits at a time and outputs 40 bits at a time, and r×40 bits in a continuous data stream output after the convolution interleaving include 40 bits output by each delay line, where the 40 bits stored in the storage unit are 4 RS symbols.

31. A chip, characterized by The chip is configured to perform the method of any one of claims 1 to 15.

32. An optical module, characterized by comprising: The optical module includes a processor and an interface, the processor being configured to perform the method of any one of claims 1 to 15, and the optical module being configured to transceive signals through the interface.

33. A communications device, characterized by The sending device includes a host-side device and the optical module of claim 32, the optical module being connected to the host-side device.

34. A communication system, characterized by Comprising: The first communication device and the second communication device, at least one of the first communication device and the second communication device being the communication device of claim 33, the first communication device and the second communication device being connected.

35. A data processing method, characterized by, Comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data streams that have been Reed-Solomon (RS) encoded to obtain symbol pair boundaries and q pieces of second data streams, p being an integer greater than or equal to 1, q being an integer, and q = 8×p; performing 1:8 K-bit distribution on the p pieces of first data streams respectively according to the obtained symbol pair boundaries to obtain 8×P pieces of fourth data streams, K being an integer greater than 1; performing cyclic shifting and inner code encoding on the 8×P pieces of fourth data streams respectively to obtain 8×P pieces of fifth data streams.

36. A data processing method, characterized by, Comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data streams that have been Reed-Solomon (RS) encoded to obtain symbol pair boundaries and q pieces of second data streams, p being an integer greater than or equal to 1, q being an integer, and q = 8×p; performing q:p symbol multiplexing on the q pieces of second data streams to obtain p pieces of third data streams; According to the obtained symbol pair boundary, the p pieces of third data are respectively subjected to K-bit distribution of 1:8 to obtain 8×P pieces of fourth data streams, K being an integer greater than 1; The 8×P pieces of fourth data streams are respectively subjected to cyclic shift and inner code encoding to obtain 8×P pieces of fifth data streams.

37. The method of claim 35 or 36, wherein, The method further comprises: The 8×P pieces of fifth data streams are subjected to 8:1 bit pair interleaving to obtain P pieces of sixth data streams; The P pieces of sixth data streams are modulated to obtain P pieces of modulated data streams.

38. A data processing apparatus, characterized by: Comprise: A first processing unit and a second processing unit; The first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain a symbol pair boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8×p; The second processing unit is configured to perform K-bit distribution of 1:8 on the p pieces of third data according to the obtained symbol pair boundary to obtain 8×P pieces of fourth data streams, K being an integer greater than 1; The 8×P pieces of fourth data streams are respectively subjected to cyclic shift and inner code encoding to obtain 8×P pieces of fifth data streams.

39. A data processing apparatus, characterized by: Comprise: A first processing unit and a second processing unit; The first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain a symbol pair boundary and q pieces of second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 8×p; The second processing unit is configured to perform q:p symbol multiplexing on the q pieces of second data streams to obtain p pieces of third data streams, and perform K-bit distribution of 1:8 on the p pieces of third data according to the obtained symbol pair boundary to obtain 8×P pieces of fourth data streams, K being an integer greater than 1; The 8×P pieces of fourth data streams are respectively subjected to cyclic shift and inner code encoding to obtain 8×P pieces of fifth data streams.

40. The device of claim 38 or 39, wherein, The second processing unit is further configured to: The 8×P pieces of fifth data streams are subjected to 8:1 bit pair interleaving to obtain P pieces of sixth data streams; The P pieces of sixth data streams are modulated to obtain P pieces of modulated data streams.

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