Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application is a data processing method, which can be applied to a cascaded FEC scheme in a 1.6T high-speed transmission scenario. The solution comprises: performing p:q symbol demultiplexing and alignment marker locking on p first data streams that have undergone Reed-Solomon (RS) encoding so as to acquire a four-symbol boundary, wherein p is an integer greater than or equal to 1, q is an integer, and the following condition is met: q=2×p or q=4×p; and on the basis of the acquired four-symbol boundary, performing data processing, including inner code encoding and modulation, on the p first data streams so as to obtain p modulated data streams. In the solution, the four-symbol boundary is provided before inner code encoding, thereby improving the error correction performance of the cascaded FEC scheme.

Description

A data processing method, device and system

[0001] The present application claims priority from the Chinese patent application No. 202410658291.7 filed on May 24, 2024, and entitled "A data processing method, device and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a data processing method, device and system. BACKGROUND

[0003] Under the continuous promotion of 5G, cloud computing, big data, artificial intelligence and other technologies, high-speed optical transmission networks are developing towards large capacity, packetization and intelligentization. Optical communication systems use the amplitude, phase, polarization or frequency of light waves to carry information. Using forward error correction (FEC) encoding to perform error correction encoding on the transmitted data can solve transmission errors, and the receiving end can recover the original data sent by the sending end from the received data. A cascaded FEC transmission scheme is currently proposed, in which a sending device and a sending processing module are connected through a connection unit interface. The sending device performs first FEC encoding on the data to be transmitted, and sends the first FEC encoded data to the sending processing module. The sending processing module performs second FEC encoding on the first FEC encoded data, and generates a corresponding modulation symbol sequence by modulation mapping of the second FEC encoded bit sequence, and finally generates an optical signal according to the modulation symbol sequence and transmits it to the receiving end through an optical fiber. The first FEC encoding is also called outer code encoding, and the second FEC encoding is also called inner code encoding. The modulation mapping is also called symbol mapping.

[0004] Generally, the sending processing module also performs interleaving before the second FEC encoding to disrupt the data order, thereby enhancing the error correction performance of the cascaded FEC scheme. For the first FEC encoded data received by the sending processing module, the symbol boundary of the first FEC encoding in the received data needs to be obtained. Using the obtained symbol boundary, the interleaving can be processed based on multiple symbols of the first FEC encoding as granularity, thereby making the cascaded FEC scheme have good error correction performance.

[0005] In the prior art, for 1.6TBASE-R inner code coding (Inner FEC) and its client sublayer being 1.6TBASE-R 8:8 symbol-multiplexing (SM) based physical media attachment (PMA), the physical media attachment layer (also referred to as 1.6TBASE-R 8:8 SM-PMA) does not provide symbol boundaries. The PMA layer does not provide symbol boundaries, which affects the error correction performance of the overall concatenated FEC scheme and is a problem to be solved. SUMMARY

[0006] Embodiments of the present application provide a data processing method, device and system, so that the outer code symbol boundary can be obtained before inner code coding, to achieve better concatenated FEC error correction performance and be applied to more transmission scenarios.

[0007] In a first aspect, embodiments of the present application provide a data processing method, comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data stream subjected to Reed-Solomon RS coding to obtain a four-symbol boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2xp or q = 4xp; and performing data processing including inner code coding and modulation on the p pieces of first data stream according to the obtained four-symbol boundary to obtain p pieces of modulated data stream.

[0008] In a second aspect, embodiments of the present application provide a data processing method, comprising: performing p:q symbol demultiplexing and alignment identification locking on p pieces of first data stream subjected to Reed-Solomon RS coding to obtain a four-symbol boundary and q pieces of second data stream, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2xp or q = 4xp; performing q:p symbol multiplexing on the q pieces of second data stream to obtain p pieces of third data stream; and performing data processing including inner code coding and modulation on the p pieces of third data stream according to the obtained four-symbol boundary to obtain p pieces of modulated data stream.

[0009] In the above embodiments of the present application, the four-symbol boundary is obtained before inner code coding, and the four-symbol boundary is used to ensure that the information bits in the inner code coding contain an integer number of RS symbols, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0010] In a first possible implementation manner of the above aspect, the p pieces of first data streams subjected to Reed-Solomon RS encoding are subjected to p:q symbol demultiplexing and alignment identification locking, specifically including: performing p:q symbol demultiplexing on the p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain q pieces of second data streams; and performing alignment identification locking on the q pieces of second data streams respectively to obtain four-symbol boundaries.

[0011] In a second possible implementation manner of the above aspect, q=2×p, and the p:q symbol demultiplexing includes p pieces of 1:2 symbol demultiplexing, where the p pieces of 1:2 symbol demultiplexing correspond to the p pieces of first data streams one by one; or q=4×p, and the p:q symbol demultiplexing includes p pieces of 1:4 symbol demultiplexing, where the p pieces of 1:4 symbol demultiplexing correspond to the p pieces of first data streams one by one. This embodiment gives two specific implementation manners of demultiplexing, which are simple to implement.

[0012] In a third possible implementation manner of the above aspect, the 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding piece of first data stream to obtain two pieces of second data streams; or the 1:4 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding piece of first data stream to obtain four pieces of second data streams. It should be understood that the round-robin manner of 40 bits can match the four-symbol boundary, which is used for alignment identification locking of each piece of second data stream, so as to obtain the four-symbol boundary of the corresponding piece of first data stream.

[0013] In a fourth possible implementation manner of the above aspect, the four-symbol boundary is p, which corresponds to the p pieces of first data streams one by one.

[0014] In a fifth possible implementation manner of the above aspect, all the second data streams obtained in any one of the 1:2 symbol demultiplexing and the 1:4 symbol demultiplexing are subjected to alignment identification locking, and the boundary of the 40 bits distributed is a four-symbol boundary.

[0015] In a seventh possible implementation of the fourth possible implementation of the above aspect, in the sixth possible implementation of the above aspect, q=4xp, within the threshold time interval, at least one of the four second data streams fails to achieve the alignment marker lock, the 40-bit boundary distributed in the 1:4 symbol demultiplexing is shifted, 1:4 symbol demultiplexing is performed again to reacquire the four second data streams, and the reacquired four second data streams are subjected to the alignment marker lock respectively to acquire one four-symbol boundary. This embodiment gives another complete process of acquiring the four-symbol boundary. Only when all the second data streams achieve the alignment marker lock can the correct four-symbol boundary be acquired.

[0016] In a seventh possible implementation of the fourth possible implementation of the above aspect, in the sixth possible implementation of the above aspect, q=4xp, within the threshold time interval, at least one of the four second data streams fails to achieve the alignment marker lock, the 40-bit boundary distributed in the 1:4 symbol demultiplexing is shifted, 1:4 symbol demultiplexing is performed again to reacquire the four second data streams, and the reacquired four second data streams are subjected to the alignment marker lock respectively to acquire one four-symbol boundary. This embodiment gives another complete process of acquiring the four-symbol boundary. Only when all the second data streams achieve the alignment marker lock can the correct four-symbol boundary be acquired.

[0017] In an eighth possible implementation of the sixth or seventh possible implementation of the above aspect, a granularity of the shifting of the distributed 40-bit boundary is 1 bit, or a granularity of the shifting of the distributed 40-bit boundary is 40xm+1 bits, where m is an integer greater than 0. The embodiments of the present application give various shifting granularities, which can match the processing bit width of specific hardware, are relatively simple to implement, and have low complexity.

[0018] In a ninth possible implementation of the above aspect, p=8 and q=16, or p=4 and q=16.

[0019] In a tenth possible implementation of the above aspect, a code word length of the inner code is 128 bits, where the information bits are 120 bits and the check bits are 8 bits, or a code word length of the inner code is 126 bits, where the information bits are 110 bits and the check bits are 16 bits.

[0020] In conjunction with the foregoing aspects and possible implementations thereof, in the eleventh possible implementation of the foregoing aspects, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols comprise 40 bits.

[0021] In conjunction with the eleventh possible implementation of the above aspects, in the twelfth possible implementation of the above aspects, each of the first data streams is further subjected to convolutional interleaving before being encoded by the internal code. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0022] In conjunction with the twelfth possible implementation of the above aspects, in the thirteenth possible implementation of the above aspects, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r×40 bits in the output data stream after convolution and interleaving include the 40 bits output by each delay line.

[0023] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0024] In conjunction with the foregoing aspects and possible implementations thereof, in the fifteenth possible implementation of the foregoing aspects, the modulation employs four-level pulse amplitude PAM4 modulation.

[0025] Thirdly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by Reed-Solomon RS to obtain four symbol boundaries, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; the second processing unit is configured to perform data processing including internal code encoding and modulation on the p first data streams according to the obtained four symbol boundaries to obtain p modulated data streams.

[0026] In a fourth aspect, an embodiment of the present application provides a data processing apparatus, comprising: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p first data streams that have been Reed-Solomon (RS) encoded, to obtain a four-symbol boundary and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2xp or q = 4xp; the second processing unit is configured to perform q:p symbol multiplexing on the q second data streams, to obtain p third data streams; and further configured to perform data processing including inner code encoding and modulation on the p third data streams according to the obtained four-symbol boundary, to obtain p modulated data streams.

[0027] In the above embodiment of the present application, the data processing apparatus obtains the four-symbol boundary before performing the inner code encoding, and uses the four-symbol boundary to ensure that the information bits in the inner code encoding contain an integer number of RS symbols, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0028] In combination with the above aspect, in a first possible implementation manner of the above aspect, the first processing unit is specifically configured to: perform p:q symbol demultiplexing on the p first data streams that have been RS encoded, to obtain the q second data streams; and perform alignment mark locking on the q second data streams respectively, to obtain the four-symbol boundary.

[0029] In combination with the above aspect and possible implementation manners of the above aspect, in a second possible implementation manner of the above aspect, q = 2xp, and the p:q symbol demultiplexing includes p pieces of 1:2 symbol demultiplexing, wherein the p pieces of 1:2 symbol demultiplexing correspond to the p first data streams one by one; or q = 4xp, and the p:q symbol demultiplexing includes p pieces of 1:4 symbol demultiplexing, wherein the p pieces of 1:4 symbol demultiplexing correspond to the p first data streams one by one. This embodiment gives two specific implementation manners of demultiplexing, which are simple to implement.

[0030] In combination with the second possible implementation manner of the above aspect, in a third possible implementation manner of the above aspect, the 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time, to demultiplex the corresponding 1 first data stream, to obtain 2 second data streams; or the 1:4 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time, to demultiplex the corresponding 1 first data stream, to obtain 4 second data streams. It should be understood that the round-robin manner of 40 bits can match the four-symbol boundary, and is used for performing alignment mark locking on each of the second data streams, to obtain the four-symbol boundary of the corresponding 1 first data stream.

[0031] In a fourth possible implementation of the above aspect, in combination with the above aspect and possible implementation of the above aspect, the four-symbol boundary corresponds to one of the p first data streams.

[0032] In a fifth possible implementation of the above aspect, in combination with the fourth possible implementation of the above aspect, all the second data streams obtained in either of the 1:2 symbol demultiplexing and the 1:4 symbol demultiplexing are subjected to alignment identification locking, and the 40-bit boundary distributed is a four-symbol boundary.

[0033] In a sixth possible implementation of the above aspect, in combination with the fourth possible implementation of the above aspect, q=2×p, and at least one of the two second data streams fails to achieve alignment identification locking within a threshold time interval, and the first processing unit is further configured to shift the 40-bit boundary distributed in the 1:2 symbol demultiplexing, re-perform 1:2 symbol demultiplexing to obtain two second data streams again, and perform alignment identification locking on the two second data streams obtained again respectively to obtain one four-symbol boundary. This embodiment provides a complete process of obtaining a four-symbol boundary, and only when all the second data streams achieve alignment identification locking can a correct four-symbol boundary be obtained.

[0034] In a seventh possible implementation of the above aspect, in combination with the fourth possible implementation of the above aspect, q=4×p, and at least one of the four second data streams fails to achieve alignment identification locking within a threshold time interval, and the first processing unit is further configured to shift the 40-bit boundary distributed in the 1:4 symbol demultiplexing, re-perform 1:4 symbol demultiplexing to obtain four second data streams again, and perform alignment identification locking on the four second data streams obtained again respectively to obtain one four-symbol boundary. This embodiment provides another complete process of obtaining a four-symbol boundary, and only when all the second data streams achieve alignment identification locking can a correct four-symbol boundary be obtained.

[0035] In an eighth possible implementation of the above aspect, in combination with the sixth or seventh possible implementation of the above aspect, a granularity of shifting the 40-bit boundary distributed is 1 bit, or a granularity of shifting the 40-bit boundary distributed is 40×m+1 bits, where m is an integer greater than 0. Embodiments of the present application provide multiple shifting granularities, which can match a specific hardware implementation processing bit width, achieve relatively simple, and have relatively low complexity.

[0036] In a ninth possible implementation of the above aspect, in combination with the above aspect and possible implementation of the above aspect, p=8 and q=16, or p=4 and q=16.

[0037] In a tenth possible implementation form of the above aspect and possible implementation forms thereof, the inner code has a code word length of 128 bits, wherein the information bits are 120 bits and the check bits are 8 bits; or the inner code has a code word length of 126 bits, wherein the information bits are 110 bits and the check bits are 16 bits.

[0038] In an eleventh possible implementation form of the above aspect and possible implementation forms thereof, the RS has a code word length of 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols include 40 bits.

[0039] In a twelfth possible implementation form of the above eleventh possible implementation form of the above aspect, the second processing unit is further configured to perform convolution interleaving on the received data stream, the convolution interleaving comprising delaying the input data stream according to r delay lines, the r being an integer greater than 1, each delay line including a different number of storage units, the delay line including the least number of storage units including 0 storage units, a difference between the number of storage units of each adjacent two delay lines being Q, each storage unit being configured to store 40 bits, the Q being an integer greater than or equal to 1.

[0040] In a thirteenth possible implementation form of the above twelfth possible implementation form of the above aspect, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and r x 40 bits in the output data stream after the convolution interleaving include the 40 bits output by each delay line.

[0041] In a fourteenth possible implementation form of the above eleventh possible implementation form of the above aspect, the 40 bits stored in each storage unit in the convolution interleaving are 4 RS symbols. In this case, it can be ensured that the 12 consecutive RS symbols output by the convolution interleaver come from 12 different RS code words, so that the concatenated FEC has better decoding performance.

[0042] In a fifteenth possible implementation form of the above aspect and possible implementation forms thereof, the modulation adopts four-level pulse amplitude modulation (PAM4) modulation.

[0043] In some possible implementation forms, the data processing apparatus provided by the embodiments of the present application is applied to scenarios including Ethernet, optical transport network, and space optical communication, etc.

[0044] In a fifth aspect, the embodiments of the present application provide a chip, which is configured to perform the method according to any of the embodiments of the first aspect or the second aspect.

[0045] In a sixth aspect, an embodiment of the present application provides an optical module. The optical module comprises a processor and an interface. The processor is configured to perform the method according to any one of the embodiments of the first aspect or the second aspect, and the interface is configured to transmit a signal from the processor or transmit a received signal to the processor.

[0046] In a seventh aspect, an embodiment of the present application provides a communication device. The communication device comprises a host device and an optical module according to any one of the embodiments of the sixth aspect. The optical module is connected to the host device.

[0047] In an eighth aspect, an embodiment of the present application provides another device. The device comprises a processor and an interface. The processor is configured to perform the method according to any one of the embodiments of the first aspect or the second aspect, and the interface is configured to transmit a signal from the processor or transmit a received signal to the processor. The device can be a router, a switch, a server, an optical transport network device, or the like.

[0048] In a ninth aspect, an embodiment of the present application provides a communication system. The communication system comprises a first communication device and a second communication device. At least one of the first communication device and the second communication device is the communication device according to any one of the embodiments of the seventh aspect. The first communication device and the second communication device are connected.

[0049] In a tenth aspect, an embodiment of the present application provides a computer readable storage medium. The computer readable storage medium stores instructions. When the instructions are executed by a computer, the method according to any one of the embodiments of the first aspect or the second aspect is implemented.

[0050] In an eleventh aspect, an embodiment of the present application provides a computer program product. The computer program product comprises program instructions. When the computer program product is executed, the method according to any one of the embodiments of the first aspect or the second aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0051] FIG. 1 is a schematic diagram of a communication system to which an embodiment of the present application is applied;

[0052] FIG. 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1;

[0053] FIG. 3 is a schematic diagram of another communication system to which an embodiment of the present application is applied;

[0054] FIG. 4 is a flowchart of a data processing method according to an embodiment of the present application;

[0055] FIG. 5(a) is a flowchart of acquiring a four-symbol boundary according to an embodiment of the present application;

[0056] Fig. 5(b) is a flow chart of a specific method for obtaining four-symbol boundary according to an embodiment of the present application;

[0057] Fig. 5(c) is a flow chart of another specific method for obtaining four-symbol boundary according to an embodiment of the present application;

[0058] Fig. 6(a) is a structure diagram of a convolution interleaving process according to an embodiment of the present application;

[0059] Fig. 6(b) is a structure diagram of another convolution interleaving process according to an embodiment of the present application;

[0060] Fig. 7 is a structure diagram of a data processing architecture according to an embodiment of the present application;

[0061] Fig. 8 is a structure diagram of another data processing architecture according to an embodiment of the present application;

[0062] Fig. 9 is a structure diagram of yet another data processing architecture according to an embodiment of the present application;

[0063] Fig. 10 is a structure diagram of still another data processing architecture according to an embodiment of the present application;

[0064] Fig. 11 is a structure diagram of a data processing device according to an embodiment of the present application;

[0065] Fig. 12 is a structure diagram of an optical module according to an embodiment of the present application;

[0066] Fig. 13 is a structure diagram of a communication device according to an embodiment of the present application. DETAILED DESCRIPTION

[0067] The embodiments of the present application provide a data processing method, device and system, which can obtain outer code symbol boundary before inner code encoding, so as to realize better performance of concatenated FEC error correction, and can be applied to more transmission scenarios.

[0068] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and in the above drawings are intended to distinguish similar objects, not to imply a specific order or sequence. It should be understood that the above terms are interchangeable under appropriate circumstances so that the embodiments described herein can be implemented in other sequences than those described herein. Moreover, the terms "comprise", "have" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device that includes a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products or devices.

[0069] FIG. 1 is a schematic diagram of a communication system to which embodiments of the present application are applied. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be a switch, a router, or a server, and the sending device 01 is also referred to as a client device at the sending end, and the receiving device 05 is also referred to as a client device at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client device is also referred to as a host device. The client device includes a client chip and an interface. The client chip is also referred to as a host chip. The connection interface between the sending device 01 and the sending processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The sending processing module 02 and the receiving processing module 04 can be an optical module, an electrical module, a connector, or other modules that process data during data transmission. For example, the processing module can be a DR optical module or a FR optical module or a LR optical module, such as a 1.6T FR1 coherent optical module (referred to as a 1.6T FR coherent optical module), a 1.6T LR1 coherent optical module (referred to as a 1.6T LR coherent optical module), a 1.6T ZR coherent optical module, and the like. Moreover, the sending device 01, the sending processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not limited here.

[0070] FIG. 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1. As shown in FIG. 2, in the process of transmitting data from the sending device 01 to the receiving device 05, the sending device 01 is configured to perform outer code encoding on the data, and then transmit the data encoded by the outer code to the sending processing module 02. The sending processing module 02 is configured to perform inner code encoding on the data encoded by the outer code, to obtain data encoded by the outer code and the inner code, and transmit the data encoded by the outer code and the inner code to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the data encoded by the outer code and the inner code to the receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the data encoded by the outer code and the inner code, and transmit the data decoded by the inner code to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the data decoded by the inner code.

[0071] It should be understood that the "inner" in the inner code and the "outer" in the outer code are only distinguished based on the distance of the execution subject operating on the data relative to the channel transmission medium 03. The execution subject operating on the inner code is closer to the channel transmission medium, and the execution subject operating on the outer code is farther away from the channel transmission medium. In the embodiments of the present application, since the data is transmitted from the sending end device 01 to the channel transmission medium 03 through the sending end processing module 02, and then transmitted from the channel transmission medium 03 to the receiving end device 05 through the receiving end processing module 04. The data encoded by the sending end device 01 is farther away from the channel transmission medium 03 than the data encoded by the sending end processing module 02, and the data decoded by the receiving end device 05 is farther away from the channel transmission medium 03 than the data decoded by the receiving end processing module 04. Therefore, the data encoded by the sending end device 01 is called data encoded by the outer code, the data encoded by the sending end processing module 02 is called data encoded by the inner code, the data decoded by the receiving end device 05 is called data decoded by the outer code, and the data decoded by the receiving end processing module 04 is called data decoded by the inner code. In a possible implementation, the inner code encoding and the outer code encoding described above are both in the form of FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the sending end device 01 can perform outer code encoding using Reed-solomon (RS) code, and the sending end processing module 02 can perform inner code encoding using Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can perform inner code encoding using Bose-Chaudhuri-Hocquenghem (BCH) code. The BCH code that can correct a single error is equivalent to Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can also perform inner code encoding using Polar code. In some specific application scenarios, the sending end device 01 can perform outer code encoding using RS (544, 514) code, also known as KP4 code.

[0072] FIG. 3 is a schematic diagram of another communication system to which embodiments of the present application are applied. As shown in FIG. 3, the communication system includes a sending device 01, a channel transmission medium 03, and a receiving device 05. The sending device 01 performs outer code encoding and inner code encoding on data, and the data after outer code encoding and inner code encoding is sent to the channel transmission medium 03. The receiving device 05 performs inner code decoding and outer code decoding on the data received from the channel transmission medium 03. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be switches, routers, servers, or the like, and the sending device 01 is also referred to as a client-side device or a host device at the sending end, and the receiving device 05 is also referred to as a client-side chip at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host chip. The sending device 01, the channel transmission medium 03, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not limited here. That is, the sending device 01 shown in FIG. 3 also integrates the functions of the sending processing module 02 shown in FIG. 2, and the receiving device 05 shown in FIG. 3 also integrates the functions of the receiving processing module 04 shown in FIG. 2. At this time, the sending device 01 can also use linear-drive pluggable optics (LPO) technology, co-packaged optics (CPO) technology, or near packaged optics (NPO) technology.

[0073] It should also be noted that the above is an exemplary description of the application scenarios of the data processing method provided by the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. Those skilled in the art can know that the application scenarios can be adjusted according to application requirements as the business requirements change, and the embodiments of the present application do not enumerate them one by one.

[0074] FIG. 4 is a flowchart of a data processing method provided by an embodiment of the present application. It should be understood that the data processing method is applied to a sending end, for example, can be implemented by the sending processing module 02 shown in FIG. 2, or can be implemented by the sending device 01 shown in FIG. 3.

[0075] 101. Perform p:q symbol demultiplexing and alignment identification locking on the p pieces of first data stream after RS encoding, to obtain a four-symbol boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2xp or q = 4xp.

[0076] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols, also known as external code RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols come from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2.

[0077] In some specific applications, for 1.6T transmission scenarios, such as under 1.6TBASE-R internal encoding, p=8. The p=8 first data streams are obtained by processing 8 AUI data streams of 1.6TAUI-8 using 1.6TBASE-R 8:8SM-PMA. In this case, the nominal rate of each data stream in the p=8 first data streams is 212.5 Gbits per second (b / s). Furthermore, each a in each first data stream... RS = 4 adjacent RS symbols from a RS = 4 RS codewords. The 8 AUI data streams of the 1.6TAUI-8 are obtained by processing 16 Physical Coding Sublayer lane (PCSL) data streams through 1.6TBASE-R 16:8SM-PMA. In the 16 PCSL data streams, every 4 adjacent RS symbols come from 4 different RS codewords.

[0078] In other specific applications, for 1.6T transmission scenarios, such as under 1.6TBASE-R internal code encoding, p=4. The p=4 first data streams are obtained by processing four AUI data streams of 1.6TAUI-4 using 1.6TBASE-R 4:4SM-PMA. In this case, the nominal rate of each data stream in the p=4 first data streams is 425 Gbits per second (b / s). Furthermore, each a in each first data stream... RS = 4 adjacent RS symbols from a RS= 4 RS codewords. The 4 AUI data streams of the 1.6T AUI-4 are obtained by processing 16 PCSL data streams through a 1.6T BASE-R 16:4 SM-PMA. Every 4 adjacent RS symbols in the 16 PCSL data streams come from 4 different RS codewords.

[0079] It should be noted that in some specific applications, the p first data streams are also called p PMA data streams.

[0080] As shown in FIG. 5(a), p:q symbol demultiplexing is performed on the p first data streams to obtain q second data streams. The cases of q = 2xp and q = 4xp are introduced respectively below.

[0081] 1) For the case of q = 2xp:

[0082] As shown in FIG. 5(b), the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, and each 1:2 symbol demultiplexing corresponds to one first data stream. Each 1:2 symbol demultiplexing adopts a round-robin method of distributing 40 bits at a time to demultiplex 1 first data stream inputted thereby to obtain 2 second data streams outputted.

[0083] Alignment marker lock is performed on the q second data streams respectively. Here, the alignment marker lock is also referred to as alignment lock. The alignment marker lock is performed by using a known alignment marker (AM) in the PCSL data stream.

[0084] It should be noted that the 2 second data streams can achieve alignment marker lock only when the 40 bits distributed in the above 1:2 symbol demultiplexing correspond to 4 symbols (i.e. 4 outer code RS symbols), that is, the boundary of the 40 bits corresponds to the boundary of the 4 symbols. Here, achieving alignment marker lock means that the alignment marker is correctly locked. At this time, the boundary of the 40 bits distributed is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, that is, p four-symbol boundaries correspond to p first data streams.

[0085] It is noted that when the 2 output second data streams do not achieve alignment marker lock in a certain time interval, which can also be referred to as a threshold time interval, or a certain bit interval (for example, 222,822,400 bits), which can also be referred to as a threshold bit interval, the 40-bit boundary in the 1:2 symbol demultiplexing is shifted, which is also referred to as slippage. In some specific applications, the 40-bit boundary in the 1:2 symbol demultiplexing is slipped by one bit. In other specific applications, the 40-bit boundary in the 1:2 symbol demultiplexing is slipped by more than one bit, and in this case, it is necessary to ensure that all possible boundaries are evaluated, and it can be slipped by 40×m+1 bits, m is an integer greater than 0, for example, 41 bits or 81 bits, etc. When the shift interval matches the bit width of the specific hardware implementation, it is relatively simple to implement and has low complexity. The above shift operation is performed until all 2 output second data streams achieve alignment marker lock.

[0086] When the 2 second data streams output by the 1:2 symbol demultiplexing achieve alignment marker lock, four-symbol lock is achieved, and at the same time, four-symbol boundaries corresponding to the first data stream are obtained.

[0087] 2) For the case of q=4×p:

[0088] As shown in FIG. 5(c), the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, and the p 1:4 symbol demultiplexings correspond to p first data streams one by one. Each 1:4 symbol demultiplexing uses a round-robin method of distributing 40 bits at a time to demultiplex the 1 first data stream input thereby to obtain 4 output second data streams.

[0089] The q second data streams are respectively subjected to alignment marker lock processing. Here, the alignment marker lock is also referred to as alignment lock.

[0090] The 4 output second data streams achieve alignment marker lock only when the 40-bit boundary corresponds to the 4-symbol boundary in the 1:4 symbol demultiplexing. Here, achieving alignment marker lock means that the alignment marker is correctly locked. At this time, the 40-bit boundary is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, i.e., p four-symbol boundaries correspond to p first data streams.

[0091] When the 4 output second data streams do not achieve alignment marker lock in a certain time interval, also referred to as a threshold time interval, or a certain bit interval (for example, 222,822,400 bits), also referred to as a threshold bit interval, the 40-bit boundary in the 1:4 symbol demultiplexing is shifted, also referred to as slippage. In some specific applications, the 40-bit boundary in the 1:4 symbol demultiplexing is slipped by one bit. In other specific applications, the 40-bit boundary in the 1:4 symbol demultiplexing is slipped by more than one bit, and at this time, it is necessary to ensure that all possible boundaries are evaluated. The 40-bit boundary can be slipped by 40xm+1 bits, m is an integer greater than 0, for example, 41 bits or 81 bits, etc. When the shift interval matches the processing bit width of specific hardware implementation, the implementation is relatively simple and has low complexity. The above shift operation is performed until all 4 output second data streams achieve alignment marker lock.

[0092] When the 2 output second data streams of the 1:2 symbol demultiplexing achieve alignment marker lock, i.e., four-symbol lock is achieved, the four-symbol boundary corresponding to the first data stream is also obtained.

[0093] For the case of q = 2xp and q = 4xp, when the q second data streams all achieve the alignment identification locking, the four-symbol (symbol-quartet) locking is achieved, and the four-symbol boundary (symbol-quartet boundary) corresponding to each first data stream is also obtained. The four-symbol boundary can be referred to as a symbol boundary. At this time, the q second data streams are q PCSL data streams. The adjacent 4 RS symbols in the q second data streams come from 4 different RS code words. More specifically, for a second data stream, the symbols in the data stream are represented in the form of A, B, C, D, A, B, C, D, …, starting from the alignment identification, where A, B, C, and D represent one RS symbol in 4 different code words.

[0094] It should be noted that each a RS = 4 adjacent RS symbols come from a RS = 4 different RS code words, and the four-symbol boundary corresponding to the first data stream is obtained, so that the adjacent 4 RS symbols in the first data stream are obtained.

[0095] 102. According to the obtained four-symbol boundary, the p first data streams are subjected to data processing including inner code encoding and modulation to obtain p modulated data streams.

[0096] According to the obtained four-symbol boundary, 40 adjacent (also referred to as continuous) bits in each first data stream corresponding to 4 RS symbols can be obtained. More specifically, the 4 RS symbols come from 4 different RS code words. The 4 RS symbols are also referred to as RS FEC symbol quartets (RS-FEC-symbol-quartet).

[0097] The following describes the inner code encoding mode by taking one first data stream as an example. Specifically, K information bits in the first data stream are subjected to inner code encoding to generate N-K check bits, so as to obtain an inner code word including N bits, where 1 < K < N. In this application, K is considered to be a multiple of 10. In combination with the obtained four-symbol boundary, the K information bits in each inner code word correspond to K / 10 outer code RS symbols.

[0098] In some embodiments, the K information bits in each inner code codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords, so that the FEC concatenation scheme including RS encoding and inner code encoding has optimal performance. For example, the inner code encoding uses BCH (126, 110), the K = 110 information bits in each inner code codeword correspond to K / 10 = 11 outer code symbols, and the corresponding K / 10 = 11 outer code symbols come from K / 10 = 11 different outer code RS codewords. For another example, the inner code encoding uses a linear block code with N = 128 and K = 120, the K = 120 information bits in each inner code codeword correspond to K / 10 = 12 outer code symbols, and the corresponding K / 10 = 12 outer code symbols come from K / 10 = 12 different outer code RS codewords. In order to make the K information bits in each inner code codeword correspond to K / 10 different outer code RS codewords, the first data stream is further subjected to convolution interleaving processing before inner code encoding. The convolution interleaving processing will be described in detail below.

[0099] Specifically, the convolution interleaver for performing convolution interleaving processing includes r delay lines, each of which includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage unit, and the difference in the number of storage units between each adjacent two delay lines is Q, where r is an integer greater than 1, and Q is an integer greater than or equal to 1. Each storage unit is used to store d bits, and d is an integer greater than or equal to 1. The bits in the input data stream of the convolution interleaver are sequentially input to the r delay lines according to the order of the r delay lines, d bits are input from each delay line at a time, and d bits are output from each delay line at a time. In some embodiments, the convolution interleaver outputs d bits at a time. In other embodiments, the convolution interleaver outputs rxd bits at a time, the rxd bits come from the r delay lines, and include the d bits output from each delay line. The rxd bits in the data stream output by the convolution interleaver include the d bits output from each delay line.

[0100] It should be understood that the r delay lines respectively include 0 storage units, Q storage units, 2Q storage units, …, (r-1)Q storage units, and each storage unit is used to store d bits. The r delay lines respectively correspond to r delay values, and the delay values include 0 bits, Qxd bits, 2Qxd bits, …, (r-1)Qxd bits. The more bits included in the delay value of a delay line, the longer the delay (also referred to as time delay) of the delay line to the data stream. It should be understood that when a delay line does not include a storage unit, the delay of the delay line is 0 bits, i.e., no delay transmission. It should be understood that the storage unit described above is also referred to as a delay element.

[0101] Figure 6(a) is a schematic diagram of a first structure of convolution interleaving processing in embodiments of the present application. As shown in Figure 6(a), the number of storage units in each of the r delay lines decreases by Q in sequence according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each of the delay lines decreases by Q storage units in sequence, and delay line r-1 has 0 storage unit. Figure 6(b) is a schematic diagram of a second structure of convolution interleaving processing in embodiments of the present application. As shown in Figure 6(b), the number of storage units in each of the r delay lines increases by Q in sequence according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage unit, each of the delay lines increases by Q storage units in sequence, and delay line r-1 has (r-1)Q storage units.

[0102] It should be noted that, at the same time, the switch of the convolution interleaver input and output is located on the same delay line, and after the current delay line is single-inputted with d bits and single-outputted with d bits, the switch is switched to the next delay line, so as to ensure that the bits in the input data stream are inputted into the r delay lines in sequence according to the sequence number of the r delay lines, and the continuous rxd bits in the output data stream include the d bits outputted by each delay line. The specific data reading and writing operation is as follows: reading out d bits from the storage unit closest to the output port of the current delay line; transferring the d bits stored in each storage unit of the current delay line to the next storage unit. Then, writing the d bits into the storage unit closest to the input port of the current delay line. Then, the switch is switched to the next delay line and the above operation is repeated, and the same is true for the next delay line.

[0103] It should be understood that, when the same parameters r, Q and d are adopted, the convolution interleaving processing of Figure 6(a) and the convolution interleaving processing of Figure 6(b) are inverse operations of each other. That is, when the convolution interleaving structure shown in Figure 6(a) is adopted by the sending processing module, the convolution de-interleaving corresponding to the receiving processing module adopts the structure shown in Figure 6(b). Similarly, when the convolution interleaving structure shown in Figure 6(b) is adopted by the sending processing module, the convolution de-interleaving corresponding to the receiving processing module adopts the structure shown in Figure 6(a).

[0104] Typically, the number of bits stored in each storage unit is d=a RS ×10=40. According to the obtained four-symbol boundary, the 40 bits stored in each storage unit come from the continuous 40 bits in one first data stream, which correspond to 4 RS symbols. The 4 RS symbols come from 4 different RS codewords.

[0105] After the p first data streams are subjected to inner code encoding, modulation is performed to obtain p modulated data streams. In some specific applications, the modulation adopts four-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM4).

[0106] In the embodiments of the present application, the data processing flow can be divided into two parts. The first data processing can include p:q symbol demultiplexing and alignment marker locking. The second data processing can include at least one of 1:8 K-bit distribution, cyclic shift, 8:1 bit-pair interleaving, pad insertion, and precoding in addition to inner code encoding and modulation.

[0107] It should be noted that in some specific applications, the convolution interleaving operation can be bypassed so that the overall cascaded FEC scheme has a lower latency and can be applied in application scenarios that require low latency.

[0108] The following provides several embodiments to introduce the possible values of p by taking an inner code encoding using a linear block code with N=128 and K=120 as an example.

[0109] Embodiment 1: Considering 1.6TBASE-R inner code encoding, p=8 and q=2xp=16.

[0110] As shown in FIG. 7, the 8 AUI data streams of the 1.6TAUI-8 are subjected to 1.6TBASE-R 8:8 SM-PMA processing to obtain p=8 first data streams. The p=8 first data streams are subjected to 8:16 symbol demultiplexing and alignment marker locking to obtain four-symbol boundaries (also referred to as 4 symbol boundaries) of the p=8 first data streams. The 8:16 symbol demultiplexing includes p=8 1:2 symbol demultiplexing as shown in FIG. 5(b). Each 1:2 symbol demultiplexing uses a round-robin method of distributing 40 bits at a time to demultiplex 1 first data stream input to obtain 2 second data streams output.

[0111] According to the obtained four-symbol boundaries, the p=8 first data streams are subjected to second data processing including inner code encoding and PAM4 modulation to obtain p=8 PAM4 modulated data streams. The second data processing can include convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit-pair interleaving, pad insertion, and PAM4 modulation.

[0112] The convolution interleaver includes r=3 delay lines, the difference of the number of storage units of each adjacent two delay lines is Q=24, and each storage unit is used for storing d=40 bits. According to the obtained four-symbol boundary, the d=40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained four-symbol boundary, the cyclic shift is a cyclic shift operation on 12 symbols in 120 information bits with symbol as granularity.

[0113] It should be noted that in the embodiment, as shown in FIG. 7, the p=8 first data streams after the second data processing are obtained by the second data processing to obtain p=8 PAM4 data streams. In the data processing performed for each first data stream, the 1024-bit padding is performed after the inner code encoding operation, or the 120-bit padding can be inserted before the inner code encoding. At this time, the 8 inner code pre-data streams are periodically inserted with 120-bit padding, and each group of 120 bits is encoded to obtain 128-bit padding after the inner code encoding. After the 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0114] In the embodiment, the four-symbol boundary is obtained before the inner code encoding, and the four-symbol boundary is used to make the 120 information bits in the inner code (128, 120) encoding come from 12 different RS code words, so that the cascaded FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0115] Embodiment 2: Considering 1.6TBASE-R inner code encoding, p=4 and q=4xp=16.

[0116] As shown in FIG. 8, the 4 AUI data streams of the 1.6TAUI-4 are processed by the 1.6TBASE-R 4:4SM-PMA to obtain p=4 first data streams. The p=4 first data streams are subjected to 4:16 symbol demultiplexing and alignment mark lock to obtain the four-symbol boundary (also referred to as four-symbol boundary) of the p=4 first data streams. The 4:16 symbol demultiplexing includes p=4 1:4 symbol demultiplexing, as shown in FIG. 5(c). Each 1:4 symbol demultiplexing adopts a round-robin manner of distributing 40 bits at a time to demultiplex the input 1 first data stream to obtain 4 output second data streams.

[0117] Based on the obtained four-symbol boundaries, a second data processing step involving internal code encoding and PAM4 modulation is performed on p=4 first data streams to obtain p=4 PAM4 modulated data streams. The second data processing step includes convolutional interleaving, 1:8 120-bit distribution, cyclic shifting, internal code (128,120) encoding, 8:1 bit pair interleaving, padding insertion, and PAM4 modulation.

[0118] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit during convolutional interleaving correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on 12 symbols out of 120 information bits at a symbol-level granularity.

[0119] It should be noted that, in this embodiment, as shown in Figure 8, after the second data processing, p=4 first data streams are processed to obtain p=4 PAM4 data streams. In the data processing of each first data stream, the 1024-bit padding insertion is performed after the internal code encoding operation, or it can be performed before the internal code encoding. In this case, the 8 data streams before internal code encoding periodically insert 120 bits of padding. Each group of 120 bits, after internal code encoding, yields 128 bits of encoded padding. After 8:1 bit pair interleaving, a total of 128 × 8 = 1024 bits of padding are obtained.

[0120] In this embodiment, before internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to make the 120 information bits of the internal code (128,120) come from 12 different RS codewords, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0121] It should be noted that in the above embodiment, the input to the second data processing, which includes internal code encoding, is the p first data streams. In some specific applications, the input to the second data processing can be p data streams obtained by q:p symbol multiplexing of the data stream implementing alignment identifier locking. In this case, another flow of the data processing method is as follows:

[0122] 201. Perform p:q symbol demultiplexing and alignment identifier locking on p first data streams encoded by RS to obtain four-symbol boundaries and obtain q second data streams that implement alignment identifier locking, where p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p;

[0123] 202. q pieces of second data streams are q:p symbol multiplexed to obtain p pieces of third data streams, and the p pieces of third data streams are subjected to a second data processing of inner code encoding and modulation according to the obtained four-symbol boundary, so as to obtain p pieces of modulated data streams.

[0124] For q=2xp, the q:p symbol multiplexing comprises p pieces of 2:1 symbol multiplexing, which corresponds to the p pieces of first data streams. More specifically, one piece of 2:1 symbol multiplexing multiplexes two pieces of second data streams obtained by 1:2 symbol demultiplexing of one piece of first data stream. The one piece of 2:1 symbol multiplexing combines the obtained four-symbol boundary, and adopts a round-robin mode of four symbols (totally containing 40 bits) to multiplex the input two pieces of second data streams to obtain one piece of output third data stream. The p pieces of 2:1 symbol multiplexing multiplex the input q=2xp pieces of second data streams to output p pieces of third data streams.

[0125] For q=4xp, the q:p symbol multiplexing comprises p pieces of 4:1 symbol multiplexing, which corresponds to the p pieces of first data streams. More specifically, one piece of 4:1 symbol multiplexing multiplexes four pieces of second data streams obtained by 1:4 symbol demultiplexing of one piece of first data stream. The one piece of 4:1 symbol multiplexing combines the obtained four-symbol boundary, and adopts a round-robin mode of four symbols (totally containing 40 bits) to multiplex the input four pieces of second data streams to obtain one piece of output third data stream. The p pieces of 4:1 symbol multiplexing multiplex the input q=4xp pieces of second data streams to output p pieces of third data streams.

[0126] It should be noted that in some specific applications, the q pieces of second data streams are subjected to deskewing before being subjected to the q:p symbol multiplexing, so that there is no offset between the deskewed q pieces of second data streams, so as to support accurate calculation of possible path data delay, and the deskewing is also called full deskewing. In other specific applications, the deskewing is based on 40-bit deskewing, that is, there is an offset of d skew bits between the q pieces of second data streams, where d skew is an integer multiple of 40, and the deskewing is also called 40-bit deskewing.

[0127] The following provides several embodiments taking linear block code with N=128 and K=120 as an example to introduce another flow of the above data processing method.

[0128] Embodiment 3: considering 1.6T BASE-R inner code encoding, p = 8 and q = 2xp = 16.

[0129] As shown in FIG. 9, the 8 AUI data streams of 1.6T AUI-8 are processed by 1.6T BASE-R 8:8 SM-PMA to obtain p = 8 first data streams. The p = 8 first data streams are processed by 8:16 symbol demultiplexing and alignment lock to obtain four-symbol boundaries (also referred to as 4 symbol boundaries) of the p = 8 first data streams and obtain q = 16 second data streams. The 8:16 symbol demultiplexing includes p = 8 1:2 symbol demultiplexing, as shown in FIG. 5(b). Each 1:2 symbol demultiplexing demultiplexes 1 first data stream input by it to obtain 2 second data streams output by round-robin distribution of 40 bits at a time.

[0130] The q = 16 second data streams are processed by 16:8 symbol multiplexing to obtain p = 8 third data streams, and the p = 8 third data streams are processed by second data processing including inner code encoding and PAM4 modulation according to the obtained four-symbol boundaries to obtain p = 8 PAM4 modulation data streams. The second data processing includes convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, padding insertion, and PAM4 modulation.

[0131] The convolution interleaver includes r = 3 delay lines, and the number of storage units of each adjacent two delay lines is different by Q = 24, and each storage unit is used to store d = 40 bits. According to the obtained four-symbol boundaries, d = 40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained four-symbol boundaries, the cyclic shift is a cyclic shift operation on 12 symbols in 120 information bits with symbol as granularity.

[0132] It should be noted that in this embodiment, as shown in FIG. 9, the p = 8 first data streams in the second data processing are processed by the second data processing to obtain p = 8 PAM4 data streams. In the data processing of each first data stream, the 1024-bit padding insertion is performed after the inner code encoding operation, or the 120-bit padding insertion can be performed before the inner code encoding. At this time, 8 first data streams before the inner code encoding are periodically inserted with 120-bit padding, and each group of 120 bits is obtained after the inner code encoding to obtain 128-bit padding after the encoding, and after the 8:1 bit pair interleaving, a total of 128x8 = 1024-bit padding is obtained.

[0133] In the embodiment, before the inner code encoding is performed, the four-symbol boundary is obtained, and the second data processing utilizes the four-symbol boundary to make the 120 information bits in the inner code (128, 120) encoding come from 12 different RS code words, so that the concatenated FEC scheme has better error correction performance and can be applied to more transmission scenarios.

[0134] Embodiment 4: Considering 1.6T BASE-R inner code encoding, p = 4 and q = 4xp = 16.

[0135] As shown in FIG. 10, the four AUI data streams of the 1.6T AUI-4 are subjected to 1.6T BASE-R 4:4 SM-PMA processing to obtain p = 4 first data streams. The p = 4 first data streams are subjected to 4:16 symbol demultiplexing and alignment mark locking to obtain four-symbol boundaries (also referred to as 4 symbol boundaries) of the p = 4 first data streams and obtain q = 16 second data streams. The 4:16 symbol demultiplexing includes p = 4 1:4 symbol demultiplexing, as shown in FIG. 5(c). Each 1:4 symbol demultiplexing uses a round-robin method of distributing 40 bits at a time to demultiplex the input 1 first data stream to obtain 4 output second data streams.

[0136] The q = 16 second data streams subjected to the alignment mark locking are subjected to 16:4 symbol multiplexing to obtain p = 4 third data streams, and the p = 4 first data streams are subjected to second data processing including inner code encoding and PAM4 modulation according to the obtained four-symbol boundaries to obtain p = 4 PAM4 modulation data streams. The second data processing includes convolution interleaving, 1:8 120-bit distribution, cyclic shift, inner code (128, 120) encoding, 8:1 bit pair interleaving, padding insertion, and PAM4 modulation.

[0137] The convolution interleaver includes r = 3 delay lines, the number of storage units of each adjacent two delay lines is different by Q = 24, and each storage unit is used to store d = 40 bits. According to the obtained four-symbol boundary, the d = 40 bits stored in each storage unit in the convolution interleaving correspond to 4 RS symbols. Moreover, according to the obtained four-symbol boundary, the cyclic shift is a cyclic shift operation on 12 symbols in the 120 information bits with symbol as granularity.

[0138] It should be noted that in the embodiment, as shown in FIG. 10, the second data processing is performed on the p=4 first data streams to obtain p=4 PAM4 data streams. In the data processing performed on each first data stream, the 1024-bit padding is inserted after the inner code encoding operation, or the 120-bit padding can be inserted before the inner code encoding. At this time, the 8 inner code pre-data streams are periodically inserted with 120-bit padding, and the 120-bit padding in each group is encoded to obtain 128-bit padding after the inner code encoding. After the 8:1 bit pair interleaving, a total of 128x8=1024-bit padding is obtained.

[0139] In the embodiment, the four-symbol boundary is obtained before the inner code encoding, and the four-symbol boundary is used to make the 120 information bits in the inner code (128, 120) encoding come from 12 different RS code words, so that the concatenated FEC scheme has good error correction performance and can be applied to more transmission scenarios.

[0140] FIG. 11 is a structural schematic diagram of a data processing apparatus in an embodiment of the present application. As shown in FIG. 11, the data processing apparatus includes a first processing unit 1101 and a second processing unit 1102. The first processing unit 1101 is configured to perform the first data processing described in the foregoing embodiments, and the second processing unit 1102 is configured to perform the second data processing described in the foregoing embodiments. The specific data processing manner has been described in detail in the foregoing embodiments, and will not be described here.

[0141] It should be understood that the data processing apparatus provided by the present application can also be implemented in other manners. For example, the division of the units in the apparatus is merely a logical function division, and the actual implementation can be in another division manner, for example, a plurality of units or components can be combined or integrated into another system. In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each functional unit can be a separate physical unit, or two or more functional units can be integrated in a processing unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0142] Figure 12 is a schematic diagram of a structure of an optical module according to an embodiment of the present application. As shown in Figure 12, the optical module includes a processor 1201 and an interface 1202. The processor 1201 is configured to perform the operations performed by the data processing apparatus in the above embodiments. The interface 1202 can be a transceiver or an input / output interface. The interface 1202 is configured to receive a signal from another apparatus and transmit the signal to the processor 1201 or transmit a signal from the processor 1201 to another apparatus. As an example, the processor 1201 performs the inner code encoding processing to obtain an encoded data stream, and transmits the encoded data stream through the interface 1202. In this example, the interface 1202 can be an electrical interface. As another example, the processor 1201 performs the inner code encoding processing to obtain an encoded data stream and performs symbol mapping (also referred to as modulation mapping) to obtain a symbol stream to be transmitted. A modulator in the optical module performs electrical-optical conversion and other signal processing on the symbol stream to be transmitted to obtain an optical signal, and transmits the optical signal through the interface 1202. In this example, the interface 1202 can be an optical interface. Optionally, the optical module can further include a memory 1203. The memory 1203 is configured to store program instructions and / or data.

[0143] Generally, an optical module includes optoelectronic devices, a processor, and an interface. The optoelectronic devices include a transmitter device and a receiver device. The transmitter of the optical module converts an electrical signal into an optical signal and transmits the optical signal through an optical fiber. The receiver of the optical module receives an optical signal and converts the optical signal into an electrical signal.

[0144] It should be noted that the types of the optical module in the embodiments of the present application include, but are not limited to, normal optical module, near package optics (NPO) module, co-packaged optics (CPO) module, and the like. The functions that can be implemented by the normal optical module include, but are not limited to, digital signal processor (DSP) and clock data recovery (CDR), and the like. For example, the normal optical module converts an analog signal into a digital signal, performs DSP on the digital signal, and then converts the digital signal into an analog signal to be sent to a host-side device. Since the DSP needs to be retimed, the normal optical module can also be referred to as a retimed module. The normal optical module is connected to the host-side device through an attachment unit interface (AUI). The NPO module and the CPO module do not have a pluggable optical module physical package form, and are closer to the host-side device. The NPO module and the CPO module can also be referred to as an optical engine. The NPO technology or the CPO technology is a technology of "packaging" the host-side device (or the host-side chip) and the optical engine. When the host-side device and the optical engine are packaged by using the NPO technology, the optical engine can be referred to as an NPO module. When the host-side device and the optical engine are packaged by using the CPO technology, the optical engine can be referred to as a CPO module.

[0145] FIG. 13 is a schematic structural diagram of a communication device according to an embodiment of the present application. As shown in FIG. 13, the communication device includes a host-side device 1301 and an optical module 1302. The host-side device 1301 is configured to send data to the optical module 1302, and the optical module 1302 generates an optical signal according to the data sent by the host-side device 1301 and sends the optical signal through a channel. For example, the host-side device can be a switch, a router, a server, or the like. The communication device can be a communication device including the host-side device 1301 and the optical module 1302.

[0146] The embodiments of the present application also provide an optical transport network (OTN) device, which comprises a line side device and a client side device. The client side device can also be referred to as a tributary side device in some scenarios. The line side device comprises a processor and an interface. The processor is configured to execute the data processing method described in the above embodiments. The interface can be a transceiver or an input / output interface. The interface is configured to receive a signal from another device outside the line side device and transmit the signal to the processor, or transmit a signal from the processor to another device outside the line side device.

[0147] The embodiments of the present application also provide a chip. The chip integrates a circuit for implementing the functions of the processor described above and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, the chip can be connected to an external memory through the interface. The chip can complete the method steps of any one or more of the above embodiments. Alternatively, the chip implements the actions performed by the data processing device in the above embodiments according to program codes stored in the memory.

[0148] As an example, the chip in the embodiments of the present application can be a central processing unit (CPU), and can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a transistor logic device, a hardware component or any combination thereof. The general-purpose processor can be a microprocessor, or can be any conventional processor, and can also be a processing circuit implementing specific functions.

[0149] The embodiments of the present application also provide a computer readable storage medium, which comprises a program or instructions. When the program or instructions are executed on a computer, the data processing method described in the above embodiments is implemented.

[0150] It should be understood that the processor mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit or the like. When implemented by software, the processor can be a general-purpose processor, which reads software codes stored in a memory to implement the functions. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0151] As an example, the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor, and can also be a processing circuit that implements specific functions.

[0152] The memory in the embodiments of the present application can be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can be a component of the processor. The processor and the storage medium can be located in an ASIC. The ASIC can be located in a network device or a terminal device. Of course, the processor and the storage medium can also exist as separate components in a network device or a terminal device.

[0153] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof.

[0154] When implemented by using hardware, the data processing method provided by the embodiments of the present application can be implemented without reading software codes or instructions, for example, by using a CPU, a DSP, an ASIC, an FPGA, other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0155] When implemented using software, the functions can be implemented using one or more computer programs or instructions stored or executed in at least one computer-readable medium. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a computer-readable signal. The computer-readable medium can include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, DVDs, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any other suitable type of machine-readable medium. Suitable machine-readable media for storing or transmitting software include hardware- or software-readable media that store data which can be accessed by one or more computer systems. A computer-readable medium stores computer-executable instructions or data that, in combination with the computer system, cause the computer system to operate. For example, a non-transitory computer-readable medium comprising a computer-readable medium that does not undergo a transformation during transmission is any medium that stores data that is not transmitted but is accessed by the computer system. Examples of non-transitory computer-readable media include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. The term "computer-readable medium" includes, but is not limited to, portable or fixed computer-readable media that store data for use by or in connection with the computer system. The computer-readable medium can be a computer- readable storage medium or a computer-readable signal medium.

[0156] Finally, it should be noted that the above merely illustrates the embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises the following steps: p:q symbol demultiplexing and alignment mark locking are performed on p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain a four-symbol boundary, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 * p or q = 4 * p; data processing including inner code encoding and modulation is performed on the p pieces of first data streams according to the obtained four-symbol boundary to obtain p pieces of modulated data streams.

2. A data processing method, characterized by, The method comprises the following steps: p:q symbol demultiplexing and alignment mark locking are performed on p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain a four-symbol boundary and q pieces of second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 * p or q = 4 * p; q:p symbol multiplexing is performed on the q pieces of second data streams to obtain p pieces of third data streams; convolution interleaving processing is respectively performed on the p pieces of third data streams according to the obtained four-symbol boundary.

3. The method according to claim 1 or 2, characterized in that, The p:q symbol demultiplexing and alignment mark locking performed on the p pieces of first data streams subjected to Reed-Solomon RS encoding specifically comprises the following steps: p:q symbol demultiplexing is performed on the p pieces of first data streams subjected to Reed-Solomon RS encoding to obtain q pieces of second data streams; alignment mark locking is respectively performed on the q pieces of second data streams to obtain a four-symbol boundary.

4. The method according to any one of claims 1 to 3, characterized in that, q = 2 * p, and the p:q symbol demultiplexing comprises p pieces of 1:2 symbol demultiplexing, wherein the p pieces of 1:2 symbol demultiplexing correspond to the p pieces of first data streams in one-to-one manner; or q = 4 * p, and the p:q symbol demultiplexing comprises p pieces of 1:4 symbol demultiplexing, wherein the p pieces of 1:4 symbol demultiplexing correspond to the p pieces of first data streams in one-to-one manner.

5. The method of claim 4, wherein, The 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding 1 piece of first data stream to obtain 2 pieces of second data stream; or The 1:4 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding 1 piece of first data stream to obtain 4 pieces of second data stream.

6. The method of claim 5, wherein, The four-symbol boundary is p, which corresponds to the p pieces of first data streams in one-to-one manner.

7. The method of claim 6, wherein, All the second data streams obtained in any one of the 1:2 symbol demultiplexing and the 1:4 symbol demultiplexing are subjected to alignment mark locking, and the boundary of the 40 bits distributed is a four-symbol boundary.

8. The method of claim 6, wherein, q = 2 * p, and within a threshold time interval, at least one of the 2 pieces of second data stream is not subjected to alignment mark locking, the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is shifted, 1:2 symbol demultiplexing is performed again to obtain 2 pieces of second data stream again; alignment mark locking is respectively performed on the 2 pieces of second data stream obtained again to obtain one four-symbol boundary.

9. The method of claim 6, wherein, q = 4 * p, and within a threshold time interval, at least one of the 4 pieces of second data stream is not subjected to alignment mark locking, the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is shifted, 1:4 symbol demultiplexing is performed again to obtain 4 pieces of second data stream again; alignment mark locking is respectively performed on the 4 pieces of second data stream obtained again to obtain one four-symbol boundary.

10. The method according to claim 8 or 9, characterized in that, The granularity of shifting the boundary of the 40 bits of the distribution is 1 bit; or The granularity of shifting the boundary of the 40 bits of the distribution is 40*m+1 bits, where m is an integer greater than 0.

11. The method according to any one of claims 1-10, characterized in that, p=8, q=16; or p=4, q=16.

12. The method of claim 1, wherein, The code word length of the inner code is 128 bits, where the information bits are 120 bits and the check bits are 8 bits; or the code word length of the inner code is 126 bits, where the information bits are 110 bits and the check bits are 16 bits.

13. The method according to any one of claims 1-12, characterized in that, The code word length of the RS is 544 symbols, where the information length is 514 symbols, and each symbol contains 10 bits.

14. The method of claim 2, wherein, The convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line including the smallest number of storage units includes 0 storage units, the difference in the number of storage units between each adjacent two delay lines is Q, each storage unit is used to store 40 bits, and Q is an integer greater than or equal to 1.

15. The method of claim 14, wherein, Each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r*40 bits in the output data stream after the convolution interleaving include the 40 bits output by each delay line, where the 40 bits stored in the storage unit are 4 RS symbols.

16. The method of claim 15, wherein, r＝3，Q＝24。 17. A data processing apparatus, characterized by: Comprise: A first processing unit and a second processing unit; The first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p first data streams subjected to Reed-Solomon (RS) encoding to obtain a four-symbol boundary, where p is an integer greater than or equal to 1, q is an integer, and q=2*p or q=4*p; The second processing unit is configured to perform data processing including inner code encoding and modulation on the p first data streams according to the obtained four-symbol boundary to obtain p modulated data streams.

18. A data processing apparatus, characterized in that, Comprise: A first processing unit and a second processing unit; The first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p first data streams subjected to Reed-Solomon (RS) encoding to obtain a four-symbol boundary and q second data streams, where p is an integer greater than or equal to 1, q is an integer, and q=2*p or q=4*p; The second processing unit is configured to perform q:p symbol multiplexing on the q second data streams to obtain p third data streams, and is further configured to perform convolution interleaving processing on the p third data streams respectively according to the obtained four-symbol boundary.

19. The apparatus of claim 17 or 18, wherein, The first processing unit is specifically configured to: perform p:q symbol demultiplexing on p first data streams subjected to Reed-Solomon (RS) encoding to obtain q second data streams; perform alignment mark locking on the q second data streams respectively to obtain a four-symbol boundary.

20. The apparatus of any one of claims 17-19, wherein, q=2*p, and the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, where the p 1:2 symbol demultiplexings correspond to the p first data streams one by one; or q=4*p, and the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, where the p 1:4 symbol demultiplexings correspond to the p first data streams one by one.

21. The apparatus of claim 20, wherein, The 1:2 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding 1 first data stream to obtain 2 second data streams. The 1:4 symbol demultiplexing adopts a round-robin manner of distributing 40 bits each time to demultiplex the corresponding 1 first data stream to obtain 4 second data streams.

22. The apparatus of claim 21, wherein, The four-symbol boundary is p, and p corresponds to one first data stream.

23. The apparatus of claim 22, wherein, All the second data streams obtained in any one of the 1:2 symbol demultiplexing and the 1:4 symbol demultiplexing achieve aligned identification locking, and the boundary of the 40 bits distributed is a four-symbol boundary.

24. The apparatus of claim 22, wherein, q = 2 × p, and at least one of the 2 second data streams does not achieve aligned identification locking within a threshold time interval, and the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing, re-perform 1:2 symbol demultiplexing, and re-obtain 2 second data streams; and perform aligned identification locking on the re-obtained 2 second data streams respectively to obtain one four-symbol boundary.

25. The apparatus of claim 22, wherein, q = 4 × p, and at least one of the 4 second data streams does not achieve aligned identification locking within a threshold time interval, and the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing, re-perform 1:4 symbol demultiplexing, and re-obtain 4 second data streams; and perform aligned identification locking on the re-obtained 4 second data streams respectively to obtain one four-symbol boundary.

26. The apparatus of claim 24 or 25, wherein, The granularity of shifting the boundary of the distributed 40 bits is 1 bit; or The granularity of shifting the boundary of the distributed 40 bits is 40 × m + 1 bits, where m is an integer greater than 0.

27. The apparatus of any of claims 17-26, wherein, p = 8, q = 16; or p = 4, q = 16.

28. The apparatus of claim 17, wherein, The code word length of the inner code is 128 bits, where the information bits are 120 bits and the check bits are 8 bits; or the code word length of the inner code is 126 bits, where the information bits are 110 bits and the check bits are 16 bits.

29. The apparatus of any of claims 17-28, wherein, The code word length of the RS is 544 symbols, where the information length is 514 symbols, and each symbol contains 10 bits.

30. The apparatus of claim 18, wherein, The convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line including the smallest number of storage units includes 0 storage units, the difference in the number of storage units between each adjacent two delay lines is Q, each storage unit is used to store 40 bits, and Q is an integer greater than or equal to 1.

31. The apparatus of claim 30, wherein, Each delay line inputs and outputs 40 bits at a time, and the continuous r × 40 bits in the output data stream after convolution interleaving include the 40 bits output by each delay line, where the 40 bits stored in the storage unit are 4 RS symbols.

32. The apparatus of claim 31, wherein, r＝3，Q＝24。 33. A chip, characterized by The chip is used to perform the method of any one of claims 1-16.

34. An optical module characterized by comprising: The optical module comprises a processor configured to perform the method of any one of claims 1 to 16, and an interface configured to transmit and receive signals.

35. A communications device, characterized by The sending device comprises a host-side device and the optical module of claim 34, wherein the optical module is connected to the host-side device.

36. A communication system, characterized by The method comprises: The first communication device and the second communication device, wherein at least one of the first communication device and the second communication device is the communication device of claim 35, and the first communication device and the second communication device are connected.

37. A data processing method, characterized by, The method comprises: performing p:q symbol demultiplexing and alignment mark locking on p first data streams subjected to Reed-Solomon (RS) encoding to obtain a four-symbol boundary and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; performing q:p symbol multiplexing on the q second data streams to obtain p third data streams; performing 1:8 K-bit distribution on the p third data streams according to the obtained four-symbol boundary to obtain 8 × P fourth data streams, K being an integer greater than 1; performing cyclic shift and inner code encoding on the 8 × P fourth data streams respectively to obtain 8 × P fifth data streams.

38. The method of claim 37, wherein, The method further comprises: performing 8:1 bit-to-bit interleaving on the 8 × P fifth data streams to obtain P sixth data streams; modulating the P sixth data streams to obtain P modulated data streams.

39. A data processing apparatus, characterized by: The method comprises: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing and alignment mark locking on p first data streams subjected to Reed-Solomon (RS) encoding to obtain a four-symbol boundary and q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p; the second processing unit is configured to perform q:p symbol multiplexing on the q second data streams to obtain p third data streams, and perform 1:8 K-bit distribution on the p third data streams according to the obtained four-symbol boundary to obtain 8 × P fourth data streams, K being an integer greater than 1; performing cyclic shift and inner code encoding on the 8 × P fourth data streams respectively to obtain 8 × P fifth data streams.

40. The device of claim 39, wherein, The second processing unit is further configured to: perform 8:1 bit-to-bit interleaving on the 8 × P fifth data streams to obtain P sixth data streams; modulate the P sixth data streams to obtain P modulated data streams.

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