Method for structuring and / or coating already pre-structured and / or pre-coated substrate surfaces of a product wafer

Abstract

The invention relates to a method for structuring and / or coating an already pre-structured and / or coated substrate surface (10) of a product wafer (12) using a protective wafer (14), having at least the following method steps: First, the protective wafer (14) is produced, said protective wafer having at least one first protective wafer part (16) and at least one second protective wafer part (18), which contain silicon material and are provided with a silicon oxide layer (20), in such a way that at least one exposable mask plane (22) is integrated into the protective wafer (14). The protective wafer (14), which is precisely adjusted relative to the substrate surface (10), is then joined (30) by means of at least one temporary or permanent bonding connection (32). At least one cavity (36, 38) in the protective wafer (14) is then partly or completely opened (34) in order to carry out etching and / or coating processes on the product wafer (12). The protective wafer (14) is then removed (40) from the pre-structured and / or coated substrate surface (10) of the product wafer (12) in order to reuse the protective wafer (14). The invention further relates to the use of the method for structuring and / or coating already pre-coated and / or pre-structured substrate surfaces (10) of product wafers (12).

Description

[0001] Description

[0002] title

[0003] Methods for structuring and / or coating pre-structured and / or pre-coated substrate surfaces of a product wafer

[0004] Technical field

[0005] The invention relates to a method for structuring and / or coating a pre-structured and / or pre-coated substrate surface of a product wafer using a protective wafer. Furthermore, the invention relates to a protective wafer with an integrated shadow mask, in particular at least one mask layer, produced according to the method, and to the use of the method for producing a protective wafer having a shadow mask and its application to a structured and / or coated substrate surface of a product wafer.

[0006] State of the art

[0007] WO 2017 / 129171 A1 discloses a method and a device for separating a microchip from a wafer and depositing the microchip onto a substrate. During the separation process, the microchip is blasted onto the free end of a tip. It adheres to the tip by adhesive force during transport to the substrate. Until the microchip is removed, it is held in place by ridges referred to as retaining tabs. These retaining tabs are broken during the removal process.

[0008] DE 10 2018 214 017 A1 relates to the production of a thin film with a microsystem, wherein the microsystem is produced on the thin film and peeled off together with the thin film. Among other things, it is proposed to form webs between an outer and an inner region of the thin film, with the microsystem located on the inner region of the thin film. When the inner region is peeled off, the webs can break. A support structure can be formed that extends over the inner region and at least partially over the webs and that is peeled off together with the inner region. It is further disclosed to design the webs with tapered sections to define predetermined breaking points.

[0009] US 2008 / 0044985 A1 discloses the use of sacrificial supports on workpieces with microfeatures such as semiconductor wafers, wherein the workpiece comprises a substrate and microelectronic dies. The workpiece further includes a sacrificial support that is attached over the dies and serves for protection and transport. The disclosure also covers the singulation of such a workpiece, wherein the singulation also involves the sacrificial support. A singulated die is deposited onto a support substrate, for example, an interposer substrate, using the associated portion of the sacrificial support. Subsequently, the sacrificial support is removed. Using such an approach, a device with microfeatures, for example, a microelectronic or micromechanical device, can be produced.

[0010] WO 2017 / 129171 A1 and DE 10 2018 214 017 A1 describe various methods for singulating wafers and then transporting the singulated chips. The use of bridges is disclosed, with DE 10 2018 214 017 A1 also proposing the use of specially shaped bridges with tapered sections.

[0011] US 2008 / 0044985 A1 reveals the general idea of ​​making special elements for transporting chips and their subsequent removal.

[0012] DE 10 2015 206 996 A1 relates to a method for fabricating microelectromechanical structures in a layer sequence and a corresponding electronic component with a microelectromechanical structure. A method for fabricating microelectromechanical structures in a layer sequence is proposed, wherein a support substrate with a first surface is first provided. An insulating layer is then applied to this first surface. This is followed by the epitaxial growth of a first silicon layer onto the insulating layer, after which the first silicon layer is structured to form grooves, the grooves extending at least partially through the first silicon layer.The first silicon layer is then passivated, filling the grooves and forming a passivation layer on the side facing away from the first surface. This passivation layer is structured, forming sacrificial and functional areas within the first silicon layer. The sacrificial areas on the side facing away from the substrate are at least partially free of the passivation layer. The sacrificial areas are then removed.

[0013] US 2007 / 125961 A1 describes a micromechanical system comprising a micromechanical structure and a shadow mask device. The micromechanical structure and the shadow mask device are fabricated from a single wafer. The micromechanical structure includes a cover surface that is actuated within a cover area. The cover surface is created during machining steps. The shadow mask device is designed to shade a portion of the micromechanical structure from a deposition or treatment beam. It has at least one geometry that defines a shading area relative to the cover surface and is generated during geometry machining steps. The micromechanical structure may be an optical mirror.

[0014] US 2012 / 299129 A1 discloses a method for preventing movable structures within a MEMS device, and in particular in recesses that can have one or more dimensions in the micrometer range or smaller, from being inadvertently bonded to non-movable structures during a bonding process. In this context, the manufacture and use of a reusable shadow mask within the described manufacturing process is disclosed.

[0015] WO 2005 / 081035 A1 discloses a microelectromechanical system with a mirror. It discloses the use of shadow masks in the production of such MEMS mirror devices to protect a mirror layer during an etching process.

[0016] In the production of MEMS components, it is often necessary to restructure an already coated and / or structured surface, for example by trench etching, or to coat it, for example by sputtering. In cases where a paint mask cannot be used for this structuring, because, for example, the coating could be damaged, or because the MEMS structures are already movable, structuring is only possible using a shadow mask.

[0017] Shadow masks have openings through which material layers can be sputtered. Etching processes are also possible through these openings, performed or supported by an ion beam, atomic beam, or molecular beam directed at the surface to be etched. The shadow masks must be aligned laterally to the substrate structures. To achieve good structural contours, the distance between the shadow mask and the substrate surface should be kept as small as possible, but large enough to prevent mechanical contact with the substrate. Maintaining this lateral and vertical alignment of the shadow masks to the substrate wafer within the systems and adapting the automated handling of the system for the stack of shadow mask and substrate wafer accordingly is generally complex and costly.The production of shadow masks is relatively expensive; furthermore, they must be cleaned in order to be reused.

[0018] Disclosure of the invention

[0019] According to the invention, a method for structuring and / or coating a pre-structured and / or coated substrate surface of a product wafer using a protective wafer is proposed, comprising the following process steps: a) manufacturing a protective wafer with at least one first protective wafer part and at least one second protective wafer part, containing silicon material and provided with a silicon oxide layer, such that b) at least one exposed mask plane is integrated into the protective wafer, c) joining the protective wafer, which is precisely aligned to the substrate surface, by means of at least one temporary or permanent bond connection, d) partially or completely opening at least one cavity in the protective wafer to perform etching and / or coating processes on the product wafer, and e) removing the protective wafer from the substrate surface of the product wafer for reuse.

[0020] Advantageously, the method proposed according to the invention makes it possible to ensure that the protective wafer remains undamaged and can be reused after cleaning.

[0021] In an advantageous further development of the method proposed according to the invention, the protective wafer is manufactured with a number of layers according to process step a), comprising at least the first protective wafer part, the second protective wafer part, and at least one mask layer. The mask layer advantageously represents the shadow mask, which is buried in the protective wafer and can remain encapsulated on all sides within it until it is exposed.

[0022] In an advantageous further development of the method proposed according to the invention, the protective wafer is manufactured such that it comprises at least one bridge plane. By providing the at least one bridge plane, the height of the protective wafer can be adjusted and adapted to the requirements of structuring already pre-structured or pre-coated substrate surfaces, so that, for example, undercutting or shading of already pre-structured areas of the substrate surface can be limited.

[0023] Advantageously, in the method proposed according to the invention, it is provided that the at least one exposed mask layer integrated into the protective wafer according to process step b) is exposed as a shadow mask by means of a trench etching process.

[0024] In the method proposed according to the invention, it is advantageously provided that, in process step d) or in addition to process step d), after exposure of the at least one mask layer, the pre-structured or coated substrate surface is structured and / or coated completely or partially using anisotropic processes, in particular sputtering, trench etching, or coating. In the method proposed according to the invention, it can advantageously be provided that the first and second cavities are partially opened and isotropic etching or coating processes are carried out on exposed areas of the product wafer via such opened first and second cavities.Furthermore, in the method proposed according to the invention, opening can advantageously be carried out by creating access openings or by completely opening the first and second cavities by removing cover layers of different thicknesses.

[0025] The method proposed according to the invention is further characterized in that the protective wafer is provided on its back side facing the substrate surface with at least one recess, the depth of which has a clear distance between the at least one mask plane and the substrate surface to be structured and / or coated, which is already pre-structured or coated.

[0026] In the method proposed according to the invention, the depth of the at least one depression on the protective wafer is in a range between 5 pm and 100 pm.

[0027] The method proposed according to the invention is further characterized in that an organic or an inorganic joining agent is used for joining according to process step c), wherein, in the case of formation of at least one temporary bond connection, this is reversible and the protective wafer is removed, or in the case of formation of at least one permanent bond connection, the protective wafer is removed by means of stealth dicing or a tape expansion process.

[0028] In an advantageous further development of the method proposed according to the invention, according to process step a), the at least one first protective wafer part is designed as a bottom wafer, and starting from its front side, recesses with sidewalls are formed which have chamfers in an angular range between 90° and 135°, which are formed by trench etching. This allows the recesses to be designed such that their sidewalls are angled and can accommodate subsequent coating or contouring processes. Furthermore, in the method proposed according to the invention, it is provided that mask openings of the at least one mask plane are preferably etched onto a back side of the first protective wafer part.

[0029] The method proposed according to the invention further provides that the mask openings are designed as circumferential, square, rectangular or trapezoidal trenches or trench structures. Of course, other geometries of the mask openings within the mask plane can also be generated.

[0030] The method proposed according to the invention is further characterized in that the recesses are designed as polygonal structures, in particular as octagons, which are spaced apart from each other at a distance b, wherein the distances between the recesses each form a bridge.

[0031] The method proposed according to the invention further provides that the bridges are made in a width that decreases with increasing etching depth and are essentially completely undercut once a depth t is reached.

[0032] Advantageously, in the method proposed according to the invention, a shading effect of the bridges during the processing processes, in particular etching or deposition processes, preferably trench etching, beam etching or sputtering, is prevented by a

[0033] Minimizing the bridge width and / or minimizing the height of the bridge plane and / or maximizing the distance between the bridges and the mask plane minimizes.

[0034] In the method proposed according to the invention, it is further advantageously provided that through-holes for gaseous etching media, preferably SFe, XeF2, HF in the gas phase, or for gaseous media for coating, in particular atomic layer deposition processes or anti-sticking coating, are introduced into the first protective wafer part from the back and / or the front. In the method proposed according to the invention, it is further provided that at least the first protective wafer part is thermally oxidized.

[0035] The method proposed according to the invention further enables the production of the second protective wafer part by

[0036] Providing a silicon wafer blank,

[0037] Incorporation of at least one partially executed annular depression, thermal oxidation of the second protective wafer part,

[0038] Including recesses on the back side of the second shielding wafer part, identical to those recesses on the front side of the first shielding wafer part.

[0039] Advantageously, the method proposed according to the invention provides that the recesses are formed at different depths.

[0040] The method proposed according to the invention further advantageously provides that the protective wafer, comprising at least the first protective wafer part, the second protective wafer part and the mask plane, is produced by

[0041] Applying the second protective wafer part with its back side to the front side of the first protective wafer part by wafer bonding, such that direct bonding without adhesive or bonding with adhesives, in particular Au-Au, Al-Ge, Nano-Cleave™ bond layer, is carried out, thinning the second protective wafer part on the front side to expose ring structures on the front side and

[0042] Applying an oxide to the front surface, leaving an area of ​​ring-shaped structures unoccupied.

[0043] In this context, thinning refers to the removal of material from the front surface. This can be achieved through grinding, polishing, or, if necessary, mechanical polishing.

[0044] Advantageously, the method proposed according to the invention further provides that the multi-layered protective wafer, which is closed on its front side by means of the second protective wafer part, is applied with its open back side to a substrate surface of the product wafer that is already structured and / or coated over its entire surface or in certain areas by means of a bonding process.

[0045] Furthermore, the invention relates to a protective wafer with an integrated shadow mask, in particular at least one mask plane, manufactured according to the inventive method.

[0046] Advantages of the invention

[0047] The method proposed according to the invention provides a shadow mask in the form of a protective wafer, which is buried and permanently or temporarily bonded to the product wafer, preferably a pre-structured silicon wafer, by means of wafer bonding. The shadow mask can be positioned very precisely relative to the product wafer using commercially available single or bonding equipment. Both organic and inorganic bonding agents can be used. When using a bonding agent suitable for a temporary bond, the bond can be dissolved after processing, and the shadow mask can also be removed.If, however, a permanent bond is created between the protective wafer with shadow mask and the product wafer, it can be removed after processing by means of stealth dicing and tape expansion in a lateral direction.

[0048] Using the method proposed according to the invention, a shadow mask can be provided that is contained within the protective wafer and remains encapsulated on all sides after bonding. The protective wafer thus also protects one side of the product wafer during isotropic etching or coating processes or other processing steps. The shadow mask preferably comprises several levels, which make it possible to create annular openings, for example in the form of trenches. Using the method proposed according to the invention, shadow masks can be exposed by means of the trench etching process. Pneumatically isolated cavities in the shadow mask wafer can be opened completely with respect to the size of the openings or only partially. Accordingly, etching or coating processes can be limited to specific areas of the substrate wafer.Using the method proposed according to the invention, a shadow mask can be manufactured, preferably from silicon or with a silicon oxide layer on its surface. Its production is possible using standard MEMS process and machining steps. The oxide layer on the surface protects the shadow mask from etching during the trench etching process on the product wafer.

[0049] Furthermore, it should be emphasized that openings on the shadow mask can be manufactured and represented with high geometric precision.

[0050] Furthermore, the clear distance between the shadow mask and the surface of the product wafer can be adjusted very precisely, which is advantageous. By providing appropriate support points at non-critical positions on the product wafer, the clear distance can be kept almost constant and very small across the entire wafer surface, for example, less than 10 pm. The smaller the clear distance between the shadow mask and the surface of the product wafer, the more accurately structural geometries can be manufactured using the shadow mask.

[0051] Brief description of the drawings

[0052] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0053] They show:

[0054] Figure 1 shows a schematic structure of a shadow mask buried in the protective wafer, depicted in cross-section, in the form of a mask plane.

[0055] Figure 2 shows a front view of a first shielding wafer section,

[0056] Figure 3 shows a section line A - A', as shown in Figure 2, on the back side of the bottom wafer, without openings in the shadow mask; Figure 4 shows a section line B - B', as shown in Figure 2.

[0057] Figure 5 shows a view of the first shield wafer section from the rear with mask openings in the mask plane.

[0058] Figure 6 shows a section line A - A', as shown in Figure 5,

[0059] Figures 7.1 - 7.7 show a schematic representation of the process flow for manufacturing the first protective wafer part (bottom wafer) with a buried shadow mask in the form of a mask plane.

[0060] Figures 8.1 - 8.4 show a schematic representation of a process flow for the production of a second protective wafer part (lid wafer) of the protective wafer with buried shadow mask in the form of a mask plane.

[0061] Figures 9 and 10 show a summary of the first and second shield wafer sections;

[0062] Figures 11-20 are schematic representations of possible uses of a protective wafer applied to a pre-structured or pre-coated substrate surface of a product wafer.

[0063] Embodiments of the invention

[0064] In the following description of embodiments of the invention, identical or similar elements are designated by the same reference numerals, and repeated descriptions of these elements are omitted in individual cases. The figures represent the subject matter of the invention only schematically.

[0065] Figure 1 shows the schematic structure of a protective wafer with an integrated, buried shadow mask in the form of at least one mask plane.

[0066] Figure 1 shows a protective wafer 14, which can be formed in multiple parts and, in the cross-sectional view shown, comprises a first protective wafer part 16, which can also be referred to as the bottom wafer, and a second protective wafer part 18, which is referred to as the top wafer. Both protective wafer parts 16 and 18 are essentially made of a silicon material. The protective wafer 14, as shown in the cross-sectional view in Figure 1, is encased in a silicon oxide layer 20. The protective wafer 14 comprises several layers, in particular a mask layer 22 and a bridge layer 24, which can be formed at a height 78. The height 78 of the bridge layer 24 of the multi-part protective wafer 14 can vary depending on the requirements with respect to the height of the first protective wafer part 16. A front side of the multi-part protective wafer 14 is designated by reference numeral 26; a rear side is identified by reference numeral 28.

[0067] The protective wafer 14, preferably multi-part and shown in cross-section in Figure 1, is applied to a product wafer 12 (not shown in Figure 1), the substrate surface 10 of which is already partially or fully structured and / or coated (see Figure 11). The protective wafer 14, as depicted in Figure 1 with the integrated shadow mask in the form of at least one mask plane 22, is itself manufactured using MEMS processes. The protective wafer 14 is temporarily or permanently bonded to the product wafer 12 (not shown in Figure 1) using wafer bonding. Vertical and lateral alignment of the protective wafer 14 with respect to the substrate surface 10 of the product wafer 12 is achieved using wafer bonding adjustment devices, thereby enabling very high accuracy.Furthermore, it should be emphasized that the shadow mask, which is formed as mask plane 22 in the cross-sectional view according to Figure 1, is also encapsulated and can be selectively exposed completely or partially as required via etching processes or other ablation methods. This results in a multitude of possible combinations for coating and / or etching processes, in the event that the protective wafer 14 is connected to the product wafer 12, for example via bond connections.

[0068] As can be further seen in Figure 1, both the outer surfaces and parts of the inner surface, in particular of the first protective wafer section 16, are provided with the silicon oxide layer 20 in the cross-sectional view. The two protective wafer sections, namely the aforementioned protective wafer section 16, which can also be referred to as the bottom wafer, and the second protective wafer section 18, which is referred to as the top wafer, are joined together by conventional temporary or permanent bond connections 32 using conventional bonding methods. An inorganic or organic bonding agent 96 is used as the bonding agent 96, which is used to form the temporary or permanent bond connections 32.

[0069] The cross-sectional view in Figure 1 also shows that first recesses 48 are formed on the rear side of the second protective wafer section 18. Corresponding to the first recesses 48 in the second protective wafer section 18, second recesses 104 are formed in the first protective wafer section 16, also referred to as the bottom wafer. The first recesses 48 in the second protective wafer section 18 preferably coincide with the second recesses 104 in the first protective wafer section 16.

[0070] Figure 1 shows that mask openings 62 are formed in the mask plane 22. These can be arranged in a regular or irregular grid within the mask plane 22, which represents the buried shadow mask. A continuous recess 42 is formed on the back side 28 of the protective wafer 14. The recess 42 has a depth 44 that can be between 5 pm and 100 pm. The depth 44 of the recess 42 creates a clearance 46 between the back side 28 of the protective wafer 14, and in particular the first protective wafer part 16, and the underlying pre-structured or pre-coated substrate surface 10 of the product wafer 12 (not shown in Figure 1).

[0071] Figure 1 further shows that through openings 82 run in side areas of the silicon material from which the first protective wafer part 16 and the second protective wafer part 18 of the multi-part protective wafer 14 are preferably manufactured.

[0072] While the through-hole 82 in the first protective wafer part 16 is continuous, i.e., free of silicon material, the through-hole 82, which runs laterally in the second protective wafer part 18, i.e., the cover wafer of the protective wafer 14, is closed by means of a silicon closure 102.

[0073] Figure 2 shows the front view of the protective wafer shown in cross-section in Figure 1. First recesses 48 are formed on a front face 80 of the protective wafer 14 shown in cross-section in Figure 1, comprising the first protective wafer part 16 and the second protective wafer part 18. The first recesses 48 can, for example, be formed in a polygonal geometry 50, in particular as an octagonal configuration 52, as shown in Figure 2. Through openings 82 extend laterally in the material of the first protective wafer part 16 as shown in Figure 2. One section through the areas of the first recesses 48 is designated A - A' (see illustration in Figure 3), and another section is designated B - B' (see illustration in Figure 4).With reference to Figures 3 and 4, which depict the cross-sectional paths A - A' and B - B' respectively in Figure 2, it should be noted that the second recesses 104 in the first protective wafer part 16 (bottom wafer) are produced by trench etching such that the side walls 54 form a chamfer 56, as shown in Figures 3 and 4. The angle 58 within which the chamfer 56 of the opposing side walls 54 in the first protective wafer part 16 runs lies between 90° and 135°. Such an angle 58 can be achieved by undercutting with adjusted etching parameters. The recess 42 attached to a rear side 60 of the first protective wafer part 16 (see illustration in Figure 1) is formed to the aforementioned depth 44, which determines the clear distance 46 between the mask plane 22, i.e. the shadow mask, and the substrate surface 10 to be structured by it, which is already pre-structured and / or pre-coated.The recess 42 prevents mechanical contact between the mask plane 22, i.e. the shadow mask, and the sensitive, already pre-structured and / or pre-coated substrate surface 10 of the product wafer 12, thus preventing damage to the highly sensitive substrate surface 10 during further structuring steps using the shadow mask.

[0074] On the reverse side of the first protective wafer part 16, i.e., the bottom wafer, the aforementioned mask openings 62, as schematically indicated in Figure 1, are created by means of an etching process. A comparison of Figures 2, 3, and 4 shows that the front-side first and second recesses 48, 104 are formed with a length b 70. The lengths b 70 form bridges 72. The openings, formed as an octagonal geometry 52 in Figure 2, lie next to each other according to a width 74 of the bridges 72, formed by the lengths b 70. By undercutting or chamfering 56 of the side walls 54 by more than 90°, the width 74 of the bridges 72 becomes progressively smaller with increasing etching depth until it reaches zero upon reaching a certain etching depth t 76. Thus, the bridges 72 formed in the silicon material are undercut.

[0075] Figure 5 shows a view of the back side 60 of the first protective wafer section 16, which can also be referred to as the bottom wafer. Analogous to the representation in Figure 2, the section lines A - A' and B - B' are indicated. The section line A - A' is shown in detail in Figure 6.

[0076] As shown in Figure 5, the mask openings 62 in the mask plane 22 can be configured as circumferential square trenches 64 or trench structures 66, as shown in Figure 1. A different grid of mask openings 62 within the mask plane 22, which represents the shadow mask and is integrated into the protective wafer 14, is also possible.

[0077] Figure 6 shows that in section A - A', according to the section profile shown there, the individual second recesses 104, bounded on the outer sides by the side walls 54 formed in the chamfer 56, are each separated from one another by the bridges 72. In the representation according to Figure 6, only the first protective wafer part 16 is shown, which reproduces the grid of trenches 64 or trench structures 66 shown from the view of the back side 60 of the first protective wafer part 16. A front side of the first protective wafer part 16 is designated by reference numeral 80, and its back side is identified by reference numeral 60. On this back side, the depression 42 already shown in Figure 1 is formed to a depth 44 between 5 pm and 100 pm.

[0078] Figures 5 and 6 show that the aforementioned through-holes 82 extend laterally in the silicon material of the first protective wafer part 16, also referred to as the bottom wafer. These represent access openings for etching media, as will be explained later. The cross-sectional view in Figure 6 shows that the through-holes 82 extend continuously from the front 80 to the back 60 of the first protective wafer part 16.

[0079] A comparison of Figures 2 and 5, i.e., the front 80 and back 60 of the first protective wafer section 16 (bottom wafer), shows that the grid of the front octagons 52 is arranged relative to the square structures of the mask openings 62 such that the bridges 72 are located in the center of each side of the squares (see illustration in Figure 5). In principle, the bridges 72 can also be located in other positions relative to a square, for example, in the corners. Within the center of the squares, as shown in Figure 5, bridge piers made of silicon material remain. The surrounding free-standing square areas in the mask plane 22 are held within the composite structure by these bridge piers and by the bridge elements in the bridge plane 24. The width 74 of the bridge 72 is typically between 10 pm and 100 pm.In order to prevent the bridges 72 from shading the opening below them within the mask plane 22, the width 74 of the bridges 72 should be minimized.

[0080] The undesirable, because shadowing, effect of the bridges 72 during the etching or deposition processes (trench etching, ion beam etching, sputtering) with the shadow mask formed by the mask plane 22 can be minimized by minimizing the width 74 of the bridges 72, the lowest possible height 78 of the bridge plane 24 and the greatest possible distance between the bridges 72 and the mask plane 22.

[0081] In the etching or deposition processes mentioned above, atomic, molecular, or ionic movements predominate, impacting the substrate surface 10. Their angle of impact is approximately 90°, with a variation that depends on the system and process parameters. The proportion of ions, atoms, or molecules with a velocity vector * 90° can reach the sensitive substrate surface 10 directly below the bridging elements and effect the desired etching and / or sputtering processes there. The bridging elements only shade this area for particles that impact approximately perpendicularly, i.e., at an angle close to 90°.

[0082] Apart from the mask openings 62 in the mask plane 22, which represents the shadow mask, through-holes 82 extending from the front 80 and / or the back 60 are optionally formed in the first protective wafer part 16 (bottom wafer). These through-holes 82 serve as access openings, for example, for gaseous etching media such as SFe, XeF2, or HF in the gas phase, or for gaseous coating media, for example, atomic layer deposition (ALD) or anti-sticking coating. These enable etching or coating of the substrate surface 10 or of partial areas of the substrate surface 10 while simultaneously protecting other areas of the front of the pre-structured and / or pre-coated substrate 10 from etching or coating.

[0083] If the shadow mask, represented by the mask plane 22, is to be used for a silicon etching process, for example using SFe or XeF2, the first protective wafer part 16 (bottom wafer) made of silicon material is thermally oxidized, i.e. provided with a silicon oxide layer 20, so that it is protected from etching during the etching or sputtering processes.

[0084] The representations of the figure sequence of figures 7.1 to 7.7 show a schematic process flow for the production of the first protective wafer part 16 (bottom wafer) with a buried shadow mask integrated into the protective wafer 14 in the form of a mask plane 22.

[0085] Figure 7.1 shows a shielding wafer blank 84, from which the first shielding wafer part 16 in the form of the bottom wafer is manufactured. Its front side is designated with reference numeral 80, its back side with reference numeral 60.

[0086] Figure 7.2 shows a section through the first protective wafer part 16 corresponding to section A-A' (see also Figure 3). Second recesses 104 are etched into the silicon material of the silicon wafer blank 84 according to Figure 7.1, as shown in Figure 7.2. The first and second recesses 48, 104, as well as the through-holes 82, which are recognizable as missing silicon material in Figures 7.2 and 7.3, are etched simultaneously. The individual second recesses 104 in the silicon material of the first protective wafer part 16 are separated from each other by the bridges 72, which are formed with a length b 70, as can be seen from the section A-A' in Figure 7.2. A depth at which the bridges 72 are formed is indicated by reference numeral 76. The individual bridges 72 are undercut, as described above.During the production of the first and second recesses 48, 104 in the silicon material of the silicon wafer blank 84, the side walls 54 are formed with chamfers 56. The chamfer angle, also referred to as the etching angle, lies within a range 58 and between bridge elements between 90° and 135°.

[0087] Figure 7.3 shows a section B-B' corresponding to Figure 4. The individual second recesses 104 are covered by silicon material according to the section B-B'. Above the second recess 104, the bridge 72 runs in longitudinal section in this cross-section. The individual second recesses 104 are separated from each other by bridge piers made of silicon material. Reference numeral 82 indicates a through-hole, which is not yet fully formed and is formed as a blind hole in the silicon material of the silicon wafer blank 84.

[0088] Figure 7.4 shows that the mask openings 62 are now etched into the mask plane 22 of the first protective wafer part 16 (bottom wafer), just as the aforementioned recess 42 is formed to a depth 44 on the back 60 of the first protective wafer part 16 (bottom wafer). The individual mask openings 62 in the mask plane 22 can be formed according to the illustration in Figure 5, in the grid shown there, having parallel square grooves 64 or groove structures 66.

[0089] Figures 7.4 and 7.5 show that in this processing step of the first protective wafer part 16 (bottom wafer), the through-holes 82 from the front 80 to the back 60 in the silicon material of the first protective wafer part 16 are also created. According to Figure 7.5, the mask openings 62 within the mask plane 22 also extend into the second recesses 104, which are formed above the mask plane 22 in the silicon material of the first protective wafer part 16.

[0090] Figures 7.6 and 7.7 show that, corresponding to the two cross-sectional paths A-A' and B-B', respectively, the exposed structures are provided with a silicon oxide layer 20 by means of a thermal oxidation process. The silicon oxide coating 20 adheres to all freely accessible sides of the first protective wafer part 16. The walls bounding the through-holes 82 are also coated with the silicon oxide layer 20, as are the interiors of the second recesses 104, the boundaries of the mask openings 62 in the mask plane 22, the front 80 and the back 60 of the first protective wafer part 16, and also the sides of the bridges 72, which taper according to the etching depth, as shown in Figure 7.6. The side walls 54, which are formed in chamfers 56, are also provided with the aforementioned silicon oxide layer 20, which forms effective protection against etching processes and media used in etching.

[0091] Figures 8.1 to 8.4 show a schematic process flow for the production of the protective wafer 14, in particular for the production of the second protective wafer part 18, the cover wafer.

[0092] Starting from the silicon wafer blank 84 shown in Figure 8.1, this material is processed from its front side 88 or its back side 90.

[0093] As shown in Figure 8.2, a ring-shaped depression 86 is laterally introduced into the silicon material of the silicon wafer blank 84.

[0094] As shown in Figure 8.3, the processed silicon wafer blank 84 is coated over its entire surface on its front 88 and its back 90 by means of a thermal coating process. During the thermal coating process, the silicon oxide layer 20 is applied to the outer surfaces. This layer is also deposited in the annular recess 86 of the second protective wafer part 18, starting from its back 90.

[0095] Figure 8.4 shows that an access opening 106 can optionally be incorporated into the silicon material of the second protective wafer part 18, for example, to provide access to the individual insulated first recesses 48. Furthermore, provisions are made on the rear side 90 next to the first recesses 48 in the form of the application of an organic or inorganic bonding agent, with the aid of which bond connections 32, as indicated in Figure 1, are created for joining the first protective wafer part 16 (bottom wafer) to the second protective wafer part 18 (top wafer).

[0096] Figures 8 and 9 show the joining of the multi-part protective wafer 14, in particular the joining of the first protective wafer part 16 (bottom wafer) with the second protective wafer part 18 (top wafer). Figures 9 and 10 show that the first recesses 48 on the rear side 90 of the second protective wafer part 18 (top wafer) are almost identical to the second recesses 104 on the front side 80 of the first protective wafer part 16. The joining of the two protective wafer parts 16, 18 takes place over a surface area at the regions of the second protective wafer part 18 provided with the inorganic or organic bonding agent 96, as shown in Figure 8.4.

[0097] Figure 8.4 shows that the silicon material is etched deeper in the area of ​​the optionally formable, annular depression 86. Optionally, the first and second recesses 48, 104 can be formed at two different depths 92, 94.

[0098] Figure 9 shows that the protective wafer 14 is composed of the joined protective wafer parts 16 (bottom wafer) and 18 (top wafer). The second protective wafer part 18 is bonded to the front 880 of the first protective wafer part 16 by means of wafer bonding with its back side 90. This can be either direct bonding without an adhesive or bonding with an adhesive 96, for example Au-Au, Al-Ge, a Nano Cleave™ bond layer for a temporary, removable bond, or an epoxy-based adhesive 96.

[0099] As further shown in Figure 9, the outer surfaces of the protective wafer 14 are all provided with the silicon oxide layer 20. Reference numeral 92 denotes a first recess depth in which the first recesses 48 can be formed in the second protective wafer part 18 (top wafer), in contrast to the second recess depth 94 in which the second recesses 104 can be formed in the first protective wafer part 16 (bottom wafer). It is also possible to produce recesses of different depths within the top wafer, i.e., the second protective wafer part 18, or within the first protective wafer part 16 (bottom wafer), as can be seen, for example, in the illustration according to Figure 17. In the representation according to Figure 9, the first recess depth 92 refers to the top wafer, i.e. the second protective wafer part 18, and the second recess depth 94 refers to the bottom wafer, i.e. the first protective wafer part 16.As can be seen from the illustration in Figure 10, the material has been thinned, i.e., silicon material has been removed from the second protective wafer part 18 (cover wafer). If an annular access opening for etching media is present, the thinning, i.e., the removal of silicon material, is carried out to such an extent that ring structures on the front side 88 of the second protective wafer part 18 are exposed, but still remain covered with a residual amount of silicon material. Subsequently, silicon oxide 20 is reapplied to the front side as a protective layer. The silicon oxide 20 is retained as a silicon oxide-free area 108 within the region inside the optionally applied annular structures, so that no silicon oxide coating is present there.Figure 10 shows a completed protective wafer 14, comprising the first protective wafer part 16 in the form of the bottom wafer and the second protective wafer part 18 in the form of the top wafer, joined together by temporary or permanent bond connections 32 in the joining plane defined by the back 90 of the second protective wafer part 18 and the front 80 of the first protective wafer part 16. The buried shadow mask formed by the mask plane 22 is closed on its front side by the second protective wafer part 18 (top wafer), but open on its back side. The back 60 of the first protective wafer part 16 is bonded to the front side, i.e., the already pre-structured substrate surface 10 of the product wafer 12.

[0100] The following figures 11 to 20 each provide examples of possible applications for the use of the applications made possible by the mask plane 22 representing the buried shadow mask.

[0101] Figure 11 shows, for example, a first isolated cavity 36 and a second isolated cavity 38 formed in the silicon material of the protective wafer 14. The first cavity 36 is accessible via an access opening 110. The access opening 110 is created, for example, by means of an etching medium, such as SFβ. The product wafer 12 comprises the aforementioned pre-structured and / or pre-coated substrate surface 10, onto which the protective wafer 14, as described with reference to Figures 1 to 10 in Figure 11, is applied. This application is carried out, for example, by temporary or permanent bond connections 32, as already described above. Figure 12 shows that the substrate, i.e., the silicon material 100 of the product wafer 12, is isotropically etched via the first cavity 36 of the protective wafer 14, which is opened by the access opening 110, using SFe.Below the mask level 22, in which the mask openings 62 designed as trenches 64 or trench structure 66 are located, material is removed, leading to a etched area 112 below the mask level 22 in the first cavity 36. The second cavity 38 within the protective wafer 14 remains closed.

[0102] Figure 13 shows that the material can be coated over the entire externally exposed surface via the open first cavity 36 in the protective wafer 14, particularly in its second protective wafer part 18, for example by means of the atomic layer deposition (ALD) process. Consequently, the structures within the closed second cavity 38 remain uncoated, as there is no access to this second cavity 38 within the protective wafer 14.

[0103] Figure 14 shows that a silicon oxide layer 20 on the surfaces of previously introduced structures 118 in the silicon material 100 of the product wafer 12 can be removed via the first cavity 38 in the protective wafer 14, which is accessible through the access opening 110. This is shown in Figure 14 below the mask plane 22. In contrast, previously introduced structures 118 below the second cavity 38 are still coated with the silicon oxide layer 20, since the second cavity 38, or the previously introduced structures 118, do not provide access for the penetration of an etching medium.

[0104] Figure 15 shows that a previously existing layer of material, depicted here as a dashed line and designated with reference numeral 120, has been removed. Reference numeral 120 designates the second protective wafer part 18 (lid wafer) as a complete layer. Consequently, both cavities 36 and 38, which were previously enclosed within the protective wafer 14, are now freely accessible. In Figure 15, the mask plane 22, i.e., the previously buried shadow mask, is exposed. The mask plane 22 can now be used as a mask for an anisotropic process, such as trench etching, ion beam etching, or sputtering. The representation in Figure 15 shows that structures 118 are introduced into the substrate, i.e., the silicon material 100 on the substrate surface 10.An additional layer applied to the surface of the product substrate, such as a reflective layer 122, is first touched via the shadow mask using ion beam etching. In a subsequent second step, the structures are etched into the silicon, also via the shadow mask, using trench etching. Trench etching then follows as a further processing step. Figure 16 illustrates another possible use of the protective wafer 14. In this case, the access opening 110 is not located within the first cavity 36 in the protective wafer 14, but rather next to it. The access opening 110 transitions into a channel extension 124, which is formed in the silicon material 100 of the product wafer 12 below the pre-structured and / or pre-coated substrate surface 10. The two cavities 36, 38, below which the mask plane 22 with the mask openings 62 runs, are closed.Through the access opening 110 and the channel extension 124, previously created structures within the silicon material 100 can be etched out using SFe or XeF2. The structures to be etched must be lined with oxide to prevent etching from occurring in the first place. This oxide can then be removed using an RF vapor-phase etching process.

[0105] Figures 17, 18, and 19 show that the cavities 36 and 38 are formed at different depths, indicated here by a first recess depth 92 and a second recess depth 94, respectively. With recesses of different depths adjacent to each other—the first cavity 36 and the second cavity 38 in the protective wafer 14—it is possible to successively expose the respective mask layer 22, which forms the shadow mask. In this way, structures can first be separated below the first cavity 36, and then coated 114 using the ALD process. Subsequently, the second cavity 38 is exposed, and its introduced structures 118 can be processed. With an aluminum oxide-containing ALD layer 114, the previously introduced structures 118 are protected from further etching during trenching in the area of ​​the second cavity 38.Before exposing the mask layer 22 below the second cavity 38, the previously applied ALD layer 114 is removed. An ALD coating 114 is applied to all exposed surfaces, including the surface of the second cavity 38 as shown in Figure 18. The ALD layer 114 obtained through the ALD coating process is not explicitly shown in Figure 18. Before a trench etching process, in which the second protective wafer part 18 (lid wafer) is etched away using the shadow mask of the second cavity 38, the ALD layer 114 in this area must first be removed without removing the ALD coating on the structures in the first cavity 36. This is achieved by the fact that the etch rate of the ALD layer 114, for example during lon-beam etching, is smaller in the structures in the first cavity 36 than on the lid above the second cavity 38.

[0106] The thickness of the coating, i.e. the ALD layer 114, is to be adjusted so that after the removal of the ALD layer 114 above the second cavity 38 (see Figure 18) a sufficient thickness of the ALD layer 114 remains in the previously introduced structures 118 below the first cavity 36.

[0107] Finally, Figure 20 shows that after processing the product wafer 12, the protective wafer 14, which includes the buried shadow mask in the form of at least one mask plane 22, is bonded, for example, via infrared laser debonding (nano cleave). TM -process) is detached and removed from the product wafer 12. This is easily possible with temporarily formed bond connections 32 using an organic or inorganic joining agent 96, so that the protective wafer 14 removed from the product wafer 12 is reusable.

[0108] In the case of permanently formed bond connections 32 between the product wafer 12 and the protective wafer 14, the protective wafer 14 can be removed, for example, by means of a tape expansion process, in which, however, the protective wafer 14 cannot be removed without damage, but fails at previously introduced predetermined breaking points.

[0109] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, within the scope specified by the claims, a multitude of modifications are possible that fall within the bounds of what is considered skilled in the art.

Claims

Claims 1. Method for structuring and / or coating an already coated and / or structured substrate surface (10) of a product wafer (12) by means of a protective wafer (14) comprising at least the following process steps: a) producing a protective wafer (14) with at least one first protective wafer part (16) and at least one second protective wafer part (18), containing silicon material and provided with a Si oxide layer (20), such that b) at least one exposed mask plane (22) is integrated into the protective wafer (14), c) joining (30) the protective wafer (14) precisely aligned with the substrate surface (10) by means of at least one temporary or permanent bond connection (32), d) partially or completely opening (34) at least one cavity (36,38) in the protective wafer (14) for carrying out etching and / or coating processes on the product wafer (12) and e) removal (40) of the protective wafer (14) from the substrate surface (10) of the product wafer (12) for reuse.

2. Method according to claim 1, characterized in that according to method step a) the protective wafer (14) is manufactured with a number of levels (16, 18, 22, 24), comprising at least the first protective wafer part (16), the second protective wafer part (18) and at least the mask level (22).

3. Method according to claims 1 and 2, characterized in that the protective wafer (14) is manufactured such that it comprises at least one bridge plane (24).

4. Method according to claims 1 to 3, characterized in that the [method] integrated into the protective wafer (14) according to method step b), at least one exposed mask layer (22) is exposed as a shadow mask by means of a trench etching process or by means of reactive ion etching (RI E-etching).

5. Method according to claims 1 to 4, characterized in that, in process step d) or in addition to process step d), after exposure of the at least one mask plane (22), the substrate surface (10) is structured and / or coated in a structured manner completely or partially using anisotropic processes, in particular sputtering, trench etching or coating.

6. Method according to claims 1 to 5, characterized in that the first and second cavities (36, 38) are partially opened and isotropic etching or coating processes are carried out on exposed areas of the product wafer (12) via such opened first and second cavities (36, 38).

7. Method according to claim 6, characterized in that the opening (34) is carried out by creating access openings or by completely opening the first and second cavities (36, 38) by removing (40) cover layers of different thicknesses.

8. Method according to claims 1 to 7, characterized in that the protective wafer (12) is provided on its back side (28) facing the substrate surface (10) with at least one recess (42) whose depth (44) has a clear distance (46) between the at least one mask plane (22) and the substrate surface (10) to be structured and / or coated.

9. Method according to claim 8, characterized in that the depth (44) of the at least one depression (42) on the protective wafer (14) is in a range between 5 pm and 100 pm.

10. Method according to claims 1 to 9, characterized in that an organic or an inorganic joining agent (96) is used for joining (30) according to process step c), wherein, when at least one temporary bond (32) is formed, it is releasable and the protective wafer (14) is removed, or, in the case of the formation of at least one permanent bond (32), the protective wafer (14) is removed by means of stealth dicing or a tape expansion process.

11. Method according to claims 1 to 10, characterized in that according to method step a) the first protective wafer part (16) is designed as a bottom wafer and starting from its front (26) recesses (48) with side walls (54) with a chamfer (56) in an angle range (58) between 90° and 135° are formed by trench etching.

12. Method according to claims 1 to 11, characterized in that mask openings (62) of the at least one mask plane (22) are formed, preferably etched, on a back side (60) of the first protective wafer part (16).

13. Method according to claims 1 to 12, characterized in that the mask openings (62) are designed as circumferential square, rectangular or trapezoidal trenches (64) or trench structures (66).

14. Method according to claims 1 to 13, characterized in that the recesses (48) are designed as a polygonal structure (50), in particular as an octagon (52), which are arranged a distance b (70) from each other, wherein the lengths b (70) each form bridges (72).

15. Method according to claims 1 to 14, characterized in that the bridges (72) are designed in a width (74) that decreases with the etching depth and are undercut at a depth t (76).

16. Method according to claims 1 to 15, characterized in that a shading effect of the bridges (72) during the processing processes, in particular etching or precipitation processes, preferably trench etching, ion-beam etching or sputtering, is achieved by a Minimizing the width (74) of the bridges (72) and / or minimizing the height (78) of the bridge plane (24) and / or maximizing the distance between the bridges (72) and the mask plane (22) is minimized.

17. Method according to claims 1 to 16, characterized in that through-holes (82) for gaseous etching media, preferably SFe, XeF2, HF in gas phase or for gaseous media for coating, in particular atomic layer deposition processes or anti-sticking coating, are provided in the first protective wafer part (16) from its rear side (60) or from its front side (80).

18. Method according to claims 1 to 17, characterized in that at least the first protective wafer part (16) is thermally oxidized.

19. Method according to claims 1 to 18, characterized in that the production of the second protective wafer part (18) by Providing a silicon wafer blank (84), introducing at least one partially executed, annular depression (86), thermally oxidizing the second protective wafer part (18), introducing recesses (104) on a back side (90) of the second protective wafer part (18) congruent with those recesses (48) on the front side (80) of the first protective wafer part (16).

20. Method according to claim 19, characterized in that the recesses (48, 104) are made at different depths (92, 94).

21. Method according to claims 1 to 20, characterized in that the protective wafer (14), comprising at least the first protective wafer part (16), the second protective wafer part (18) and the mask layer (22), is produced by Applying the second protective wafer part (18) with its back side (90) to the front side (80) of the first protective wafer part (16) by means of wafer bonding such that direct bonding without bonding agent (96) or bonding with bonding agent (96), in particular Au-Au, Al-Ge or a Nano Cleave™ bond layer, is carried out, Thinning the second protective wafer part (18) at the front (88) to expose ring structures (98) on the front (88) and applying an oxide to the front (88), removing it in the area of ​​the ring structures (98).

22. Method according to claims 1 to 21, characterized in that the protective wafer (14), which has several levels (16, 18, 22, 24) and is closed on its front side (26) by means of the second protective wafer part (18), and has an open back side (28), is applied to a substrate surface (10) of the product wafer (12) that is already fully or partially pre-structured and / or coated by bonding.

23. Protective wafer (14) with integrated shadow mask, in particular at least one mask plane (22), manufactured according to the method of any one of claims 1 to 22.

24. Use of the method according to one of the preceding claims for producing a protective wafer (14) having a shadow mask and applying it to a structured / coated substrate surface (10) of a product wafer (12).

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