Beamformer integrated circuit and phased array antenna module

Abstract

This beamformer integrated circuit comprises: a memory (13) that stores an intensity setting value that defines the intensity adjustment amount of a high-frequency signal that is a signal to be supplied to each of a plurality of antenna elements or a signal to be supplied from each of the plurality of antenna elements; a circuit unit that has at least one amplifier (for example, a variable gain amplifier (63), a power amplifier (65)) that amplifies the high-frequency signal; and a power supply control unit (70) that can interrupt power supply to the at least one amplifier if the intensity setting value read from the memory (13) is 0.

Description

Beamformer integrated circuit and phased array antenna module

[0001] This disclosure relates to a beamformer integrated circuit and a phased array antenna module. This application claims priority to Japanese Patent Application No. 2024-082748, filed May 21, 2024, the contents of which are incorporated herein by reference.

[0002] A phased array antenna is an antenna that can freely change its beam pattern (antenna directivity) by adjusting at least one of the strength and phase of a signal (transmitted signal) supplied to a plurality of antenna elements or a signal (received signal) supplied from a plurality of antenna elements. In recent years, such phased array antennas have been used in various fields, including the automotive and communications fields.

[0003] A phased array antenna module is a module including multiple antenna elements and a beamformer integrated circuit. The beamformer integrated circuit includes multiple phase shifters corresponding to the multiple antenna elements and a circuit for setting phase shift amounts for the multiple phase shifters. In addition, the beamformer integrated circuit may also include intensity controllers corresponding to the multiple antenna elements. A required beam pattern is formed by setting appropriate settings for the phase shifters and intensity controllers and adjusting the phases and intensities of multiple signals supplied from (or to) the multiple antenna elements. For a conventional phased array antenna module, see, for example, Patent Document 1 below.

[0004] U.S. Pat. No. 1,133,603

[0005] In recent years, growing environmental awareness has led to demands for energy conservation in various devices. Energy conservation is also being demanded for base station equipment used in wireless communication systems. For example, wireless communication systems using millimeter waves require base station equipment to be installed at a higher density than conventional wireless communication systems, making energy conservation in base station equipment extremely important. To achieve energy conservation in base station equipment equipped with phased array antennas, it is necessary to reduce the power consumption of beamformer integrated circuits and phased array antenna modules.

[0006] The present disclosure has been made in consideration of the above circumstances, and aims to provide a beamformer integrated circuit and a phased array antenna module that can reduce power consumption more than conventional ones.

[0007] In order to solve the above problem, a beamformer integrated circuit (10) according to a first aspect of the present disclosure comprises a memory (13) that stores an intensity setting value that specifies the amount of intensity adjustment of a high-frequency signal that is a signal supplied to a plurality of antenna elements (21) or a signal supplied from a plurality of the antenna elements, a circuit unit (12) having at least one amplifier (63, 65, 67, 68) that amplifies the high-frequency signal, and a power supply control unit (70) that can cut off the power supply to the at least one amplifier when the intensity setting value read from the memory is 0.

[0008] In a beamformer integrated circuit according to a first aspect of the present disclosure, a memory stores an intensity setting value that defines an intensity adjustment amount for a radio frequency signal that is a signal supplied to or from a plurality of antenna elements. When the intensity setting value read from the memory is 0, the power supply control unit can cut off the power supply to the amplifier that amplifies the radio frequency signal. This makes it possible to reduce power consumption more than before.

[0009] Furthermore, a beamformer integrated circuit according to a second aspect of the present disclosure is a beamformer integrated circuit according to the first aspect of the present disclosure, wherein the circuit unit includes as the amplifiers a first amplifier (63, 68) that amplifies the high-frequency signal based on the intensity setting value stored in the memory, and a second amplifier (65, 67) that amplifies the high-frequency signal at a predetermined amplification factor, and the power supply control unit is capable of cutting off the power supply to at least one of the first amplifier and the second amplifier.

[0010] In addition, a beamformer integrated circuit according to a third aspect of the present disclosure is a beamformer integrated circuit according to the first or second aspect of the present disclosure, wherein the power supply control unit includes a judgment circuit (71) that judges whether the intensity setting value read from the memory is 0 or not, and a circuit breaker (72, 73) that can cut off the power supply to the amplifier depending on the judgment result of the judgment circuit.

[0011] Furthermore, a beamformer integrated circuit according to a fourth aspect of the present disclosure is a beamformer integrated circuit according to the third aspect of the present disclosure, which includes a memory unit (74) that stores a first setting value that enables the cutting off of power supply to the amplifier, or a second setting value that disables the cutting off of power supply to the amplifier, and the circuit breaker cuts off the power supply to the amplifier when the first setting value is stored in the memory unit, and supplies power to the amplifier when the second setting value is stored in the memory unit.

[0012] Furthermore, a beamformer integrated circuit according to a fifth aspect of the present disclosure is a beamformer integrated circuit according to any one of the first to fourth aspects of the present disclosure, wherein the memory further stores a phase shift amount setting value that specifies the phase shift amount of the high-frequency signal, and the circuit unit further includes a phase shifter (61) that adjusts the phase shift amount of the high-frequency signal based on the phase shift amount setting value stored in the memory.

[0013] Furthermore, a beamformer integrated circuit according to a sixth aspect of the present disclosure is a beamformer integrated circuit according to the fifth aspect of the present disclosure, in which the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory stores a beam table (BT) in which multiple combinations of the intensity setting value and the phase shift setting value are stored.

[0014] A phased array antenna module (1) according to a seventh aspect of the present disclosure comprises a plurality of antenna elements (21) and a beamformer integrated circuit (10) according to any one of the first to sixth aspects of the present disclosure connected to the plurality of antenna elements.

[0015] According to the present disclosure, there is an effect that power consumption can be reduced more than before.

[0016] FIG. 1 is a system configuration diagram showing the configuration of a phased array antenna module according to a first embodiment of the present disclosure. FIG. 2 is a block diagram showing the configuration of a main part of a beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing the connection relationship between a digital circuit unit and an analog circuit unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 4 is a block diagram showing the configuration of a main part of a power supply control unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure. FIG. 5 is a diagram for explaining a beam table used in the first embodiment of the present disclosure. FIG. 6 is a flowchart for explaining a beam pattern setting method according to the first embodiment of the present disclosure. FIG. 7 is a block diagram showing the configuration of a main part of a power supply control unit provided in the RF front end of the beamformer integrated circuit according to a second embodiment of the present disclosure. FIG. 8 is a diagram showing the power consumption of a phased array antenna module according to an embodiment of the present disclosure and a conventional phased array antenna module.

[0017] Hereinafter, beamformer integrated circuits and phased array antenna modules according to embodiments of the present disclosure will be described in detail with reference to the drawings.

[0018] A phased array antenna module according to a first embodiment of the present disclosure is provided in, for example, a wireless communication device that uses millimeter waves and is capable of beamforming, which allows the beam pattern to be freely changed. The phased array antenna module includes, for example, a plurality of integrated circuits (ICs) mounted on one side of a substrate such as a known printed circuit board, and an antenna array mounted on the other side.

[0019] The integrated circuits and antenna array constituting the phased array antenna module are formed using known materials and methods. Furthermore, the electrical connection structures between the integrated circuits and between the integrated circuits and the antenna array are not particularly limited. Known connection structures may be used as the electrical connection structures.

[0020] 1 is a system configuration diagram showing the configuration of a phased array antenna module according to a first embodiment of the present disclosure. As shown in Fig. 1, the phased array antenna module 1 includes eight beamformer integrated circuits 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H (hereinafter referred to as beamformer integrated circuits 10A to 10H), an antenna array 20, a frequency conversion integrated circuit 30, and an RF signal coupler / splitter 40.

[0021] The phased array antenna module 1 is connected to the control device 50 via a signal line 51, a control line 52, and a power line 53. An RF signal at an IF (intermediate frequency) signal frequency is transmitted and received between the control device 50 and the phased array antenna module 1 via the signal line 51. Communication messages related to control are transmitted and received between the control device 50 and the phased array antenna module 1 via the control line 52. Power is supplied from the control device 50 to the phased array antenna module 1 via the power line 53.

[0022] The beamformer integrated circuits 10A to 10H are integrated circuits that control the beam pattern of the antenna array 20. A plurality of antenna elements 21 that constitute the antenna array 20 are connected to each of the beamformer integrated circuits 10A to 10H. For example, eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization are connected to each of the beamformer integrated circuits 10A to 10H. In other words, the antenna array 20 is composed of a total of 128 antenna elements 21, including 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. The beamformer integrated circuits 10A to 10H will be described in detail later.

[0023] The frequency conversion integrated circuit 30 is an integrated circuit that performs frequency conversion between an RF signal at an IF signal frequency and an RF signal at a frequency that is transmitted and received by the beamformer integrated circuits 10A to 10H and the antenna array 20.

[0024] The RF signal coupler / splitter 40 distributes the RF signal output from the frequency conversion integrated circuit 30 to each of the beamformer integrated circuits 10A to 10H. The RF signal coupler / splitter 40 also combines the RF signals received by each of the beamformer integrated circuits 10A to 10H and inputs the combined signals to the frequency conversion integrated circuit 30.

[0025] <Beamformer Integrated Circuit> Figure 2 is a block diagram showing the configuration of the main parts of a beamformer integrated circuit according to the first embodiment of the present disclosure. The eight beamformer integrated circuits 10A to 10H have the same configuration. Therefore, in the following description, only one of the beamformer integrated circuits 10A to 10H, i.e., the beamformer integrated circuit 10, may be described. Description of the other seven beamformer integrated circuits may be omitted.

[0026] The beamformer integrated circuit 10 includes 16 RF front ends (RFFEs) 5A to 5P, a digital circuit 6, an analog circuit 7, and an RF signal coupler / splitter 8. The 16 RF front ends 5A to 5P have the same configuration. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., the RF front end 5, may be described. Description of the other 15 RF front ends may be omitted.

[0027] 2, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P so that there is a one-to-one correspondence between one antenna element 21 and one RF front end 5. Of the 16 RF front ends 5A to 5P and the 16 antenna elements 21A to 21P, eight RF front ends (e.g., RF front ends 5A to 5H) and eight antenna elements (e.g., antenna elements 21A to 21H) are for horizontal polarization, and the remaining eight RF front ends (e.g., RF front ends 5I to 5P) and eight antenna elements (e.g., antenna elements 21I to 21P) are for vertical polarization.

[0028] The 16 antenna elements 21A to 21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A to 21P, i.e., antenna element 21, may be described. Description of the other 15 antenna elements may be omitted. The antenna elements 21A to 21P may have the same configuration. Regarding the configuration of each of the antenna elements 21A to 21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may be slightly different.

[0029] In this way, in one beamformer integrated circuit 10, each of the 16 RF front ends 5A to 5P is connected to each of the 16 antenna elements 21A to 21P in a one-to-one correspondence. Therefore, in the entire phased array antenna module 1 having eight beamformer integrated circuits 10A to 10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A to 5P in each of the eight beamformer integrated circuits 10A to 10H.

[0030] The 128 antenna elements 21 that make up the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. The eight beamformer integrated circuits 10A-10H control the transmission and reception of horizontally polarized radio waves in the 64 antenna elements 21, and also control the transmission and reception of vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized radio waves and vertically polarized radio waves, the beamformer integrated circuits 10A-10H set the phase and intensity of each of the 64 antenna elements so that the direction of the composite radio waves transmitted or received from the 64 antenna elements 21 is a predetermined direction.

[0031] 2, the RF front end 5 includes a digital circuit unit 11 and an analog circuit unit 12 (circuit unit). The digital circuit unit 11 transmits and receives control-related communication messages to and from the control device 50 via the control line 52 shown in FIG. 1. The digital circuit unit 11 controls the RF front end 5 based on the communication messages transmitted from the control device 50.

[0032] In this embodiment, communication messages related to control are transmitted and received between the phased array antenna module 1 and the control device 50 through parallel communication. That is, the digital circuit unit 11 transmits and receives communication messages related to control with the control device 50 through parallel communication. Note that the communication between the phased array antenna module 1 and the control device 50 is not limited to parallel communication. It may be serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).

[0033] The digital circuit unit 11 is connected to the digital circuit 6 by wiring (not shown) inside the beamformer integrated circuit 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 50. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the contents of a communication message transmitted from the control device 50.

[0034] Each communication transaction sent from the control device 50 to the phased array antenna module 1 includes additional information, a command, and data. The communication transaction has a fixed bit length. The command is a register address when instructing writing to or reading from a register. Alternatively, the command is a numerical value indicating an operation instruction to the beamformer integrated circuit 10 or the RF front end 5. The command and data have a fixed length. In this embodiment, the command is 8 bits and the data is 16 bits.

[0035] The digital circuit unit 11 includes a memory 13, which is a storage area for storing a beam table BT (see FIG. 5 ) used for beamforming. The beam table BT is a lookup table that stores multiple combinations of phase-shift setting values ​​and intensity setting values, which are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (a beam table with 2048 items) that defines 2048 combinations of phase-shift setting values ​​and intensity setting values ​​is stored in the memory 13. The beam table BT is written to or read from the memory 13 using an 11-bit address. For example, the phase-shift setting value is 7 bits, and the intensity setting value is 5 bits. In other words, 12 bits of information are stored in each address of the memory 13. Details of the beam table BT will be described later.

[0036] The memory 13 is realized using, for example, a static random access memory (SRAM). Although it is preferable that the memory 13 be realized using an SRAM, the memory 13 may also be realized using a register, a dynamic random access memory (DRAM), a flash memory, or a read only memory (ROM).

[0037] The analog circuit unit 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit unit 11, the analog circuit unit 12 adjusts the phase and intensity of the RF signal transmitted and received by the antenna element 21 connected to the RF front end 5.

[0038] The analog circuit unit 12 is connected to the analog circuit 7 via an RF signal coupler / splitter 8. The RF signal coupler / splitter 8 distributes the RF signal output from the analog circuit 7 to the analog circuit units 12 provided in each of the RF front ends 5A to 5P. The RF signal coupler / splitter 8 also combines the RF signals output from the analog circuit units 12 provided in each of the RF front ends 5A to 5H and outputs the combined signal to the analog circuit 7.

[0039] As shown in FIG. 2 , the analog circuit unit 12 includes a phase shifter (PS) 61, a changeover switch (SW) 62, a variable gain amplifier (VGA) 63, a phase inverter (PI) 64, a power amplifier (PA) 65, a changeover switch (SW) 66, a low noise amplifier (LNA) 67, a variable gain amplifier (VGA) 68, and a phase inverter (PI) 69.

[0040] The variable gain amplifier 63, phase inverter 64, and power amplifier 65 are provided on the transmission path R1, while the low-noise amplifier 67, variable gain amplifier 68, and phase inverter 69 are provided on the reception path R2. The transmission path R1 is a path through which an RF signal (high-frequency signal) output to the antenna element 21 passes, and the reception path R2 is a path through which an RF signal (high-frequency signal) input from the antenna element 21 passes. The changeover switches 62 and 66 switch between connecting the transmission path R1 or the reception path R2 between the phase shifter 61 and the antenna element 21 at specified time intervals. This allows the phased array antenna module 1 to transmit and receive high-frequency signals as a time-division multiplexing system.

[0041] The phase shifter 61 adjusts the phase shift of the RF signal passing through the transmission path R1 or the RF signal passing through the reception path R2 in accordance with the phase shift setting value of the beam table BT read from the memory 13 of the digital circuit unit 11. In other words, the phase shifter 61 is provided in common to the transmission path R1 and the reception path R2. Note that the phase shifter 61 common to the transmission path R1 and the reception path R2 may be omitted, and a phase shifter may be provided separately for the transmission path R1 and the reception path R2.

[0042] The variable gain amplifier 63 (amplifier, first amplifier) ​​amplifies the RF signal passing through the transmission path R1 in accordance with the intensity setting value of the beam table BT read from the memory 13. The phase inverter 64 inverts the phase of the RF signal passing through the transmission path R1 in accordance with the phase shift setting value of the beam table BT read from the memory 13. The power amplifier 65 (amplifier, second amplifier) ​​amplifies the RF signal passing through the transmission path R1 by a predetermined amplification factor. By adjusting the phase shift and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0043] The low-noise amplifier 67 (amplifier, second amplifier) ​​amplifies the RF signal output from the selector switch 66 at a predetermined amplification factor. The variable gain amplifier 68 (amplifier, first amplifier) ​​amplifies the RF signal passing through the receiving path R2 in accordance with the intensity setting value of the beam table BT read from the memory 13. The phase inverter 69 inverts the phase of the RF signal passing through the receiving path R2 in accordance with the phase shift setting value of the beam table BT read from the memory 13. By adjusting the phase shift and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0044] 3 is a diagram showing the connection relationship between a digital circuit unit and an analog circuit unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure. As shown in FIG. 3, a phase shifter 61, variable gain amplifiers 63 and 68, and phase inverters 64 and 69 provided in the analog circuit unit 12 are controlled according to the contents of a beam table BT stored in the memory 13. In contrast, selector switches 62 and 66, a power amplifier 65, and a low-noise amplifier 67 provided in the analog circuit unit 12 are controlled by logic circuits (not shown), such as registers, provided in the digital circuit unit 11.

[0045] 3, the digital circuit unit 11 includes a memory 13 and an expansion circuit 14. The expansion circuit 14 expands the bit string of the phase shift amount setting value of the beam table BT read from the memory 13 into a bit string of a control value (phase shifter control value) for controlling the phase shifter 61. For example, the expansion circuit 14 expands a bit string of 6 bits of the 7-bit phase shift amount setting value into a bit string of a 46-bit control value. The remaining 1 bit of the phase shift amount setting value is used to control the phase inverters 64 and 69. The number of bits of the phase shift amount setting value is set according to the resolution of the phase shift amount, and the number of bits of the control value is set according to the number of division units constituting the phase shifter 61.

[0046] In this embodiment, the power supply to at least one of the variable gain amplifier 63 and the power amplifier 65 provided on the transmission path R1 can be cut off. Also, in this embodiment, the power supply to at least one of the low noise amplifier 67 and the variable gain amplifier 68 provided on the reception path R2 can be cut off. This is to suppress the power consumption of the beamformer integrated circuit 10, and therefore the power consumption of the phased array antenna module 1.

[0047] 4 is a block diagram showing the configuration of a main part of a power supply control unit provided in the RF front end of the beamformer integrated circuit according to the first embodiment of the present disclosure, in which a power supply control unit 70 provided for the variable gain amplifier 63 and the power amplifier 65 on the transmission path R1 is illustrated as an example.

[0048] 4, the power supply control unit 70 includes a determination circuit 71, a circuit breaker 72, and a circuit breaker 73. When the intensity setting value of the beam table BT read from the memory 13 is 0, the power supply control unit 70 cuts off the power supply to the variable gain amplifier 63 and the power amplifier 65 provided on the transmission path R1.

[0049] The determination circuit 71 is provided, for example, inside the digital circuit unit 11, and determines whether or not the intensity setting value of the beam table BT read from the memory 13 is 0. Note that the determination circuit 71 may be provided outside the digital circuit unit 11, as long as it can determine whether or not the intensity setting value of the beam table BT read from the memory 13 is 0.

[0050] The circuit breaker 72 is provided between the bias circuit 80 and the variable gain amplifier 63. When the determination circuit 71 determines that the intensity setting value of the beam table BT read from the memory 13 is 0, the circuit breaker 72 cuts off the power supplied from the bias circuit 80 to the variable gain amplifier 63. The circuit breaker 73 is provided between the bias circuit 80 and the power amplifier 65. When the determination circuit 71 determines that the intensity setting value of the beam table BT read from the memory 13 is 0, the circuit breaker 73 cuts off the power supplied from the bias circuit 80 to the power amplifier 65.

[0051] Here, when the receive path R2 is connected between the phase shifter 61 and the antenna element 21 by the changeover switches 62 and 66, the circuit breakers 72 and 73 preferably cut off the power supplied from the bias circuit 80 to the variable gain amplifier 63 and the power amplifier 65. This makes it possible to suppress unnecessary power consumption by the variable gain amplifier 63 and the power amplifier 65 during reception. Note that, while it is preferable to cut off the power supplied to both the variable gain amplifier 63 and the power amplifier 65 during reception, it is also possible to cut off the power supplied to either the variable gain amplifier 63 or the power amplifier 65.

[0052] The bias circuit 80 supplies the variable gain amplifier 63 and the power amplifier 65 with the power required to operate the variable gain amplifier 63 and the power required to operate the power amplifier 65. The bias circuit 80 may be divided into one that supplies power to the variable gain amplifier 63 and one that supplies power to the power amplifier 65.

[0053] 4 may also be provided for the low-noise amplifier 67 and the variable gain amplifier 68 on the reception path R2. When the transmission path R1 is connected between the phase shifter 61 and the antenna element 21 by the selector switches 62 and 66, the circuit breakers 72 and 73 of this power supply control unit preferably cut off the power supplied from the bias circuit 80 to the low-noise amplifier 67 and the variable gain amplifier 68. This makes it possible to suppress unnecessary power consumption by the low-noise amplifier 67 and the variable gain amplifier 68 during transmission. While it is preferable to cut off the power supplied to both the low-noise amplifier 67 and the variable gain amplifier 68 during transmission, it is also possible to cut off the power supplied to either the low-noise amplifier 67 or the variable gain amplifier 68.

[0054] <Beam Table> Fig. 5 is a diagram for explaining the beam table used in the first embodiment of the present disclosure. Note that Fig. 5 shows the beam table BT stored in the memory 13, in association with a parameter P1 for specifying an address in the memory 13 and a parameter P2 for specifying a beam pattern.

[0055] 5, the beam table BT stored in the memory 13 defines 2048 combinations of phase-shift setting values ​​and intensity setting values ​​(a beam table with 2048 items). For example, a phase-shift setting value indicated as "RFFE00Phase0000" and an intensity setting value indicated as "RFFE00Gain0000" are stored at address "0" of the memory 13. Also, a phase-shift setting value indicated as "RFFE00Phase2047" and an intensity setting value indicated as "RFFE00Gain2047" are stored at address "2047" of the memory 13.

[0056] 5, the phase shift amount setting value is 7 bits, and the intensity setting value is 5 bits. That is, 12 bits of information are stored in each address of the memory 13. Of the 7 bits of the phase shift amount setting value, the most significant bit (MSB) is used to control the phase inverters 64 and 69, and the remaining 6 bits are used to control the phase shifter 61.

[0057] When the most significant bit of the phase shift amount setting value is "1", phase inversion is instructed to the phase inverters 64 and 69. This corresponds to setting a phase shift amount of 180 degrees. The lowest 6 bits of the phase shift amount setting value are used to specify which of the 46 divided units constituting the phase shifter 61 is to change its state. When the value of the lowest 6 bits of the phase shift amount setting value is "0", all of the 46 divided units constituting the phase shifter 61 are in the reference state. When the value is "1" to "46", the divided units corresponding to that value are set to the phase-shifted state. Note that when the value of the lowest 6 bits of the phase shift amount setting value is "46", all of the 46 divided units constituting the phase shifter 61 are set to the phase-shifted state. In other words, when the phase shifter 61 is composed of 46 divided units, the phase shift state of the phase shifter 61 can be set to 47 stages.

[0058] The phase shifter 61 is designed so that the phase shift amount exceeds 180 degrees when all 46 divided units are set to a phase-shifted state in the frequency range used by the phased array antenna module 1. Note that, in this embodiment, a configuration is described as an example in which the phase shift amount of the RF signal passing through the transmission path R1 or the reception path R2 is adjusted by combining the phase inverters 64, 69 with the phase shifter 61 capable of setting a phase shift amount exceeding 180 degrees, but this configuration is not limited to this. A configuration may also be used in which only a phase shifter capable of setting a phase shift amount exceeding 360 degrees is used without using the phase inverters 64, 69.

[0059] As described above, the least significant 6 bits of the phase shift amount setting value are expanded by the expansion circuit 14 shown in Fig. 3 into a bit string (46 bits) of a control value (phase shifter control value) for controlling the phase shifter 61. That is, the least significant 6 bits of the phase shift amount setting value are expanded into a bit string having the same number of bits as the number of division units constituting the phase shifter 61. The number of division units constituting the phase shifter 61 is not limited to 46, and any number may be used.

[0060] The five bits of the intensity setting value are amplification factor setting values ​​that define the amplification factors of the variable gain amplifiers 63, 68. By individually setting the five-bit intensity setting values ​​to the variable gain amplifiers 63, 68, the signal strengths of the RF signal passing through the transmission path R1 and the RF signal passing through the reception path R2 are individually adjusted. When the intensity setting value is "31" (binary notation "11111"), the gains of the variable gain amplifiers 63, 68 are maximized, and when the intensity setting value is "0" (binary notation "00000"), the gains of the variable gain amplifiers 63, 68 are minimized.

[0061] In this embodiment, as described above, when the intensity setting value of the beam table read from the memory 13 is 0, the power supply to the variable gain amplifier 63 and the power amplifier 65 provided on the transmission path R1 is cut off. This stops the radiation of electromagnetic waves from the antenna elements 21 corresponding to the variable gain amplifier 63 and the power amplifier 65 to which the power supply has been cut off. Note that when the intensity setting value of the beam table read from the memory 13 is 0, the power supply to the low noise amplifier 67 and the variable gain amplifier 68 provided on the reception path R2 may also be cut off.

[0062] <Beam Pattern Setting Method> Fig. 6 is a flowchart for explaining a beam pattern setting method according to the first embodiment of the present disclosure. For ease of understanding, the following description will be given taking as an example a case where a beam pattern is set during transmission. Note that a beam pattern during reception is also set by performing processing similar to the processing of the flowchart shown in Fig. 6.

[0063] <<First Step>> In the first step S11, the control device 50 transmits a communication message having a fixed bit length in a communication transaction specifying a beam index to the phased array antenna module 1 via the control line 52. This communication message includes a command indicating beam selection and data specifying the beam index. In the example shown in Fig. 5, the data specifying the beam index is a numerical value ranging from "0" to "2047," and this numerical value is used to specify an address in the memory 13.

[0064] The communication message transmitted from the control device 50 to the phased array antenna module 1 via the control line 52 is input to the beamformer integrated circuit 10 shown in Fig. 2. Then, in the beamformer integrated circuit 10, the communication message is input to the digital circuit section 11 of the RF front end 5 via the digital circuit 6.

[0065] In the second step S12, the digital circuit unit 11 of the RF front end 5 reads the beam table BT from the memory 13 based on the contents of the communication message transmitted from the control device 50. Specifically, the digital circuit unit 11 uses the beam index included in the communication message as a read address, and reads the 12-bit data DT stored at that address.

[0066] 5, the 12-bit data DT read from the memory 13 includes a 7-bit phase shift amount setting value and a 5-bit intensity setting value. The 7-bit phase shift amount setting value includes a 1-bit phase inverter setting value and a 6-bit phase shifter setting value.

[0067] The third step S13, the fourth step S14, the fifth step S15 and the sixth step S16 following the second step S12 are each performed in parallel.

[0068] <<Third Step>> In the third step S13, the digital circuit unit 11 outputs the 1-bit phase inverter setting value of the beam table BT read out in the second step to the phase inverter 64 as a 1-bit phase inverter control value. In addition, the expansion circuit 14 of the digital circuit unit 11 expands the 6-bit phase shifter setting value into a 46-bit phase shifter control value and outputs it to the phase shifter 61. The phase inverter control value and the phase shifter control value are input to the phase inverter 64 and the phase shifter 61, respectively, to set a phase shift amount corresponding to the 7-bit phase shift amount setting value of the beam table BT. This sets the beam pattern of the phased array antenna module 1.

[0069] <<Fourth Step>> In the fourth step S14, the digital circuit unit 11 converts the 5-bit intensity setting value of the beam table BT read out in the second step into a 5-bit intensity control value and outputs it to the variable gain amplifier 63. By inputting this intensity control value to the variable gain amplifier 63, a gain corresponding to the 5-bit intensity setting value of the beam table BT is set in the variable gain amplifier 63.

[0070] <<Fifth Step>> In the fifth step S15, the determination circuit 71 shown in Fig. 4 determines whether the intensity setting value of the beam table BT read out in the second step is 0. If the determination circuit 71 determines that the intensity setting value of the beam table BT is 0, the process proceeds to the sixth step S16.

[0071] 4 cut off the power supplied from the bias circuit 80 to the variable gain amplifier 63 and the power amplifier 65. Note that, because the power is cut off, the variable gain amplifier 63 and the power amplifier 65 do not operate, and therefore, the phase shift amount set value set in the third step S13 and the intensity set value set in the processing of the fourth step S14 do not function effectively.

[0072] As described above, in this embodiment, the beam table BT including the intensity setting values ​​that define the intensity adjustment amounts of the RF signals supplied to the plurality of antenna elements 21 or the RF signals supplied from the plurality of antenna elements 21 is stored in the memory 13. When the intensity setting value of the beam table BT read from the memory 13 is 0, the power supply to at least one amplifier that amplifies the RF signals (for example, the variable gain amplifier 63 and the power amplifier 65) is cut off. This makes it possible to reduce power consumption more than in the past.

[0073] Here, conventionally, power is supplied to an amplifier (for example, a variable gain amplifier) ​​even when the intensity setting value of the beam table read from memory is 0. Therefore, even when the gain of the variable gain amplifier is set to the minimum, the variable gain amplifier has a constant gain, and therefore, electromagnetic waves of a constant intensity are emitted from the antenna element corresponding to the variable gain amplifier.

[0074] In contrast, in this embodiment, when the intensity setting value of the beam table BT read from the memory 13 is 0, the power supply to the amplifiers (the variable gain amplifier 63 and the power amplifier 65) is cut off. This stops the emission of electromagnetic waves from the antenna element corresponding to that amplifier. In this way, this embodiment can reduce power consumption more than conventional systems.

[0075] Second Embodiment Next, a second embodiment of the present disclosure will be described. The phased array antenna module and beamformer integrated circuit of this embodiment have substantially the same configurations as the phased array antenna module 1 of the first embodiment shown in Fig. 1 and the beamformer integrated circuit 10 shown in Fig. 2, but the configuration of the power supply control unit 70 (see Fig. 4) is slightly different. The following mainly describes the parts that are different from the first embodiment.

[0076] Fig. 7 is a block diagram showing the configuration of the main parts of a power supply control unit provided in the RF front end of a beamformer integrated circuit according to a second embodiment of the present disclosure. In Fig. 7, the same components as those shown in Fig. 4 are denoted by the same reference numerals. Similarly to Fig. 4, Fig. 7 illustrates a power supply control unit 70 provided for a variable gain amplifier 63 and a power amplifier 65 on a transmission path R1 as an example.

[0077] 7 , the power supply control unit 70 in this embodiment includes a register 74 (storage unit) in addition to a determination circuit 71, a circuit breaker 72, and a circuit breaker 73. The power supply control unit 70 can enable or disable the cutoff of power supply to the variable gain amplifier 63 and the power amplifier 65 according to the setting value stored in the register 74.

[0078] In the first embodiment, when the intensity setting value of the beam table BT read from the memory 13 is 0, the power supply to the variable gain amplifier 63 and the power amplifier 65 is cut off, thereby reducing power consumption more than in the past. However, depending on the application of the phased array antenna module 1, there are cases where forming a desired beam pattern takes priority over reducing power consumption. This embodiment can also accommodate such cases.

[0079] The register 74 is provided, for example, inside the digital circuit unit 11, and stores a first setting value that enables the cutoff of power supply to the variable gain amplifier 63 and the power amplifier 65 on the transmission path R1, or a second setting value that disables the cutoff of power supply. Note that the register 74 may be provided outside the digital circuit unit 11 and connected to the circuit breakers 72 and 73.

[0080] The first set value or the second set value is stored in the register 74 in accordance with an instruction from an operator, for example, before the beamformer integrated circuit or the phased array antenna module 1 is shipped from a factory or when the phased array antenna module is installed. For example, if priority is given to reducing power consumption, the first set value is stored in the register 74, and if priority is given to forming a desired beam pattern, the second set value is stored in the register 74.

[0081] When a first set value is stored in the register 74, the circuit breakers 72 and 73 can cut off the power supply to the variable gain amplifier 63 and the power amplifier 65. In contrast, when a second set value is stored in the register 74, the circuit breakers 72 and 73 cannot cut off the power supply to the variable gain amplifier 63 and the power amplifier 65. In other words, when the second set value is stored in the register 74, the circuit breakers 72 and 73 cannot cut off the power supply to the variable gain amplifier 63 and the power amplifier 65 even if the intensity set value of the beam table BT read from the memory 13 is 0.

[0082] A power supply control unit similar to the power supply control unit 70 shown in FIG. 7 may also be provided for the low noise amplifier 67 and the variable gain amplifier 68 on the receiving path R2.

[0083] As described above, the phased array antenna module and beamformer integrated circuit of this embodiment make it possible to enable or disable the cutoff of power supply to the variable gain amplifier 63 and the power amplifier 65 according to the setting value stored in the register 74. When the first setting value is stored in the register 74, the beam pattern is set by performing the processing of the flowchart shown in Fig. 6, as in the first embodiment. On the other hand, when the second setting value is stored in the register 74, the beam pattern is set by performing the same processing as in the conventional case, except that the fifth step S15 and the sixth step S16 in the flowchart shown in Fig. 6 are omitted.

[0084] As described above, in this embodiment, as in the first embodiment, the beam table BT including intensity setting values ​​that define the intensity adjustment amounts of the RF signals supplied to the plurality of antenna elements 21 or the RF signals supplied from the plurality of antenna elements 21 is stored in the memory 13. When the intensity setting value of the beam table BT read from the memory 13 is 0, the power supply to at least one amplifier that amplifies the RF signals (for example, the variable gain amplifier 63 and the power amplifier 65) is cut off. This makes it possible to reduce power consumption more than in the past.

[0085] Furthermore, in this embodiment, a register 74 is provided that stores a first setting value that enables cutting off the power supply to the amplifier, or a second setting value that disables cutting off the power supply to the amplifier. When the first setting value is stored in the register 74, the circuit breakers 72 and 73 can cut off the power supply to the amplifier, and when the second setting value is stored in the register 74, the circuit breakers 72 and 73 cannot cut off the power supply to the amplifier. This makes it possible to switch between prioritizing suppression of power consumption and formation of a desired beam pattern depending on the situation.

[0086] 8 is a diagram showing the power consumption of the phased array antenna module according to the embodiment of the present disclosure and a conventional phased array antenna module. In Fig. 8, the power consumption of the phased array antenna module 1 according to the embodiment of the present disclosure is indicated as "Example," and the power consumption of the conventional phased array antenna module is indicated as "Comparative Example." In the second embodiment of the present disclosure, the first setting value is stored in the register 74, and the same operation as in the first embodiment is performed.

[0087] Here, 64 RF front ends 5 connected to 64 antenna elements 21 for horizontal polarization or 64 RF front ends 5 connected to 64 antenna elements 21 for vertical polarization were set to a transmitting state, and an experiment was performed using 64 antenna elements 21. Note that, hereinafter, "the power setting value of the variable gain amplifier 63 provided in the RF front end 5 connected to the antenna element 21" will be abbreviated as "the power setting value of the antenna element 21."

[0088] Comparative Example 1 and Example 1 shown in Fig. 8 are experimental results when the intensity setting values ​​of all 64 antenna elements 21 were set to "31." Comparative Example 2 and Example 2 are experimental results when the intensity setting values ​​of 36 of the 64 antenna elements 21 were set to "31" and the intensity setting values ​​of the remaining 28 antenna elements 21 were set to "0." Comparative Example 3 and Example 3 are experimental results when the intensity setting values ​​of 16 of the 64 antenna elements 21 were set to "31" and the intensity setting values ​​of the remaining 48 antenna elements 21 were set to "0."

[0089] Note that the antenna elements 21 with an intensity setting value of "31" have the maximum gain, and the antenna elements 21 with an intensity setting value of "0" have the minimum gain. Also, as the number of antenna elements 21 with an intensity setting value of "0" increases, the electromagnetic wave beam emitted from the phased array antenna module becomes thicker (the half-width of the beam becomes wider). That is, in the example shown in Figure 8, the half-width of the electromagnetic wave beam emitted from the phased array antenna module is narrowest in Comparative Example 1 and Example 1, wider than Comparative Example 1 and Example 1 in Comparative Example 2 and Example 1, and wider than Comparative Example 2 and Example 2 in Comparative Example 3 and Example 3.

[0090] 8, in the conventional phased array antenna module, the power consumption was the same, 24 W, in all of Comparative Examples 1 to 3. In other words, in the conventional phased array antenna module, the power consumption was almost the same regardless of the number of antenna elements 21 whose intensity setting value was set to "0."

[0091] In contrast, in the phased array antenna module 1 according to the embodiment of the present disclosure, power consumption was reduced in the order of Example 1, Example 2, and Example 3. Specifically, the power consumption in Example 1 was 24 W, the power consumption in Example 2 was 20 W, and the power consumption in Example 3 was 17 W. Thus, in the phased array antenna module 1 according to the embodiment of the present disclosure, the power consumption could be further reduced as the number of antenna elements 21 whose intensity setting value was set to "0" increased.

[0092] Although the beamformer integrated circuit and the phased array antenna module according to the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments and can be freely modified within the scope of the present disclosure. For example, the phased array antenna module described in the above embodiments is for a time division multiplexing system. However, the phased array antenna module of the present disclosure may be for a frequency division multiplexing system.

[0093] In the above-described embodiment, an example has been described in which one antenna element 21 is connected to one RF front end 5 in a one-to-one correspondence. However, in the present disclosure, two front ends may be connected to a dual-polarized antenna element having a connection terminal for horizontal polarization and a connection terminal for vertical polarization.

[0094] In the above-described embodiment, the beamformer integrated circuit 10 includes a memory 13 that stores an intensity setting value that specifies the intensity adjustment amount of a high-frequency signal that is a signal supplied to or from a plurality of antenna elements 21, an analog circuit unit 12 (circuit unit) that has at least one amplifier (e.g., a variable gain amplifier 63, a power amplifier 65, a low-noise amplifier 67, a variable gain amplifier 68) that amplifies the high-frequency signal, and a power supply control unit 70 that can cut off the power supply to the at least one amplifier when the intensity setting value read out from the memory 13 is 0.

[0095] In addition, in the beamformer integrated circuit 10, the analog circuit unit 12 includes, as the amplifiers, a first amplifier (e.g., variable gain amplifiers 63, 68) that amplifies a high-frequency signal based on an intensity setting value stored in the memory 13, and a second amplifier (e.g., power amplifier 65, low-noise amplifier 67) that amplifies the high-frequency signal at a predetermined amplification factor, and the power supply control unit 70 is capable of cutting off the power supply to at least one of the first amplifier and the second amplifier.

[0096] In addition, in the beamformer integrated circuit 10, the power supply control unit 70 is equipped with a judgment circuit 71 that judges whether the intensity setting value read from the memory 13 is 0 or not, and circuit breakers 72 and 73 that can cut off the power supply to the amplifier depending on the judgment result of the judgment circuit 71.

[0097] The beamformer integrated circuit 10 also includes a register 74 (memory unit) that stores a first setting value that enables the cutting off of power supply to the amplifier, or a second setting value that disables the cutting off of power supply to the amplifier, and when the first setting value is stored in the register 74, the circuit breakers 72 and 73 cut off the power supply to the amplifier, and when the second setting value is stored in the register 74, they supply power to the amplifier.

[0098] In addition, in the beamformer integrated circuit 10, the memory 13 further stores a phase shift amount setting value that defines the phase shift amount of the high-frequency signal, and the analog circuit unit 12 further includes a phase shifter 61 that adjusts the phase shift amount of the high-frequency signal based on the phase shift amount setting value stored in the memory 13.

[0099] In addition, in the beamformer integrated circuit 10, the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory 13 stores a beam table BT in which multiple combinations of intensity setting values ​​and phase shift setting values ​​are stored.

[0100] The phased array antenna module 1 includes a plurality of antenna elements 21 and a beamformer integrated circuit 10 connected to the plurality of antenna elements 21 .

[0101] 1...phased array antenna module, 10...beamformer integrated circuit, 12...analog circuit section (circuit section), 13...memory, 21...antenna element, 63...variable gain amplifier, 65...power amplifier, 67...low noise amplifier, 68...variable gain amplifier, 70...power supply control section, 71...determination circuit, 72, 73...breaker, 74...register (storage section), 61...phase shifter, BT...beam table

Claims

1. A beamformer integrated circuit comprising: a memory that stores an intensity setting value that specifies the amount of intensity adjustment of a high-frequency signal that is a signal supplied to a plurality of antenna elements or a signal supplied from a plurality of said antenna elements; a circuit unit having at least one amplifier that amplifies said high-frequency signal; and a power supply control unit that can cut off the power supply to said at least one amplifier when said intensity setting value read from said memory is 0.

2. A beamformer integrated circuit as claimed in claim 1, wherein the circuit unit comprises as the amplifiers: a first amplifier that amplifies the high frequency signal based on the intensity setting value stored in the memory; and a second amplifier that amplifies the high frequency signal at a predetermined amplification factor; and the power supply control unit is capable of cutting off the power supply to at least one of the first amplifier and the second amplifier.

3. A beamformer integrated circuit as claimed in claim 1 or claim 2, wherein the power supply control unit comprises: a judgment circuit that judges whether the intensity setting value read from the memory is 0; and a circuit breaker that can cut off the power supply to the amplifier depending on the judgment result of the judgment circuit.

4. A beamformer integrated circuit as described in claim 3, further comprising a memory unit that stores a first setting value that enables the cutoff of power supply to the amplifier, or a second setting value that disables the cutoff of power supply to the amplifier, wherein the circuit breaker cuts off the power supply to the amplifier when the first setting value is stored in the memory unit, and supplies power to the amplifier when the second setting value is stored in the memory unit.

5. A beamformer integrated circuit as claimed in any one of claims 1 to 4, wherein the memory further stores a phase shift amount setting value that defines the phase shift amount of the high frequency signal, and the circuit section further comprises a phase shifter that adjusts the phase shift amount of the high frequency signal based on the phase shift amount setting value stored in the memory.

6. A beamformer integrated circuit as claimed in claim 5, wherein the intensity setting value and the phase shift setting value are set in combination according to the beam pattern to be controlled, and the memory stores a beam table in which a plurality of combinations of the intensity setting value and the phase shift setting value are stored.

7. A phased array antenna module comprising: a plurality of antenna elements; and a beamformer integrated circuit according to any one of claims 1 to 6 connected to the plurality of antenna elements.

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