Apparatus for signal compensation in wireless communication system

Abstract

A digital pre-distortion (DPD) module according to one embodiment of the present disclosure comprises: at least one memory for storing at least one look-up table (LUT) group including at least one LUT determined on the basis of characteristics of a plurality of power amplifiers; a plurality of bit concatenation circuits for extracting, on the basis of the number of bits allocated to each LUT, consecutive bits of data output from the memory; and a DPD circuit for identifying each LUT on the basis of data output from the plurality of bit concatenation circuits, determining a DPD model on the basis of each LUT, and performing, on the basis of the DPD model, pre-distortion on at least one power amplifier with respect to an input signal input into the at least one power amplifier.

Description

Device for signal compensation in wireless communication systems

[0001] The present disclosure relates to a wireless communication system, and more particularly, to a digital pre-distortion (DPD) technology for compensating a signal of a power amplifier (PA) in a wireless communication system.

[0002] A transceiver including a power amplifier (PA) may include a digital pre-distorter (DPD) capable of generating a power amplifier input signal to compensate for nonlinear characteristics of the power amplifier.

[0003] Digital predistorters (DPRs) compensate for the nonlinearities and memory effects of power amplifiers in analog circuits at the digital level. They utilize a look-up table (LUT) approach. With increasing numbers of LUTs being used to compensate for a variety of power amplifiers, LUTs are being used. Because LUTs are stored in memory, this requires more memory, necessitating operational strategies that reduce hardware resources and power consumption related to memory management.

[0004] Based on the above discussion, the present disclosure provides a device for performing compensation of a power amplifier in a wireless communication system.

[0005] Specifically, the present disclosure provides a device capable of saving hardware resources in designing a digital circuit including a DPD module for compensating nonlinearity of an analog circuit including a power amplifier.

[0006] Additionally, the present disclosure provides a device capable of reducing power consumption by using a DPD module including a memory storing a plurality of LUTs or grouped LUTs and / or a DPD module including a clock gating circuit.

[0007] According to one embodiment of the present disclosure, a digital pre-distortion (DPD) module is characterized by including: at least one memory storing at least one look-up table (LUT) group including at least one LUT determined based on characteristics of a plurality of power amplifiers; a plurality of bit concatenate circuits extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and a DPD circuit that identifies each LUT based on data output from the plurality of bit concatenate circuits, determines a DPD model based on each LUT, and performs pre-distortion on an input signal input to at least one power amplifier based on the DPD model.

[0008] According to one embodiment of the present disclosure, a transceiver for a wireless communication system includes a plurality of power amplifiers; and a digital pre-distortion (DPD) module, wherein the DPD module includes at least one memory storing at least one look-up table (LUT) group including at least one LUT determined based on characteristics of the plurality of power amplifiers; a bit concatenate circuit extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and a digital pre-distortion (DPD) circuit identifying each LUT based on data output from the plurality of bit concatenate circuits, determining a DPD model based on each LUT, and performing pre-distortion on an input signal input to the at least one power amplifier based on the DPD model.

[0009] According to one embodiment of the present disclosure, in a transceiver device including a power amplifier and a DPD module, the DPD module includes a memory (or memory) that groups and stores a plurality of LUTs (Look-Up Tables), and the area occupied by the memory is reduced, thereby saving hardware resources.

[0010] According to one embodiment of the present disclosure, a transceiver including a DPD module can reduce power consumption required to perform clock gating by supplying a clock to a memory that groups and stores a plurality of LUTs.

[0011] FIG. 1 illustrates an example of a wireless communication environment according to various embodiments of the present disclosure.

[0012] FIG. 2 illustrates a functional configuration for signal amplification of a communication unit of a transmitting and receiving device in a wireless communication system according to various embodiments of the present disclosure.

[0013] FIG. 3 illustrates an example of a radio frequency integrated circuit (RFIC) including a power amplifier according to embodiments of the present disclosure.

[0014] FIG. 4 illustrates a functional configuration of a transceiver device including a digital pre-distorter (DPD) according to embodiments of the present disclosure.

[0015] FIG. 5 illustrates a functional configuration of a transmitter / receiver including a digital pre-distorter according to embodiments of the present disclosure.

[0016] FIG. 6 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0017] FIG. 7 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0018] FIG. 8 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0019] FIG. 9 illustrates a functional configuration of a transceiver device according to one embodiment of the present disclosure.

[0020] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0021] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0022] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the attached drawings. It should be noted that, where possible, identical components are represented by identical reference numerals throughout the attached drawings. Furthermore, detailed descriptions of well-known functions and configurations that may obscure the gist of the present disclosure will be omitted.

[0023] In describing the embodiments herein, descriptions of technical details that are well known in the technical field to which the present disclosure pertains and are not directly related to the present disclosure will be omitted. This is to avoid obscuring the gist of the present disclosure by omitting unnecessary explanations and to convey the gist more clearly.

[0024] For the same reason, some components in the attached drawings are exaggerated, omitted, or schematically depicted. Furthermore, the dimensions of each component do not entirely reflect its actual size. Identical or corresponding components in each drawing are assigned the same reference numbers.

[0025] The advantages and features of the present disclosure, and methods for achieving them, will become clearer with reference to the embodiments described below in detail with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the disclosure, and the present disclosure is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0026] At this time, it will be understood that each block of the processing flow diagrams and combinations of the flow diagrams can be performed by computer program instructions. These computer program instructions can be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions executed by the processor of the computer or other programmable data processing equipment create a means for performing the functions described in the flow diagram block(s). These computer program instructions can also be stored in a computer-available or computer-readable memory that can direct a computer or other programmable data processing equipment to implement the functions in a specific manner, so that the instructions stored in the computer-available or computer-readable memory can also produce a manufactured item that includes an instruction means for performing the functions described in the flow diagram block(s). Since the computer program instructions may be installed on a computer or other programmable data processing device, a series of operational steps may be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform the steps for performing the functions described in the flowchart block(s) may also provide steps for performing the functions described in the flowchart block(s).

[0027] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0028] Here, the term '~ unit' used in this embodiment means a software or hardware component such as an FPGA or ASIC, and the '~ unit' performs certain roles. However, the '~ unit' is not limited to software or hardware. The '~ unit' may be configured to be on an addressable storage medium and may be configured to regenerate one or more processors. Thus, as an example, the '~ unit' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. In addition, the components and '~ units' may be implemented to regenerate one or more CPUs within a device or a secure multimedia card.

[0029] The present disclosure relates to a digital pre-distortion (DPD) technology for compensating for nonlinearity of a power amplifier (PA) in a wireless communication system.

[0030] Specifically, a transceiver including a power amplifier (PA) and a digital pre-distorter (DPD) includes a single memory configuration that stores LUTs with similar usage among a plurality of LUTs set in a DPD module as a single LUT group, thereby enabling access to data of all LUTs included in a LUT group by processing a single memory, thereby reducing hardware resources and power consumption.

[0031] Accordingly, the present disclosure describes a wireless communication environment and functional configuration of a transceiver device including a power amplifier and a DPD module.

[0032] FIG. 1 illustrates an example of a wireless communication environment according to various embodiments of the present disclosure. In the present disclosure, a transceiver may refer to a node that utilizes a wireless channel in a wireless communication system. Referring to FIG. 1 , a base station (110) and a terminal (120) are exemplified as nodes. The terminal (120) may also be connected to multiple base stations. Although not illustrated in FIG. 1 , the base stations may also be connected to the terminal (120) via multiple connectivity (e.g., dual connectivity (DC)).

[0033] A base station (110) is a network infrastructure that provides wireless access to terminals (120). The base station (110) has coverage defined as a certain geographical area based on the distance at which a signal can be transmitted. Hereinafter, the term "coverage" used may refer to a service coverage area provided by the base station (110). The base station (110) may cover one cell or multiple cells. Here, the multiple cells may be distinguished by the frequency they support and the area of ​​the sector they cover.

[0034] The base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', '5G NodeB (NB)', 'next generation node B (gNB)', 'wireless point', 'transmission / reception point (TRP)', 'distributed unit (DU)', 'radio unit (RU), remote radio head (RRH)' or other terms having equivalent technical meanings thereto, in addition to a base station. According to various embodiments, the base station (110) may be connected to one or more 'transmission / reception points (TRPs).' The base station (110) may transmit a downlink signal to a terminal (120) or receive an uplink signal through one or more TRPs.

[0035] The terminal (120) is a device used by a user and performs communication with the base station (110) via a wireless channel. In some cases, the terminal (120) may be operated without the involvement of the user. That is, at least one of the terminals (120) is a device that performs machine type communication (MTC) and may not be carried by the user. The terminal (120) may be referred to as a 'user equipment (UE)', a 'mobile station', a 'subscriber station', a 'customer premises equipment (CPE)', a 'remote terminal', a 'wireless terminal', an 'electronic device', a 'vehicle terminal', a 'user device', or other terms having an equivalent technical meaning thereto.

[0036] The base station (110) and the terminal (120) include an amplifier capable of amplifying transmission and reception signals, and may include a digital pre-distorter to compensate for nonlinearity or distortion characteristics of the amplifier. Of course, FIG. 1 is merely an example, and the transceiver of the present disclosure is not limited to the base station and the terminal. The present disclosure can be applied to all transceiver devices that include a power amplifier (PA) capable of amplifying transmission and reception signals.

[0037] Since various embodiments of the present disclosure relate to a transceiver including a power amplifier and a digital pre-distorter for compensating for nonlinearity of the power amplifier, the following describes in detail the functional configuration of the transceiver for signal amplification, the RFIC including the power amplifier, and the functional configuration of the transceiver including the digital pre-distorter.

[0038] FIG. 2 illustrates a functional configuration for signal amplification of a communication unit of a transmitting and receiving device in a wireless communication system according to various embodiments of the present disclosure.

[0039] The transceiver of FIG. 2, with reference to FIG. 2, includes a wireless communication unit or communication unit including an encoding and modulation unit (202), a digital beamforming unit (204), a plurality of transmission paths (206-1 to 206-N), and an analog beamforming unit (208). However, FIG. 2 is merely an example and does not limit the configuration of the transceiver of the present disclosure. The present disclosure can be applied to all transceiver devices including a power amplifier (PA).

[0040] The encoding and modulation unit (202) performs channel encoding. For channel encoding, at least one of a low density parity check (LDPC) code, a convolution code, and a polar code may be used. The encoding and modulation unit (202) generates modulation symbols by performing constellation mapping.

[0041] The digital beamforming unit (204) performs beamforming on a digital signal (e.g., modulation symbols). To this end, the digital beamforming unit (204) multiplies the modulation symbols by beamforming weights. Here, the beamforming weights are used to change the magnitude and phase of the signal, and may be referred to as a 'precoding matrix', a 'precoder', etc. The digital beamforming unit (204) outputs digitally beamformed modulation symbols to multiple transmission paths (206-1 to 206-N). At this time, according to a MIMO (multiple input multiple output) transmission technique, the modulation symbols may be multiplexed, or the same modulation symbols may be provided to multiple transmission paths (206-1 to 206-N).

[0042] The plurality of transmission paths (206-1 to 206-N) convert digital beamformed digital signals into analog signals. For this purpose, each of the plurality of transmission paths (206-1 to 206-N) may include an inverse fast Fourier transform (IFFT) operation unit, a cyclic prefix (CP) insertion unit, a DAC, and an upconversion unit. The CP insertion unit is for the orthogonal frequency division multiplexing (OFDM) method and may be excluded when another physical layer method (e.g., filter bank multi-carrier (FBMC)) is applied. That is, the plurality of transmission paths (206-1 to 206-N) provide independent signal processing processes for the plurality of streams generated through digital beamforming. However, depending on the implementation method, some of the components of the plurality of transmission paths (206-1 to 206-N) may be used in common.

[0043] The analog beamforming unit (208) performs beamforming on analog signals. To this end, the digital beamforming unit (204) multiplies the analog signals by beamforming weights. Here, the beamforming weights are used to change the magnitude and phase of the signal. Specifically, the analog beamforming unit (240) can be configured in various ways depending on the connection structure between the multiple transmission paths (206-1 to 206-N) and the antennas. For example, each of the multiple transmission paths (206-1 to 206-N) can be connected to one antenna array. As another example, the multiple transmission paths (206-1 to 206-N) can be connected to one antenna array. As yet another example, the multiple transmission paths (206-1 to 206-N) can be adaptively connected to one antenna array or to two or more antenna arrays.

[0044] FIG. 3 illustrates an example of a radio frequency integrated circuit (RFIC) including a power amplifier according to embodiments of the present disclosure.

[0045] In 5G communications, mmWave phased array RFICs are being developed to enable efficient communications in the mmWave band. To achieve high performance in the mmWave band, the development of high-power, highly efficient, and highly linear power amplifiers (PAs) within the IC (e.g., complementary metal-oxide-semiconductor (CMOS) / silicon (Si)-based PAs) is required.

[0046] Referring to FIG. 3, the RFIC (300) may include a plurality of RF chains (316, 316-1). The plurality of RF chains (316, 316-1) may include a power amplifier (PA) and a low noise amplifier (LNA). Unlike the power amplifier (PA) that amplifies signals at the output of the transmitter, the low noise amplifier (LNA) amplifies signals at the input of the receiver, and is located close to the antenna to amplify weak signals picked up by the antenna, thereby reducing attenuation in the transmission line.

[0047] The RF signal (312) input to the RFIC (300) can be distributed to each RF chain through a distributor (or combiner, coupler) (314). According to one embodiment, the distributor (314) can be composed of a passive component or an active component.

[0048] Each of the plurality of RF chains (316, 316-1) may include a power amplifier (PA). In a wireless communication system, a transmission signal of a base station (110) or a terminal (120) is transmitted through a wireless channel and thus suffers from severe attenuation. To this end, the transmitter of the base station (110) or the terminal (120) may be configured to include an amplifier for amplifying the transmission signal. To amplify a signal transmitted through the air, a power amplifier (PA) may be arranged in each of the plurality of RF chains. The PA may amplify an applied signal and transmit it to an antenna. Although not illustrated in FIG. 3, a signal passing through the PA is transmitted to an antenna (e.g., an antenna element of an array antenna) via a filter and a transmission line.

[0049] In Fig. 3, an exemplary structure of an RFIC proposed through embodiments of the present disclosure is described. Meanwhile, the RFIC structure illustrated in Fig. 3 is merely an example for explaining the transmission process from RF signal input to the antenna. In other words, Fig. 3 is not interpreted as excluding an RFIC having a structure different from Fig. 3, but including a power amplifier described below, among the embodiments of the present disclosure.

[0050] Since the performance of the power amplifier affects the overall performance of the RFIC, a predistorter may be included to preprocess the input signal of the power amplifier to improve nonlinearity for high performance and high efficiency.

[0051] FIG. 4 illustrates a functional configuration of a transceiver device including a digital pre-distorter (DPD) according to embodiments of the present disclosure.

[0052] The transceiver may include a base station (110) or a terminal (120). Referring to FIG. 4, the transceiver may include a DPD (404), a power amplifier (407), and a correction unit (413). The transceiver may include a DPD module (415) including the DPD (404) and the correction unit (413).

[0053] Although not shown, the transceiver device of FIG. 4 may further include a frequency downconverter and a frequency upconverter outside the DPD module. However, FIG. 4 does not limit the arrangement of the frequency downconverter and the frequency upconverter, and the frequency downconverter and the frequency upconverter may be included in the DPD module depending on the implementation.

[0054] The operation of the DPD (404) acquiring the input signal (402) and the operation of the correction unit (413) acquiring the output signal (409) from the frequency down converter can be performed in the DPD module (415). Unlike the output signal (409), which is an analog signal, the digital block can perform the operation like the input signal (402). For example, when the transmitting and receiving device is a base station (110), the input signal (402) can include at least one of a physical downlink shared channel (PDCCH), a physical downlink shared channel (PDSCH), a demodulation reference signal (DMRS), and a channel state information-reference signal (CSI-RS) as a downlink signal.

[0055] Wireless communication systems that provide high-speed wireless Internet must process signals with a bandwidth of several megahertz (MHz) to several tens of MHz, and therefore, linear amplification technology for wideband signals is increasingly required. Techniques for removing nonlinearities of active elements used in power amplifiers may include predistortion. The predistortion method using the DPD (404) can have better linearity improvement performance than the analog predistortion method because the signal generated through the distortion removal loop is a baseband digital signal. As illustrated in Fig. 4, the DPD (404) can compare the input signal and the output signal to linearize the signal transmitted to the power amplifier. The DPD (404) can perform signal processing to minimize the distortion component of the output signal so that the input modulation signal can be linearly amplified and output.

[0056] Specifically, the input signal may be pre-distorted in the DPD (404) after undergoing digital baseband processing. The pre-distorted signal may be transmitted to the power amplifier as an RF (radio frequency) signal through a frequency up-converter. The pre-distorted RF band signal may be output as an output signal with a linear gain by canceling out the nonlinear characteristics of the power amplifier. In addition, the DPD (404) may receive an output signal of a correction unit (413) that extracts a distortion component of the output signal that has passed through the power amplifier. In order to adaptively control based on the error of the signal, the DPD (404) may further include a DSP (digital signal processor) for controlling digital pre-distortion and a memory for storing an LUT.

[0057] Referring to FIG. 4, the DPD (404) can pre-distort a signal input to the power amplifier in order to remove nonlinearity of a signal output from the power amplifier. The DPD (404) must know the nonlinear output characteristics of the power amplifier in order to perform pre-distortion. Therefore, the DPD (404) must understand the characteristics of the power amplifier (e.g., the characteristics of the output signal (409)). The input signal can be input to the DPD (404) as a digital signal. Signal correction can be performed by the correction unit (413) within the DPD (404) on the input signal input to the DPD (404). The input signal on which the correction algorithm has been performed can be converted into an RF signal through an up-converter as a pre-distorted signal in order to remove the nonlinearity of the power amplifier and transmitted to the power amplifier. Since the input signal has a nonlinearity opposite to the nonlinearity of the power amplifier, the input signal transmitted to the power amplifier can cancel out the nonlinearity of the power amplifier and be transmitted as an output signal.

[0058] Nonlinear distortion characteristics of a signal can cause signal quality degradation, such as noise and interference. To improve the signal error vector size and ensure high communication quality, distortion characteristics of the power amplifier must be prevented during signal transmission.

[0059] FIG. 5 illustrates a functional configuration of a transmitter / receiver including a digital pre-distorter according to embodiments of the present disclosure.

[0060] Referring to FIG. 5, an input signal that has gone through a digital baseband process (501) may be input to a DPD (502). For example, if the transmitting / receiving device of FIG. 5 is a base station (110), the input signal may include at least one of a physical downlink shared channel (PDCCH), a physical downlink shared channel (PDSCH), a demodulation reference signal (DMRS), and a channel state information-reference signal (CSI-RS) as a downlink signal.

[0061] The input signal input to the DPD (502) can be pre-distorted to have a nonlinearity opposite to the nonlinearity of the power amplifier by the DSP (506) for controlling digital pre-distortion and the memory (504) storing the LUT (look-up table) that pre-calculates and loads the digital distortion signal value. The DPD module (503) of Fig. 5 may include the DPD (502), the memory (504) storing the LUT, the DSP (506), the ADC (analog-to-digital converter) (508), the frequency down-converter (510), and the attenuator (512). However, the DPD module (503) described below is not limited thereto, and may be separately referred to as a digital signal processing unit including the DPD (502), the memory (504) storing the LUT, and the DSP (506) as a digital DPD module.

[0062] An input signal input to a DPD (502) can be modulated into an analog signal through a digital-to-analog converter (DAC) (507). The input signal modulated into an analog signal can be modulated through a frequency up-converter (509) and input to a power amplifier (511). The input signal input to the power amplifier can be amplified and output and transmitted to an antenna (523) through an isolator (521) and a bandpass filter (BPF) (513). In this case, a distortion removal loop for generating a digital pre-distortion signal can be configured.

[0063] The output signal output from the power amplifier can be demodulated into a digital signal through an attenuator (512), a frequency down converter (510), and an ADC (508). Based on the output signal demodulated into a digital signal, a DSP (506) and a memory (504) storing an LUT can identify the distortion characteristics of the DPD input signal and, based on this, perform a correction algorithm to apply a distortion characteristic opposite to the distortion characteristic of the DPD input signal to the DPD (502).

[0064] FIG. 6 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0065] Referring to FIG. 6, the DPD module may include a magnitude operation circuit (603), a quantization circuit (605), a memory (610, 620, or 630) for storing an LUT, and a delay circuit (623, 625, 633, 635, 637, or 639). When a signal x(n) is input to the DPD module of FIG. 6, the DPD module may output a signal y(n). For example, the DPD module of FIG. 6 may include the DPD module (415) or the DPD module (503) of FIG. 4. Of course, the DPD module of FIG. 6 is only one example for the convenience of explanation, and thus the DPD module of the present disclosure is not limited thereto.

[0066] The DPD module can preprocess the input signal input to the power amplifier to minimize distortion of the signal output from the power amplifier. The DPD circuit implements the DPD formula to compensate for the nonlinearity of the power amplifier, and the DPD formula includes the Volterra series.

[0067] The Volterra series is a fundamental mathematical concept in DPD and is used to model nonlinear systems with memory. A simple form of this series used in DPD can be expressed as shown in Equation 1.

[0068]

[0069] In mathematical expression 1, a, b, and c are DPD coefficients, and the DPD coefficients can reflect the changing characteristics of the power amplifier. The DPD coefficients can be determined based on the input and output signals of the DPD module and the output signal of the power amplifier. For example, a device including a DPD module (e.g., a base station (110) or a terminal (120)) can identify the input and output signals of the DPD module and the output signal of the power amplifier, and determine the DPD coefficients through machine learning based on these signals. For example, the DPD coefficients can be determined through the least squares estimation method.

[0070] The DPD module is a circuit implementation of the DPD formula using determined DPD coefficients. The DPD circuit can output DPD output signals in real time. Implementing all terms of the DPD formula as a DPD circuit requires the addition of multipliers and adders for each term, which can consume significant hardware resources.

[0071] To solve these problems, for some DPD formulas with complex calculations, the software processes the calculations, stores the calculation results in a look-up table (LUT), and the hardware (DPD circuit) can determine the calculation results by simply reading the stored calculation results without performing the calculations. This method is called the LUT method, and the LUT can refer to a table that can determine an output value based on an input value. According to the LUT method, the calculations for the addition and multiplication terms of each term of the DPD formula are processed by the software of the device including the DPD module, thereby reducing the amount of hardware calculations and saving hardware resources.

[0072] The memory (610, 620, or 630) can store an LUT to simplify the DPD formula of the DPD module. The LUT for the DPD formula stored in the memory can be calculated and updated by software. The DPD circuit can perform operations related to the DPD formula simply by reading the memory where the LUT calculated by the software is stored, thereby reducing the amount of hardware calculations and saving hardware resources. The input value corresponding to the output value in the LUT can be referred to as an index.

[0073] Memory (storage device) may include main memory characterized by volatility and fast processing speed. For example, random access memory (RAM) may be used as memory.

[0074] The DPD module of FIG. 6 may include a memory (610) for storing LUT 0, a memory (620) for storing LUT 1, and a memory (630) for storing LUT 2. Each LUT may be assigned a number of bits related to an output signal. For example, LUT 0 may be assigned 32 bits, and the memory (610) for storing LUT 0 may output a 32-bit output signal. The DPD circuit may perform a predistortion compensation operation according to a DPD formula corresponding to LUT 0 in units of 32 bits by reading the memory (610) for storing LUT 0. However, 32 bits is only an example, and the number of bits assigned to each LUT is not limited to 32 bits.

[0075] The absolute value operation circuit (603) can convert the input signal x(n) of the DPD module into an absolute value signal (magnitude signal) and output it, and can include, for example, a CORDIC (coordinate rotation digital computer) abs function.

[0076] The quantization circuit (605) can quantize the absolute value signal output by the absolute value operation circuit (603) to a specified level. The quantization level can be determined in relation to the usage resources related to the LUT, or the LUT size can be determined according to the quantization level. For example, the quantization circuit can quantize to 64 levels. When the DPD circuit reads the memory (610), the LUT output can be output based on the LUT data corresponding to any one of the 64 levels. Which level of LUT data among multiple levels is to be read can be indicated through indexing.

[0077] For example, a transceiver including a DPD module can calculate and update DPD coefficients (e.g., a, b, c in Equation 1) that can reflect the characteristics of a changing PA using DPD software. In Equation 1 above, an input signal x(n) is input to the absolute value operation circuit (603), and an absolute value signal can be output. The quantization circuit (605) can quantize the absolute value signal to form a quantization level for the absolute value signal. At this time, the data of the LUT is indexed according to the quantization level, so that the quantization level that the DPD circuit should read can be indexed.

[0078]

[0079] A transceiver including a DPD module can configure terms commonly grouped in Equation 2 as a LUT and store it in a memory arranged in a DPD circuit. That is, Equation 2 can be reorganized as Equation 3.

[0080]

[0081] The DPD output signal y(n) in Equation 3 is the result of adding all terms related to the used LUT, and Fig. 6 illustrates a DPD circuit in which all these terms are implemented. In this way, by simplifying and using the Volterra series, each term of the DPD stage model can effectively compensate for power amplifier nonlinearity and memory components in a digital system in real time.

[0082] In a transceiver device including multiple power amplifiers, each power amplifier may have a different DPD formula suitable for compensating for its nonlinearity, and thus, each power amplifier may also have a different LUT suitable for the same. Accordingly, multiple LUTs may be configured for the DPD module to compensate for the multiple power amplifiers included in the transceiver device.

[0083] Some of the multiple LUTs configured for the DPD module may be used frequently. For example, LUTs primarily used to compensate for power amplifiers in transmitters and receivers may be used frequently. Alternatively, some of the multiple LUTs may be used infrequently, as they are LUTs used only under specific conditions or only in specific cases. As another example, some other LUTs may be used as the characteristics of the power amplifier change.

[0084] In this way, when multiple LUTs are set for a DPD module, the configuration of the LUTs actually used can dynamically change depending on the use of the transceiver. According to one embodiment, the DPD module further includes a clock gating circuit for a memory storing at least one LUT among the multiple LUTs, so that when at least one LUT is used, a clock can be supplied to the memory storing the at least one LUT, or when at least one LUT is not used, a clock can be blocked to the memory storing the at least one LUT.

[0085] For example, at least one LUT may mean at least one LUT that is used only in a specific case. Or, at least one LUT may mean at least one LUT that is used frequently.

[0086] Referring to FIG. 6, the DPD module may further include a clock gating circuit for each of a memory (610) storing LUT 0, a memory (610) storing LUT 1, and a memory (610) storing LUT 2, and may block a clock for the memory (610) when LUT 0 is not used. Alternatively, the clock for the memory (620) may be blocked when LUT 1 is not used, and the clock for the memory (630) may be blocked when LUT 2 is not used.

[0087] In this way, when multiple LUTs are set for a DPD module, the configuration of LUTs actually used can be dynamically changed depending on the use of the transceiver, and the clock can be cut off for the memory storing the unused LUTs based on whether they are actually used, thereby reducing power consumption.

[0088] FIG. 7 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0089] As wider frequency bandwidths are used, the operating frequency bandwidth of the power amplifier increases, which can lead to increased power amplifier nonlinearity. To effectively compensate for power amplifier nonlinearity and memory components, DPD models become more complex and contain more terms. The more terms in the DPD model, the more LUTs are required, and the more memory is needed to store them. Consequently, when a DPD module contains a large amount of memory, the hardware resources required for the DPD circuit to read and use the LUTs increase, and power consumption also increases significantly.

[0090] To address this issue, the present disclosure describes LUT grouping. LUT grouping may refer to storing multiple LUTs, which may or may not be used simultaneously, in a common memory. LUT grouping can save hardware implementation resources for a DPD model. Furthermore, the present disclosure combines LUT grouping with clock gating technology to save hardware implementation resources for a DPD model while also reducing power consumption for the DPD circuit. First, the concept of LUT grouping will be described.

[0091] At least one memory included in a DPD module according to one embodiment may store multiple LUTs that are used simultaneously depending on the characteristics or operating conditions of the power amplifier. For example, referring to FIG. 7, the DPD module may include two LUTs in one memory (710), and the two LUTs may be characterized as always being used simultaneously or not.

[0092] When multiple LUTs that are used or not used simultaneously are stored in a common memory, the LUT outputs for multiple LUTs can all be read by reading only the output signal of one memory.

[0093] For example, in FIG. 7, two LUTs (e.g., LUT 0 and LUT 1) set for the DPD module are stored in a common memory (710), and an operation of reading the memory (710) can be performed once to read the two LUT outputs. This saves hardware resources and power consumption compared to a case where memory 0 storing LUT 0 and memory 1 storing LUT 1 are provided, and the operation of reading the memory must be performed a total of two times (an operation of reading memory 0 and an operation of reading memory 1) to read the two LUT outputs.

[0094] When applying the above-described features to an extended scenario where 100 LUTs are configured for the DPD module, the hardware resource and power savings are even greater. For example, if the 100 LUTs are grouped into 40 LUT groups, the DPD module is configured with 40 memories. This results in significant hardware resource and power savings compared to storing the 100 LUTs in 100 memories.

[0095] That is, when multiple LUTs (e.g., LUT 0, LUT 1, LUT 2, etc.) are set for a DPD module, configuring the DPD module with a memory that stores the multiple LUTs at once can save hardware resources and power consumption compared to configuring the DPD module with a memory that stores LUT 0, a memory that stores LUT 1, a memory that stores LUT 2, etc.

[0096] According to one embodiment, when storing a plurality of LUTs that are used or not used simultaneously in a common (or, one) memory, the DPD module may further include a bit concatenate circuit and / or a delay circuit. The bit concatenate circuit may receive an output signal output from a memory storing the plurality of LUTs as an input, and may perform bit extraction on the output signal based on the number of output bits set for each of the plurality of LUTs, thereby outputting the output signal as divided bits. In the present disclosure, the bit concatenate circuit outputting a selection of consecutive bits from the input signal of the bit concatenate circuit may be referred to as bit extraction or bit division. The delay circuit may compensate for various delay components of the plurality of LUTs stored in the common memory. Hereinafter, the bit concatenate circuit and the delay circuit will be described with reference to FIG. 7.

[0097] When an LUT is set for a DPD module, the LUT setting may include setting the number of bits of the LUT output. The number of bits of the output signal output from the memory may be the sum of the number of output bits of multiple LUTs stored in the memory. Referring to FIG. 7, the memory (710) stores LUT 0 with a 32-bit LUT output and LUT 1 with a 32-bit LUT output. At this time, the number of bits of the output signal output from the memory (710) may be 64 bits, which is the sum of the number of LUT output bits (32 bits) of LUT 0 and the number of LUT output bits (32 bits) of LUT 1. However, the number of output bits of each LUT being 32 bits is merely an example, and the number of output bits of each LUT may be the same or different.

[0098] As mentioned in Fig. 6, the LUT stored in the memory can be operated and updated by software. If the memory stores multiple LUTs or LUT groups, when the multiple LUTs are updated, the multiple LUTs can be updated in a sequential or serial manner. For example, in Fig. 7, when the LUTs stored in the memory (710) are updated by software, the 32-bit information of LUT 0 and the 32-bit information of LUT 1 can be updated in a sequentially concatenated form or in a serial form. Accordingly, the output signal output by the memory (710) includes information in a form in which the information of LUT 0 and the information of LUT 1 are concatenated.

[0099] The DPD module of FIG. 7 may include a bit concatenate circuit (720, 730) for bit extracting an output signal output from a memory (710). In order for the DPD circuit to read the output signal output from the memory (710), the bit concatenate circuit (720, 730) may perform bit extraction on the output signal output from the memory (710).

[0100] For example, depending on the hardware settings, LUT settings, and / or the quantization level of the LUT, the DPD circuit can read 32 bits of LUT at a time. For example, if LUT 0 and LUT 1 are stored in the memory (710), the memory (710) can output serial information in which information of LUT 0 and LUT 1 is continuously connected, and the DPD circuit set to read 32 bits at a time may not obtain information of LUT 0 and information of LUT 1 from the serial information output by the memory (710). To compensate for this problem, the DPD module may further include bit concatenate circuits (720 and 730).

[0101] The bit concatenate circuit (720) and the bit concatenate circuit (730) can output serial information output by the memory (710) by dividing the information into 32 bits. The bit concatenate circuit (720) can output a 32 bit output signal based on the number of output bits of LUT 0 (i.e., 32 bits), and the bit concatenate circuit (730) can output a 32 bit output signal based on the number of output bits of LUT 1 (i.e., 32 bits). For example, the bit concatenate circuit (720) and the bit concatenate circuit (730) may cut the serially connected information of LUT 0 and LUT 1 output by the memory (710) between the 31st and 32nd bits, and the bit concatenate circuit (720) may select and output contiguous bits from the 0th bit to the 31st bit, and the bit concatenate circuit (730) may select and output contiguous bits from the 32nd bit to the 63rd bit. The bit concatenate circuit may include an extract bits circuit that outputs a selection of contiguous bits.

[0102] In the present disclosure, since the number of output bits of each LUT may vary, the number of output bits of each bit concatenate circuit may also vary. FIG. 7 illustrates an example in which a bit concatenate circuit (720) outputs a 32-bit output signal and a bit concatenate circuit (730) outputs a 32-bit output signal, but the number of output bits of each bit concatenate circuit of the present disclosure is not limited to 32 bits, nor is the number of output bits of each bit concatenate circuit limited to the same. For example, if the number of output bits of each LUT is different, the number of output bits of each bit concatenate circuit may be different.

[0103] The DPD module of Fig. 7 may include an absolute value operation circuit (703) and a quantization circuit (705). Any descriptions that overlap with those of the absolute value operation circuit (603) and the quantization circuit (605) in Fig. 6 have been omitted.

[0104] When a quantization circuit quantizes an input signal into N levels, a memory storing multiple LUTs can output information of the multiple LUTs in a form in which the information of each level is concatenated. For example, when a quantization circuit (705) quantizes an absolute value signal output from an absolute value operation circuit (703) into 64 levels, any one of the 64 levels can be selected for indexing. When a DPD circuit reads the memory (710), LUT data corresponding to the indexing can be read. Since the memory (710) continuously outputs information of the multiple LUTs, the output of the memory (710) at the indexed level can include information of the multiple LUTs in the form of serial information. The bit concatenate circuit (720, 730) selects and outputs consecutive bits from bit 0 to bit 31 (corresponding to 32-bit LUT 0 information) from 64-bit information stored in one level, and selects and outputs consecutive bits from bit 32 to bit 63 (32-bit LUT 1 information), thereby allowing the DPD circuit to read each extracted 32-bit information.

[0105] Referring to FIG. 7, the DPD module may further include a delay circuit to compensate for the delay component of the LUT output signal. In some cases, the LUT output signal may have a delay component, and the delay component of the LUT output signal may also vary for each LUT. For example, the delay component of the LUT output signal may vary from 0 to 9.

[0106] A memory included in a DPD module may store multiple LUTs, and each of the multiple LUTs may have different delay components. However, as shown in FIG. 7, when multiple LUTs having different delay components are included in one memory, since the DPD circuit can read a specific level of information based on the above-described indexing when reading one memory, it is necessary to compensate for the delay components of the multiple LUTs in order to synchronize the above-described indexing. Accordingly, when multiple LUTs included in a LUT group stored in one memory are indexed with signals having different delay components, the DPD module can be configured by including more delay circuits than when indexed with signals having the same delay component.

[0107] For example, if multiple LUTs included in a LUT group stored in one memory are indexed by signals having the same delay component, there is no need to include a delay circuit to compensate for different delay components because the LUT output signals have the same delay component. In this case, the DPD module only needs to include an additional bit concatenate circuit, and the bit concatenate circuit can process bit extraction for the output signal of the memory according to the number of output bits of one LUT and output the bit-extracted output signal. Each of the multiple LUTs included in the LUT group can have a different number of output bits, and in this case, the bit concatenate circuit can output an output signal according to the number of output bits of each LUT.

[0108] When multiple LUTs included in a LUT group stored in one memory are indexed with signals having different delay components, synchronization must be performed on the delay components of the LUT output signals so that the DPD circuit can read the LUTs based on the indexing. For example, in FIG. 7, when LUT 0 read with a delay 0 value and LUT 2 read with a delay 2 value are grouped into LUT group A, the output signal output from the memory storing LUT group A or the LUT group A output signal may have a shape that is a combination of the output signals of LUT 0 and LUT 2.

[0109] As shown in Fig. 6, when LUT 0 and LUT 2 are not grouped, since the DPD circuit reads the output signal of LUT 0 and the output signal of LUT 2 separately, each output signal can be read as a signal suitable for each delay, and signal synchronization of the output signals can be possible without the help of a delay circuit.

[0110] As shown in FIG. 7, when LUT 0 and LUT 2 are grouped into one LUT group, the DPD circuit must read the output signal of the grouped LUT group as a signal with one type of delay. Therefore, when LUT 0 read with a delay 0 value and LUT 2 read with a delay 2 value are grouped into a LUT group, the output signals of the LUT groups have a delay difference of 2, and thus must be synchronized. According to one embodiment, LUT 0 and LUT 2 can be synchronized by reading the LUT group value with a delay 0 value, extracting LUT 0 and LUT 2 bits from the output signal of the LUT group, and then delaying the output signal of LUT 2 by delay 2. To this end, the DPD module may further include a delay circuit (733) after the bit concatenate circuits (720, 730).

[0111] Below, a device combining LUT grouping and clock gating techniques is described. As illustrated in FIG. 6, the DPD module may additionally include a clock gating circuit for providing or blocking a clock to a memory storing an LUT based on whether the LUT is in use. Specifically, the DPD module may include a clock gating circuit for each memory.

[0112] When designing RFIC chips for transceivers, numerous DPD models can be implemented on the RFIC chip to compensate for the various power amplifiers included in the transceiver. Therefore, instead of using all DPD models implemented on the RFIC chip to compensate for each power amplifier, only the effective DPD models for that specific power amplifier are used. By blocking the clocks for DPD models less relevant to compensating for the nonlinearities of the target power amplifier, power consumption can be reduced.

[0113] Referring to Figure 7, the DPD model can vary depending on the operating frequency bandwidth. Generally, a wider operating frequency bandwidth requires a more complex DPD model, while a narrower bandwidth requires a simpler DPD model. Even when a large number of LUTs are configured for a DPD module, a simpler DPD model can be used for unused LUTs by limiting their output. Blocking the clock to the memory storing the LUT can limit the output of that LUT.

[0114] As described above, depending on the operating situation, some of the LUTs (e.g., N LUTs) included in the DPD module may be used simultaneously, so all N memories storing each LUT may need to be clocked, and the outputs from the memories may need to be read N times. Alternatively, depending on the operating situation, some of the LUTs included in the DPD module may not be used simultaneously, and clocks may be restricted to all memories storing each LUT.

[0115] In this way, by grouping LUTs that are used or not used simultaneously and storing them in a single memory, and reading the output of that single memory or providing a clock to that single memory or blocking (limiting) it, the hardware resources that may be consumed by the DPD circuit reading the output of the memory and turning the clock on / off can be saved. For example, as shown in Fig. 7, if two LUTs are stored in a single memory, the DPD circuit manages one memory, so hardware resources can be saved compared to managing two memories.

[0116] A clock gating circuit can control the clock for each memory, thereby providing a clock to the memory that stores the LUT to be used, and blocking the clock to the memory that stores the LUT that will not be used. For example, if an LUT stored in a memory is not being used, the clock gating circuit controlling the clock of that memory can block the clock of that memory. Alternatively, if an LUT stored in a memory is being used, the clock gating circuit can provide a clock to that memory.

[0117] According to one embodiment, when some of the memories used in the DPD module store a plurality of LUTs or grouped LUTs, hardware resources and power consumption can be saved by adding a clock gating circuit to the memories used in the DPD module. Specifically, when one memory stores a plurality of LUTs or grouped LUTs, the clock gating circuit can block the clock for all LUTs stored in the memory by blocking the clock for the one memory. At this time, since the clock can be blocked for the memory storing all LUTs without performing clock gating for the number of all LUTs set for the DPD module, power consumed for clock gating can be saved compared to when each memory included in the DPD module stores one LUT.

[0118] In addition, since multiple LUTs (i.e., grouped LUTs) stored in a single memory are stored together on the condition that they are used or not used at the same time, there is no problem even if all LUTs stored together in that single memory are powered ON / OFF at the same time. Therefore, if some of the memories used in the DPD module store multiple LUTs or grouped LUTs, by adding an additional clock gating circuit to the memories used in the DPD module, the hardware resources and power consumption required for clock gating can be effectively reduced.

[0119] Referring to FIG. 7, two LUTs (i.e., LUT 0 and LUT 1) are set for the DPD module, and a memory (710) included in the DPD module stores the two LUTs at once. At this time, the DPD circuit may further include a clock gating circuit, and when the two LUTs are not used, the clock gating circuit may cut off power to the two LUTs by cutting off the clock to the memory (710).

[0120] If two LUTs (e.g., LUT 0 and LUT 1) are set for a DPD module, and this DPD module includes two memories, each storing LUT 0 or LUT 1, then when the two LUTs are not in use and the clocks are to be blocked, a clock gating circuit is required for each of the two memories. In addition, when the clocks for the two LUTs are to be blocked, additional hardware resources and power are consumed for clock control for each clock gating circuit.

[0121] That is, when multiple LUTs (e.g., LUT 0, LUT 1, LUT 2, etc.) are set for a DPD module, if the DPD module is configured with a memory that stores the multiple LUTs at once and a clock gating circuit for controlling the clock for the memory, hardware resources and power consumption can be reduced compared to configuring the DPD module with a memory that stores LUT 0, a memory that stores LUT 1, a memory that stores LUT 2, ..., and clock gating circuits for each memory.

[0122] The bit concatenate circuit (720, 730) for bit-extracting the output signal of the memory storing the grouped LUT (e.g., LUT group A) and the delay circuit (733) for synchronization do not need to operate when LUT group A is not used. Therefore, the clock gating circuit according to one embodiment can provide or block a clock to the memory (710) storing the grouped LUT and the bit concatenate circuit (720, 730) and the delay circuit (733) associated with the memory at one time.

[0123] FIG. 8 illustrates a circuit for implementing a DPD module according to one embodiment of the present disclosure.

[0124] Referring to FIG. 8, the DPD module may include an absolute value operation circuit (803), a quantization circuit (805), a memory (810), a bit concatenate circuit (820, 830, 840), and delay circuits. Details overlapping with the description of FIG. 7 with respect to the absolute value operation circuit (803), the quantization circuit (805), the memory (810), the bit concatenate circuit (820, 830, 840), and the delay circuit are omitted.

[0125] The memory (810) of FIG. 8 can store three LUTs (e.g., LUT 0, LUT 1, LUT 2). At this time, LUT 0, LUT 1, and LUT 2 can have the characteristics of being used and not used simultaneously.

[0126] The DPD circuit can read the LUT outputs for all of LUT 0, LUT 1, and LUT 2 by reading only the output signals of the memory (810). The operation of reading the output signals of the memory (810) can save hardware resources and power consumption compared to the operation of reading the output signals for all of the memory storing LUT 0, the memory storing LUT 1, and the memory storing LUT 2.

[0127] When the number of LUTs set for the DPD module is the same, the smaller the number of memories required to store the multiple LUTs (i.e., the more LUTs a single memory stores), the greater the effect of saving hardware resources and power consumption.

[0128] For example, unlike that illustrated in FIG. 7, if the DPD module of FIG. 7 further includes a memory (not shown) that stores LUT 2 separately from the memory (710), and LUT 0 and LUT 1 included in the memory (710) are always used or not used simultaneously with the LUT, the LUT outputs of LUT 0, LUT 1, and LUT 2 can be read by reading the outputs of the memory (710) and the memory (not shown), respectively. In contrast, in FIG. 8, the DPD module includes a memory (810) that stores LUT 0, LUT 1, and LUT 2, and the LUT outputs of LUT 0, LUT 1, and LUT 2 can be read by reading only the output of the memory (810). That is, when three LUTs are set for the DPD module, the effect of saving hardware resources and power consumption can be greater when storing the three LUTs in one memory than when storing them in two memories.

[0129] Referring to FIG. 8, the bit concatenate circuit (820, 830, 840) receives an output signal output by a memory (810) storing LUT 0, LUT 1, and LUT 2, and can extract bits from the output signals of the memory (810) based on the number of LUT output bits of each of LUT 0, LUT 1, and LUT 2. The delay circuit can synchronize various delay components of LUT 0, LUT 1, and LUT 2 stored in a common memory (810).

[0130] Referring to FIG. 8, the memory (810) stores LUT 0 having a LUT output of 32 bits, LUT 1 having a LUT output of 32 bits, and LUT 2 having a LUT output of 32 bits. At this time, the number of bits of the output signal output from the memory (810) may be 96 bits, which is the sum of the number of LUT output bits (32 bits) of LUT 0, the number of LUT output bits (32 bits) of LUT 1, and the number of LUT output bits (32 bits) of LUT 2. Although FIG. 8 describes a case where the number of output bits of each LUT is 32 bits, this is merely an example for the convenience of explanation, and is not limited to the case where the number of output bits of a plurality of LUTs included in the LUT group of the present disclosure is the same. The number of output bits of each of the plurality of LUTs included in the LUT group may be the same or different.

[0131] When the LUTs stored in the memory (810) are updated by software, the 32-bit information of LUT 0, the 32-bit information of LUT 1, and the 32-bit information of LUT 2 may be updated in a sequentially concatenated form or serial form. Accordingly, the output signal output by the memory (810) may include information in a form in which the information of LUT 0, the information of LUT 1, and the information of LUT 2 are concatenated.

[0132] The DPD module of FIG. 8 may include a bit concatenate circuit (820, 830, 840) for bit-extracting an output signal output from a memory (810). The bit concatenate circuit (820, 830, 840) may bit-extract an output signal output from the memory (810) so that the DPD circuit can read the output signal output from the memory (810).

[0133] Specifically, the DPD circuit can be set to read 32 bits of LUT at a time. For example, if LUT 0, LUT 1, and LUT 2 are stored in the memory (810), the memory (810) can output serial information in which information of LUT 0 and LUT 1 is continuously connected, and the DPD circuit set to read 32 bits at a time may not obtain information of LUT 0, information of LUT 1, and information of LUT 2 from the serial information output by the memory (810). To compensate for this problem, the DPD module can further include bit concatenate circuits (820, 830, and 840).

[0134] The bit concatenate circuit (820), the bit concatenate circuit (830), and the bit concatenate circuit (840) can extract bits so that the serial information output by the memory (810) is divided into 32 bits of information. The bit concatenate circuit (820) can output a 32 bits output signal based on the number of output bits of LUT 0 (i.e., 32 bits), the bit concatenate circuit (830) can output a 32 bits output signal based on the number of output bits of LUT 1 (i.e., 32 bits), and the bit concatenate circuit (840) can output a 32 bits output signal based on the number of output bits of LUT 1 (i.e., 32 bits). For example, the bit concatenate circuit (820), the bit concatenate circuit (830), and the bit concatenate circuit (840) can cut the serially connected information of LUT 0, LUT 1, and LUT 2 output by the memory (810) between the 31st and 32nd bits, and between the 63rd and 64th bits. The bit concatenate circuit (820) can output bits 0 to 31, the bit concatenate circuit (830) can output bits 32 to 63, and the bit concatenate circuit (840) can output bits 64 to 95.

[0135] Figure 9 illustrates the functional configuration of a transceiver according to one embodiment of the present disclosure. Terms such as "...unit" and "...unit" used hereinafter refer to a unit that processes at least one function or operation, which may be implemented using hardware, software, or a combination of hardware and software.

[0136] Referring to FIG. 9, the transmitter / receiver device (110 or 120) includes a communication unit (901), a storage unit (903), and a control unit (905).

[0137] The communication unit (901) performs functions for transmitting and receiving signals via a wireless channel. For example, the communication unit (901) performs a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the communication unit (901) generates complex symbols by encoding and modulating the transmission bit stream. In addition, when receiving data, the communication unit (901) restores the reception bit stream by demodulating and decoding the baseband signal. The communication unit (901) may be configured to perform at least one of the operations of the transmitting end or the receiving end of the transmitting and receiving device described through FIGS. 1 to 8 .

[0138] The communication unit (901) up-converts a baseband signal into an RF (radio frequency) band signal and transmits it through an antenna, and down-converts an RF band signal received through the antenna into a baseband signal. To this end, the communication unit (901) may include a transmission filter, a reception filter, an amplifier, a mixer, an oscillator, a digital to analog convertor (DAC), an analog to digital convertor (ADC), etc. In addition, the communication unit (901) may include a plurality of transmission and reception paths. Furthermore, the communication unit (901) may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit (901) may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc. According to one embodiment, the communication unit (901) may include a unit that forms a beam, i.e., a beamforming unit. For example, the communication unit (901) may include an MMU (massive MIMO unit) for beamforming.

[0139] The communication unit (901) can transmit and receive signals. For this purpose, the communication unit (901) can include at least one transceiver. For example, the communication unit (901) can transmit a synchronization signal, a reference signal, system information, a message, control information, or data. In addition, the communication unit (901) can perform beamforming. The communication unit (901) can apply beamforming weights to signals to be transmitted and received in order to impart directionality according to the settings of the control unit (905). According to one embodiment, the communication unit (901) can generate a baseband signal according to the scheduling result and the transmission power calculation result. In addition, the RF unit within the communication unit (901) can transmit the generated signal through an antenna.

[0140] The communication unit (901) transmits and receives signals as described above. Accordingly, all or part of the communication unit (901) may be referred to as a "transmitter," a "receiver," or a "transmitting and receiving unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that processing as described above is performed by the communication unit (901).

[0141] When the transmitting and receiving device is a base station (110), the communication unit (901) further includes a backhaul communication unit that provides an interface for performing communication with other nodes within the network. That is, the backhaul communication unit converts a bit string transmitted from the base station (110) to another node, such as another access node, another base station, an upper node, a core network, etc., into a physical signal, and converts a physical signal received from another node into a bit string.

[0142] The storage unit (903) stores data such as basic programs, application programs, and setting information for the operation of the transmitting and receiving device. The storage unit (903) may include memory. The storage unit (903) may be composed of volatile memory, nonvolatile memory, or a combination of volatile and nonvolatile memory. In addition, the storage unit (903) provides stored data upon request from the control unit (905).

[0143] For example, the storage unit (903) may include a memory (e.g., a random access memory (RAM)) that stores at least one LUT, and the memory may output LUT data according to a request from a control unit (e.g., a DPD circuit). The control unit may indicate the requested LUT data based on LUT indexing, and the memory may output an LUT output mapped to the LUT indexing.

[0144] The control unit (905) controls the overall operations of the transceiver. For example, the control unit (905) transmits and receives signals through the communication unit (901) or the backhaul communication unit (in the case of a base station). In addition, the control unit (905) records and reads data in the storage unit (903). In addition, the control unit (905) can perform the functions of the protocol stack required by the communication standard. For this purpose, the control unit (905) can include at least one processor. According to various embodiments, the control unit (905) can control the transceiver to perform operations according to the various embodiments described above.

[0145] For example, the control unit (905) may receive information related to the input / output signals of the DPD module and information related to the output signals of the power amplifier from the communication unit (901), calculate an LUT for the DPD formula based on the information, and update the memory of the storage unit (903).

[0146] Alternatively, the control unit (905) may request an LUT stored in the memory of the storage unit (903) and determine a DPD model based on the LUT data output from the memory. The control unit (905) may perform preprocessing on an input signal input to the power amplifier of the communication unit (901) based on the DPD model.

[0147] The configuration of the transceiver device illustrated in FIG. 9 is merely an example of a transceiver device, and examples of transceiver devices that perform various embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 9. That is, some configurations may be added, deleted, or changed according to various embodiments.

[0148] The present disclosure is applied to a transceiver including a power amplifier and a DPD module for compensating for its nonlinearity. In FIG. 9, the transceiver is described as a single entity, but as described above, the present disclosure is not limited thereto.

[0149] Specifically, the base station (110) may be implemented to form an access network having a distributed deployment as well as an integrated deployment (e.g., an eNB of LTE). The base station (110) may be divided into a central unit (CU) and a digital unit (DU), and the CU may be implemented to perform upper layer functions (e.g., packet data convergence protocol (RRC) (PDCP)) and the DU may be implemented to perform lower layer functions (e.g., medium access control (MAC), physical (PHY)). In this way, a base station having a separate deployment may further include a configuration for fronthaul interface communication. According to one embodiment, the base station, as a DU, may perform functions for transmitting and receiving signals in a wired communication environment. The DU may include a wired interface for controlling direct connections between devices through a transmission medium (e.g., copper wire, optical fiber). For example, a DU may transmit electrical signals to other devices via copper wires, or perform conversion between electrical signals and optical signals. A DU may be connected to a CU in a distributed arrangement. However, this description should not be construed as excluding a scenario in which a DU is connected to a CU via a wireless network. Furthermore, a DU may additionally be connected to a radio unit (RU). However, this description should not be construed as excluding a wireless environment consisting solely of a CU and a DU.

[0150] According to one embodiment of the present disclosure, a digital pre-distortion (DPD) module may include at least one memory storing at least one look-up table (LUT) group including at least one LUT determined based on characteristics of a plurality of power amplifiers; a plurality of bit concatenate circuits extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and a DPD circuit that identifies each LUT based on data output from the plurality of bit concatenate circuits, determines a DPD model based on each LUT, and performs pre-distortion on an input signal input to the at least one power amplifier based on the DPD model.

[0151] According to one embodiment, the at least one LUT group may include the at least one LUT that is used together for predistortion for the at least one power amplifier among the plurality of power amplifiers.

[0152] According to one embodiment, the at least one memory may further include at least one clock gating circuit corresponding to each of the at least one memories and blocking a clock of the corresponding memory.

[0153] According to one embodiment, the circuit further includes at least one delay circuit for compensating for a delay component of data output by the plurality of bit concatenate circuits, and the at least one delay circuit can compensate for the delay component of the data based on an LUT having the smallest delay component among the at least one LUT.

[0154] According to one embodiment, the number of said at least one delay circuit may be one less than the number of said plurality of bit concatenate circuits.

[0155] According to one embodiment, the number of bits of data output from the memory may be equal to the sum of the number of bits allocated to each LUT included in the LUT group, and the number of bits of data output from each of the plurality of bit concatenate circuits may be equal to the number of bits allocated to each LUT.

[0156] According to one embodiment, the method may further include a magnitude operation circuit that receives an input signal of the DPD module and outputs an absolute value signal of the input signal, and a quantization circuit that quantizes an output signal of the absolute value operation circuit and divides LUT data corresponding to each LUT included in the LUT group into a plurality of sections.

[0157] According to one embodiment, the DPD model of the DPD module is determined based on LUT data corresponding to one section among the plurality of sections, and the one section can be indexed based on a delay component of a designated LUT among the at least one LUT.

[0158] According to one embodiment, the designated LUT may include a LUT having the smallest delay component among the at least one LUT.

[0159] According to one embodiment of the present disclosure, a transceiver for a wireless communication system may include a plurality of power amplifiers; and a digital pre-distortion (DPD) module, wherein the DPD module may include at least one memory storing at least one look-up table (LUT) group including at least one LUT determined based on characteristics of the plurality of power amplifiers; a bit concatenate circuit extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and a digital pre-distortion (DPD) circuit identifying each LUT based on data output from the plurality of bit concatenate circuits, determining a DPD model based on each LUT, and performing pre-distortion on an input signal input to the at least one power amplifier based on the DPD model.

[0160] According to one embodiment, the at least one LUT group may include the at least one LUT that is used together for predistortion for the at least one power amplifier among the plurality of power amplifiers.

[0161] According to one embodiment, the at least one memory may further include at least one clock gating circuit corresponding to each of the at least one memories and blocking a clock of the corresponding memory.

[0162] According to one embodiment, the circuit further includes at least one delay circuit for compensating for a delay component of data output by the plurality of bit concatenate circuits, and the at least one delay circuit can compensate for the delay component of the data based on an LUT having the smallest delay component among the at least one LUT.

[0163] According to one embodiment, the number of said at least one delay circuit may be one less than the number of said plurality of bit concatenate circuits.

[0164] According to one embodiment, the number of bits of data output from the memory may be equal to the sum of the number of bits allocated to each LUT included in the LUT group, and the number of bits of data output from each of the plurality of bit concatenate circuits may be equal to the number of bits allocated to each LUT.

[0165] According to one embodiment, the method may further include a magnitude operation circuit that receives an input signal of the DPD module and outputs an absolute value signal of the input signal, and a quantization circuit that quantizes an output signal of the absolute value operation circuit and divides LUT data corresponding to each LUT included in the LUT group into a plurality of sections.

[0166] According to one embodiment, the DPD model of the DPD module is determined based on LUT data corresponding to one section among the plurality of sections, and the one section can be indexed based on a delay component of a designated LUT among the at least one LUT.

[0167] According to one embodiment, the designated LUT may include a LUT having the smallest delay component among the at least one LUT.

Claims

1. In the DPD (digital pre-distortion) module, At least one memory storing at least one look-up table (LUT) group including at least one LUT determined based on characteristics of a plurality of power amplifiers; A plurality of bit concatenate circuits for extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and A DPD module including a DPD (digital pre-distortion) circuit that verifies each LUT based on data output from the plurality of bit concatenate circuits, determines a DPD model based on each LUT, and performs pre-distortion on at least one power amplifier for an input signal input to at least one power amplifier based on the DPD model.

2. In paragraph 1, At least one LUT group above, A DPD module comprising at least one LUT used together for predistortion of at least one power amplifier among the plurality of power amplifiers.

3. In paragraph 1, A DPD module further comprising at least one clock gating circuit corresponding to each of the at least one memory and blocking a clock of the corresponding memory.

4. In paragraph 1, Further comprising at least one delay circuit for compensating for the delay component of data output by the above plurality of bit concatenate circuits, A DPD module in which the at least one delay circuit compensates for the delay component of the data based on the LUT with the smallest delay component among the at least one LUT.

5. In paragraph 1, The number of bits of data output from the above memory is equal to the sum of the number of bits allocated to each LUT included in the LUT group, A DPD module in which the number of bits of data output from each of the above plurality of bit concatenate circuits is equal to the number of bits allocated to each LUT.

6. In paragraph 1, An absolute value (magnitude) operation circuit that receives an input signal of the above DPD module and outputs an absolute value signal of the input signal, and A DPD module further comprising a quantization circuit that quantizes the output signal of the absolute value operation circuit and divides LUT data corresponding to each LUT included in the LUT group into a plurality of sections.

7. In paragraph 6, The DPD model of the DPD module is determined based on LUT data corresponding to one section among the plurality of sections, A DPD module wherein the above one section is indexed based on the delay component of a designated LUT among the at least one LUT.

8. In a transceiver for a wireless communication system, multiple power amplifiers; and Includes a DPD (digital pre-distortion) module, The above DPD module, At least one memory storing at least one look-up table (LUT) group including at least one look-up table (LUT) determined based on the characteristics of the plurality of power amplifiers; A plurality of bit concatenate circuits for extracting consecutive bits of data output from the memory based on the number of bits allocated to each LUT; and A transceiver device including a DPD (digital pre-distortion) circuit that verifies each LUT based on data output from the plurality of bit concatenate circuits, determines a DPD model based on each LUT, and applies pre-distortion to at least one power amplifier for an input signal input to at least one power amplifier based on the DPD model.

9. In paragraph 8, At least one LUT group above, A transceiver device comprising at least one LUT used together for predistortion of at least one power amplifier among the plurality of power amplifiers.

10. In paragraph 8, A transceiver device further comprising at least one clock gating circuit corresponding to each of the at least one memory and blocking a clock of the corresponding memory.

11. In paragraph 8, Further comprising at least one delay circuit for compensating for the delay component of data output by the above plurality of bit concatenate circuits, A transceiver device in which the at least one delay circuit compensates for the delay component of the data based on the LUT with the smallest delay component among the at least one LUT.

12. In paragraph 9, The number of at least one delay circuit is, A transceiver having one less than the number of the above-mentioned multiple bit concatenate circuits.

13. In paragraph 8, The number of bits of data output from the above memory is equal to the sum of the number of bits allocated to each LUT included in the LUT group, A transceiver device in which the number of bits of data output from each of the plurality of bit concatenate circuits is equal to the number of bits allocated to each LUT.

14. In paragraph 8, An absolute value (magnitude) operation circuit that receives an input signal of the above DPD module and outputs an absolute value signal of the input signal, and A transceiver further comprising a quantization circuit that quantizes the output signal of the absolute value operation circuit and divides LUT data corresponding to each LUT included in the LUT group into a plurality of sections.

15. In paragraph 14, The DPD model of the DPD module is determined based on LUT data corresponding to one section among the plurality of sections, A transceiver device, wherein the above one section is indexed based on the delay component of a designated LUT among the at least one LUT.

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