Hardware efficient randomized compiling

Abstract

Techniques are described for a hardware-based Randomized Compiling (RC) protocol in quantum computing to perform random Pauli selection, commutation of these Paulis through two-qubit gates, and single-qubit gate combination during circuit execution, eliminating the need to do these steps in software before runtime. The hardware-based RC protocol may be implemented on a FPGA. A core module for a qubit of a quantum circuit may select randomly a twirling gate for the qubit for each one of two-qubit gate cycles during execution of the quantum circuit. The core module may determine an undo gate of the twirling gate for each one of the two-qubit gate cycle. The core module may further combine the qubit with the twirling gate for the qubit for a current one of the two-qubit gate cycles and the undo gate for a previous one of the two-qubit gate cycles to generate a randomization of the quantum circuit.

Description

Attorney Docket No.: 2024-053-02 HARDWARE EFFICIENT RANDOMIZED COMPILING Inventors: Gang Huang, Neelay Fruitwala, Akel Hashim, Yilun Xu, Abhi Rajagopala, Ravi Naik CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of filing date of U.S. Provisional Application No. 63 / 651,033, filed on May 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. STATEMENT OF GOVERNMENT SUPPORT

[0002] This invention was made with government support under Contract No. DE-AC02- 05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention. BACKGROUND

[0003] The successful implementation of algorithms on quantum processors relies on the accurate control of quantum bits (qubits) to perform logic gate operations. In noisy intermediate-scale quantum (NISQ) computing, systematic miscalibrations, drift, and crosstalk in the control of qubits can lead to a coherent form of error that has no classical analog. Coherent errors severely limit the performance of quantum algorithms in an unpredictable manner, and mitigating their impact is necessary for realizing reliable quantum computations. Moreover, the average error rates measured by randomized benchmarking and related protocols are not sensitive to the full impact of coherent errors and therefore do not reliably predict the global performance of quantum algorithms, making it difficult to validate the accuracy of future large-scale quantum computations. Randomized Compiling (RC) is a protocol designed to overcome these performance limitations by converting coherent errors into stochastic noise, dramatically reducing unpredictable errors in quantum algorithms and enabling accurate predictions of algorithmic performance from error rates measured via cycle benchmarking. It is desired to perform a fully randomized compiling (FRC) by sampling a different randomized circuit per experimental trial, referred to as a shot. However, the standard method for performing RC has a high experimental overhead, as it requires generating many randomized logically-equivalent circuits in software prior to run-time, measuring each circuitAttorney Docket No.: 2024-053-02 independently, and combining the results in post-processing. Therefore, the overhead scales linearly with the number of desired randomizations. The result is that FRC remains impractical for many applications which require more than a few tens or hundreds of shots. Improving the run-time performance of RC and related methods would be beneficial to enable measuring more randomizations in the same amount of clock time. SUMMARY

[0004] RC is a protocol used to convert arbitrary Markovian noise to Pauli stochastic noise when executing a quantum circuit. Traditionally, RC is implemented at the software level before generating sequences to send to a quantum computer. Disclosed is a hardware-efficient protocol for performing RC that generates the twirling gates and the correction gates on a hardware platform, such as the Field Programmable Gate Array (FPGA) in the qubit control system, on a cycle-by-cycle basis during the execution of the quantum circuit. The method performs a different randomization per shot without incurring additional overhead beyond measuring a circuit without RC. This technique removes the pre-generation and pre- compilation of the randomized circuits, and so it improves the quantum circuit execution time significantly. The technique also significantly reduces the variance in measured observables and can be used for any other protocol that utilizes Pauli twirling, such as cycle benchmarking, Pauli noise reconstruction, averaged circuit eigenvalue sampling, mirror circuit fidelity estimation, etc.

[0005] In one aspect, the hardware-based RC protocol performs random Pauli selection, commutation of these Paulis through two-qubit gates, and single-qubit gate combination all on the control FPGA during circuit execution, eliminating the need to do these steps in software before runtime. The method has zero additional experimental overhead for most single-qubit gate durations and negligible compile time overhead, eliminating the dependence of the overhead on the number of randomizations, and reducing the overall time complexity of compilation and upload.

[0006] Details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.Attorney Docket No.: 2024-053-02 BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 shows a block diagram of an implementation of the hardware-based RC protocol according to an embodiment.

[0008] Figure 2 shows a timing diagram for operating a core module of the hardware- based RC protocol for the Pauli twirling, inversion of the Pauli twirl, and the single-qubit gate combination of a qubit according to an embodiment.

[0009] Figure 3(A) shows a quantum circuit split into interleaved cycles of single-qubit gates and two-qubit gates for noise tailoring using RC according to an embodiment.

[0010] Figure 3(B) shows a logically equivalent circuit of the quantum circuit of Figure 3(a) after inserting random twirling gates for a current gate cycle and undo gates for a previous gate cycle adjacent to single-qubit gates when operating the RC protocol according to an embodiment.

[0011] Figure 3(C) shows the quantum circuit of Figure 3(b) after combining adjacent single-qubit gates when operating the RC protocol according to an embodiment.

[0012] Figure 4 shows the results of tailoring the noise of the coherent errors of a quantum circuit using the RC protocol illustrated in figures 3(B) and 3(C) to mitigate the effects of coherent errors in a quantum circuit according to an embodiment.

[0013] Figure 5 shows a flow diagram of a method for implementing the hard-based RC protocol according to an embodiment. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to some specific examples of the invention including the best modes contemplated by the inventors for carrying out the invention. Examples of these specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

[0015] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. Particular example embodiments of the present invention may be implemented without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.Attorney Docket No.: 2024-053-02

[0016] Various techniques and mechanisms of the present invention will sometimes be described in singular form for clarity. However, it should be noted that some embodiments include multiple iterations of a technique or multiple instantiations of a mechanism unless noted otherwise.

[0017] The terms “about” or “approximate” and the like are synonymous and are used to indicate that the value modified by the term has an understood range associated with it, where the range can be ± 20%, ± 15%, ± 10%, ± 5%, or ± 1%. The terms “substantially” and the like are used to indicate that a value is close to a targeted value, where close can mean, for example, the value is within 80% of the targeted value, within 85% of the targeted value, within 90% of the targeted value, within 95% of the targeted value, or within 99% of the targeted value.

[0018] Randomized compiling (RC) is a noise mitigation protocol that interleaves “hard” two-qubit gates with randomized Pauli twirling operations. When a single quantum circuit is compiled over many randomizations, coherent two-qubit gate errors are transformed into incoherent errors, greatly improving the overall performance and predictability of the circuit. The compilation protocol comprises the following transformations, where the quantum circuit is assumed to include alternating cycles of “easy” single qubit gates and “hard” two qubit gates: 1) apply a random Pauli gate to each qubit before each two-qubit gate cycle; 2) add inversion Paulis which “undo” the Pauli twirl applied in operation 1 after the two-qubit gate cycle; 3) combine all temporally-adjacent single qubit gates (i.e., P U3 P’ → U3’; where P’ is the undo Pauli from operation 2 for a previous cycle, P is the twirling operation for the current cycle, and U3 is the pre-existing single qubit gate cycle.

[0019] Traditionally, RC is performed entirely in software; for each randomization, a new circuit is generated with the appropriate Pauli twirling and inversion gates compiled into the single-qubit gate cycles. This constitutes a single “randomization” of the original “bare” circuit. RC repeats this process many times to generate n different randomizations of the bare circuit. RC measures each randomization independently, and then combines the results from all randomizations in post-processing to generate an output distribution that is equivalent to a single quantum circuit. This imposes an O(n*w*d) overhead on the circuit compilation and upload time, where n is the number of randomizations, and w and d are the circuit width and depth, respectively.

[0020] Disclosed is a hardware-efficient RC implementation that performs random Pauli selection, commutation of these Paulis through the two-qubit gates, and single-qubit gate combination all on the control FPGA during circuit execution, eliminating the need to do these operations in software before runtime. The hardware-based RC protocol has zero real-timeAttorney Docket No.: 2024-053-02 overhead for most single-qubit gate implementations (e.g., gate time greater than 12 ns), and negligible compile time overhead, reducing the overall time complexity of compilation to O(1*w*d).

[0021] Figure 1 shows a block diagram of a FPGA for implementing the hardware-based RC protocol. The FPGA implementation is integrated with a FPGA-based control hardware 130, such as the open-source QubiC hardware targeted to run quantum programs. The FPGA- based control hardware 130 may have a distributed architecture in which each core is responsible for control and measurement of a single qubit. Each core may be connected to a dedicated RC_module, which is responsible for the Pauli twirling, inversion of the Pauli twirl, and the single-qubit gate combination for the corresponding qubit. Figure 1 shows a core for qubit 1 (131) connected to an RC_module for qubit 1 (121); a core for qubit 2 (132) connected to an RC_module for qubit 2 (121), and a core for qubit 3 (133) connected to an RC_module for qubit 3 (123). All RC_modules (121, 122, 123) may be connected to a global pseudorandom number generator (PRNG) 110 for sampling twirling. In one embodiment, the FPGA may be implemented in Verilog. The operations of the RC_modules (121, 122, 123) may include random Pauli selection and latching, commutation through two-qubit gate for the undo operation of the Pauli twirling, combination of adjacent single-qubit gates, and interfacing with the FPGA-based control hardware.

[0022] For the random Pauli selection and latching operation, the global PRNG 110 may generate random numbers for selecting twirling gates using a 2 × Nqubit bit-width LFSR (linear feedback shift register), where Nqubitis the number of qubits. The LFSR (referred to interchangeably with PRNG 110) may generate a new random number every FPGA clock cycle by drawing from a uniform distribution of pseudorandom numbers. Each RC_module (121, 122, 123) operating the gate cycles for a qubit may select a 2-bit slice from the 2 × Nqubit LFSR for Pauli selection. For example, at the beginning of each two-qubit gate cycle, each RC_module (121, 122, 123) may latch its corresponding 2-bit slice (171, 172, 173) to draw a twirling gate from the set of four possible single-qubit Paulis {I, X, Y, Z}. The RC_module may cache the random twirling gate from the previous clock cycle for the inversion Pauli.

[0023] In one embodiment, to provide maximum flexibility, the global PRNG 110 may store the full random word of the 2 × Nqubit LFSR for both the current and previous clock cycles. In one embodiment, an external latch_enable signal (141, 142, 143) from a pulse sequencing core (not shown) of the FPGA-based control hardware 130 may indicate the beginning of a new gate cycle, which may include a cycle of single-qubit gates followed by a cycle of two- qubit gates. The latch_enable signal (141, 142, 143) is synchronized within all pairs of qubitsAttorney Docket No.: 2024-053-02 performing entangling during that cycle. The RC_modules (121, 122, 123) may use the latch_enable signals (141, 142, 143) to latch in their respective 2-bit slices (171, 172, 173) from the current output of the LFSR for the new set of twirling gates, and to latch in 2-bit slices from LFSR for the previous clock cycle for computing the inversion Pauli. Using a global PRNG 110 ensures that every RC_module (121, 122, 123) is aware of the selected twirling gates for all of the qubits, thus enabling the RC_modules (121, 122, 123) to compute the inversion Paulis across each two-qubit slice.

[0024] In one embodiment, the pulse sequencing core may provide the latch_enable signals (141, 142, 143) as an extension of the instruction set architecture (ISA) of the control hardware 130 (e.g., an extension of the QubiC ISA). The pulse sequencing core may assert the latch_enable signal (141, 142, 143) indicating a new gate cycle at a specific timestamp provided in the instruction. This allows for the latch_enable signals (141, 142, 143) to be synchronized across different processor cores (131, 132, 133), ensuring that qubits sharing a two-qubit gate during a given cycle also share a common set of twirling gates (i.e., the 2 × NqubitLFSR value is latched in during the same clock cycle). The timestamp is referenced to the processor core internal counter, which is also used for controlling the pulse trigger time.

[0025] For the undo (also called inversion) operation, the RC_modules (121, 122, 123) may propagate a pair of Pauli gates through a two-qubit gate using a function of the form: ^^^^ᇱ,^^ᇱ^^ ൌ ^^ଶொ^^^^, ^^^^ (Equation 1)where ^^^is the applied twirling gate on qubit i, ^^^ᇱis the undo gate of the twirling on qubit i, and ^^ଶொis the commutation operation.

[0026] In one embodiment, the two-qubit gates are Clifford gates. Therefore, propagating a pair of Pauli gates through a two-qubit gate yields another pair of Paulis. The undo operation can be represented as a 16-element lookup table, mapping the two-qubit Pauli ^^^⊗ ^^^∈ ^^^,^^,^^,^^^⊗ଶto an-other two-qubit Pauli ^^^ᇱ⊗ ^^^ᇱ∈ ^^^,^^,^^,^^^⊗ଶ, depending on which two- qubit Clifford gate(s) are used in the circuit. In one embodiment, the hardware-based RC protocol may support two types of two-qubit gates (e.g., CNOT and CZ) of the Clifford group. The FPGA fabric may then implement two of the 16-element lookup tables, as well as supporting the identity operation where ^^ᇱ^ ൌ ^^^.

[0027] For the single-qubit gate combination operation, the Pauli twirling and undo operation inserts Pauli gates around either side of each two-qubit gate cycle. Because the circuit is structured into alternating cycles of single- and two-qubit gates, the inserted Paulis will always be adjacent to another cycle of single-qubit gates. Therefore, any single qubit gate U3Attorney Docket No.: 2024-053-02 becomes ^^^^^3^^^ᇱି^, where ^^^is the current twirling gate and ^^^ᇱି^is the inversion gate from the previous cycle.

[0028] The hardware-based RC protocol assumes that the U3 is decomposed into ^^^∅ଶ^^^ଽ^^^^∅^^^^ଽ^^^^∅^^, where ^^^∅^^ are the virtual-Z gates with arbitrary phases, and ^^ଽ^is a π / 2 gate about the x-axis. In this decomposition, Pauli operators may be absorbed into the virtual-Z phases: ^^^^^^∅ଶ^^^ଽ^^^^∅^^^^ଽ^^^^∅^^^^ᇱ^ି^ ൌ ^^^∅ᇱଶ ^^^ଽ^^^^∅^ᇱ^^^ଽ^^^^∅ᇱ^ ^ (Equation 2)

[0029] The new phases ∅ᇱ^ are given by a function of the form: ∅ᇱ^ ൌ േ∅^ (േ^^^ (Equation 3)depending on the specific Pauli operators being absorbed. The FPGA fabric may implement the absorption of the Pauli operators as a 64-element map (four possibilities each for ^^^and ^^ᇱ^ି^ and three values of ^^ ∈ ^0,1,2^ to the set of functions ^^^∅^^ ൌ ^∅^,െ∅^,^^ െ ∅^,^^ ^∅^^.

[0030] In one embodiment, the pulse sequencing core of the FPGA-based control hardware 130 may provide signaling (151, 152, 153) to the RC_modules (121, 122, 123) to modify the virtual-Z phase parameters for the single-qubit gate combination. The signaling (151, 152, 153) may provide to each RC_module an initial phase ∅^, metadata indicating the previous gate in the two-qubit gate cycle (e.g., CNOT, CZ, or identity), qubit pair (for computing the inversion operations for a two-qubit gate), as well as the location of the virtual-Z phase in the ^^^∅ଶ^^^ଽ^^^^∅^^^^ଽ^^^^∅^^ U3 gate. The RC_module (121, 122, 123) may then determine the appropriate inversion Paulis from the provided metadata, and return a modified phase∅ᇱ^ ^161, 162, 163^ to the processor core ^131, 132, 133^. A processor core ALU (arithmeticlogic unit) (not shown) may save the modified phase ∅ᇱ^ ^161, 162, 163^ to a register or use itto increment a phase accumulator to track the accumulated phase. In one embodiment, the signaling (151, 152, 153) to modify the virtual-Z phase parameters may be an extension of the ISA of the control hardware 130 (e.g., an extension of the QubiC ISA).

[0031] Figure 2 shows a timing diagram for operating a core module of the hardware-based RC protocol for the Pauli twirling, inversion of the Pauli twirl, and the single-qubit gate combination of a qubit according to an embodiment. For example, the core module may be one of the RC_modules (121, 122, 123) of the FPGA-based control hardware 130 of Figure 1.

[0032] The FPGA-based control hardware 130 generates a FPGA clock (210). Each FPGA clock (210) may represent a gate cycle (240), which includes a cycle of single-qubit gatesAttorney Docket No.: 2024-053-02 followed by a cycle of two-qubit gates. Figure 2 shows for gate cycle i, there is a single-qubit gate cycle i followed by a two-qubit gate cycle i; for gate cycle i+1, there is a single-qubit gate cycle i+1 followed by a two-qubit gate cycle i+1.

[0033] A LFSR (220) (e.g., a global PRNG 110 of Figure 1) generates a random number for each FPGA clock (210).

[0034] A pulse sequencing core of the FPGA-based control hardware 130 generates a latch_enable signal (230) (e.g., latch_enable signals (141, 142, 143) of Figure 1) to indicate the beginning of each new gate cycle (240) to each RC_module.

[0035] An RC module uses the latch_enable signal (230) to latch its corresponding 2-bit slice (e.g., 2-bit slice (171, 172, 173) of Figure 1) of the LFSR (220) to draw a twirling gate from the set of four possible single-qubit Paulis {I, X, Y, Z} during each single-qubit gate cycle of the Pauli selection and undo operation 250. Figure 2 shows during single-qubit gate cycle i, the RC_module latches its 2-bit slice of the LFSR (220) to draw a twirling gate Pi for cycle i; during single-qubit gate cycle i+1, the RC_module latches its 2-bit slice of the LFSR (220) to draw a twirling gate Pi+1 for cycle i+1.

[0036] The RC module propagates the twirling gate to generate the undo gate during each two-qubit gate cycle of the Pauli selection and undo operation 250. Figure 2 shows during two-qubit gate cycle i, the RC_module propagates twirling gate Pi to generate an undo gate P’i;during two-qubit gate cycle i+1, the RC_module propagates twirling gate Pi+1to generate an undo gate P’i+1. The propagation of a pair of twirling gates through a two-qubit gate is shown in Equation 1. In one embodiment, the FPGA-based control hardware 130 may provide the RC_module with metadata indicating the previous gate in the two-qubit gate cycle (e.g., CNOT, CZ, or identity) and the qubit pair for the RC_module to compute the inversion operations for the two-qubit gate. For a one-qubit gate, the undo gate may be the same as the twirling gate.

[0037] The pulse sequencing core of the FPGA-based control hardware 130 provides an RC_alu instruction (260) during each gate cycle to instruct the RC_module to combine the twirling gate for the current gate cycle and the undo gate from the previous gate cycle with the single-qubit gate to perform the single-qubit gate combination operation 270. The operation of the single-qubit gate combination is shown in Equation 2. The RC_alu instruction may provide to each RC_module an initial phase ∅^of the virtual-Z gates of the single-qubit gate, as well as the location of the virtual-Z phase in the ^^^∅ଶ^^^ଽ^^^^∅^^^^ଽ^^^^∅^^. Figure 2 shows during gate cycle i, the RC_module performs the single-qubit gate combination operation toAttorney Docket No.: 2024-053-02 generate ^^^^^3^^^ᇱି^, where ^^^ᇱି^is the undo gate from gate cycle gate cycle i-1; during gate cycle i+1, the RC_module performs the single-qubit gate combination operation to generate ^^^ା^^^3^^^ᇱ, where U3 is the single qubit gate.

[0038] Figure 3(A) shows a quantum circuit split into interleaved cycles of single-qubit gates (310) and two-qubit gates (320) for noise tailoring using RC according to an embodiment.

[0039] Four single-qubit gates (310) are shown for each gate cycle. Gate cycle i includes single-qubit gate cycle i (330) and two-qubit gate cycle i (335). Gate cycle i+1 includes single- qubit gate cycle i+1 (340) and two-qubit gate cycle i (345). In a first gate cycle, single-qubit gates H and Z are paired to form a two-qubit gate (320). In a second gate cycle, single-qubit gates T and Z are paired to two form two-qubit gates.

[0040] Figure 3(B) shows a logically equivalent circuit of the quantum circuit of Figure 3(A) after inserting random twirling gates for a current gate cycle and undo gates for a previous gate cycle adjacent to single-qubit gates when operating the RC protocol according to an embodiment. During gate cycle i, twirling gate Pi(350) (X, X, X, Y) is inserted adjacent to single-qubit gates (310) (X, H, Z, X). Propagation of the twirling gate Pi (350) generates the undo gate P’i(355) (X, X, I, Y). During gate cycle i+1, twirling gate Pi+1(360) (X, X, Z, I) is inserted adjacent to single-qubit gates (T, Z, I, Y). Propagation of the twirling gate Pi+1 (360) generates the undo gate P’i+1(365) (X, X, Z, I).

[0041] Figure 3(C) shows the quantum circuit of Figure 3(B) after combining adjacent single-qubit gates using RC when operating the RC protocol according to an embodiment. Combining Pi+1 (360) (X, X, Z, I) for gate cycle i+1, undo gate P’i (355) (X, X, I, Y) for gate cycle i, and single-qubit gates (T, Z, I, Y) generates combined gate ^^^ା^^^3^^^ᇱ(370) (Z, Z, Z, I) where U3 represents the single qubit gate (T, Z, I, Y).

[0042] Figure 4 shows the results of tailoring the noise of the coherent errors of a quantum circuit using the RC protocol illustrated in figures 3(B) and 3(C) to mitigate the effects of coherent errors in a quantum circuit according to an embodiment.

[0043] The ideal state (410) of a qubit shows the noiseless state vector. Measured state of the qubit (420) show an over-rotation caused by coherent errors compared to the ideal (noiseless) state (410). By tailoring the coherent noise using RC, the resulting state (430) is more closely aligned with the ideal (noiseless) state (410).

[0044] Figure 5 shows a flow diagram of a method 500 for implementing the hard-based RC protocol according to an embodiment. The method 500 may be implemented by aAttorney Docket No.: 2024-053-02 RC_module (121, 122, 123) under control of a FPGA-based control hardware control hardware 130.

[0045] In operation 502, the RC_module selects randomly a twirling gate for a qubit for each one of two-qubit gate cycles during execution of a quantum circuit.

[0046] In operation 504, the RC_module determines an undo gate of the twirling gate for each one of the two-qubit gate cycle.

[0047] In operation 506, the RC_module combines the qubit with the twirling gate for the qubit for a current one of the two-qubit gate cycles and the undo gate for a previous one of the two-qubit gate cycles to generate a randomization of the quantum circuit.

[0048] Embodiments described herein may be implemented using different types of hardware and are not limited to FPGAs.

[0049] In one embodiment, the present disclosure provides for a method to mitigate errors through application of Randomized Compiling at run-time, without prior individual compilation of mitigated circuits.

[0050] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of invention.

Claims

Attorney Docket No.: 2024-053-02 CLAIMS What is claimed is:

1. A method for tailoring noise in quantum computing, comprising: selecting randomly a twirling gate for a qubit for each one of two-qubit gate cycles during execution of a quantum circuit; determining an undo gate of the twirling gate for each one of the two-qubit gate cycle; and combining the qubit with the twirling gate for the qubit for a current one of the two-qubit gate cycles and the undo gate for a previous one of the two-qubit gate cycles to generate a randomization of the quantum circuit.

2. The method of claim 1, wherein the quantum circuit comprises alternating cycles of single-qubit gates and two-qubit gates, wherein the single-qubit gates are associated with single-qubit gate cycles, and wherein the two-qubit gates are associated with the two-qubit gate cycles.

3. The method of claim 2, wherein selecting randomly the twirling gate comprises: selecting randomly a Pauli twirling gate during each cycle of the single- qubit gate cycles for one of the single-qubit gates.

4. The method of claim 3, wherein determining the undo gate of the twirling gate comprises: propagating the Pauli twirling gate through the two-qubit gates during each cycle of the two-qubit gate cycles.

5. The method of claim 3, wherein said selecting the Pauli twirling gate for each one of the single-qubit gates are synchronized.

6. The method of claim 3, wherein determining the undo gate of the twirling gate comprises: propagating a pair of Pauli twirling gates through the two-qubit gates to generate a second pair of Pauli twirling gates.Attorney Docket No.: 2024-053-02 7. The method of claim 2, wherein determining the undo gate of the twirling gate comprises: storing the undo gate for a current one of the two-qubit gate cycles for combining with the twirling gate for a next one of the two-qubit gate cycles and one of the single-qubit gates associated with a next one of the single-qubit gate cycles.

8. The method of claim 2, wherein selecting randomly the twirling gate and determining the undo gate of the twiring gate comprises: inserting the twirling gate for the current one of the two-qubit gate cycles and the undo gate for the previous one of the two-qubit gate cycles adjacent to each one of the single-qubit gates.

9. The method of claim 8, wherein combing the qubit with the twirling gate and the undo gate comprises: decomposing each one of the single-qubit gates into virtual Z-gate phases; and modifying the virtual Z-gate phases based on the twirling gate for the current one of the two-qubit gate cycles and the undo gate for the previous one of the two- qubit gate cycles.

10. The method of claim 1, further comprising: repeating said selecting, determining, and combining to generate a plurality of randomizations of the quantum circuit during execution of the quantum circuit; and combining the plurality of randomizations of the quantum circuit to tailor coherent errors of the quantum circuit into incoherent errors.

11. An apparatus, comprising: a control hardware configured to sequence execution of a quantum circuit based on a clock cycle; a pseudorandom number generator configured to generate a random number for every one of the clock cycle; a module for a qubit configured to receive control signals from the control hardware to:Attorney Docket No.: 2024-053-02 select randomly a twirling gate for the qubit for each one of two-qubit gate cycles based on the random number during execution of the quantum circuit; determine an undo gate of the twirling gate for each one of the two-qubit gate cycle; and combine the qubit with the twirling gate for the qubit for a current one of the two-qubit gate cycles and the undo gate for a previous one of the two- qubit gate cycles to generate a randomization of the quantum circuit.

12. The apparatus of claim 11, wherein the quantum circuit comprises alternating cycles of single-qubit gates and two-qubit gates, wherein the single-qubit gates are associated with single-qubit gate cycles, and wherein the two-qubit gates are associated with the two-qubit gate cycles.

13. The apparatus of claim 12, wherein to select randomly the twirling gate, the module is configured to: select, based on the random number, a Pauli twirling gate during each cycle of the single-qubit gate cycles for one of the single-qubit gates.

14. The apparatus of claim 13, wherein to determine the undo gate of the twirling gate, the module is configured to: propagate the Pauli twirling gate through the two-qubit gates during each cycle of the two-qubit gate cycles.

15. The apparatus of claim 13, wherein the control hardware is further configured to generate a control signal to synchronize selecting the Pauli twirling gate for each one of the single-qubit gates.

16. The apparatus of claim 13, wherein to determine the undo gate of the twirling gate, the module is configured to: propagate a pair of Pauli twirling gates through the two-qubit gates to generate a second pair of Pauli twirling gates.Attorney Docket No.: 2024-053-02 17. The apparatus of claim 12, wherein to determine the undo gate of the twirling gate, the module is configured to: store the undo gate for a current one of the two-qubit gate cycles, and wherein to combine the qubit with the twirling gate and the undo gate, the module is configured to: receive a control signal at a next one of the two-qubit gate cycles from the control hardware; and combine the undo gate that is stored with the twirling gate for a next one of the two-qubit gate cycles and one of the single-qubit gates associated with a next one of the single-qubit gate cycles.

18. The apparatus of claim 12, wherein to select randomly the twirling gate and to determine the undo gate of the twirling gate, the module is configured to: insert the twirling gate for the current one of the two-qubit gate cycles and the undo gate for the previous one of the two-qubit gate cycles adjacent to each one of the single-qubit gates.

19. The apparatus of claim 18, wherein to combine the qubit with the twirling gate and the undo gate, the module is configured to: decompose each one of the single-qubit gates into virtual Z-gate phases; and modify the virtual Z-gate phases based on the twirling gate for the current one of the two-qubit gate cycles and the undo gate for the previous one of the two- qubit gate cycles.

20. The apparatus of claim 11, wherein the module is further configured to: repeatedly select randomly a twirling gate, determine an undo gate of the twirling gate, and combine the qubit with the twirling gate and the undo gate to generate a plurality of randomizations of the quantum circuit during execution of the quantum circuit, and wherein the control hardware is further configured to: combine the plurality of randomizations of the quantum circuit to tailor coherent errors of the quantum circuit into incoherent errors.

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