Shift register and driving method therefor, and display apparatus

Abstract

A shift register and a driving method therefor, and a display apparatus. The shift register may comprise an input sub-circuit, a control sub-circuit and an output sub-circuit, wherein under the control of a signal from at least one of a first clock signal terminal and a second clock signal terminal, the input sub-circuit provides a signal from a signal input terminal to a first node; under the control of signals from at least one of the first clock signal terminal and the second clock signal terminal and from a third clock signal terminal, a second power supply terminal and the first node, the control sub-circuit provides a signal from a first power supply terminal to the first node, provides to a second node a signal from the second power supply terminal, at least one of the first clock signal terminal and the second clock signal terminal, or the first power supply terminal, and provides a signal from the first node to a fourth node; and under the control of signals from the second node and the fourth node, the output sub-circuit provides to a signal output terminal the signal from the first power supply terminal or the third clock signal terminal.

Description

Shift register and driving method thereof, and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, display technology, in particular to a shift register and driving method thereof, and display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: an input sub-circuit, a control sub-circuit, and an output sub-circuit;

[0006] The input sub-circuit is electrically connected with a signal input end, a first node, and at least one of a first clock signal end and a second clock signal end, and is configured to provide a signal of the signal input end to the first node under the control of a signal of at least one of the first clock signal end and the second clock signal end;

[0007] The control sub-circuit is electrically connected with the first node, a second node, a fourth node, a first power supply end, a second power supply end, a third clock signal end, and at least one of the first clock signal end and the second clock signal end, and is configured to provide a signal of the first power supply end to the first node, a signal of the second power supply end, or at least one of the first clock signal end and the second clock signal end, or the first power supply end to the second node, and a signal of the first node to the fourth node, under the control of signals of at least one of the first clock signal end and the second clock signal end, the third clock signal end, the second power supply end, and the first node;

[0008] The output sub-circuit is electrically connected with the second node, the first power supply end, the fourth node, the third clock signal end and the signal output end respectively, and is configured to provide the signal output end with the signal of the first power supply end or the third clock signal end under the control of the signals of the second node and the fourth node.

[0009] In some possible implementation manners, the input sub-circuit comprises a first transistor.

[0010] The control electrode of the first transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node.

[0011] In some possible implementation manners, the control sub-circuit comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a fourth control sub-circuit.

[0012] The first control sub-circuit is electrically connected with the first node, the second node, at least one of the first clock signal end and the second clock signal end respectively, and is configured to adjust the signal of the second node under the control of at least one of the first node and at least one of the signals of the first clock signal end and the second clock signal end.

[0013] The second control sub-circuit is electrically connected with at least one of the first clock signal end and the second clock signal end, the second power supply end and the second node respectively, and is configured to provide the second node with the signal of the second power supply end under the control of the signal of at least one of the first clock signal end and the second clock signal end.

[0014] The third control sub-circuit is electrically connected with the first node, the second node, the first power supply end and the third clock signal end respectively, and is configured to provide the first node with the signal of the first power supply end under the control of the signals of the second node and the third clock signal end.

[0015] The fourth control sub-circuit is electrically connected with the first node, the fourth node and the second power supply end respectively, and is configured to provide the fourth node with the signal of the first node under the control of the signal of the second power supply end.

[0016] In some possible implementation manners, the first control sub-circuit is configured to provide the second node with the signal of at least one of the first clock signal end and the second clock signal end under the control of the signal of the first node.

[0017] In some possible implementation manners, the first control sub-circuit comprises a second transistor.

[0018] The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with at least one of the first clock signal end and the second clock signal end.

[0019] In some possible implementation manners, the first control sub-circuit is further electrically connected with the first power supply end and is configured to provide a signal of the first power supply end to the second node under control of signals of the first node and at least one of the first clock signal end and the second clock signal end.

[0020] In some possible implementation manners, the first control sub-circuit includes a second transistor and a ninth transistor.

[0021] The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the fifth node; the control electrode of the ninth transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the first power supply end.

[0022] In some possible implementation manners, the first control sub-circuit includes a second transistor and a ninth transistor.

[0023] The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the fifth node, and the second electrode of the second transistor is electrically connected with the first power supply end; the control electrode of the ninth transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the fifth node.

[0024] In some possible implementation manners, the second control sub-circuit includes a third transistor.

[0025] The control electrode of the third transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node.

[0026] In some possible implementation manners, the third control sub-circuit includes a sixth transistor and a seventh transistor.

[0027] The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the third node; the control electrode of the seventh transistor is electrically connected with the third clock signal end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first node.

[0028] In some possible implementation manners, the third control sub-circuit includes a sixth transistor and a seventh transistor.

[0029] The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first node; the control electrode of the seventh transistor is electrically connected with the third clock signal terminal, the first electrode of the seventh transistor is electrically connected with the first power supply terminal, and the second electrode of the seventh transistor is electrically connected with the third node.

[0030] In some possible implementation manners, the fourth control sub-circuit includes an eighth transistor.

[0031] The control electrode of the eighth transistor is electrically connected with the second power supply terminal, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fourth node.

[0032] In some possible implementation manners, the output sub-circuit includes a fourth transistor, a fifth transistor, a first capacitor and a second capacitor.

[0033] The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the first power supply terminal, and the second electrode of the fourth transistor is electrically connected with the signal output terminal;

[0034] The control electrode of the fifth transistor is electrically connected with the fourth node, the first electrode of the fifth transistor is electrically connected with the signal output terminal, and the second electrode of the fifth transistor is electrically connected with the third clock signal terminal;

[0035] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply terminal, and the second plate of the first capacitor is electrically connected with the second node;

[0036] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the signal output terminal, and the second plate of the second capacitor is electrically connected with the fourth node.

[0037] In a second aspect, the embodiments of the present disclosure provide a display device having a display area and a non-display area, including: a gate drive circuit and a clock signal line group located in the non-display area, the gate drive circuit including a plurality of cascaded shift registers as described in any of the embodiments of the first aspect, and the clock signal line group including a first clock signal line to an Nth clock signal line, N being a positive integer greater than or equal to 3.

[0038] The signal output terminal of the mth shift register is electrically connected with the signal input terminal of the m+2th shift register, 1≤m≤M-2, and M is the total number of stages of the shift registers.

[0039] The at least one stage shift register is electrically connected with three clock signal lines among the first clock signal line to the Nth clock signal line, and the first clock signal line to the Nth clock signal line are arranged in sequence along the direction close to the display area.

[0040] In some possible implementation manners, N=4;

[0041] The first clock signal end of the 4a-3 stage shift register is electrically connected with the first clock signal line, the second clock signal end is electrically connected with the second clock signal line, and the third clock signal end is electrically connected with the third clock signal line.

[0042] The first clock signal end of the 4a-2 stage shift register is electrically connected with the second clock signal line, the second clock signal end is electrically connected with the third clock signal line, and the third clock signal end is electrically connected with the fourth clock signal line.

[0043] The first clock signal end of the 4a-1 stage shift register is electrically connected with the third clock signal line, the second clock signal end is electrically connected with the fourth clock signal line, and the third clock signal end is electrically connected with the first clock signal line.

[0044] The first clock signal end of the 4a stage shift register is electrically connected with the fourth clock signal line, the second clock signal end is electrically connected with the first clock signal line, and the third clock signal end is electrically connected with the second clock signal line, 1≤a≤M / 4.

[0045] In some possible implementation manners, N=3;

[0046] The first clock signal end of the 3a-2 stage shift register is electrically connected with the first clock signal line, the second clock signal end is electrically connected with the second clock signal line, and the third clock signal end is electrically connected with the third clock signal line.

[0047] The first clock signal end of the 3a-1 stage shift register is electrically connected with the second clock signal line, the second clock signal end is electrically connected with the third clock signal line, and the third clock signal end is electrically connected with the first clock signal line.

[0048] The first clock signal end of the 3a stage shift register is electrically connected with the third clock signal line, the second clock signal end is electrically connected with the first clock signal line, and the third clock signal end is electrically connected with the second clock signal line, 1≤b≤M / 3.

[0049] In some possible implementation manners, the display device further includes a high-level power supply line and a low-level power supply line located in the non-display area, the high-level power supply line is located on the side of the clock signal line group close to the display area, and the low-level power supply line is located on the side of the clock signal line group away from the display area or close to the display area.

[0050] The first power supply end of the at least one stage of shift registers is electrically connected to the high-level power supply line, and the second power supply end of the at least one stage of shift registers is electrically connected to the low-level power supply line.

[0051] The wiring width of the high-level power supply line is greater than or equal to the wiring width of the low-level power supply line.

[0052] In some possible implementation manners, the display device further includes one initial signal line.

[0053] The signal input ends of the first stage of shift registers and the second stage of shift registers are electrically connected to the initial signal line.

[0054] In some possible implementation manners, the display device further includes a first initial signal line and a second initial signal line.

[0055] The signal input end of the first stage of shift registers is electrically connected to the first initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the second initial signal line.

[0056] In some possible implementation manners, the display device further includes j virtual shift registers and one initial signal line, 1≤j≤2.

[0057] When j=1, the signal input end of the virtual shift register and the signal input end of the first stage of shift registers are respectively electrically connected to the initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the virtual shift register.

[0058] Alternatively,

[0059] When j=2, the signal input end of the first virtual shift register and the signal input end of the second virtual shift register are respectively electrically connected to the initial signal line, the signal input end of the first stage of shift registers is electrically connected to the signal output end of the first virtual shift register, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the second virtual shift register.

[0060] In some possible implementation manners, the display device further includes j virtual shift registers and a first initial signal line and a second initial signal line, 1≤j≤2.

[0061] When j=1, the signal input end of the virtual shift register is electrically connected to the first initial signal line, the signal input end of the first stage of shift registers is electrically connected to the second initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the virtual shift register.

[0062] Alternatively,

[0063] j=2, a signal input end of the first virtual shift register is electrically connected with the first initial signal line, a signal input end of the second virtual shift register is electrically connected with the second initial signal line, a signal input end of the first stage shift register is electrically connected with a signal output end of the first virtual shift register, and a signal input end of the second stage shift register is electrically connected with a signal output end of the second virtual shift register.

[0064] In some possible implementation manners, the display device further includes a high-level power supply line, a low-level power supply line, a light-emitting power supply line and at least one initial signal line located in the non-display area.

[0065] At least one signal line in the clock signal line group, the high-level power supply line, the low-level power supply line, the light-emitting power supply line and the at least one initial signal line has a projection on the substrate that at least partially overlaps with a projection of the at least one stage shift register on the substrate.

[0066] In some possible implementation manners, the display device further includes a high-level power supply line, a low-level power supply line, a light-emitting power supply line and at least one initial signal line located in the non-display area.

[0067] At least one signal line in the clock signal line group, the light-emitting power supply line and the at least one initial signal line has a projection on the substrate that does not overlap with a projection of the at least one stage shift register on the substrate, and the projection of the high-level power supply line and the low-level power supply line on the substrate at least partially overlaps with the projection of the at least one stage shift register on the substrate.

[0068] In a third aspect, an embodiment of the present disclosure provides a driving method of a shift register, configured to drive the shift register as described in any of the embodiments of the first aspect, and the method comprises:

[0069] The input sub-circuit provides a signal of the signal input end to the first node under the control of a signal of at least one of the first clock signal end and the second clock signal end;

[0070] The control sub-circuit provides a signal of the first power supply end to the first node, a signal of the second power supply end or at least one of the first clock signal end and the second clock signal end or the first power supply end to the second node, and a signal of the first node to the fourth node under the control of signals of the first clock signal end and the second clock signal end, the third clock signal end, the second power supply end and the first node;

[0071] The output sub-circuit provides a signal of the first power supply end or the third clock signal end to the signal output end under the control of signals of the second node and the fourth node.

[0072] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0073] SUMMARY

[0074] The accompanying drawings are intended to provide a better understanding of the technical scheme of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure serve to explain the technical scheme of the present disclosure, and do not constitute a limitation on the technical scheme of the present disclosure.

[0075] Fig. 1 is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure;

[0076] Fig. 2 is an equivalent circuit diagram of an input sub-circuit provided by an exemplary embodiment;

[0077] Fig. 3 is an equivalent circuit diagram of a control sub-circuit provided by an exemplary embodiment;

[0078] Fig. 4A is an equivalent circuit diagram of a first control sub-circuit provided by an exemplary embodiment;

[0079] Fig. 4B is an equivalent circuit diagram of a first control sub-circuit provided by an exemplary embodiment;

[0080] Fig. 4C is an equivalent circuit diagram of a first control sub-circuit provided by an exemplary embodiment;

[0081] Fig. 5 is an equivalent circuit diagram of an input sub-circuit provided by an exemplary embodiment;

[0082] Fig. 6A is an equivalent circuit diagram of a third control sub-circuit provided by an exemplary embodiment;

[0083] Fig. 6B is an equivalent circuit diagram of a third control sub-circuit provided by an exemplary embodiment;

[0084] Fig. 7 is an equivalent circuit diagram of a fourth control sub-circuit provided by an exemplary embodiment;

[0085] Fig. 8 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment;

[0086] Fig. 9 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0087] Fig. 10 is a working timing diagram of a shift register provided by an exemplary embodiment;

[0088] Fig. 11 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0089] Fig. 12 is a working timing diagram of a shift register provided by an exemplary embodiment;

[0090] Fig. 13 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0091] FIG. 14 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0092] FIG. 15 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0093] FIG. 16 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0094] FIG. 17 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0095] FIG. 18 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0096] FIG. 19 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0097] FIG. 20 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0098] FIG. 21 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0099] FIG. 22 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0100] FIG. 23 is a structural circuit diagram of a display device according to an example embodiment;

[0101] FIG. 24 is a timing chart of a display device according to an example embodiment;

[0102] FIG. 25 is a structural circuit diagram of a display device according to an example embodiment;

[0103] FIG. 26A is a structural circuit diagram of a display device according to an example embodiment;

[0104] FIG. 26B is a structural circuit diagram of a display device according to an example embodiment;

[0105] FIG. 27A is a structural circuit diagram of a display device according to an example embodiment;

[0106] FIG. 27B is a structural circuit diagram of a display device according to an example embodiment;

[0107] FIG. 28 is a wiring diagram of a display device according to an example embodiment;

[0108] FIG. 29 is a wiring diagram of a display device according to an example embodiment;

[0109] FIG. 30 is a diagram of simulation results according to an example embodiment;

[0110] FIG. 31 is a schematic diagram of simulation results according to an example embodiment.

[0111] DETAILED DESCRIPTION

[0112] For the purposes of the present disclosure, technical solutions and advantages, the following will be described in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. It will be readily understood by those skilled in the art that the specific form and content of the embodiments can be changed to various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0113] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0114] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0115] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0116] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, can be fixedly connected, or detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected via an intervening member, or internal communication of two elements. The specific meaning of the above terms in the present disclosure can be understood in light of the specific circumstances for those skilled in the art.

[0117] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0118] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, the "source electrode" and the "drain electrode" can be interchanged with each other in this specification.

[0119] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit or receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include an electrode and a wiring as well as a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0120] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0121] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0122] In the present specification, "co-deposition" refers to two (or more) structures formed by the same patterning process, and the materials of the two (or more) structures can be the same or different. For example, the materials of the precursors forming the two (or more) structures are the same, and the final materials of the two (or more) structures can be the same or different.

[0123] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly in the sense that they can be approximately a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation caused by tolerances, there can be lead angles, arc edges, and deformations, etc.

[0124] In the present disclosure, "about" refers to not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0125] The OLED display substrate includes a pixel circuit, a light emitting element, and a gate drive circuit, wherein the gate drive circuit is configured to provide a gate signal to the pixel circuit, so that the pixel circuit can drive the light emitting element to emit light. At present, the gate drive circuit adopts a clock signal line for driving output, and there are problems of high frequency and large load of the clock signal line, and high power consumption of the gate drive circuit.

[0126] Figure 1 is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure, as shown in Figure 1, the shift register provided by the embodiment of the present disclosure can include an input sub-circuit, a control sub-circuit, and an output sub-circuit.

[0127] The input sub-circuit is electrically connected with the signal input end IN, the first node N1, and at least one of the first clock signal end CK1 and the second clock signal end CK2, respectively, and is configured to provide the signal of the signal input end IN to the first node N1 under the control of the signal of at least one of the first clock signal end CK1 and the second clock signal end CK2.

[0128] The control sub-circuit is electrically connected with the first node N1, the second node N2, the fourth node N4, the first power supply end V1, the second power supply end V2, the third clock signal end CK3, and at least one of the first clock signal end CK1 and the second clock signal end CK2, respectively, and is configured to provide the signal of the first power supply end V1 to the first node N1, provide the signal of the second power supply end V2, or at least one of the first clock signal end CK1 and the second clock signal end CK2, or the first power supply end V1 to the second node N2, and provide the signal of the first node N1 to the fourth node N4, under the control of the signals of at least one of the first clock signal end CK1 and the second clock signal end CK2, the third clock signal end CK3, the second power supply end V2, and the first node N1.

[0129] In an example embodiment, when the input sub-circuit is electrically connected with one of the first clock signal terminal CK1 and the second clock signal terminal CK2 (such as CK1), the control sub-circuit is electrically connected with the other one of the first clock signal terminal CK1 and the second clock signal terminal CK2 (such as CK2).

[0130] The output sub-circuit is electrically connected with the second node N2, the first power supply terminal V1, the fourth node N4, the third clock signal terminal CK3 and the signal output terminal OUT respectively, and is configured to provide the signal of the first power supply terminal V1 or the third clock signal terminal CK3 to the signal output terminal OUT under the control of the signals of the second node N2 and the fourth node N4.

[0131] In an example embodiment, the signals of the first clock signal terminal CK1, the second clock signal terminal CK2 and the third clock signal terminal CK3 can be periodic pulse signals.

[0132] In an example embodiment, the first power supply terminal V1 continuously provides a high-level signal, and the second power supply terminal V2 continuously provides a low-level signal.

[0133] The shift register provided by the embodiments of the present disclosure can provide the signal of the signal input terminal IN to the first node N1 under the control of the signal of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2, and can provide the signal of the first power supply terminal V1 to the first node N1 and the signal of the second power supply terminal V2 or at least one of the second clock signal terminal CK2 and the first clock signal terminal CK1 or the first power supply terminal V1 to the second node N2 under the control of the signals of at least one of the second clock signal terminal CK2 and the first clock signal terminal CK1, the third clock signal terminal CK3, the second power supply terminal V2 and the first node N1, which can be driven and output by the signals of the three clock signal terminals, i.e., the first clock signal terminal CK1, the second clock signal terminal CK2 and the third clock signal terminal CK3, so that the signal output capability is strong, the driving stability is good, the load of the clock signal terminal is reduced, and the power consumption is reduced.

[0134] FIG. 2 is an equivalent circuit diagram of the input sub-circuit provided by an example embodiment, as shown in FIG. 2, in an example embodiment, the input sub-circuit can include: a first transistor T1.

[0135] In an example embodiment, as shown in FIG. 2, the control electrode of the first transistor T1 is electrically connected with at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected with the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0136] An exemplary structure of the input sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the input sub-circuit is not limited to this.

[0137] FIG. 3 is an equivalent circuit diagram of the control sub-circuit according to an exemplary embodiment. As shown in FIG. 3, in an exemplary embodiment, the control sub-circuit can include a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a fourth control sub-circuit.

[0138] The first control sub-circuit is electrically connected to at least one of the first node N1, the second node N2, the first clock signal terminal CK1, and the second clock signal terminal CK2, and is configured to adjust the signal of the second node under the control of at least one of the first node N1, the first clock signal terminal CK1, and the second clock signal terminal CK2.

[0139] The second control sub-circuit is electrically connected to at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2, the second power supply terminal V2, and the second node N2, and is configured to provide the signal of the second power supply terminal V2 to the second node N2 under the control of the signal of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2.

[0140] In an exemplary embodiment, when the input sub-circuit is electrically connected to one of the first clock signal terminal CK1 and the second clock signal terminal CK2 (such as CK1), the first control sub-circuit and the second control sub-circuit are respectively electrically connected to the other of the first clock signal terminal CK1 and the second clock signal terminal CK2 (such as CK2).

[0141] The third control sub-circuit is electrically connected to the first node N1, the second node N2, the first power supply terminal V1, and the third clock signal terminal CK3, and is configured to provide the signal of the first power supply terminal V1 to the first node N1 under the control of the signals of the second node N2 and the third clock signal terminal CK3.

[0142] The fourth control sub-circuit is electrically connected to the first node N1, the fourth node N4, and the second power supply terminal V2, and is configured to provide the signal of the first node N1 to the fourth node N4 under the control of the signal of the second power supply terminal V2.

[0143] In an exemplary embodiment, the first control sub-circuit is configured to provide the signal of at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2 to the second node N2 under the control of the signal of the first node N1.

[0144] Figure 4A is an equivalent circuit diagram of the first control sub-circuit according to an example embodiment. As shown in Figure 4A, in an example embodiment, the first control sub-circuit can include a second transistor T2.

[0145] In an example embodiment, as shown in Figure 4A, a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the second node N2, and a second electrode of the second transistor T2 is electrically connected to at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2.

[0146] An example structure of the first control sub-circuit is shown in Figure 4A. It is easily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited thereto.

[0147] In an example embodiment, the first control sub-circuit is further electrically connected to the first power supply terminal V1 and is configured to provide a signal of the first power supply terminal V1 to the second node N2 under the control of signals of the first node N1 and at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2.

[0148] Figure 4B is an equivalent circuit diagram of the first control sub-circuit according to an example embodiment. As shown in Figure 4B, in an example embodiment, the first control sub-circuit can include a second transistor T2 and a ninth transistor T9.

[0149] In an example embodiment, as shown in Figure 4B, a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the second node N2, and a second electrode of the second transistor T2 is electrically connected to a fifth node N5; a control electrode of the ninth transistor T9 is electrically connected to at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2, a first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and a second electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1. By adding the ninth transistor T9, the output stability can be improved.

[0150] An example structure of the first control sub-circuit is shown in Figure 4B. It is easily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited thereto.

[0151] Figure 4C is an equivalent circuit diagram of the first control sub-circuit according to an example embodiment. As shown in Figure 4C, in an example embodiment, the first control sub-circuit can include a second transistor T2 and a ninth transistor T9.

[0152] In an example embodiment, as shown in FIG. 4C, the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the fifth node N5, and the second electrode of the second transistor T2 is electrically connected with the first power supply end V1; the control electrode of the ninth transistor T9 is electrically connected with at least one of the first clock signal end CK1 and the second clock signal end CK2, the first electrode of the ninth transistor T9 is electrically connected with the second node N2, and the second electrode of the ninth transistor T9 is electrically connected with the fifth node N5. By adding the ninth transistor T9, the output stability can be improved.

[0153] An example structure of the first control sub-circuit is shown in FIG. 4C. It is easily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this.

[0154] FIG. 5 is an equivalent circuit diagram of an input sub-circuit provided by an example embodiment. As shown in FIG. 5, in an example embodiment, the second control sub-circuit can include a third transistor T3.

[0155] In an example embodiment, as shown in FIG. 5, the control electrode of the third transistor T3 is electrically connected with at least one of the first clock signal end CK1 and the second clock signal end CK2, the first electrode of the third transistor T3 is electrically connected with the second power supply end V2, and the second electrode of the third transistor T3 is electrically connected with the second node N2.

[0156] An example structure of the second control sub-circuit is shown in FIG. 5. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0157] FIG. 6A is an equivalent circuit diagram of a third control sub-circuit provided by an example embodiment. As shown in FIG. 6A, in an example embodiment, the third control sub-circuit can include a sixth transistor T6 and a seventh transistor T7.

[0158] In an example embodiment, as shown in FIG. 6A, the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first power supply end V1, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3; the control electrode of the seventh transistor T7 is electrically connected with the third clock signal end CK3, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first node N1.

[0159] An example structure of the third control sub-circuit is shown in FIG. 6A. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0160] Fig. 6B is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment. As shown in Fig. 6B, in an example embodiment, the third control sub-circuit can include a sixth transistor T6 and a seventh transistor T7.

[0161] In an example embodiment, as shown in Fig. 6B, a control electrode of the sixth transistor T6 is electrically connected with the second node N2, a first electrode of the sixth transistor T6 is electrically connected with the third node N3, and a second electrode of the sixth transistor T6 is electrically connected with the first node N1; a control electrode of the seventh transistor T7 is electrically connected with the third clock signal terminal CK3, a first electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1, and a second electrode of the seventh transistor T7 is electrically connected with the third node N3.

[0162] An example structure of the third control sub-circuit is shown in Fig. 6B. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0163] Fig. 7 is an equivalent circuit diagram of a fourth control sub-circuit according to an example embodiment. As shown in Fig. 7, in an example embodiment, the fourth control sub-circuit can include an eighth transistor T8.

[0164] In an example embodiment, as shown in Fig. 7, a control electrode of the eighth transistor T8 is electrically connected with the second power supply terminal V2, a first electrode of the eighth transistor T8 is electrically connected with the first node N1, and a second electrode of the eighth transistor T8 is electrically connected with the fourth node N4.

[0165] An example structure of the fourth control sub-circuit is shown in Fig. 7. It is easily understood by those skilled in the art that the implementation of the fourth control sub-circuit is not limited to this.

[0166] Fig. 8 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in Fig. 8, in an example embodiment, the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0167] In an example embodiment, as shown in FIG. 8, the control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply end V1, and the second electrode of the fourth transistor T4 is electrically connected with the signal output end OUT; the control electrode of the fifth transistor T5 is electrically connected with the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected with the signal output end OUT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal end CK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply end V1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the signal output end OUT, and the second plate C22 of the second capacitor is electrically connected with the fourth node N4.

[0168] An example structure of the output sub-circuit is shown in FIG. 8. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited to this.

[0169] FIG. 9 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 9, in an example embodiment, the shift register can include an input sub-circuit, a control sub-circuit, and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to an eighth transistor T8, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0170] In an example embodiment, as shown in FIG. 9, the control electrode of the first transistor T1 is electrically connected with the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected with the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second node N2, and the second electrode of the second transistor T2 is electrically connected with the second clock signal terminal CK2; the control electrode of the third transistor T3 is electrically connected with the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected with the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected with the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected with the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected with the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3; the control electrode of the seventh transistor T7 is electrically connected with the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first node N1; the control electrode of the eighth transistor T8 is electrically connected with the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected with the fourth node N4.

[0171] An example structure of the shift register is shown in FIG. 9. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0172] FIG. 10 is a working timing diagram of the shift register provided by an example embodiment. The working process of the shift register shown in FIG. 9 is used to explain the example embodiments of the disclosure.

[0173] In an example embodiment, as shown in FIG. 10, the working process of the shift register can include:

[0174] The first stage P1: the signal of the first clock signal end CK1 and the signal input end IN is a low level signal, and the signal of the second clock signal end CK2 and the third clock signal end CK3 is a high level signal; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 writes the high level signal of the second clock signal end CK2; the eighth transistor T8 is always open, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Wherein, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0175] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signal of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 is a high level signal; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, and the second node N2 is pulled low through the second transistor T2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1. Wherein, the seventh transistor T7 is closed.

[0176] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signal of the signal input end IN, the first clock signal end CK1 and the second clock signal end CK2 is a high level signal; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on; the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 writes the high level signal of the second clock signal end CK2. Wherein, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0177] The fourth stage P4: the signals of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed. Since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0178] The fifth stage P5: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, and the first transistor T1 is turned on. The first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Since the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0179] The sixth stage P6: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, and the first transistor T1 is closed. The signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1. Among them, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0180] Fig. 11 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in Fig. 11, in an exemplary embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to an eighth transistor T8, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0181] In an example embodiment, as shown in FIG. 11, the control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected to the second node N2; and the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0182] An example structure of the shift register is shown in FIG. 11. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0183] FIG. 12 is a timing diagram of the working process of the shift register according to an example embodiment. The working process of the shift register shown in FIG. 11 is described below to illustrate the example embodiments of the present disclosure.

[0184] In an example embodiment, as shown in FIG. 12, the working process of the shift register can include:

[0185] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0186] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0187] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0188] The fourth stage P4: the signals of the signal input end IN, the second clock signal end CK2, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed. Since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0189] The fifth stage P5: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, and the first transistor T1 is turned on. The first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Since the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0190] The sixth stage P6: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1. Among them, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0191] Fig. 13 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in Fig. 13, in an exemplary embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to an eighth transistor T8, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0192] In an example embodiment, as shown in FIG. 13, the control electrode of the first transistor T1 is electrically connected with the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected with the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second node N2, and the second electrode of the second transistor T2 is electrically connected with the second clock signal terminal CK2; the control electrode of the third transistor T3 is electrically connected with the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected with the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected with the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected with the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected with the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first node N1; the control electrode of the seventh transistor T7 is electrically connected with the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected with the fourth node N4.

[0193] An example structure of the shift register is shown in FIG. 13. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0194] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register shown in FIG. 13 is used to illustrate the example embodiment of the disclosure.

[0195] In an example embodiment, the working process of the shift register can include:

[0196] The first stage P1: the signal of the first clock signal end CK1 and the signal input end IN is a low level signal, and the signal of the second clock signal end CK2 and the third clock signal end CK3 is a high level signal; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 writes the high level signal of the second clock signal end CK2; the eighth transistor T8 is always open, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0197] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, and the second node N2 is pulled low through the second transistor T2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1. Among them, the seventh transistor T7 is closed.

[0198] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the second clock signal end CK2 are high level signals; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply end V1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 writes the high level signal of the second clock signal end CK2. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0199] The fourth stage P4: the signals of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed. Since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0200] The fifth stage P5: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, and the first transistor T1 is turned on. The first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Since the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0201] The sixth stage P6: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1. Among them, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0202] Fig. 14 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in Fig. 14, in an exemplary embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to an eighth transistor T8, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0203] In an example embodiment, as shown in FIG. 14, the control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected to the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0204] An example structure of the shift register is shown in FIG. 14. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0205] Based on the working timing diagram of the shift register shown in FIG. 12, the working process of the shift register shown in FIG. 14 is used to illustrate the example embodiment of the disclosure.

[0206] In an example embodiment, the working process of the shift register can include:

[0207] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0208] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0209] The signal of the second clock signal terminal CK2 is a low-level signal, the first transistor T1 is turned on, and the first node N1 writes the low-level signal of the signal input terminal IN. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the second node N2 writes the high-level signal of the first clock signal terminal CK1; the eighth transistor T8 is always open, the fourth node N4 writes the low-level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output terminal OUT outputs the high-level signal of the third clock signal terminal CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0210] The fourth stage P4: the signals of the signal input end IN, the second clock signal end CK2, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed. Since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0211] The fifth stage P5: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, and the first transistor T1 is turned on. The first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Since the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are closed.

[0212] The sixth stage P6: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply end V2, the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is communicated with the first node N1. Among them, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0213] Fig. 15 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in Fig. 15, in an exemplary embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to a ninth transistor T9, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0214] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected with the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected with the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second node N2, and the second electrode of the second transistor T2 is electrically connected with the fifth node N5; the control electrode of the third transistor T3 is electrically connected with the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected with the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected with the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected with the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected with the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3; the control electrode of the seventh transistor T7 is electrically connected with the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first node N1; the control electrode of the eighth transistor T8 is electrically connected with the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the second clock signal terminal CK2, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply terminal V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected with the fourth node N4.

[0215] An example structure of the shift register is shown in FIG. 15. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0216] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register shown in FIG. 15 is used to illustrate the example embodiment of the disclosure below.

[0217] In an example embodiment, the working process of the shift register can include:

[0218] The first stage P1: the signals of the first clock signal end CK1 and the signal input end IN are low level signals, and the signals of the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is connected with the fifth node N5. The eighth transistor T8 is always open, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0219] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1. The signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end V1 is provided to the second node N2 through the fifth node N5. Among them, the seventh transistor T7 is closed.

[0220] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the second clock signal end CK2 are high level signals; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2 to ensure that the fifth transistor T5 is completely turned on. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is connected with the fifth node N5. The signal of the second clock signal end CK2 is a high level signal, and the ninth transistor T9 is closed. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0221] The fourth stage P4: the signals of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed, because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Wherein, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are closed.

[0222] The fifth stage P5: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, and the first transistor T1 is turned on, the first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Because the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Wherein, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0223] The sixth stage P6: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, the signal output end OUT outputs the high level signal of the first power supply end V1; the sixth transistor T6 is turned on, the third node N3 writes the high level signal of the first power supply end V1; the signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the fifth node N5 is in communication with the second node N2. Wherein, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0224] Figure 16 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 16, the shift register can include an input sub-circuit, a control sub-circuit, and an output sub-circuit. The input sub-circuit can include a first transistor T1. The control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6, and a ninth transistor T9. The output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0225] In an example embodiment, as shown in Figure 16, a control electrode of the first transistor T1 is electrically connected to a first clock signal terminal CK1. A first electrode of the first transistor T1 is electrically connected to a signal input terminal IN. A second electrode of the first transistor T1 is electrically connected to a first node N1. A control electrode of the second transistor T2 is electrically connected to the first node N1. A first electrode of the second transistor T2 is electrically connected to a fifth node N5. A second electrode of the second transistor T2 is electrically connected to a first power supply terminal V1. A control electrode of the third transistor T3 is electrically connected to a second clock signal terminal CK2. A first electrode of the third transistor T3 is electrically connected to a second power supply terminal V2. A second electrode of the third transistor T3 is electrically connected to a second node N2. A control electrode of the fourth transistor T4 is electrically connected to the second node N2. A first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1. A second electrode of the fourth transistor T4 is electrically connected to a signal output terminal OUT. A control electrode of the fifth transistor T5 is electrically connected to a fourth node N4. A first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT. A second electrode of the fifth transistor T5 is electrically connected to a third clock signal terminal CK3. A control electrode of the sixth transistor T6 is electrically connected to the second node N2. A first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1. A second electrode of the sixth transistor T6 is electrically connected to a third node N3. A control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3. A first electrode of the seventh transistor T7 is electrically connected to the third node N3. A second electrode of the seventh transistor T7 is electrically connected to the first node N1. A control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. A first electrode of the eighth transistor T8 is electrically connected to the first node N1. A second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A control electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal CK2. A first electrode of the ninth transistor T9 is electrically connected to the second node N2. A second electrode of the ninth transistor T9 is electrically connected to the fifth node N5. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1. The second plate C12 of the first capacitor is electrically connected to the second node N2. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT. The second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0226] An exemplary structure of the shift register is shown in FIG. 16. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0227] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register exemplified by FIG. 16 is described below to illustrate the exemplary embodiments of the present disclosure.

[0228] In an exemplary embodiment, the working process of the shift register can include:

[0229] The first stage P1: the signals of the first clock signal end CK1 and the signal input end IN are low level signals, and the signals of the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the fifth node N5 writes the high level signal of the first power supply end V1. The eighth transistor T8 is always on, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0230] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is turned off, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1. The signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the second node N2 writes the high level signal of the first power supply end V1. Among them, the seventh transistor T7 is turned off.

[0231] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is closed. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0232] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is closed. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0233] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is closed. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0234] In the sixth stage P6, the signal of the second clock signal terminal CK2 is a low-level signal, the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals; the signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 is closed, the signal of the second clock signal terminal CK2 is a low-level signal, the third transistor T3 is turned on, and the second node N2 writes the low-level signal of the second power supply terminal V2; the fourth transistor T4 is turned on, the signal output terminal OUT outputs the high-level signal of the first power supply terminal V1; the sixth transistor T6 is turned on, the third node N3 writes the high-level signal of the first power supply terminal V1; the signal of the second clock signal terminal CK2 is a low-level signal, the ninth transistor T9 is turned on, and the fifth node N5 is in communication with the second node N2. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0235] Fig. 17 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in Fig. 17, in an example embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to a ninth transistor T9, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0236] In an example embodiment, as shown in FIG. 17, the control electrode of the first transistor T1 is electrically connected with the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected with the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second node N2, and the second electrode of the second transistor T2 is electrically connected with the fifth node N5; the control electrode of the third transistor T3 is electrically connected with the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected with the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected with the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected with the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected with the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected with the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first node N1; the control electrode of the seventh transistor T7 is electrically connected with the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the second clock signal terminal CK2, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the first power supply terminal V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected with the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected with the fourth node N4.

[0237] An example structure of the shift register is shown in FIG. 17. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0238] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register shown in FIG. 17 is used to illustrate the example embodiment of the disclosure as follows.

[0239] In an example embodiment, the working process of the shift register can include:

[0240] The first stage P1: the signals of the first clock signal end CK1 and the signal input end IN are low level signals, and the signals of the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5; the eighth transistor T8 is always open, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0241] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1. The signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end V1 is provided to the second node N2 through the fifth node N5. Among them, the seventh transistor T7 is closed.

[0242] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the second clock signal end CK2 are high level signals; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply end V1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so as to ensure that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal end CK2 is a high level signal, and the ninth transistor T9 is closed. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0243] The fourth stage P4: the signals of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed, because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Wherein, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are closed.

[0244] The fifth stage P5: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, and the first transistor T1 is turned on, the first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Because the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Wherein, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0245] The sixth stage P6: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1, the third clock signal end CK3 and the fourth clock signal end CK4 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, the signal output end OUT outputs the high level signal of the first power supply end V1; the sixth transistor T6 is turned on, the third node N3 is communicated with the first node N1; the signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the fifth node N5 is communicated with the second node N2. Wherein, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0246] Figure 18 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 18, the shift register can include an input sub-circuit, a control sub-circuit, and an output sub-circuit. The input sub-circuit can include a first transistor T1. The control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6, and a ninth transistor T9. The output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0247] In an example embodiment, as shown in Figure 18, a control electrode of the first transistor T1 is electrically connected to a first clock signal terminal CK1. A first electrode of the first transistor T1 is electrically connected to a signal input terminal IN. A second electrode of the first transistor T1 is electrically connected to a first node N1. A control electrode of the second transistor T2 is electrically connected to the first node N1. A first electrode of the second transistor T2 is electrically connected to a fifth node N5. A second electrode of the second transistor T2 is electrically connected to a first power supply terminal V1. A control electrode of the third transistor T3 is electrically connected to a second clock signal terminal CK2. A first electrode of the third transistor T3 is electrically connected to a second power supply terminal V2. A second electrode of the third transistor T3 is electrically connected to a second node N2. A control electrode of the fourth transistor T4 is electrically connected to the second node N2. A first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1. A second electrode of the fourth transistor T4 is electrically connected to a signal output terminal OUT. A control electrode of the fifth transistor T5 is electrically connected to a fourth node N4. A first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT. A second electrode of the fifth transistor T5 is electrically connected to a third clock signal terminal CK3. A control electrode of the sixth transistor T6 is electrically connected to the second node N2. A first electrode of the sixth transistor T6 is electrically connected to a third node N3. A second electrode of the sixth transistor T6 is electrically connected to the first node N1. A control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3. A first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1. A second electrode of the seventh transistor T7 is electrically connected to the third node N3. A control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. A first electrode of the eighth transistor T8 is electrically connected to the first node N1. A second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A control electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal CK2. A first electrode of the ninth transistor T9 is electrically connected to the second node N2. A second electrode of the ninth transistor T9 is electrically connected to the fifth node N5. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1. The second plate C12 of the first capacitor is electrically connected to the second node N2. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT. The second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0248] An exemplary structure of the shift register is shown in FIG. 18. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0249] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register exemplified by FIG. 18 is used to illustrate the exemplary embodiments of the present disclosure below.

[0250] In an exemplary embodiment, the working process of the shift register can include:

[0251] The first stage P1: the signals of the first clock signal end CK1 and the signal input end IN are low level signals, and the signals of the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the fifth node N5 writes the high level signal of the first power supply end V1. The eighth transistor T8 is always on, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0252] The second stage P2: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the first clock signal end CK1 is a high level signal, the first transistor T1 is turned off, the signal of the second clock signal end CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1; the signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1. The signal of the second clock signal end CK2 is a low level signal, the ninth transistor T9 is turned on, and the second node N2 writes the high level signal of the first power supply end V1. Among them, the seventh transistor T7 is turned off.

[0253] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is turned off. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0254] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is turned off. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0255] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the second clock signal terminal CK2 is a high level signal, and the ninth transistor T9 is turned off. The first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0256] In the sixth stage P6, the signal of the second clock signal terminal CK2 is a low level signal, the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high level signals; the signal of the first clock signal terminal CK1 is a high level signal, the first transistor T1 is closed, the signal of the second clock signal terminal CK2 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply terminal V2; the fourth transistor T4 is turned on, the signal output terminal OUT outputs the high level signal of the first power supply terminal V1; the sixth transistor T6 is turned on, the third node N3 is in communication with the first node N1; the signal of the second clock signal terminal CK2 is a low level signal, the ninth transistor T9 is turned on, and the fifth node N5 is in communication with the second node N2. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0257] Fig. 19 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in Fig. 19, in an example embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit. The input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to a ninth transistor T9, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0258] In an example embodiment, as shown in FIG. 19, the control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected to the second node N2; and the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0259] An example structure of the shift register is shown in FIG. 19. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0260] Based on the working timing diagram of the shift register shown in FIG. 12, the working process of the shift register shown in FIG. 19 is used to illustrate the example embodiment of the disclosure below.

[0261] In an example embodiment, the working process of the shift register can include:

[0262] The first stage P1: the signals of the second clock signal end CK2 and the signal input end IN are low level signals, and the signals of the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The eighth transistor T8 is always on, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0263] The second stage P2: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end V1 is provided to the second node N2 through the fifth node N5. Among them, the seventh transistor T7 is closed.

[0264] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the first clock signal end CK1 are high level signals; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so as to ensure that the fifth transistor T5 is completely turned on. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal end CK1 is a high level signal, and the ninth transistor T9 is closed. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0265] The fourth stage P4: the signals of the signal input end IN, the second clock signal end CK2, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed, because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Wherein, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are closed.

[0266] The fifth stage P5: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, and the first transistor T1 is turned on, the first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Because the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Wherein, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0267] The sixth stage P6: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, the signal output end OUT outputs the high level signal of the first power supply end V1; the sixth transistor T6 is turned on, the third node N3 writes the high level signal of the first power supply end V1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the fifth node N5 is in communication with the second node N2. Wherein, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0268] Figure 20 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 20, in an example embodiment, the shift register can include an input sub-circuit, a control sub-circuit, and an output sub-circuit. The input sub-circuit can include a first transistor T1. The control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6, and a ninth transistor T9. The output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0269] In an example embodiment, as shown in Figure 20, a control electrode of the first transistor T1 is electrically connected to a second clock signal terminal CK2. A first electrode of the first transistor T1 is electrically connected to a signal input terminal IN. A second electrode of the first transistor T1 is electrically connected to a first node N1. A control electrode of the second transistor T2 is electrically connected to the first node N1. A first electrode of the second transistor T2 is electrically connected to a fifth node N5. A second electrode of the second transistor T2 is electrically connected to a first power supply terminal V1. A control electrode of the third transistor T3 is electrically connected to a first clock signal terminal CK1. A first electrode of the third transistor T3 is electrically connected to a second power supply terminal V2. A second electrode of the third transistor T3 is electrically connected to a second node N2. A control electrode of the fourth transistor T4 is electrically connected to the second node N2. A first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1. A second electrode of the fourth transistor T4 is electrically connected to a signal output terminal OUT. A control electrode of the fifth transistor T5 is electrically connected to a fourth node N4. A first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT. A second electrode of the fifth transistor T5 is electrically connected to a third clock signal terminal CK3. A control electrode of the sixth transistor T6 is electrically connected to the second node N2. A first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1. A second electrode of the sixth transistor T6 is electrically connected to a third node N3. A control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3. A first electrode of the seventh transistor T7 is electrically connected to the third node N3. A second electrode of the seventh transistor T7 is electrically connected to the first node N1. A control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. A first electrode of the eighth transistor T8 is electrically connected to the first node N1. A second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1. A first electrode of the ninth transistor T9 is electrically connected to the second node N2. A second electrode of the ninth transistor T9 is electrically connected to the fifth node N5. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1. The second plate C12 of the first capacitor is electrically connected to the second node N2. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT. The second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0270] An exemplary structure of the shift register is shown in FIG. 20. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0271] Based on the working timing diagram of the shift register shown in FIG. 12, the working process of the shift register exemplified by FIG. 20 is used to illustrate the exemplary embodiments of the present disclosure below.

[0272] In an exemplary embodiment, the working process of the shift register can include:

[0273] The first stage P1: the signals of the second clock signal end CK2 and the signal input end IN are low level signals, and the signals of the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the fifth node N5 writes the high level signal of the first power supply end V1. The eighth transistor T8 is always on, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0274] The second stage P2: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is turned off, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 writes the high level signal of the first power supply end V1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end V1 is provided to the second node N2 through the fifth node N5. Among them, the seventh transistor T7 is turned off.

[0275] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0276] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0277] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the low level signal of the first node N1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0278] In the sixth stage P6, the signal of the first clock signal terminal CK1 is a low level signal, the signals of the signal input terminal IN, the second clock signal terminal CK2 and the third clock signal terminal CK3 are high level signals; the signal of the second clock signal terminal CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal terminal CK1 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply terminal V2; the fourth transistor T4 is turned on, the signal output terminal OUT outputs the high level signal of the first power supply terminal V1; the sixth transistor T6 is turned on, the third node N3 writes the high level signal of the first power supply terminal V1; the signal of the first clock signal terminal CK1 is a low level signal, the ninth transistor T9 is turned on, the fifth node N5 is in communication with the second node N2. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0279] Fig. 21 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment, as shown in Fig. 21, in an exemplary embodiment, the shift register can include an input sub-circuit, a control sub-circuit and an output sub-circuit, the input sub-circuit can include a first transistor T1, the control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6 to a ninth transistor T9, and the output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0280] In an example embodiment, as shown in FIG. 21, the control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT, and the second electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CK3; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1; the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1, and the second plate C12 of the first capacitor is electrically connected to the second node N2; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT, and the second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0281] An example structure of the shift register is shown in FIG. 21. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0282] Based on the working timing diagram of the shift register shown in FIG. 10, the working process of the shift register shown in FIG. 21 is used to illustrate the example embodiment of the disclosure below.

[0283] In an example embodiment, the working process of the shift register can include:

[0284] The first stage P1: the signals of the second clock signal end CK2 and the signal input end IN are low level signals, and the signals of the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, and the first transistor T1 is turned on to write the low level signal of the first node N1 into the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5; the eighth transistor T8 is always open, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0285] The second stage P2: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end V1 is provided to the second node N2 through the fifth node N5. Among them, the seventh transistor T7 is closed.

[0286] The third stage P3: the signal of the third clock signal end CK3 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the first clock signal end CK1 are high level signals; the signal of the third clock signal end CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply end V1; because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output end OUT outputs the low level signal of the third clock signal end CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2 to ensure that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal end CK1 is a high level signal, and the ninth transistor T9 is closed. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are closed.

[0287] The fourth stage P4: the signals of the signal input end IN, the second clock signal end CK2, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the third clock signal end CK3 is a high level signal, and the seventh transistor T7 is closed, because the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Wherein, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the ninth transistor T9 are closed.

[0288] The fifth stage P5: the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, and the first transistor T1 is turned on, the first node N1 writes the high level signal of the signal input end IN, and the second transistor T2 is closed. Because the signal of the fourth node N4 in the last stage is a low level signal, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. The eighth transistor T8 is always open, the fourth node N4 writes the high level signal of the first node N1, and the fifth transistor T5 is closed. Wherein, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are closed.

[0289] The sixth stage P6: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2, the third clock signal end CK3 and the fourth clock signal end CK4 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, the signal output end OUT outputs the high level signal of the first power supply end V1; the sixth transistor T6 is turned on, the third node N3 is communicated with the first node N1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the fifth node N5 is communicated with the second node N2. Wherein, the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0290] Figure 22 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 22, the shift register can include an input sub-circuit, a control sub-circuit, and an output sub-circuit. The input sub-circuit can include a first transistor T1. The control sub-circuit can include a second transistor T2, a third transistor T3, a sixth transistor T6, and a ninth transistor T9. The output sub-circuit can include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0291] In an example embodiment, as shown in Figure 22, a control electrode of the first transistor T1 is electrically connected to a second clock signal terminal CK2. A first electrode of the first transistor T1 is electrically connected to a signal input terminal IN. A second electrode of the first transistor T1 is electrically connected to a first node N1. A control electrode of the second transistor T2 is electrically connected to the first node N1. A first electrode of the second transistor T2 is electrically connected to a fifth node N5. A second electrode of the second transistor T2 is electrically connected to a first power supply terminal V1. A control electrode of the third transistor T3 is electrically connected to a first clock signal terminal CK1. A first electrode of the third transistor T3 is electrically connected to a second power supply terminal V2. A second electrode of the third transistor T3 is electrically connected to a second node N2. A control electrode of the fourth transistor T4 is electrically connected to the second node N2. A first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1. A second electrode of the fourth transistor T4 is electrically connected to a signal output terminal OUT. A control electrode of the fifth transistor T5 is electrically connected to a fourth node N4. A first electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT. A second electrode of the fifth transistor T5 is electrically connected to a third clock signal terminal CK3. A control electrode of the sixth transistor T6 is electrically connected to the second node N2. A first electrode of the sixth transistor T6 is electrically connected to a third node N3. A second electrode of the sixth transistor T6 is electrically connected to the first node N1. A control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3. A first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1. A second electrode of the seventh transistor T7 is electrically connected to the third node N3. A control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. A first electrode of the eighth transistor T8 is electrically connected to the first node N1. A second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A control electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1. A first electrode of the ninth transistor T9 is electrically connected to the second node N2. A second electrode of the ninth transistor T9 is electrically connected to the fifth node N5. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first power supply terminal V1. The second plate C12 of the first capacitor is electrically connected to the second node N2. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the signal output terminal OUT. The second plate C22 of the second capacitor is electrically connected to the fourth node N4.

[0292] An exemplary structure of the shift register is shown in FIG. 22. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0293] Based on the working timing diagram of the shift register shown in FIG. 12, the working process of the shift register exemplified by FIG. 22 is used to illustrate the exemplary embodiments of the present disclosure below.

[0294] In an exemplary embodiment, the working process of the shift register can include:

[0295] The first stage P1: the signals of the second clock signal end CK2 and the signal input end IN are low level signals, and the signals of the first clock signal end CK1 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a low level signal, the first transistor T1 is turned on, and the first node N1 writes the low level signal of the signal input end IN. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, and the fifth node N5 writes the high level signal of the first power supply end V1. The eighth transistor T8 is always on, the fourth node N4 writes the low level signal of the first node N1, the fifth transistor T5 is turned on, and the signal output end OUT outputs the high level signal of the third clock signal end CK3. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0296] The second stage P2: the signal of the first clock signal end CK1 is a low level signal, and the signals of the signal input end IN, the second clock signal end CK2 and the third clock signal end CK3 are high level signals; the signal of the second clock signal end CK2 is a high level signal, the first transistor T1 is turned off, the signal of the first clock signal end CK1 is a low level signal, the third transistor T3 is turned on, and the second node N2 writes the low level signal of the second power supply end V2; the fourth transistor T4 is turned on, and the signal output end OUT outputs the high level signal of the first power supply end V1. The signal of the second node N2 is a low level signal, the sixth transistor T6 is turned on, and the third node N3 is in communication with the first node N1; the signal of the first clock signal end CK1 is a low level signal, the ninth transistor T9 is turned on, and the second node N2 writes the high level signal of the first power supply end V1. Among them, the seventh transistor T7 is turned off.

[0297] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0298] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0299] The signal of the third clock signal terminal CK3 is a low level signal, the signal of the signal input terminal IN, the second clock signal terminal CK2 and the first clock signal terminal CK1 is a high level signal; the signal of the third clock signal terminal CK3 is a low level signal, the seventh transistor T7 is turned on, and the third node N3 writes the high level signal of the first power supply terminal V1; since the signals of the first node N1 and the fourth node N4 in the last stage are low level signals, the fifth transistor T5 is turned on, the signal output terminal OUT outputs the low level signal of the third clock signal terminal CK3, and the fourth node N4 is pulled to a lower potential through the second capacitor C2, so that the fifth transistor T5 is completely turned on. The first node N1 is a low level signal, the second transistor T2 is turned on, and the second node N2 is in communication with the fifth node N5. The signal of the first clock signal terminal CK1 is a high level signal, and the ninth transistor T9 is turned off. Among them, the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0300] The sixth stage P6: the signal of the first clock signal terminal CK1 is a low level signal, the signals of the signal input terminal IN, the second clock signal terminal CK2 and the third clock signal terminal CK3 are high level signals; the signal of the second clock signal terminal CK2 is a high level signal, the first transistor T1 is closed, the signal of the first clock signal terminal CK1 is a low level signal, the third transistor T3 is turned on, the second node N2 writes the low level signal of the second power supply terminal V2; the fourth transistor T4 is turned on, the signal output terminal OUT outputs the high level signal of the first power supply terminal V1; the sixth transistor T6 is turned on, the third node N3 is in communication with the first node N1; the signal of the first clock signal terminal CK1 is a low level signal, the ninth transistor T9 is turned on, the fifth node N5 is in communication with the second node N2. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are closed.

[0301] In an example embodiment, the type of the at least one transistor is a P-type transistor.

[0302] In an example embodiment, the types of the first transistor T1 to the ninth transistor T9 are P-type transistors.

[0303] The display device provided by the embodiments of the present disclosure has a display area and a non-display area, and can include: a gate drive circuit and a clock signal line group located in the non-display area, the clock signal line group can include a first clock signal line to an Nth clock signal line, N is a positive integer greater than or equal to 3.

[0304] The gate drive circuit can include a plurality of cascaded shift registers, and the shift registers are the shift registers provided by any one of the foregoing embodiments, and have similar implementation principles and effects, which will not be described here again.

[0305] The signal output terminal of the mth shift register is electrically connected with the signal input terminal of the m+2th shift register, 1≤m≤M-2, and M is the total number of stages of the shift registers; at least one shift register is electrically connected with three clock signal lines in the first clock signal line to the Nth clock signal line, and the first clock signal line to the Nth clock signal line are arranged in sequence along the direction close to the display area.

[0306] In the embodiments of the present disclosure, the signal output terminal of the mth shift register is electrically connected with the signal input terminal of the m+2th shift register, that is, the signal input terminal of the m+2th shift register is connected with the signal output terminal of the mth shift register in front, and the signal of the signal output terminal of the mth shift register in front is written into the signal input terminal (also the first node N1) of the m+2th shift register, so that the first node N1 can be fully pulled down, and the output capability of the shift register can be ensured.

[0307] In an example embodiment, N=4, the first clock signal end of the 4th a-3 stage shift register is electrically connected with the first clock signal line, the second clock signal end is electrically connected with the second clock signal line, and the third clock signal end is electrically connected with the third clock signal line; the first clock signal end of the 4th a-2 stage shift register is electrically connected with the second clock signal line, the second clock signal end is electrically connected with the third clock signal line, and the third clock signal end is electrically connected with the fourth clock signal line; the first clock signal end of the 4th a-1 stage shift register is electrically connected with the third clock signal line, the second clock signal end is electrically connected with the fourth clock signal line, and the third clock signal end is electrically connected with the first clock signal line; the first clock signal end of the 4th a stage shift register is electrically connected with the fourth clock signal line, the second clock signal end is electrically connected with the first clock signal line, and the third clock signal end is electrically connected with the second clock signal line, 1≤a≤M / 4.

[0308] The clock signal line group can include the first clock signal line to the fourth clock signal line, which can be arranged in sequence or in reverse sequence along the direction close to the display area. The first clock signal end to the third clock signal end of each stage of shift register can be connected to the first clock signal line to the fourth clock signal line in the order of 123→234→341→412→…, to ensure the output shift relationship.

[0309] Compared with the shift register connected with two clock signal lines, the shift register connected with four clock signal lines can save power consumption, and the specific calculation result is:

[0310] Power consumption of dynamic signal f is the signal frequency, C is the total capacitance, and V is the jump voltage;

[0311] For two clock signal lines (2CK for short):

[0312] For four clock signal lines (4CK for short): C(4CK)≈0.7C(2CK), V(4CK)=V(2CK), in the theoretical case, C(4CK)=0.5C(2CK), under the influence of the actual environment, C(4CK) is between 0.6C(2CK) and 0.8C(2CK), and C(4CK)=0.7C(2CK) is calculated, then:

[0313] Therefore, compared with the shift register connected with two clock signal lines, the shift register connected with four clock signal lines can save about 30% to 50% of the shift register power consumption.

[0314] In an example embodiment, N=3, the first clock signal terminal of the 3a-2 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line; the first clock signal terminal of the 3a-1 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line; the first clock signal terminal of the 3a stage shift register is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line, 1≤b≤M / 3.

[0315] The clock signal line group can include the first clock signal line to the third clock signal line, which can be arranged in sequence or in reverse sequence along the direction close to the display area. The first clock signal terminal to the third clock signal terminal of each stage of shift register can be connected to the first clock signal line to the third clock signal line in the order of 123→231→312→…, which can ensure the output shift relationship and can save the number of channels.

[0316] In an example embodiment, the display device can further include a high-level power supply line and a low-level power supply line located in the non-display area, the high-level power supply line being located on the side of the clock signal line group close to the display area, and the low-level power supply line being located on the side of the clock signal line group away from the display area or close to the display area.

[0317] The first power supply terminal of the at least one stage of shift register is electrically connected to the high-level power supply line, and the second power supply terminal of the at least one stage of shift register is electrically connected to the low-level power supply line; the line width of the high-level power supply line is greater than or equal to the line width of the low-level power supply line.

[0318] FIG. 23 is a structural circuit diagram of a display device according to an example embodiment, as shown in FIG. 23, the display device can further include an initial signal line GSTV.

[0319] The signal input terminal IN of the first stage shift register GOA(1) and the second stage shift register GOA(2) is electrically connected to the initial signal line GSTV.

[0320] The signal input terminal IN of the first stage shift register and the second stage shift register can share the initial signal line GSTV, and the initial signal line GSTV can be a single pulse or a multi-pulse waveform with a width of 2 rows.

[0321] FIG. 24 is a timing diagram of the operation of a display device according to an example embodiment, and the timing diagram shown in FIG. 24 is described by the connection relationship of the display device shown in FIG. 23. The at least one stage of shift register in the display device can be any of the shift registers described in the above embodiments, and the operation of the shift register can refer to the operation of the shift register described in the above embodiments, which will not be described again in the example embodiments of the present disclosure.

[0322] As shown in FIG. 24, there can be no overlap between the time periods in which the signals of at least two of the first to fourth clock signal lines CLK1-CLK4 are low-level signals.

[0323] FIG. 25 is a structural circuit diagram of a display device according to an example embodiment, and as shown in FIG. 25, the display device can further include a first initial signal line GSTV1 and a second initial signal line GSTV2.

[0324] The signal input end of the first stage of shift registers GOA(1) is electrically connected to the first initial signal line GSTV1, and the signal input end of the second stage of shift registers GOA(2) is electrically connected to the second initial signal line GSTV2.

[0325] The signal input end of the first stage of shift registers can be connected to the first initial signal line GSTV1, and the signal input end of the second stage of shift registers can be connected to the second initial signal line GSTV2. The first initial signal line GSTV1 and the second initial signal line GSTV2 can be a single-pulse or multi-pulse waveform of 1 row width.

[0326] FIG. 26A is a structural circuit diagram of a display device according to an example embodiment, and FIG. 26B is a structural circuit diagram of a display device according to an example embodiment, and as shown in FIGS. 26A and 26B, the display device can further include j virtual shift registers and one initial signal line GSTV, where 1≤j≤2.

[0327] In an example embodiment, as shown in FIG. 26A, j=1, the signal input end of the virtual shift register GOAD(1) and the signal input end of the first stage of shift registers GOA(1) are electrically connected to the initial signal line GSTV, and the signal input end of the second stage of shift registers GOA(2) is electrically connected to the signal output end OUTD[1] of the virtual shift register GOAD(1).

[0328] A virtual shift register can be added before the gate drive circuit. The signal input terminal of the virtual shift register GOAD(1) ​​and the signal input terminal of the first-stage shift register GOA(1) are electrically connected to the initial signal line GSTV, respectively. The signal input terminal of the second-stage shift register GOA(2) is electrically connected to the signal output terminal OUTD[1] of the virtual shift register GOAD(1), which can ensure the stability of the output.

[0329] In one exemplary embodiment, as shown in FIG26B, the signal input terminals of the first virtual shift register GOAD(1) ​​and the second virtual shift register GOAD(2) are electrically connected to the initial signal line GSTV, respectively. The signal input terminal of the first-stage shift register GOA(1) is electrically connected to the signal output terminal OUTD[1] of the first virtual shift register GOAD(1), and the signal input terminal of the second-stage shift register GOA(2) is electrically connected to the signal output terminal GOAD(2) of the second virtual shift register GOAD(2).

[0330] Two virtual shift registers can be added before the gate drive circuit: the first virtual shift register GOAD(1) ​​and the second virtual shift register GOAD(2). The signal input terminals of the first virtual shift register GOAD(1) ​​and the second virtual shift register GOAD(2) are electrically connected to the initial signal line GSTV, respectively. The signal input terminal of the first-stage shift register GOA(1) is electrically connected to the signal output terminal OUTD[1] of the first virtual shift register GOAD(1), and the signal input terminal of the second-stage shift register GOA(2) is electrically connected to the signal output terminal GOAD(2) of the second virtual shift register GOAD(2), which can ensure the stability of the output.

[0331] Figure 27A is a structural circuit diagram of a display device provided in an exemplary embodiment, and Figure 27B is a structural circuit diagram of a display device provided in an exemplary embodiment. As shown in Figures 27A and 27B, the display device may further include: j virtual shift registers and a first initial signal line GSTV1 and a second initial signal line GSTV2, where 1≤j≤2.

[0332] In one exemplary embodiment, as shown in FIG27A, j=1, the signal input terminal of the virtual shift register GOAD(1) ​​is electrically connected to the first initial signal line GSTV1, the signal input terminal of the first-stage shift register GOA(1) is electrically connected to the second initial signal line GSTV2, and the signal input terminal of the second-stage shift register GOA(2) is electrically connected to the signal output terminal OUTD[1] of the virtual shift register GOAD(1).

[0333] A dummy shift register can be added in front of the gate driving circuit. The signal input end of the dummy shift register GOAD(1) is electrically connected with the first initial signal line GSTV1, the signal input end of the first stage shift register GOA(1) is electrically connected with the second initial signal line GSTV2, and the signal input end of the second stage shift register GOA(2) is electrically connected with the signal output end OUTD[1] of the dummy shift register GOAD(1), so as to ensure the stability of the output.

[0334] In an example embodiment, as shown in FIG. 27B, the signal input end of the first dummy shift register GOAD(1) is electrically connected with the first initial signal line GSTV1, the signal input end of the second dummy shift register GOAD(2) is electrically connected with the second initial signal line GSTV2, the signal input end of the first stage shift register GOA(1) is electrically connected with the signal output end OUTD[1] of the first dummy shift register GOAD(1), and the signal input end of the second stage shift register GOA(2) is electrically connected with the signal output end GOAD(2) of the second dummy shift register GOAD(2).

[0335] In an example embodiment, as shown in FIG. 27B, the signal input end of the first dummy shift register GOAD(1) is electrically connected with the first initial signal line GSTV1, the signal input end of the second dummy shift register GOAD(2) is electrically connected with the second initial signal line GSTV2, the signal input end of the first stage shift register GOA(1) is electrically connected with the signal output end OUTD[1] of the first dummy shift register GOAD(1), and the signal input end of the second stage shift register GOA(2) is electrically connected with the signal output end GOAD(2) of the second dummy shift register GOAD(2).

[0336] FIG. 28 is a wiring diagram of a display device according to an example embodiment. As shown in FIG. 28, the display device can further include a high-level power supply line VGH, a low-level power supply line VGL, a light-emitting power supply line VSS, and at least one initial signal line GSTV in the non-display area.

[0337] In an example embodiment, the clock signal line group can include a first clock signal line CLK1 to a fourth clock signal line CLK4.

[0338] The normal projection of at least one of the clock signal line group, the high-level power supply line VGH, the low-level power supply line VGL, the light-emitting power supply line VSS, and the at least one initial signal line GSTV on the substrate at least partially overlaps with the normal projection of the at least one stage shift register GOA on the substrate.

[0339] At least one of the clock signal line group, the high level power supply line VGH, the low level power supply line VGL, the light emitting power supply line VSS and the at least one initial signal line GSTV can be routed above the shift register GOA, and the light emitting power supply line VSS is arranged therein. By compact narrow frame routing, a narrow frame display device can be realized.

[0340] In an example embodiment, the position of the light emitting power supply line VSS can be adjusted, but the plurality of clock signal lines of the clock signal line group cannot be separated, and the light emitting power supply line VSS is located on the side of the clock signal line group away from the display area or close to the display area.

[0341] In an example embodiment, the light emitting power supply line VSS can completely cover the routing of the shift register GOA, and the clock signal line group, the high level power supply line VGH, the low level power supply line VGL, the light emitting power supply line VSS and the at least one initial signal line GSTV, but it is necessary to ensure that the capacitance load of the plurality of clock signal lines of the clock signal line group is the same.

[0342] FIG. 29 is a schematic diagram of the routing of a display device provided by an example embodiment. As shown in FIG. 29, the display device can further include the high level power supply line VGH, the low level power supply line VGL, the light emitting power supply line VSS and the at least one initial signal line GSTV located in the non-display area.

[0343] In an example embodiment, the clock signal line group can include a first clock signal line CLK1 to a fourth clock signal line CLK4.

[0344] The orthogonal projection of at least one of the clock signal line group, the light emitting power supply line VSS and the at least one initial signal line GSTV on the substrate does not overlap with the orthogonal projection of the at least one stage of shift register on the substrate, and the orthogonal projection of the high level power supply line VGH and the low level power supply line VGL on the substrate at least partially overlaps with the orthogonal projection of the at least one stage of shift register on the substrate.

[0345] At least one of the clock signal line group, the light emitting power supply line VSS and the at least one initial signal line GSTV can be routed side by side with the shift register GOA, and the high level power supply line VGH and the low level power supply line VGL are routed above the shift register. By non-compact routing, the routing position can be flexibly adjusted.

[0346] In an example embodiment, FIG. 30 is a schematic diagram of simulation results provided by an example embodiment. As shown in FIG. 30, unipolar output of the shift register can be realized.

[0347] In an example embodiment, FIG. 31 is a schematic diagram of simulation results provided by an example embodiment, as shown in FIG. 31, a shift register multi-stage (such as 16 stages) continuous output can be achieved.

[0348] The disclosure also provides a driving method of a shift register configured to drive a shift register, which can include:

[0349] The input sub-circuit provides a signal of a signal input terminal to the first node under the control of a signal of at least one of the first clock signal terminal and the second clock signal terminal;

[0350] The control sub-circuit provides a signal of the first power supply terminal to the first node, a signal of the second power supply terminal or at least one of the first clock signal terminal and the second clock signal terminal or the first power supply terminal to the second node, and a signal of the first node to the fourth node under the control of signals of at least one of the first clock signal terminal and the second clock signal terminal, the third clock signal terminal, the second power supply terminal, and the first node;

[0351] The output sub-circuit provides a signal of the first power supply terminal or the third clock signal terminal to the signal output terminal under the control of signals of the second node and the fourth node.

[0352] The shift register is the shift register provided by any one of the foregoing embodiments, and has similar principles and effects, which will not be described here.

[0353] The drawings in the disclosure only involve structures related to the embodiments of the disclosure, and other structures can be referred to general designs.

[0354] For the sake of clarity, in the drawings used to describe the embodiments of the disclosure, the thickness and size of a layer or microstructure are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0355] Although the embodiments disclosed in the disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the disclosure, and is not intended to limit the disclosure. Any person skilled in the art of the disclosure can make any modification and change in the form and details without departing from the spirit and scope of the disclosure disclosed, but the patent protection scope of the disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A shift register comprising: The input sub-circuit, the control sub-circuit and the output sub-circuit; The input sub-circuit, the control sub-circuit and the output sub-circuit; The control sub-circuit, respectively, is electrically connected with the first node, the second node, the fourth node, the first power supply end, the second power supply end, the third clock signal end, and at least one of the first clock signal end and the second clock signal end, and is configured to provide the signal of the first power supply end to the first node, the signal of the second power supply end, or at least one of the first clock signal end and the second clock signal end, or the first power supply end to the second node, and provide the signal of the first node to the fourth node under the control of the signals of at least one of the first clock signal end and the second clock signal end, the third clock signal end, the second power supply end and the first node. The output sub-circuit, respectively, is electrically connected with the second node, the first power supply end, the fourth node, the third clock signal end and the signal output end, and is configured to provide the signal of the first power supply end or the third clock signal end to the signal output end under the control of the signals of the second node and the fourth node.

2. The shift register of claim 1, wherein, The input sub-circuit includes a first transistor; The control electrode of the first transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node.

3. The shift register of claim 1, wherein, The control sub-circuit includes a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a fourth control sub-circuit; The first control sub-circuit, respectively, is electrically connected with the first node, the second node, at least one of the first clock signal end and the second clock signal end, and is configured to adjust the signal of the second node under the control of at least one of the signals of the first node and at least one of the first clock signal end and the second clock signal end. The second control sub-circuit, respectively, is electrically connected with at least one of the first clock signal end and the second clock signal end, the second power supply end and the second node, and is configured to provide the signal of the second power supply end to the second node under the control of the signal of at least one of the first clock signal end and the second clock signal end. The third control sub-circuit, respectively, is electrically connected with the first node, the second node, the first power supply end and the third clock signal end, and is configured to provide the signal of the first power supply end to the first node under the control of the signals of the second node and the third clock signal end. The fourth control sub-circuit, respectively, is electrically connected with the first node, the fourth node and the second power supply end, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the second power supply end. The first control sub-circuit is configured to provide the signal of at least one of the first clock signal end and the second clock signal end to the second node under the control of the signal of the first node.

4. The shift register of claim 3, wherein, The first control sub-circuit includes a second transistor; 5. The shift register of claim 4, wherein, ​ The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with at least one of the first clock signal end and the second clock signal end.

6. The shift register of claim 3, wherein, The first control sub-circuit is further electrically connected with the first power supply end and is configured to provide a signal of the first power supply end to the second node under the control of signals of the first node and at least one of the first clock signal end and the second clock signal end.

7. The shift register of claim 6, wherein, The first control sub-circuit comprises a second transistor and a ninth transistor. The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the fifth node; the control electrode of the ninth transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the first power supply end.

8. The shift register of claim 6, wherein, The first control sub-circuit comprises a second transistor and a ninth transistor. The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the fifth node, and the second electrode of the second transistor is electrically connected with the first power supply end; the control electrode of the ninth transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the fifth node.

9. The shift register of claim 3, wherein, The second control sub-circuit comprises a third transistor. The control electrode of the third transistor is electrically connected with at least one of the first clock signal end and the second clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node. The third control sub-circuit comprises a sixth transistor and a seventh transistor.

10. The shift register of claim 3, wherein, The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the third node; the control electrode of the seventh transistor is electrically connected with the third clock signal end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first node. The third control sub-circuit comprises a sixth transistor and a seventh transistor.

11. The shift register of claim 3, wherein, The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first node; the control electrode of the seventh transistor is electrically connected with the third clock signal end, the first electrode of the seventh transistor is electrically connected with the first power supply end, and the second electrode of the seventh transistor is electrically connected with the third node. The fourth control sub-circuit comprises an eighth transistor.

12. The shift register of claim 3, wherein, The control electrode of the eighth transistor is electrically connected with the second power supply end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fourth node. The output sub-circuit comprises a fourth transistor, a fifth transistor, a first capacitor and a second capacitor.

13. The shift register of claim 1, wherein, The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the first power supply end, and the second electrode of the fourth transistor is electrically connected with the signal output end. The control electrode of the fifth transistor is electrically connected with the fourth node, the first electrode of the fifth transistor is electrically connected with the third node, and the second electrode of the fifth transistor is electrically connected with the signal output end. The control electrode of the fifth transistor is electrically connected with the fourth node, the first electrode of the fifth transistor is electrically connected with the signal output end, and the second electrode of the fifth transistor is electrically connected with the third clock signal end; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the first power supply end, and the second plate of the first capacitor is electrically connected with the second node; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the signal output end, and the second plate of the second capacitor is electrically connected with the fourth node.

14. A display device having a display area and a non-display area, comprising: The gate drive circuit and the clock signal line group are located in the non-display area, the gate drive circuit comprises a plurality of cascaded shift registers as claimed in any one of claims 1 to 13, and the clock signal line group comprises a first clock signal line to an Nth clock signal line, N being a positive integer greater than or equal to 3; The signal output end of the mth shift register is electrically connected with the signal input end of the m+2th shift register, 1≤m≤M-2, and M is the total number of stages of the shift registers; At least one shift register is electrically connected with three clock signal lines in the first clock signal line to the Nth clock signal line, and the first clock signal line to the Nth clock signal line are arranged in sequence along the direction close to the display area.

15. The display device of claim 14, wherein, N＝4； The first clock signal end of the 4a-3th shift register is electrically connected with the first clock signal line, the second clock signal end is electrically connected with the second clock signal line, and the third clock signal end is electrically connected with the third clock signal line; The first clock signal end of the 4a-2th shift register is electrically connected with the second clock signal line, the second clock signal end is electrically connected with the third clock signal line, and the third clock signal end is electrically connected with the fourth clock signal line; The first clock signal end of the 4a-1th shift register is electrically connected with the third clock signal line, the second clock signal end is electrically connected with the fourth clock signal line, and the third clock signal end is electrically connected with the first clock signal line; The first clock signal end of the 4ath shift register is electrically connected with the fourth clock signal line, the second clock signal end is electrically connected with the first clock signal line, and the third clock signal end is electrically connected with the second clock signal line, 1≤a≤M / 4.

16. The display device of claim 14, wherein, N＝3； The first clock signal end of the 3a-2th shift register is electrically connected with the first clock signal line, the second clock signal end is electrically connected with the second clock signal line, and the third clock signal end is electrically connected with the third clock signal line; The first clock signal end of the 3a-1th shift register is electrically connected with the second clock signal line, the second clock signal end is electrically connected with the third clock signal line, and the third clock signal end is electrically connected with the first clock signal line; The first clock signal end of the 3ath shift register is electrically connected with the third clock signal line, the second clock signal end is electrically connected with the first clock signal line, and the third clock signal end is electrically connected with the second clock signal line, 1≤b≤M / 3.

17. The display device of claim 14, wherein, The display device further comprises a high-level power supply line and a low-level power supply line located in the non-display area, the high-level power supply line is located on the side of the clock signal line group close to the display area, and the low-level power supply line is located on the side of the clock signal line group away from the display area or close to the display area. The first power supply end of the at least one stage of shift registers is electrically connected to the high-level power supply line, and the second power supply end of the at least one stage of shift registers is electrically connected to the low-level power supply line. The wiring width of the high-level power supply line is greater than or equal to the wiring width of the low-level power supply line.

18. The display device of claim 14, wherein, The display device further comprises an initial signal line. The signal input ends of the first stage of shift registers and the second stage of shift registers are electrically connected to the initial signal line.

19. The display device of claim 14, wherein, The display device further comprises a first initial signal line and a second initial signal line. The signal input end of the first stage of shift registers is electrically connected to the first initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the second initial signal line.

20. The display device of claim 14, wherein, The display device further comprises j virtual shift registers and an initial signal line, 1≤j≤2. When j=1, the signal input end of the virtual shift register and the signal input end of the first stage of shift registers are respectively electrically connected to the initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the virtual shift register. Alternatively, When j=2, the signal input end of the first virtual shift register and the signal input end of the second virtual shift register are respectively electrically connected to the initial signal line, the signal input end of the first stage of shift registers is electrically connected to the signal output end of the first virtual shift register, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the second virtual shift register.

21. The display device of claim 14, wherein, The display device further comprises j virtual shift registers and a first initial signal line and a second initial signal line, 1≤j≤2. When j=1, the signal input end of the virtual shift register is electrically connected to the first initial signal line, the signal input end of the first stage of shift registers is electrically connected to the second initial signal line, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the virtual shift register. Alternatively, When j=2, the signal input end of the first virtual shift register is electrically connected to the first initial signal line, the signal input end of the second virtual shift register is electrically connected to the second initial signal line, the signal input end of the first stage of shift registers is electrically connected to the signal output end of the first virtual shift register, and the signal input end of the second stage of shift registers is electrically connected to the signal output end of the second virtual shift register.

22. The display device of claim 14, wherein, The display device further comprises a high-level power supply line, a low-level power supply line, a light-emitting power supply line, and at least one initial signal line located in the non-display area. The normal projection of at least one of the clock signal line group, the high-level power supply line, the low-level power supply line, the light-emitting power supply line, and the at least one initial signal line on the substrate at least partially overlaps the normal projection of the at least one stage of shift registers on the substrate.

23. The display device of claim 14, wherein, The display device further comprises a high-level power supply line, a low-level power supply line, a light-emitting power supply line, and at least one initial signal line located in the non-display area. The orthogonal projection of at least one of the clock signal line group, the light-emitting power supply line, and the at least one initial signal line on the substrate does not have an overlapping area with the orthogonal projection of the at least one stage of shift register on the substrate, and the orthogonal projection of the high-level power supply line and the low-level power supply line on the substrate at least partially overlaps with the orthogonal projection of the at least one stage of shift register on the substrate.

24. A driving method of a shift register configured to drive the shift register according to any one of claims 1 to 13, the method comprising: an input sub-circuit providing a signal of a signal input end to a first node under control of a signal of at least one of a first clock signal end and a second clock signal end; a control sub-circuit providing a signal of a first power supply end to the first node, a signal of the second power supply end or at least one of the first clock signal end and the second clock signal end or the first power supply end to a second node, and a signal of the first node to a fourth node under control of signals of the first clock signal end and the second clock signal end, a third clock signal end, the second power supply end, and the first node; an output sub-circuit providing a signal of the first power supply end or the third clock signal end to a signal output end under control of signals of the second node and the fourth node.

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