Array substrate, display panel and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate, wherein the base substrate comprises a display region and a non-display region, the non-display region comprises a first non-display region located on one side of the display region, a second non-display region opposite to the first non-display region, and two third non-display regions connecting the first non-display region and the second non-display region, the first non-display region comprises a plurality of binding regions arranged in a first direction, and a binding region closest to the third non-display regions is a first binding region; a plurality of data lines, which extend in a second direction in the display region and are arranged in the first direction, the second direction intersecting the first direction; a plurality of fan-out lines, which are connected between the plurality of data lines and first binding terminals of the plurality of binding regions; a plurality of test lines, which are connected to second binding terminals of the at least one first binding region, and pass through the non-display region after crossing the fan-out lines connected to the first binding region; and a plurality of transistors, which are located in the non-display region, the plurality of transistors being connected to the plurality of test lines.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, embodiments of this disclosure provide an array substrate, including:

[0006] A substrate includes a display area and a non-display area. The non-display area includes a first non-display area, a second non-display area, and a third non-display area. The first non-display area is located on one side of the display area, the second non-display area is opposite to the first non-display area, and the third non-display area connects the first non-display area and the second non-display area. The first non-display area includes a plurality of bonding areas arranged along a first direction, and the bonding area closest to the third non-display area is the first bonding area.

[0007] Multiple data lines extend along a second direction and are arranged along the first direction in the display area, the second direction intersecting the first direction;

[0008] Multiple fan-out lines are connected between the multiple data lines and the first bonding terminals of the multiple bonding areas;

[0009] Multiple detection lines are connected to at least one second bonding terminal of the first bonding area, and after crossing the fan-out line connected to the first bonding area, they pass through the non-display area;

[0010] Multiple transistors are located in the non-display area, and the multiple transistors are connected to the multiple detection lines.

[0011] In some embodiments, in the array substrate provided in the present disclosure, a plurality of detection lines extend from the third non-display area to the second non-display area; a plurality of transistors are located in the second non-display area.

[0012] In some embodiments, the array substrate provided in this disclosure further includes a plurality of gate lines extending along the first direction and arranged along the second direction in the display area;

[0013] The fan-out line includes a first fan-out portion integrally formed with the data line, and the detection line includes a first detection portion formed on the same layer as the gate line; the orthographic projection of the first detection portion on the substrate and the orthographic projection of the first fan-out portion corresponding to the first bonding area on the substrate intersect each other.

[0014] In some embodiments, in the array substrate provided in the present disclosure, the detection line further includes a second detection part disposed on the same layer as the data line, the second detection part being connected to the first detection part, and the second detection part extending from the connection position through the third non-display area to the second non-display area.

[0015] In some embodiments, the array substrate provided in this disclosure further includes a common electrode line extending along the second direction in the first non-display area, wherein the connection position is located on the side of the common electrode line away from the corner between the first non-display area and the third non-display area.

[0016] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of shielding lines disposed on the same layer as the data lines, the shielding lines being located on at least one side of at least a portion of the second detection unit.

[0017] In some embodiments, the array substrate provided in this disclosure further includes a first electrostatic discharge structure connected to the first fan-out portion corresponding to the first bonding region, and at least one second electrostatic discharge structure connected to the first electrostatic discharge structure. The first electrostatic discharge structure extends along the first direction, the second electrostatic discharge structure extends along the second direction, and at least one second electrostatic discharge structure is located on the side of the first bonding region away from the third non-display region. The first detection portion is disposed around the second electrostatic discharge structure away from the third non-display region.

[0018] In some embodiments, in the array substrate provided in the present disclosure, the bonding area other than the first bonding area is the second bonding area;

[0019] The array substrate also includes multiple compensation lines disposed on the same layer as the gate lines, and the orthographic projection of the compensation lines on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the second bonding area on the substrate.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the extension line of the compensation line in the first direction substantially coincides with the extension line of the first detection unit in the first direction.

[0021] In some embodiments, in the array substrate provided in the present disclosure, the compensation lines corresponding to two adjacent second bonding regions are arranged approximately symmetrically.

[0022] In some embodiments, the array substrate provided in this disclosure further includes a third electrostatic discharge structure connected to the first fan-out portion corresponding to the second bonding region, and a fourth electrostatic discharge structure connected to the third electrostatic discharge structure. The third electrostatic discharge structure extends along the first direction, and the fourth electrostatic discharge structure extends along the second direction. The compensation line is wound around the third electrostatic discharge structure and the fourth electrostatic discharge structure.

[0023] In some embodiments, in the array substrate provided in the present disclosure, the third non-display area includes a gate driving circuit area, and the plurality of detection lines of the third non-display area are located between the gate driving circuit area and the display area.

[0024] In some embodiments, in the array substrate provided in the present disclosure, the gate of the transistor includes a bottom gate and / or a top gate, wherein the bottom gate is a metal electrode or a transparent electrode, and the top gate is a transparent electrode.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the orthogonal projection of the gate of the transistor on the substrate extends outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode of the transistor on the substrate.

[0026] In some embodiments, the array substrate provided in this disclosure further includes a plurality of dummy transistors located in the non-display area, wherein the dummy transistors are distributed at equal intervals between adjacent transistors.

[0027] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the gate of the dummy transistor on the substrate generally coincides with the orthographic projection of the first pole of the dummy transistor and the region enclosed by the first pole of the dummy transistor on the substrate.

[0028] In some embodiments, in the array substrate provided in the present disclosure, at least one of the gate, first electrode, and second electrode of the dummy transistor is floating.

[0029] In some embodiments, in the array substrate provided in the present disclosure, the detection line includes a first detection line, a second detection line, and a plurality of third detection lines;

[0030] The gates of the plurality of transistors are connected to the first detection line, the second terminals of the plurality of transistors are connected to the second detection line, the plurality of transistors are divided into multiple groups, and the first terminals of the transistors in different groups are connected to different third detection lines.

[0031] In some embodiments, in the array substrate provided in the present disclosure, the first detection lines corresponding to the two third non-display areas are integrally disposed in the second non-display area or are independent of each other;

[0032] The second detection lines corresponding to the two third non-display areas are either integrally arranged in the second non-display areas or are independent of each other.

[0033] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0034] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a black matrix, and the orthographic projections of the plurality of data lines, the plurality of fan-out lines, the plurality of detection lines, and the plurality of transistors on the substrate are all located within the orthographic projection of the black matrix on the substrate.

[0035] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the structure of the array substrate provided in an embodiment of this disclosure;

[0037] Figure 2 is an enlarged structural diagram of region Z1 in Figure 1;

[0038] Figure 3 is a magnified structural diagram of region Z2 in Figure 1;

[0039] Figure 4 is an enlarged structural diagram of region Z3 in Figure 1;

[0040] Figure 5 is an enlarged structural diagram of region Z4 in Figure 1;

[0041] Figure 6 is an enlarged structural diagram of region Z5 in Figure 1;

[0042] Figure 7 is an enlarged structural diagram of region Z6 in Figure 1;

[0043] Figure 8 is an enlarged structural diagram of region Z7 in Figure 2;

[0044] Figure 9 is a schematic diagram of a transistor structure provided in an embodiment of this disclosure;

[0045] Figure 10 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0046] Figure 11 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0047] Figure 12 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0048] Figure 13 is a schematic diagram of a display panel provided in an embodiment of this disclosure;

[0049] Figure 14 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0050] Figure 15 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0053] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0054] While pursuing high picture quality, related LCD products (such as TVs) are also gradually developing towards intelligence and multi-functionality. Light sensing detection is an important means to realize the intelligent design of TV products. In some embodiments, detection can be performed using an external integrated circuit of the liquid crystal cell, but this is costly, has limited detection location, and the measurement results are not accurate enough.

[0055] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides an array substrate. Figure 1 is a structural schematic diagram of the array substrate provided in this disclosure embodiment; Figure 2 is an enlarged structural schematic diagram of region Z1 in Figure 1; Figure 3 is an enlarged structural schematic diagram of region Z2 in Figure 1; Figure 4 is an enlarged structural schematic diagram of region Z3 in Figure 1; Figure 5 is an enlarged structural schematic diagram of region Z4 in Figure 1; Figure 6 is an enlarged structural schematic diagram of region Z5 in Figure 1; and Figure 7 is an enlarged structural schematic diagram of region Z6 in Figure 1. As can be seen from Figures 1 to 7, the array substrate provided in this disclosure embodiment may include:

[0056] The substrate 101 includes a display area AA and a non-display area. The non-display area includes a first non-display area BB1, a second non-display area BB2, and a third non-display area BB3. The first non-display area BB1 is located on one side of the display area AA, the second non-display area BB2 is opposite to the first non-display area BB1, and the third non-display area BB3 is connected to the first non-display area BB1 and the second non-display area BB2. The first non-display area BB1 includes a plurality of bonding areas (e.g., BD1, BD2) arranged along a first direction X. The bonding area closest to the third non-display area BB3 is the first bonding area BD1. Optionally, the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, or plastic.

[0057] Multiple data lines 102 extend along the second direction Y and are arranged along the first direction X in the display area AA, and the second direction Y intersects the first direction X. The material of the data lines 102 may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni). The data lines 102 can be a single-layer structure or a multilayer structure. For example, the data lines 102 are multilayer structures composed of titanium metal layers / aluminum metal layers / titanium metal layers.

[0058] Multiple gate lines 103 extend along the first direction X and are arranged along the second direction Y in the display area AA; the material of the gate lines 103 may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni); the gate lines 103 may be a single-layer structure or a stacked structure, for example, the gate lines 103 may be a single-layer structure composed of a molybdenum metal layer.

[0059] Multiple fan-out lines 104 are connected between multiple data lines 102 and the first bonding terminal pd1 of multiple bonding areas (e.g., BD1, BD2). Optionally, the fan-out line 104 includes a first fan-out portion 104' integrally formed with the data line 102, and a second fan-out portion 104" formed with the same layer and material as the gate line 103 and bonded to the first bonding terminal pd1. Optionally, an electrostatic discharge circuit (e.g., a first electrostatic discharge structure 110) is provided between the first fan-out portion 104' and the second fan-out portion 104".

[0060] Multiple detection lines 105 are connected to at least one second bonding terminal pd2 of a first bonding area BD1 and cross the fan-out line 104 connected to the first bonding area BD1. Optionally, the multiple detection lines 105 extend through a third non-display area BD3 to a second non-display area BD2. In some embodiments, the detection line 105 includes a first detection portion 105' on the same layer and made of the same material as the gate line 103, and a second detection portion 105" on the same layer and made of the same material as the data line 102, wherein the orthographic projection of the first detection portion 105' on the substrate 101 intersects with the orthographic projection of the first fan-out portion 104' on the substrate 101, the second detection portion 105" is connected to the first detection portion 105', and the second detection portion 105" extends from the connection position C through the third non-display area BB3 to the second non-display area BB2.

[0061] Multiple transistors 106 are located in the second non-display area BB2, and are connected to multiple detection lines 105. Optionally, the multiple detection lines 105 include a first detection line 1051, a second detection line 1052, and multiple third detection lines 1053. The gate G of all transistors 106 is electrically connected to the first detection line 1051, and the second terminal D of all transistors 106 is electrically connected to the second detection line 1052. The multiple transistors 106 can be divided into multiple groups, each group including at least one transistor 106. The first terminal S of transistors 106 in the same group can be electrically connected to the same third detection line 1053, and the first terminal S of transistors 106 in different groups is electrically connected to different third detection lines 1053. Optionally, the first detection lines 1051 corresponding to two third non-display areas BB3 are integrated into the second non-display area BB2 or are independent of each other, and the second detection lines 1052 corresponding to two third non-display areas BB3 are integrated into the second non-display area BB2 or are independent of each other. In some embodiments, when it is necessary to detect the backlight brightness, voltage can be applied to the gate G and the second electrode D of the transistor 106 through the first detection line 1051 and the second detection line 1052, respectively, and the current value generated by the backlight illumination can be obtained through the third detection line 1053, which is electrically connected to the first electrode S of the transistor 106. The greater the backlight brightness, the greater the corresponding current value. Referring to Figure 1, the detection line 105 introduced from the left third non-display area BB3 to the second non-display area BB2 and the detection line 105 introduced from the right third non-display area BB3 to the second non-display area BB2 are disconnected, that is, they are designed independently of each other. The detection line 105 corresponding to the left third non-display area BB3 and the detection line 105 corresponding to the right third non-display area BB3 can be provided with detection signals by different circuit boards.

[0062] It is worth noting that in this disclosure, multiple transistors 106 can be disposed in at least one of the four non-display areas, and the corresponding detection line 105 is also located at the position where the transistors 106 are connected. This disclosure illustrates the case of multiple transistors 106 disposed in the second non-display area BB2.

[0063] In the array substrate provided in this embodiment, the photosensitive characteristics of transistor 106 are utilized to integrate it into the display panel as a backlight detection tool, which can effectively improve detection accuracy and reduce costs. Furthermore, the area where the second fan-out portion 104” corresponding to the first bonding area BD1 is located is a patterned region (PLG). Due to dense wiring, including gate drive circuit signal lines such as clock signal lines, initial trigger signal lines (STV), high-voltage signal lines, and low-voltage signal lines near the second fan-out portion 104”, the PLG area suffers from poor heat dissipation and high temperature. The multiple detection lines 105 of this disclosure are wound around the inside of the fan-out line 104 corresponding to the first bonding area BD1, avoiding the PLG location and preventing the detection lines 105 from overheating, thus improving detection accuracy. Therefore, this disclosure does not increase the process flow or cost, but can effectively detect backlight intensity and color temperature, improving detection accuracy. This provides a new solution and approach for photosensitive product design.

[0064] It is worth noting that this disclosure illustrates the setting scheme of the detection line 105 by taking the example of having multiple binding areas. In some embodiments, there may be only one binding area, and the detection line 105 may also adopt the above-described winding setting to avoid the PLG position.

[0065] In some embodiments, as shown in FIG2 and FIG6, the array substrate provided in the present disclosure may further include a common electrode line 107 extending along the second direction Y in the first non-display area BB1. Optionally, the common electrode line 107 is disposed in the same layer and with the same material as the gate line 103. The common electrode line 107 is used to electrically connect with the common electrode of the display area AA. The connection position C between the first detection unit 105' and the second detection unit 105" is located on the side of the common electrode line 107 away from the corner between the first non-display area BB1 and the third non-display area BB3. To prevent the first detection unit 105' of the layer containing the gate line 103 from short-circuiting with the common electrode line 107. On the other hand, to prevent the second detection unit 105" of the layer containing the data line 102 from short-circuiting with the first fan-out portion 104', the connection position C is set between the first fan-out portion 104' closest to the third non-display area BB3 and the common electrode line 107. The connection position C may optionally be provided with an electrode layer of the same material and layer as the pixel electrode of the display area AA or the common electrode, for the purpose of realizing the electrical connection between the first detection unit 105' and the second detection unit 105".

[0066] When detecting backlight brightness, all third detection lines 1053 exhibit currents that vary with light intensity. Due to electromagnetic induction, the currents in each third detection line 1053 can interfere with each other, thus affecting the accuracy of light sensing. On one hand, the spacing between the third detection lines 1053 can be increased to reduce interference; however, excessive spacing would increase the bezel size, which is not conducive to narrow bezel designs. Therefore, the adjustment of the spacing between the traces is limited. On the other hand, metal traces of the same layer and material can be added between the third detection lines 106. These metal traces can be floating or simultaneously connected to ground (GND) to absorb and shield the mutual interference between the third detection lines 1053, thereby improving the accuracy of light sensing.

[0067] Based on this, as shown in Figures 2, 6, and 8, this disclosure may also include multiple shielding lines 108 disposed on the same layer and made of the same material as the data line 102. The shielding lines 108 may be floating or grounded, and the shielding lines 108 are located on at least one side of at least a portion of the second detection section 105”, for example, the shielding lines 108 are located on the left and right sides of the second detection section 105” included in the third detection line 1053. Since the electrical signals on the first detection line 1051 and the second detection line 1052 are stable and the mutual interference is small or even negligible, the shielding lines 108 may not be provided between the second detection section 105” of the first detection line 1051 and the second detection section 105” of the second detection line 1052, so as to reduce the width of the third non-display area BB3 and achieve a narrow bezel effect. Alternatively, the shielding line 108 may be a single signal line or may be formed by multiple segments, which is not limited here.

[0068] In some embodiments, as shown in FIG3, 4, and 7, the array substrate provided in this disclosure may further include multiple compensation lines 109 disposed on the same layer and made of the same material as the gate line 103. The compensation lines 109 are electrically connected to the second bonding terminal pd2 of the second bonding region BD2, and the orthographic projection of the compensation lines 109 on the substrate 101 intersects with the orthographic projection of the first fan-out portion 104' corresponding to the second bonding region BD2 on the substrate 101. For the first bonding region BD1, the overlapping area of ​​the detection line 105 and the fan-out line 104 increases the capacitive load of the data line 102 corresponding to the fan-out line 104. In order to keep the load of all data lines 102 consistent, thereby ensuring the uniformity of the display screen, it is necessary to perform overlapping capacitance compensation on the fan-out line 104 corresponding to the second bonding region BD2. This disclosure provides a compensation line 109 that intersects with the fan-out line 104 corresponding to the second binding area BD2 by leading out a compensation line 109 from the second binding terminals pd2 at both ends of the second binding area BD2. This can reduce the load difference of the data line 102 to a certain extent and improve the uniformity of the display screen.

[0069] In some embodiments, the present disclosure may provide an extension of the compensation line 109 in the first direction X, which substantially coincides with the extension of the first detection unit 105' in the first direction X. In other words, the present disclosure may provide metal traces of the same width and spacing as the detection line 105 as capacitor compensation traces by extending them from the second binding terminals pd2 at both ends of the second binding area BD2. This ensures that the load on all data lines 102 is consistent, thus guaranteeing better image uniformity. In addition, as shown in FIG4, to ensure better uniformity of the compensation capacitor and simplify the wiring design, the compensation lines 109 corresponding to two adjacent second binding areas BD2 may be arranged approximately symmetrically.

[0070] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the allowable error, it falls within the protection scope of this disclosure. Similarly, "approximately symmetrical" may be completely symmetrical, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately symmetrical" between related features meets the allowable error, it falls within the protection scope of this disclosure.

[0071] In some embodiments, as shown in Figures 2 to 7, the array substrate provided in this disclosure may further include a first fan-out portion 104' and a second fan-out portion 104" connected to the first bonding region BD1, a second electrostatic discharge structure 111 (which may be located on the left and right sides of the first bonding region BD1) connected to the first electrostatic discharge structure 110 via a first connection line CL1 (located in the layer where the gate line 103 is located), a third electrostatic discharge structure 112 connected to the first fan-out portion 104' and the second fan-out portion 104" corresponding to the second bonding region BD2, and a third electrostatic discharge structure 112 connected to the third electrostatic discharge structure via a second connection line CL2 (located in the layer where the gate line 103 is located). The fourth electrostatic discharge structure 113 connected to 112 (may be located on the left and right sides of the second bonding area BD2), the first electrostatic discharge structure 110 and the third electrostatic discharge structure 112 extend along the first direction X, the second electrostatic discharge structure 111 and the fourth electrostatic discharge structure 113 extend along the second direction Y, and the second electrostatic discharge structure 111 and the fourth electrostatic discharge structure 113 can be connected to the first common electrode bus 115 through different short-circuit rings 114 (may be located on the layer where the data line 102 is located), or the second electrostatic discharge structure 111 near the third non-display area BB3 can be directly connected to the first common electrode bus 115. The first common electrode bus 115 can be integrated with the common electrode line 107.

[0072] In some embodiments, to avoid short-circuiting the first detection unit 105' with the first electrostatic discharge structure 110 and the second electrostatic discharge structure 111, the first detection unit 105' can be provided around the second electrostatic discharge structure 111 located on the side of the first bonding area BD1 away from the third non-display area BB3 (i.e., the side closer to the second bonding area BD2). For example, the first detection unit 105 starts from the side of the first electrostatic discharge structure 110 near the display area AA, and sequentially passes through the second electrostatic discharge structure 111 (located on the side of the first bonding area BD1 away from the third non-display area BB3) near the second bonding area BD2, the side away from the display area AA, and the side close to the first bonding area BD1. After passing through one side, it connects to the second binding terminal pd2 of the first binding area BD1; similarly, to avoid short-circuiting between the compensation line 109 and the third electrostatic discharge structure 112 and the fourth electrostatic discharge structure 113, the compensation line 109 can be wound around the third electrostatic discharge structure 112 and the fourth electrostatic discharge structure 113. In some embodiments, the compensation line 109 can start from the side of the third electrostatic discharge structure 112 near the display area AA, pass sequentially to the left and right sides through the side of the fourth electrostatic discharge structure 113 near the first binding area BD1, the side away from the display area AA, and the side near the second binding area BD2, and then connect to the second binding terminal pd2 of the second binding area BD2. In some embodiments, to simplify the structural design, the first electrostatic discharge structure 110, the second electrostatic discharge structure 111, the third electrostatic discharge structure 112, and the fourth electrostatic discharge structure 113 can be made to have the same structure.

[0073] In some embodiments, as shown in FIG2 and FIG8, in the array substrate provided in the present disclosure, the third non-display area BB3 may include the gate driving circuit area GOA, and the multiple detection lines 105 of the third non-display area BB3 may be located between the gate driving circuit area GOA and the display area AA, so as to make full use of the space between the gate driving circuit area GOA and the display area AA and achieve a narrow bezel effect.

[0074] In some embodiments, in the array substrate provided in the present disclosure, Figures 9 to 12 are schematic diagrams of the structure of the transistor provided in the present disclosure. As can be seen from Figures 9 to 12, the gate G of the transistor 106 includes a bottom gate GB and / or a top gate GP. Here, the bottom gate GB refers to the gate G being disposed between the substrate 101 and the semiconductor layer (also known as the active layer), and the top gate GP refers to the gate G being disposed on the side of the semiconductor layer away from the substrate 101. In this case, for the simultaneous provision of the top gate GP and the bottom gate GB, they can be disposed separately or electrically connected, which is not limited here. The bottom gate GB is a metal electrode or a transparent electrode, and the top gate GP is a transparent electrode. The transparent electrode can be disposed in the same layer and with the same material as the pixel electrode or common electrode of the display area AA. Optionally, when the transistor 106 has both a bottom gate GB and a top gate GP, connecting the bottom gate GB and the top gate GP can reduce the number of terminals connected to the gate G. During light sensing detection, the magnitude of the current of the first electrode S affects the light sensing detection accuracy. Using both the bottom gate GB and the top gate GP as the gate G of the transistor 106 can increase the current of the first electrode S, which is beneficial for backlight detection. It should be noted that when the bottom gate GB is a metal electrode, the backlight brightness can be characterized by detecting scattered light and diffracted light within the liquid crystal cell. When the gate G is a transparent electrode, the backlight brightness can be characterized by detecting scattered light and diffracted light within the liquid crystal cell, as well as backlight incident on the transistor 106 through the substrate 101.

[0075] In some embodiments, as shown in Figures 9 to 12, the orthogonal projection of the gate G of transistor 106 onto the substrate 101 can be extended outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode S of transistor G onto the substrate 101, for example, the extension distance is greater than 0 μm. In some embodiments, the extension distance can be 5 μm, 10 μm, 15 μm, 20 μm, etc. Within this distance range, the sensitivity of the detection current of transistor 106 and the recoverability of characteristic drift can be balanced. Referring to Figure 9, optionally, in this embodiment, the gate layer and the ITO electrode layer can be fabricated using a single mask.

[0076] In some embodiments, as shown in Figures 1 and 5, the array substrate of this disclosure may further include a plurality of dummy transistors 116 located in a non-display area (e.g., a second non-display area BB2). The dummy transistors 116 are evenly spaced between adjacent transistors 106 to improve the uniformity of the alignment layer (PI) orientation environment. Optionally, as shown in Figure 5, unlike the larger gate G size of transistor 106, the orthographic projection of the gate G of the dummy transistor 116 on the substrate 101 in this disclosure may substantially coincide with the orthographic projection of the first electrode S (e.g., a U-shaped structure) of the dummy transistor 116 and the region enclosed by the first electrode S of the dummy transistor 116 (e.g., an opening region within the U-shaped structure) on the substrate 101, so that the morphology of the double-layer metal is the same everywhere, thereby better improving the uniformity of the alignment layer (PI) orientation environment. Since the dummy transistor 116 in this disclosure is not used to detect backlight brightness, it does not need to have conduction or cutoff characteristics. Based on this, at least one of the gate G, first electrode S, and second electrode D of the dummy transistor 116 in this disclosure can be floating.

[0077] In some embodiments, transistor 106 and dummy transistor 116 in this disclosure can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), without limitation herein. In some embodiments, transistor 106 and dummy transistor 116 can be P-type transistors or N-type transistors. The first terminal S can be the source and the second terminal D can be the drain, or the first terminal S can be the drain and the second terminal D can be the source, without limitation herein. The active layer of transistor 106 and dummy transistor 116 can be one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene.

[0078] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG2, 4 and 8, may further include a second common electrode bus 117 extending along a first direction X. The second common electrode bus 117 may be integrally disposed with the common electrode line 107 and the second common electrode bus 117. Other essential components of the array substrate are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0079] Based on the same inventive concept, this disclosure provides a display panel. Figures 13 and 14 are schematic diagrams of the structure of the display panel provided in this disclosure. As shown in Figures 13 and 14, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle by which this display panel solves the problem is similar to the principle by which the array substrate solves the problem, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be described again.

[0080] In some embodiments, as shown in FIG13, the opposing substrate 002 includes a black matrix 201, and the orthographic projections of multiple data lines 102, multiple gate lines 103, multiple fan-out lines 104, multiple detection lines 105, and multiple transistors 106 on the substrate 101 are all located within the orthographic projection of the black matrix 201 on the substrate 101, in order to avoid the reflection of metal lines from affecting the display effect.

[0081] In some embodiments, as shown in FIG14, the display panel provided in this disclosure may further include a liquid crystal layer 003 disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0082] Based on the same inventive concept, this disclosure provides a display device. Figure 15 is a schematic diagram of the structure of the display device provided in this disclosure. As shown in Figure 15, the display device of this disclosure includes the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0083] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0084] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0085] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0086] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate includes a display area and a non-display area. The non-display area includes a first non-display area, a second non-display area, and a third non-display area. The first non-display area is located on one side of the display area, the second non-display area is opposite to the first non-display area, and the third non-display area connects the first non-display area and the second non-display area. The first non-display area includes a plurality of bonding areas arranged along a first direction, and the bonding area closest to the third non-display area is the first bonding area. Multiple data lines extend along a second direction and are arranged along the first direction in the display area, the second direction intersecting the first direction; Multiple fan-out lines are connected between the multiple data lines and the first bonding terminals of the multiple bonding areas; Multiple detection lines are connected to at least one second bonding terminal of the first bonding area, and after crossing the fan-out line connected to the first bonding area, they pass through the non-display area; Multiple transistors are located in the non-display area, and the multiple transistors are connected to the multiple detection lines.

2. The array substrate as claimed in claim 1, wherein, Multiple detection lines extend from the third non-display area to the second non-display area; multiple transistors are located in the second non-display area.

3. The array substrate as described in claim 1 or 2, wherein, It also includes a plurality of grid lines extending along the first direction and arranged along the second direction in the display area; The fan-out line includes a first fan-out portion integrally formed with the data line, and the detection line includes a first detection portion formed on the same layer as the gate line; the orthographic projection of the first detection portion on the substrate and the orthographic projection of the first fan-out portion corresponding to the first bonding area on the substrate intersect each other.

4. The array substrate as claimed in claim 3, wherein, The detection line also includes a second detection section disposed on the same layer as the data line. The second detection section is connected to the first detection section, and the second detection section extends from the connection position through the third non-display area to the second non-display area.

5. The array substrate as claimed in claim 4, wherein, It also includes a common electrode line extending along the second direction in the first non-display area, the connection point being located on the side of the common electrode line away from the corner between the first non-display area and the third non-display area.

6. The array substrate as claimed in claim 4 or 5, wherein, It also includes multiple shielding lines disposed on the same layer as the data line, the shielding lines being located on at least one side of at least a portion of the second detection unit.

7. The array substrate according to any one of claims 3 to 6, wherein, It also includes a first electrostatic discharge structure connected to the first fan-out portion corresponding to the first bonding area, and at least one second electrostatic discharge structure connected to the first electrostatic discharge structure. The first electrostatic discharge structure extends along the first direction, the second electrostatic discharge structure extends along the second direction, and at least one second electrostatic discharge structure is located on the side of the first bonding area away from the third non-display area; the first detection unit is arranged around the second electrostatic discharge structure away from the third non-display area.

8. The array substrate according to any one of claims 3 to 7, wherein, The binding area outside the first binding area is the second binding area; The array substrate also includes multiple compensation lines disposed on the same layer as the gate lines, and the orthographic projection of the compensation lines on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the second bonding area on the substrate.

9. The array substrate as claimed in claim 8, wherein, The extension of the compensation line in the first direction roughly coincides with the extension of the first detection unit in the first direction.

10. The array substrate as claimed in claim 8 or 9, wherein, The compensation lines corresponding to two adjacent second binding areas are set approximately symmetrically.

11. The array substrate according to any one of claims 8 to 10, wherein, It also includes a third electrostatic discharge structure connected to the first fan-out portion corresponding to the second binding area, and a fourth electrostatic discharge structure connected to the third electrostatic discharge structure, wherein the third electrostatic discharge structure extends along the first direction and the fourth electrostatic discharge structure extends along the second direction; The compensation wire is wound around the third electrostatic discharge structure and the fourth electrostatic discharge structure.

12. The array substrate according to any one of claims 1 to 11, wherein, The third non-display area includes a gate driving circuit area, and the plurality of detection lines of the third non-display area are located between the gate driving circuit area and the display area.

13. The array substrate according to any one of claims 1 to 12, wherein, The gate of the transistor includes a bottom gate and / or a top gate, wherein the bottom gate is a metal electrode or a transparent electrode, and the top gate is a transparent electrode.

14. The array substrate according to any one of claims 1 to 13, wherein, The orthogonal projection of the gate of the transistor on the substrate extends outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode of the transistor on the substrate.

15. The array substrate according to any one of claims 1 to 14, wherein, It also includes a plurality of dummy transistors located in the non-display area, the dummy transistors being distributed at equal intervals between adjacent transistors.

16. The array substrate as claimed in claim 15, wherein, The orthographic projection of the gate of the dummy transistor on the substrate roughly coincides with the orthographic projection of the first electrode of the dummy transistor and the region enclosed by the first electrode of the dummy transistor on the substrate.

17. The array substrate as claimed in claim 15 or 16, wherein, The dummy transistor has at least one of its gate, first electrode, and second electrode floating.

18. The array substrate according to any one of claims 1 to 17, wherein, The detection lines include a first detection line, a second detection line, and multiple third detection lines; The gates of the plurality of transistors are connected to the first detection line, the second terminals of the plurality of transistors are connected to the second detection line, the plurality of transistors are divided into multiple groups, and the first terminals of the transistors in different groups are connected to different third detection lines.

19. The array substrate as claimed in claim 18, wherein, The first detection lines corresponding to the two third non-display areas are either integrally disposed in the second non-display area or are independent of each other; The second detection lines corresponding to the two third non-display areas are integrated in the second non-display area. The settings can be independent of each other.

20. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 19.

21. The display panel as claimed in claim 20, wherein, The opposing substrate includes a black matrix, and the orthographic projections of the multiple data lines, the multiple fan-out lines, the multiple detection lines, and the multiple transistors on the substrate are all located within the orthographic projection of the black matrix on the substrate.

22. A display device, wherein, It includes the display panel as described in claim 20 or 21, and a backlight module located on the light-incident side of the display panel.

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