Driving backplane and manufacturing method therefor, display panel, and display device

Abstract

The present invention relates to a driving backplane and a manufacturing method therefor, a display panel, and a display device. The driving backplane is configured to drive a pixel layer to emit light. The driving backplane comprises a substrate and a plurality of driving units arranged in an array; each driving unit comprises a switching transistor and a driving transistor. At least one driving unit comprises a first metal layer, a first insulating layer, an active semiconductor layer, a second insulating layer and a second metal layer which are sequentially arranged in the thickness direction of the driving unit. The active semiconductor layer is provided with a source and a drain which are located on two opposite sides in the thickness direction. The driving unit further comprises a first via hole and a second via hole which are located on two opposite sides in the thickness direction of the active semiconductor layer, the first via hole runs through the first insulating layer and is communicated with the first metal layer and the source, and the second via hole runs through the second insulating layer and is communicated with the second metal layer and the drain. The first via hole and the second via hole are located on two opposite sides of the active semiconductor layer, thereby avoiding a bridging connection, reducing pixel area occupation, and improving the resolution of the display device.

Description

Drive backplane and its manufacturing method, display panel, display device Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving backplate and its manufacturing method, a display panel, and a display device. Background Technology

[0002] Light-emitting devices, especially organic light-emitting diodes (OLEDs), are increasingly being used in high-performance displays as current-driven light-emitting devices. Among them, active matrix organic light-emitting displays (AMOLEDs) have become widespread in mobile smart terminal applications.

[0003] In AMOLED, thin-film transistors (TFTs) are used to construct the pixel circuitry, providing the necessary current to the OLED device. Low-temperature polycrystalline silicon (LTPS) TFTs or oxide TFTs are commonly used. Regardless of the TFT technology employed, all emitting pixels require at least several basic driving power supplies and signal supply connections: power supply potential connection, light-emitting device cathode connection, scan signal connection (used to control pixel drive selection), and data signal connection (used to provide the voltage or current signal corresponding to the pixel brightness).

[0004] In traditional high-resolution screens, the small pixel area and unreasonable pixel layout design limit the improvement of screen resolution and display effect. Summary of the Invention

[0005] The present invention provides a driving backplate and its manufacturing method, a display panel, and a display device to solve the problem that unreasonable pixel layout spatial arrangement design in high-resolution screens limits the improvement of resolution and display effect.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a driving backplane for driving the light emission of a pixel layer, characterized in that the driving backplane includes a substrate and a plurality of driving units arranged in an array, the driving unit including transistors, at least one of the driving units including a first metal layer, a first insulating layer, an active semiconductor layer, a second insulating layer and a second metal layer arranged sequentially along its thickness direction, the active semiconductor layer having a source and a drain located on opposite sides of its thickness direction, the driving unit further including a first via and a second via located on opposite sides of the active semiconductor layer in the thickness direction, the first via penetrating the first insulating layer and connecting the first metal layer and the source, the second via penetrating the second insulating layer and connecting the second metal layer and the drain.

[0008] In one embodiment, the orthographic projection of the first metal layer on the substrate at least partially coincides with the orthographic projection of the second via on the substrate; and / or, the orthographic projection of the second metal layer on the substrate at least partially coincides with the orthographic projection of the first via on the substrate.

[0009] In one embodiment, the first metal layer is a VDD line layer, the second metal layer is an anode metal layer, the first via connects the VDD line layer and the source, and the second via connects the anode metal layer and the drain.

[0010] In one embodiment, the driving unit further includes a VDD line layer and an anode metal layer, wherein the first metal layer is electrically connected to the VDD line layer to electrically connect the source to the VDD line layer; and the second metal layer is electrically connected to the anode metal layer to electrically connect the drain to the anode metal layer.

[0011] In one embodiment, the first via extends along the thickness direction of the drive backplate to penetrate the first insulating layer, and the second via extends along the thickness direction of the drive backplate to penetrate the second insulating layer.

[0012] In a second aspect, the present invention provides a method for fabricating a driving backplate, the driving backplate being used to drive the emission of a pixel layer, the fabrication method comprising:

[0013] A first metal layer is formed on one side of the substrate;

[0014] A first insulating layer is formed on the side of the first metal layer away from the substrate;

[0015] A first via is formed that penetrates the first insulating layer and connects to the first metal layer;

[0016] An active semiconductor layer is formed on the side of the first insulating layer away from the substrate, and the first via connects the first metal layer and the source of the active semiconductor layer.

[0017] A second insulating layer is formed on the side of the active semiconductor layer away from the substrate;

[0018] A second via is formed that penetrates the second insulating layer, and the second via is connected to the drain of the active semiconductor layer;

[0019] A second metal layer is formed on the side of the second insulating layer away from the substrate, and the second via connects the drain of the active semiconductor layer and the second metal layer.

[0020] In one embodiment, the first metal layer is a VDD line layer, the second metal layer is an anode metal layer, and the fabrication method further includes forming a gate layer between the VDD line layer and the active semiconductor layer;

[0021] The specific steps for forming the first insulating layer are as follows: forming a first inorganic insulating layer between the first metal layer and the gate layer, and forming a second inorganic insulating layer between the gate layer and the active semiconductor layer; the first inorganic insulating layer and the second inorganic insulating layer constitute the first insulating layer.

[0022] In one embodiment, the preparation method further includes:

[0023] A VDD line layer is formed that is electrically connected to the first metal layer, so that the VDD line layer is electrically connected to the drain.

[0024] An anode metal layer is formed that is electrically connected to the second metal layer, so that the anode metal layer is electrically connected to the drain.

[0025] Thirdly, the present invention provides a display panel, including the driving backplate described above or a driving backplate prepared by the method described above.

[0026] Fourthly, the present invention provides a display device, including the driving backplate described above or a driving backplate prepared by the method described above.

[0027] As can be seen from the above technical solutions, the embodiments of the present invention have at least the following advantages and positive effects:

[0028] In an embodiment of the present invention, at least one driving unit of the driving backplane includes a first metal layer, a first insulating layer, an active semiconductor layer, a second insulating layer, and a second metal layer arranged sequentially along its thickness direction. A first via and a second via are located on opposite sides of the active semiconductor layer in the thickness direction. The first via connects the source of the first metal layer and the active semiconductor layer, and the second via connects the drain of the second metal layer and the active semiconductor layer to achieve electrical connection. This optimizes the circuit layout, avoids bridge connections, reduces pixel area occupation, improves integration, and thus improves the resolution of the display device. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0030] Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention;

[0031] Figure 2 is a cross-sectional view of the driving transistor in the driving unit of the driving backplane shown in Figure 1;

[0032] Figure 3 is a 2T1C driving circuit diagram according to an embodiment of the present invention;

[0033] Figure 4 is a flowchart of the fabrication process of a drive backplate according to an embodiment of the present invention;

[0034] Figures 5 and 6 are schematic diagrams of the structure formed during the fabrication process of the drive backplate according to an embodiment of the present invention.

[0035] The annotations in the attached figures are explained as follows:

[0036] 1. Display panel; 10. Driver backplane; 120. Driver unit; 121. First metal layer; 121a. VDD line layer; 122. First insulating layer; 122a. First inorganic insulating layer; 122b. Second inorganic insulating layer; 123. Active semiconductor layer; 1231. Source; 1232. Drain; 124. Second insulating layer; 125. Second metal layer; 125a. Anode metal layer; 126. First via; 127. Second via; 128. Gate layer; 20. Pixel layer. Detailed Implementation

[0037] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the descriptions and illustrations herein are for illustrative purposes only and not intended to limit the present invention.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0040] Referring to Figures 1 and 2, in a first aspect, this application provides a driving backplane 10 for driving the light emission of a pixel layer 20. The driving backplane 10 is generally used on a display panel 1. The driving backplane 10 includes a substrate and a plurality of driving units 120 arranged in an array. Each driving unit 120 includes a transistor. At least one driving unit 120 includes a first metal layer 121, a first insulating layer 122, an active semiconductor layer 123, a second insulating layer 124, and a second metal layer 125 arranged sequentially along its thickness direction. Specifically, the active semiconductor layer 123 has a source electrode 1231 and a drain electrode 1232 located on opposite sides of its thickness direction. The driving unit 120 also includes a first via 126 and a second via 127 located on opposite sides of the thickness direction of the active semiconductor layer 123. The first via 126 penetrates the first insulating layer 122 and connects the first metal layer 121 and the source electrode 1231. The second via 127 penetrates the second insulating layer 124 and connects the second metal layer 125 and the drain electrode 1232. The active semiconductor layer 123 is the core component of the transistor in the driving unit 120. It can be understood that the transistor here can be a driving transistor or a switching transistor, and this application does not limit it.

[0041] In existing OLED display devices, transistors are generally incorporated. Each transistor has at least three terminals: a source (S), a drain (D), and a gate (G). The gate is typically made of a conductive material. The drain (S) and source (D) are formed on the active semiconductor layer (G). The transistor also typically has vias in the insulating layer to allow the drain (S) and source (D) to form ohmic contacts with other conductive layers for electrical connection. When vias connecting the drain (S) or source (D) are connected to conductive layers of different types, transition vias or even bridging connections (bridging connections refer to vias containing at least two channels with different extension directions) are required, thus occupying pixel area.

[0042] In the driving unit 120 of this application, the first via 126 and the second via 127 are located on opposite sides of the thickness direction of the active semiconductor layer 123. The first via 126 connects the first metal layer 121 and the source 1231, and the second via 127 connects the second metal layer 125 and the drain 1232 to achieve electrical connection. This optimizes the circuit layout and avoids bridge connections, thereby reducing the pixel area occupied, improving the integration, and improving the resolution of the display device.

[0043] The orthographic projection of the first metal layer 121 on the substrate at least partially overlaps with the orthographic projection of the second via 127 on the substrate, and / or, the orthographic projection of the second metal layer 125 on the substrate at least partially overlaps with the orthographic projection of the first via 126 on the substrate. That is, the orthographic projections of the first metal layer 121, which is in ohmic contact with the source 1231, and the second via 127 on the substrate overlap, as do the orthographic projections of the second metal layer 125, which is in ohmic contact with the drain 1232, and the first via 126 on the substrate. This overlap makes the display device structure more compact and facilitates improved resolution. Furthermore, the orthographic projection of the first via 126 on the substrate is covered by the orthographic projection of the second metal layer 125 on the substrate, and the orthographic projection of the second via 127 on the substrate is covered by the orthographic projection of the second metal layer 121 on the substrate, to achieve optimal spatial layout.

[0044] In one embodiment, the driving backplane 10 uses the P-type 2T1C circuit shown in Figure 3. Figure 2 is a schematic diagram of the driving transistor in this circuit. It can be understood that in other embodiments, an N-type 2T1C driving circuit can also be provided, or more transistors and capacitors can be provided. The specific circuit layout can be set as needed. As long as it includes the layout design and wiring design scheme of this embodiment, it should be within the protection scope of this application.

[0045] Specifically, the first metal layer 121 is the VDD circuit layer 121a, the second metal layer 125 is the anode metal layer 125a, the first via 126 connects the VDD circuit layer 121a and the source 1231, and the second via 127 connects the anode metal layer 125a and the drain 1232. In other words, the first via 126 directly connects to the VDD circuit layer 121a without any intermediate conductive layer, and the second via 127 directly connects to the anode metal layer 125a without any intermediate conductive layer.

[0046] In another embodiment, both the first metal layer 121 and the second metal layer 125 are intermediate conductive layers. The driving unit 120 further includes a VDD line layer 121a and an anode metal layer 125a. The first metal layer 121, as an intermediate conductive layer, is electrically connected to the VDD line layer 121a to connect the source 1231 to the VDD line layer 121a. The second metal layer 125, as an intermediate conductive layer, is electrically connected to the anode metal layer 125a to connect the drain 1232 to the anode metal layer 125a. The first metal layer 121 can be one or more intermediate conductive layers, and the second metal layer 125 can be one or more intermediate conductive layers.

[0047] In summary, the connection between the first via 126 and the second via 127 and the target conductive layer in this application includes two cases. One case involves the source 1231 being directly connected to the target conductive layer (such as VDD line layer 121a or other conductive layers) through the first via 126, and the drain 1232 being directly connected to the target conductive layer (such as anode metal layer 125a or other conductive layers) through the second via 127. The other case involves the source 1231 being connected to the target conductive layer (such as VDD line layer 121a or other conductive layers) through one or more intermediate conductive layers, and the drain 1232 being connected to the target conductive layer (such as anode metal layer 125a or other conductive layers) through one or more intermediate conductive layers.

[0048] For example, the substrate is made of glass or carbon-based material. The first metal layer 121, VDD line layer 121a, second metal layer 125, anode metal layer 125a, and gate layer 128 can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0049] Furthermore, the first via 126 extends along the thickness direction of the driving backplate 10 to penetrate the first insulating layer 122, and the second via 127 extends along the thickness direction of the driving backplate 10 to penetrate the second insulating layer 124. The extension of the first via 126 and the second via 127 along the thickness direction of the driving backplate 10 can reduce the projected area on the substrate, reduce the occupied pixel area, and reduce the processing difficulty.

[0050] Referring to Figure 4, this application provides a method for fabricating a driving backplate 10, which is used to drive the light emission of the pixel layer 20. The fabrication method includes:

[0051] Step S110: Form a first metal layer on one side of the substrate.

[0052] Step S120: A first insulating layer is formed on the side of the first metal layer away from the substrate.

[0053] Step S130: Form a first via through the first insulating layer, the first via connecting to the first metal layer.

[0054] Step S140: An active semiconductor layer is formed on the side of the first insulating layer away from the substrate, and a first via connects the source of the first metal layer and the active semiconductor layer.

[0055] Step S150: Form a second insulating layer on the side of the active semiconductor layer away from the substrate;

[0056] Step S160: Form a second via through the second insulating layer, the second via connecting to the drain of the active semiconductor layer;

[0057] Step S170: A second metal layer is formed on the side of the second insulating layer away from the substrate, and a second via connects the drain of the active semiconductor layer and the second metal layer.

[0058] Referring again to Figure 2, in one embodiment, the first metal layer 121 is a VDD line layer 121a, and the second metal layer 125 is an anode metal layer 125a. The fabrication method further includes forming a gate layer 128 between the VDD line layer 121a and the active semiconductor layer 123. Specifically, the step of forming the first insulating layer 122 involves forming a first inorganic insulating layer 122a between the first metal layer 121 and the gate layer 128, and forming a second inorganic insulating layer 122b between the gate layer 128 and the active semiconductor layer 123. The first inorganic insulating layer 122a and the second inorganic insulating layer 122b constitute the first insulating layer 122.

[0059] In another embodiment, the preparation method further includes:

[0060] A circuit layer electrically connected to the first metal layer is formed so that the VDD circuit layer is electrically connected to the source.

[0061] An anode metal layer is formed that is electrically connected to the second metal layer, so that the anode metal layer is electrically connected to the drain.

[0062] In summary, one end of the first via 126 is connected to the source 1231 of the active semiconductor layer 123, and the other end can be directly connected to the target conductive layer (such as the VDD line layer 121a), or it can be electrically connected to the target conductive layer through the first metal layer 121. The first metal layer 121, which serves as an intermediate conductive layer, can be one or more layers. Furthermore, the arrangement of the second via 127 is similar to that of the first via 126, and will not be described in detail here.

[0063] The following describes, in conjunction with a specific process flow, an exemplary method for fabricating the drive backplane 10 of the circuit shown in Figure 3. This fabrication method exemplarily describes the fabrication of the drive transistor in the 2T1C circuit, and the fabrication process flow for the switching transistor and other components is not limited. It should be noted that any existing fabrication process can be used to form the structure of the drive unit 120. In the context of "patterning" throughout this application, when the material of "patterning" is inorganic or metallic, "patterning" includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; when the material of "patterning" is organic, "patterning" includes processes such as mask exposure and development. Furthermore, this application can also employ existing fabrication processes such as evaporation, deposition, coating, and plating.

[0064] Referring to Figures 2, 5, and 6, Figure 2 is a cross-sectional view of the driving unit 120 along the thickness direction, and Figures 5 and 6 are schematic diagrams of the orthographic projection of the driving unit 120 onto the substrate obtained in each step of the fabrication process. The specific fabrication process is as follows:

[0065] A metal layer is formed on one side of the substrate, and the VDD line layer 121a and other necessary signal lines are patterned thereon. The structural schematic diagram of the drive unit 120 at this time is shown in Figure 5a.

[0066] A first inorganic insulating layer 122a is formed on the side of the VDD line layer 121a away from the substrate.

[0067] A metal layer is formed on the side of the first inorganic insulating layer 122a away from the substrate, and a gate layer 128 is patterned thereon. At this time, the driving unit 120 is shown in Figure 5b.

[0068] A second inorganic insulating layer 122b is formed on the side of the gate layer 128 away from the substrate, and the second inorganic insulating layer 122b and the first inorganic insulating layer 122a constitute the first insulating layer 122.

[0069] A first via 126 is formed by sequentially penetrating the second inorganic insulating layer 122b and the first inorganic insulating layer 122a along the thickness direction of the driving unit 120. The first via 126 connects the VDD line layer 121a and the source 1231 of the active semiconductor layer 123. The driving unit 120 is shown in Figure 5c at this time.

[0070] An active semiconductor layer 123 is formed on the side of the second inorganic insulating layer 122b away from the substrate, and a channel region for driving transistors is patterned thereon. At this time, the driving unit 120 is shown in Figure 5d.

[0071] The source and drain regions of the driving transistor are patterned in the active semiconductor layer 123. The source 1231 is connected to the VDD line layer 121a through the first via 126. At this time, the driving unit 120 is shown in Figure 6a.

[0072] A second insulating layer 124 is formed on the side of the active semiconductor layer 123 away from the substrate.

[0073] A second via 127 is formed that passes through the second insulating layer 124 along the thickness direction of the driving unit 120. The second via 127 is connected to the drain 1232 of the active semiconductor layer 123. At this time, the driving unit is shown in Figure 6b.

[0074] A metal layer is formed on the side of the second insulating layer 124 away from the substrate, and an anode metal layer 125a is patterned therein. A second via 127 connects the anode metal layer 125a and the drain 1232. The drive unit 120 is shown in Figure 6c at this time.

[0075] Referring again to FIG1, in a second aspect, this application provides a display surface 1, the display panel 1 including the aforementioned driving backplate 10 or the driving backplate 10 prepared by the aforementioned method, and other components of the display panel 1 can be any existing components.

[0076] In a third aspect, this application provides a display device, which includes the aforementioned driving backplate 10 or the driving backplate 10 prepared by the aforementioned method, and other components of the display device can be any existing components.

[0077] Although the invention has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A drive backplane for driving light emission of a pixel layer, characterized by, The driving backplane comprises a substrate and a plurality of driving units arranged in an array, the driving units comprising transistors, at least one of the driving units comprising a first metal layer, a first insulating layer, an active semiconductor layer, a second insulating layer and a second metal layer arranged in sequence along the thickness direction of the driving unit, the active semiconductor layer having a source and a drain located at opposite sides along the thickness direction of the active semiconductor layer, the driving unit further comprising a first via and a second via located at opposite sides along the thickness direction of the active semiconductor layer, the first via penetrating the first insulating layer and connecting the first metal layer and the source, and the second via penetrating the second insulating layer and connecting the second metal layer and the drain.

2. The drive backplane of claim 1, wherein, The orthographic projection of the first metal layer on the substrate at least partially overlaps the orthographic projection of the second via on the substrate. And / or, the orthographic projection of the second metal layer on the substrate at least partially overlaps the orthographic projection of the first via on the substrate.

3. The drive backplane of claim 1, wherein, The first metal layer is a VDD wiring layer, the second metal layer is an anode metal layer, the first via connects the VDD wiring layer and the source, and the second via connects the anode metal layer and the drain.

4. The drive backplane of claim 1, wherein, The driving unit further comprises a VDD wiring layer and an anode metal layer, the first metal layer is electrically connected with the VDD wiring layer so that the source is electrically connected with the VDD wiring layer, and the second metal layer is electrically connected with the anode metal layer so that the drain is electrically connected with the anode metal layer.

5. The drive backplane of claim 1, wherein, The first via extends to penetrate the first insulating layer along the thickness direction of the driving backplane, and the second via extends to penetrate the second insulating layer along the thickness direction of the driving backplane.

6. A method for manufacturing a drive backplane for driving light emission of a pixel layer, characterized by, The preparation method comprises: forming a first metal layer on one side of a substrate; forming a first insulating layer on the side of the first metal layer away from the substrate; forming a first via penetrating the first insulating layer, the first via connecting the first metal layer; forming an active semiconductor layer on the side of the first insulating layer away from the substrate, the first via connecting the first metal layer and the source of the active semiconductor layer; forming a second insulating layer on the side of the active semiconductor layer away from the substrate; forming a second via penetrating the second insulating layer, the second via connecting the drain of the active semiconductor layer; forming a second metal layer on the side of the second insulating layer away from the substrate, the second via connecting the drain of the active semiconductor layer and the second metal layer.

7. The preparation method according to claim 6, characterized in that, The first metal layer is a VDD wiring layer, and the second metal layer is an anode metal layer, and the preparation method further comprises forming a gate layer between the VDD wiring layer and the active semiconductor layer; The step of forming the first insulating layer specifically comprises: forming a first inorganic insulating layer between the first metal layer and the gate layer, and forming a second inorganic insulating layer between the gate layer and the active semiconductor layer; the first inorganic insulating layer and the second inorganic insulating layer constitute the first insulating layer.

8. The preparation method according to claim 6, characterized in that, The preparation method further comprises: forming a VDD line layer electrically connected with the first metal layer, so that the VDD line layer is electrically connected with the source electrode; forming an anode metal layer electrically connected with the second metal layer, so that the anode metal layer is electrically connected with the drain electrode.

9. A display panel, characterized by, The drive backplane prepared by the method for preparing the drive backplane according to any one of claims 6 to 8.

10. A display device, characterized by The drive backplane prepared by the method for preparing the drive backplane according to any one of claims 6 to 8.

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