Driving backplate and manufacturing method therefor, display panel, and display device

Abstract

The present invention relates to a driving backplate and a manufacturing method therefor, a display panel, and a display device. The driving backplate is used for driving a pixel layer to emit light; the driving backplate comprises a substrate and a plurality of driving units; each driving unit comprises a first transistor and a second transistor; the first transistor comprises a first active semiconductor layer and a first trench region; the second transistor comprises a second active semiconductor layer and a second trench region; in at least one driving unit, the orthographic projection of the first active semiconductor layer on the substrate at least partially overlaps with the orthographic projection of the second active semiconductor layer on the substrate, and the direction of extension of the first trench region is parallel to the direction of extension of the second trench region. Due to the overlapping design of the first active semiconductor layer and the second active semiconductor layer, the layout space is saved, and the resolution of a display device is improved. Furthermore, the direction of extension of the first trench region is parallel to the direction of extension of the second trench region, so that the layout space is saved, and the resolution of the display device is improved.

Description

Drive backplane and its manufacturing method, display panel, display device

[0001] Technical Field

[0002] This invention relates to the field of display technology, and in particular to a driving backplate and its manufacturing method, a display panel, and a display device.

[0003] Background Technology

[0004] Light-emitting devices, especially organic light-emitting diodes (OLEDs), are increasingly being used in high-performance displays as current-driven light-emitting devices. Among them, active matrix organic light-emitting displays (AMOLEDs) have become widespread in mobile smart terminal applications.

[0005] In AMOLED, thin-film transistors (TFTs) are used to construct the pixel circuitry, providing the necessary current to the OLED device. AMOLEDs can be classified into three main categories based on their driving type: digital, current-driven, and voltage-driven. Unlike LCDs, which typically require only one TFT, AMOLEDs, as active-matrix driven light-emitting devices, generally require two or more TFTs within each pixel. At high resolutions, the pixel area of ​​the display device is limited, and the difficulty in accommodating TFTs within this limited area severely restricts the realization of high-resolution display pixels.

[0006] Summary of the Invention

[0007] The present invention provides a driving backplane and its preparation method, a display panel, and a display device to solve the problem that the pixel area of ​​display devices is limited and the TFT is difficult to accommodate within a limited area, which seriously limits the pixel realization of high-resolution display devices.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] In a first aspect, this application provides a driving backplane for driving the light emission of a pixel layer. The driving backplane includes a substrate and a plurality of driving units. Each driving unit includes a first transistor and a second transistor. The first transistor includes a first active semiconductor layer and a first channel region, and the second transistor includes a second active semiconductor layer and a second channel region.

[0010] The first active semiconductor layer and the second active semiconductor layer are located in different layers of the driving backplane. In at least one driving unit, the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap. The first channel region is formed in the first active semiconductor layer, the second channel region is formed in the second active semiconductor layer, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

[0011] In one embodiment, the orthographic projection of the first channel region on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

[0012] In one embodiment, the region where the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate coincide is defined as the overlapping region. The area of ​​the overlapping region is greater than half the area of ​​the orthographic projection of the first channel region on the substrate and greater than half the area of ​​the orthographic projection of the second channel region on the substrate.

[0013] In one embodiment, the first transistor further includes a first gate layer, the second transistor further includes a second gate layer, and at least one of the driving units is configured such that:

[0014] A first active semiconductor layer is located on one side of the substrate, and the first channel region is formed in the first active semiconductor layer;

[0015] The first gate layer is located on the side of the first active semiconductor layer away from the substrate;

[0016] The VDD line layer is located on the side of the first gate layer away from the substrate;

[0017] The DATA line layer and the second gate layer are both located on the side of the VDD line layer away from the substrate, and the DATA line layer and the second gate layer have the same depth in the thickness direction of the driving backplane.

[0018] The second active semiconductor layer is located on the side of the DATA line layer away from the substrate, and the second channel region is formed in the second active semiconductor layer;

[0019] An anode metal layer is located on the side of the second active semiconductor layer away from the substrate.

[0020] In one embodiment, the drive unit further includes:

[0021] A first insulating layer is located between the substrate and the first gate layer;

[0022] The second insulating layer is located between the first gate layer and the VDD line layer;

[0023] The third insulating layer is located between the VDD line layer and the DATA line layer;

[0024] A fourth insulating layer is located between the DATA line layer and the second active semiconductor layer;

[0025] The fifth insulating layer is located between the second active semiconductor layer and the anode metal layer;

[0026] The first via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The first via connects the DATA line layer and the first active semiconductor layer.

[0027] The second via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The second via connects the second gate layer and the first active semiconductor layer.

[0028] The third via is formed by sequentially passing through the fourth insulating layer and the third insulating layer along the thickness direction of the drive backplane. The third via connects the VDD line layer and the second active semiconductor layer.

[0029] The fourth via extends through the fifth insulating layer along the thickness direction of the drive backplate, and the third via connects the second active semiconductor layer and the anode metal layer;

[0030] Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the fourth via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0031] In a second aspect, this application provides a method for fabricating a driving backplate, the driving backplate being used to drive the light emission of a pixel layer, the fabrication method comprising simultaneously forming a plurality of driving units on a substrate to form the driving backplate; wherein, in the step of forming the driving units, at least one of the driving units comprises:

[0032] A first active semiconductor layer is formed on one side of the substrate;

[0033] A first channel region is formed in the first active semiconductor layer;

[0034] A first gate layer is formed on the side of the first active semiconductor layer away from the substrate;

[0035] A VDD line layer is formed on the side of the first gate layer away from the substrate;

[0036] A DATA line layer and a second gate layer are formed on the side of the VDD line layer away from the substrate, wherein the DATA line layer and the second gate layer have the same depth in the thickness direction of the driving backplane.

[0037] A second active semiconductor layer is formed on the side of the DATA line layer away from the substrate;

[0038] A second channel region is formed in the second active semiconductor layer;

[0039] An anode metal layer is formed on the side of the second active semiconductor layer away from the substrate;

[0040] Wherein, the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

[0041] In one embodiment, the preparation method further includes:

[0042] A first insulating layer is formed between the substrate and the first active semiconductor layer;

[0043] A second insulating layer is formed between the second active semiconductor layer and the VDD line layer;

[0044] A third insulating layer is formed between the VDD line layer and the DATA line layer;

[0045] A fourth insulating layer is formed between the DATA line layer and the second active semiconductor layer;

[0046] A fifth insulating layer is formed between the second active semiconductor layer and the anode metal layer.

[0047] In one embodiment, the preparation method further includes:

[0048] After the third insulating layer is formed

[0049] A first via is formed that sequentially penetrates the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplane; the first via is used to connect the first active semiconductor layer and the DATA line layer;

[0050] A second via is formed by sequentially penetrating the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplate. The second via is used to connect the first active semiconductor layer and the second gate layer.

[0051] After the fifth insulating layer is formed, a third via is formed that passes through the fifth insulating layer along the thickness direction of the drive back plate. The third via is used to connect the second active semiconductor layer and the anode metal layer.

[0052] Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0053] In a third aspect, this application provides a display panel, including the aforementioned driving backplate or a driving backplate prepared by the aforementioned method.

[0054] In a fourth aspect, this application provides a display device, including the aforementioned driving backplane or a driving backplane prepared by the aforementioned method.

[0055] As can be seen from the above technical solutions, the embodiments of the present invention have at least the following advantages and positive effects:

[0056] In the driving backplane of this embodiment, at least one driving unit features an overlapping design of the first active semiconductor layer in the first transistor and the active semiconductor layer in the second transistor, saving layout space and improving the resolution of the display device. Furthermore, the extension direction of the first channel region formed in the first active semiconductor layer is parallel to the extension direction of the second channel region formed in the second active semiconductor layer, maximizing the utilization of the layout area and further improving the resolution of the display device.

[0057] Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0059] Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention;

[0060] Figure 2 is a 2T1C driving circuit diagram according to an embodiment of the present invention;

[0061] Figure 3 is a cross-sectional view of the driving unit along the thickness direction according to an embodiment of the present invention;

[0062] Figure 4 is a flowchart of a method for preparing a drive backplate according to an embodiment of the present invention;

[0063] Figures 5 to 7 are schematic projections of the drive unit during the fabrication process of the drive backplate according to an embodiment of the present invention.

[0064] The annotations in the attached figures are explained as follows:

[0065] 1. Display panel; 10. Driver backplane; 100. Driver unit; 110. First transistor; 111. Substrate; 112. First active semiconductor layer; 113. First gate layer; 114. VDD line layer; 115. DATA line layer; 116. Second gate layer; 117. Second active semiconductor layer; 118. Anode metal layer; 120. Second transistor; 130. Insulating layer; 131. First insulating layer; 132. Second insulating layer; 133. Third insulating layer; 134. Fourth insulating layer; 135. Fifth insulating layer; 141. First via; 142. Second via; 143. Third via; 144. Fourth via; 20. Pixel layer; 30. Driver chip.

[0066] Detailed Implementation

[0067] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the descriptions and illustrations herein are for illustrative purposes only and not intended to limit the present invention.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0070] Referring to Figures 1 to 3, in a first aspect, the present invention provides a driving backplane 10 for driving the light emission of a pixel layer 20. A display panel 1 includes the driving backplane 10, a pixel layer 20, and a driving chip 30. The pixel layer 20 emits light, and the driving backplane 10 drives the pixel layer 20 to emit light. The driving backplane 10 includes a substrate 111 and a plurality of driving units 100. Each driving unit 100 includes a first transistor 110 and a second transistor 120. The first transistor 110 includes a first active semiconductor layer 112 and a first channel region. The second transistor 120 includes a second active semiconductor layer 117 and a second channel region. The first active semiconductor layer 112 and the second active semiconductor layer 117 are located on different layers of the driving backplane 10.

[0071] In at least one driving unit 100, the orthographic projection of the first active semiconductor layer 112 on the substrate 111 and the orthographic projection of the second active semiconductor layer 117 on the substrate 111 at least partially overlap, that is, the first active semiconductor layer 112 and the second active semiconductor layer 117 are designed to overlap. A first channel region is formed on the first active semiconductor layer 112, and a second channel region is formed on the second active semiconductor layer 117, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

[0072] In AMOLED (Active Matrix Organic Light Emitting Diode), the driving unit 100 of the driving pixel unit is provided with two or more transistors. When the resolution is high, the pixel area of ​​the display device is limited, and it is difficult to accommodate transistors in a limited area, which severely limits the pixel realization of high-resolution display devices.

[0073] To address the limitation in pixel implementation, the driving backplane 10 of this application features an overlapping design in at least one driving unit 100, where the first active semiconductor layer 112 in the first transistor 110 and the second active semiconductor layer 117 in the second transistor 120. This design saves layout space and improves the resolution of the display device. Furthermore, the extension direction of the first channel region formed in the first active semiconductor layer 112 is parallel to the extension direction of the second channel region formed in the second active semiconductor layer 117, maximizing the utilization of the layout area and further improving the resolution of the display device.

[0074] Specifically, the area where the orthographic projection of the first active semiconductor layer 112 on the substrate 111 coincides with the orthographic projection of the second active semiconductor layer 117 on the substrate 111 is defined as the overlapping area. The area of ​​the overlapping area is greater than half the area of ​​the orthographic projection of the first channel region on the substrate 111 and greater than half the area of ​​the orthographic projection of the second channel region on the substrate 111.

[0075] Furthermore, the orthographic projection of the first channel region on the substrate 111 at least partially overlaps with the orthographic projection of the second channel region on the substrate 111, so as to optimize the layout and improve the resolution of the display device.

[0076] In one embodiment, the driving unit 100 includes a plurality of transistors, and more than half (including half) of the transistors are designed in a stacked manner to save layout space. It should be noted that, in this embodiment, "stacked" refers to a structural arrangement in which the orthographic projection of the first transistor 110 on the substrate 111 coincides with the orthographic projection of the second transistor 120 on the substrate 111 and the channel region extends in parallel directions, as well as a transistor arrangement scheme that can be obtained through reasonable derivation.

[0077] Figure 2 shows a 2T1C type driving circuit, and Figure 3 illustrates a driving backplane 10 designed based on the 2T1C driving circuit. 2T1C refers to two transistors and one capacitor. It should be noted that the driving circuit shown in Figure 3 is a P-type 2T1C circuit. In other embodiments, an N-type 2T1C driving circuit can also be set, or more transistors and capacitors can be set. The specific layout can be set as needed. As long as it includes the layout design and wiring design scheme of this application, it should be within the protection scope of this application.

[0078] Specifically, the first transistor 110 further includes a first gate layer 113, and the second transistor 120 further includes a second gate layer 116. The structure of at least one driving unit 100 is configured to include a substrate 111, a first active semiconductor layer 112, a first gate layer 113, a DATA line layer 115, a second gate layer 116, a second active semiconductor layer 117, and an anode metal layer 118, sequentially disposed along its thickness direction. The DATA line layer 115 and the second gate layer 116 have the same depth along the thickness direction of the driving unit 100. A first channel region is formed in the first active semiconductor layer 112, and a second channel region is formed in the second active semiconductor layer 117.

[0079] Furthermore, the orthographic projections of the first active semiconductor layer 112, the first gate layer 113, the second active semiconductor layer 117, and the second gate layer 116 onto the substrate 111 at least partially overlap. That is, at least a portion of the first active semiconductor layer 112, the first gate layer 113, the second active semiconductor layer 117, and the second gate layer 116 are designed in a stacked configuration, further saving layout space.

[0080] The substrate 111 is made of glass or carbon. The DATA line layer 115, the first gate layer 113, the VDD line layer 114, the second gate layer 116, and the anode metal layer 118 can be made of metal, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0081] In the driving unit 100, an insulating layer 130 is provided between every two adjacent layers. Specifically, a first insulating layer 131 is provided between the substrate 111 and the first gate layer 113; a second insulating layer 132 is provided between the first gate layer 113 and the VDD line layer 114; a third insulating layer 133 is provided between the VDD line layer 114 and the DATA line layer 115; a fourth insulating layer 134 is provided between the DATA line layer 115 and the second active semiconductor layer 117; and a fifth insulating layer 135 is provided between the second active semiconductor layer 117 and the anode metal layer 118. The first insulating layer 131, the second insulating layer 132, the third insulating layer 133, and the fourth insulating layer 134 are all composed of inorganic materials, specifically silicon dioxide, etc. The fifth insulating layer 135 is an organic insulating layer.

[0082] The driving unit 100 is further provided with a first via 141, a second via 142, a third via 143, and a fourth via 144. The first via 141 passes through the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 sequentially along the thickness direction of the driving backplate 10, and connects the DATA line layer 115 and the first active semiconductor layer 112. The second via 142 passes through the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 sequentially along the thickness direction of the driving backplate 10, and connects the second gate layer 116 and the first active semiconductor layer 112. The third via 143 passes through the fourth insulating layer 134 and the third insulating layer 133 sequentially along the thickness direction of the driving backplate 10, and connects the VDD line layer 114 and the second active semiconductor layer 117. The fourth via 144 passes through the fifth insulating layer 135 along the thickness direction of the drive backplate 10, and the fourth via 144 connects the second active semiconductor layer 117 and the anode metal layer 118.

[0083] The orthographic projections of the first via 141, the second via 142, the third via 143, the fourth via 144, the first active semiconductor layer 112, and the second active semiconductor layer 117 on the substrate 111 at least partially overlap. In other words, at least one of the first via 141, the second via 142, the third via 143, and the fourth via 144 is stacked with either the first active semiconductor layer 112 or the second active semiconductor layer 117, saving layout space.

[0084] Referring to FIG4, in a second aspect, this application provides a method for fabricating a driving backplate 10, which is used to drive the light emission of a pixel layer 20. The fabrication method includes simultaneously forming a plurality of driving units 100 on a substrate 111 to form the driving backplate 10. In the step of forming the driving units 100, the step of forming at least one driving unit 100 includes:

[0085] Step S110: Form a first active semiconductor layer on one side of the substrate.

[0086] Step S120: Form a first channel region in the first active semiconductor layer.

[0087] Step S130: A first gate layer is formed on the side of the first active semiconductor layer away from the substrate.

[0088] Step S140: Form a VDD line layer on the side of the first gate layer away from the substrate.

[0089] Step S150: A DATA line layer and a second gate layer are formed on the side of the VDD line layer away from the substrate. The DATA line layer and the second gate layer have the same depth in the thickness direction of the driving backplane.

[0090] Step S160: Form a second active semiconductor layer on the side of the DATA line layer away from the substrate.

[0091] Step S170: Form a second channel region in the second active semiconductor layer.

[0092] Step S180: An anode metal layer is formed on the side of the second active semiconductor layer away from the substrate.

[0093] Wherein, the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

[0094] Specifically, the preparation method further includes the step of forming an insulating layer 130, which is as follows:

[0095] Step S210: Form a first insulating layer between the substrate and the first gate layer.

[0096] Step S220: A second insulating layer is formed between the first gate layer and the VDD line layer.

[0097] Step S230: Form a third insulating layer between the VDD line layer and the second active semiconductor layer.

[0098] Step S240: A fourth insulating layer is formed between the DATA line layer and the second active semiconductor layer.

[0099] Step S250: A fifth insulating layer is formed between the second active semiconductor layer and the anode metal layer.

[0100] An insulating layer 130 is provided between different layers of the drive unit 100 to prevent short circuits caused by contact between metal layers.

[0101] Furthermore, the preparation method also includes a step of forming vias, specifically:

[0102] Step S235: After forming the third insulating layer, a first via is formed that sequentially passes through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive backplane. The first via is used to connect the first active semiconductor layer and the DATA line layer.

[0103] Step S236: Form a second via through which the third insulating layer, the second insulating layer and the first insulating layer are sequentially passed in the thickness direction of the driving backplate. The second via is used to connect the first active semiconductor layer and the second gate layer.

[0104] Step S245: After forming the fourth insulating layer, a third via is formed that passes through the fourth insulating layer and the third insulating layer sequentially along the thickness direction of the drive backplane. The third via is used to connect the VDD line layer and the second active semiconductor layer.

[0105] Step S255: After forming the fifth insulating layer, a fourth via is formed that penetrates the fifth insulating layer along the thickness direction of the drive backplate. The fourth via is used to connect the second active semiconductor layer and the anode metal layer.

[0106] Among them, the orthographic projections of the first via 141, the second via 142, the third via 143, the fourth via 144, the first active semiconductor layer 112, and the second active semiconductor layer 117 on the substrate 111 at least partially overlap.

[0107] The following describes the fabrication method of the drive backplane 10 by way of example, with reference to a specific process flow. It should be noted that any fabrication process in the prior art can be used when forming the structure of the drive unit 100. In the context of "patterning" throughout this application, when the material of "patterning" is inorganic or metallic, "patterning" includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. When the material of "patterning" is organic, "patterning" includes processes such as mask exposure and development. In addition, this application can also use existing fabrication processes such as evaporation, deposition, coating, and plating.

[0108] Figure 3 is a cross-sectional view of the driving unit 100 along the thickness direction, and Figures 5 to 7 are schematic diagrams of the orthographic projection of the driving unit 100 obtained in each step of the fabrication process onto the substrate 111. The specific fabrication process is as follows:

[0109] A first active semiconductor layer 112 is formed on one side of the substrate 111, and a first channel region is patterned thereon. At this time, the driving unit 100 is shown in Figure 5a.

[0110] A first insulating layer 131 is formed on the side of the first active semiconductor layer 112 away from the substrate 111.

[0111] A metal layer is formed on the side of the first insulating layer 131 away from the substrate 111, and after patterning, a first gate layer 113 is formed. At this time, the driving unit 100 is shown in Figure 5b.

[0112] A second insulating layer 132 is formed on the side of the first gate layer 113 away from the substrate 111.

[0113] A VDD line layer 114 is formed on the side of the second insulating layer 132 away from the substrate 111, and the driving unit 100 is shown in Figure 5c.

[0114] A third insulating layer 133 is formed on the side of the VDD line layer 114 away from the substrate 111.

[0115] A first via 141 is patterned to sequentially penetrate the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 along the thickness direction of the drive backplane 10. The first via 141 is used to connect the first active semiconductor layer 112 and the DATA line layer 115. A second via 142 is patterned to sequentially penetrate the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 along the thickness direction of the drive backplane 10. The second via 142 is used to connect the first active semiconductor layer 112 and the second gate layer 116. At this time, the drive unit 100 is as shown in Figure 6a.

[0116] A metal layer is formed on the side of the third insulating layer 133 away from the substrate 111, and a DATA line layer 115 and a second gate layer 116 are patterned therein, wherein a storage capacitor is formed in the overlapping area of ​​the second gate layer 116 and the VDD line layer 114. At this time, the driving unit 100 is as shown in FIG6b.

[0117] A fourth insulating layer 134 is formed on the side of the DATA line layer 115 and the second gate layer 116 away from the substrate 111.

[0118] A third via 143 is formed by sequentially passing through the fourth insulating layer 134 and the third insulating layer 133 along the thickness direction of the drive backplate 10. The third via 143 is used to connect the VDD circuit layer and the second active semiconductor layer 117. At this time, the drive unit 100 is as shown in Figure 6c.

[0119] A second active semiconductor layer 117 is formed on the side of the fourth insulating layer 134 away from the substrate 111, and a second channel region is patterned thereon. At this time, the driving unit 100 is as shown in FIG7a.

[0120] A fifth insulating layer 135 is formed on the side of the second active semiconductor layer 117 away from the substrate 111.

[0121] A fourth via 144 is patterned to pass through the fifth insulating layer 135. The fourth via 144 is used to connect the second active semiconductor layer 117 and the anode metal layer 118. At this time, the driving unit 100 is shown in Figure 7b.

[0122] A metal layer is formed on the side of the fifth insulating layer 135 away from the substrate 111, and an anode metal layer 118 is patterned. The anode metal layer 118 is electrically connected to the second active semiconductor layer 117 through the fourth via 144. At this time, the driving unit 100 is as shown in FIG7c.

[0123] In a third aspect, this application provides a display panel including the aforementioned driving backplate 10 or the driving backplate 10 prepared by the aforementioned method, and other components of the display panel 1 can be any existing components.

[0124] In a fourth aspect, this application provides a display device, which includes the aforementioned driving backplate 10 or a driving backplate 10 formed by the aforementioned manufacturing direction, and other components of the display device can be any existing components.

[0125] Although the invention has been described with reference to several typical embodiments, it should be understood that the terminology used is illustrative and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A driving backplate for driving the light emission of a pixel layer, characterized in that, The driving backplane includes a substrate and a plurality of driving units. Each driving unit includes a first transistor and a second transistor. The first transistor includes a first active semiconductor layer and a first channel region, and the second transistor includes a second active semiconductor layer and a second channel region. The first active semiconductor layer and the second active semiconductor layer are located in different layers of the driving backplane. In at least one driving unit, the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap. The first channel region is formed in the first active semiconductor layer, the second channel region is formed in the second active semiconductor layer, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

2. The drive backplane according to claim 1, characterized in that, The orthographic projection of the first channel region on the substrate and the orthographic projection of the second channel region on the substrate at least partially overlap.

3. The drive backplane according to claim 1, characterized in that, The region where the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate coincide is defined as the overlapping region. The area of ​​the overlapping region is greater than half the area of ​​the orthographic projection of the first channel region on the substrate and greater than half the area of ​​the orthographic projection of the second channel region on the substrate.

4. The drive backplane according to claim 1, characterized in that, The first transistor further includes a first gate layer, the second transistor further includes a second gate layer, and at least one of the driving units is configured such that: A first active semiconductor layer is located on one side of the substrate, and the first channel region is formed in the first active semiconductor layer; The first gate layer is located on the side of the first active semiconductor layer away from the substrate; The VDD line layer is located on the side of the first gate layer away from the substrate; The DATA line layer and the second gate layer are both located on the side of the VDD line layer away from the substrate, and the DATA line layer and the second gate layer have the same depth in the thickness direction of the driving backplane. The second active semiconductor layer is located on the side of the DATA line layer away from the substrate, and the second channel region is formed in the second active semiconductor layer; An anode metal layer is located on the side of the second active semiconductor layer away from the substrate.

5. The drive backplane according to claim 4, characterized in that, The drive unit further includes: A first insulating layer is located between the substrate and the first gate layer; The second insulating layer is located between the first gate layer and the VDD line layer; The third insulating layer is located between the VDD line layer and the DATA line layer; A fourth insulating layer is located between the DATA line layer and the second active semiconductor layer; The fifth insulating layer is located between the second active semiconductor layer and the anode metal layer; The first via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The first via connects the DATA line layer and the first active semiconductor layer. The second via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The second via connects the second gate layer and the first active semiconductor layer. The third via is formed by sequentially passing through the fourth insulating layer and the third insulating layer along the thickness direction of the drive backplane. The third via connects the VDD line layer and the second active semiconductor layer. The fourth via extends through the fifth insulating layer along the thickness direction of the drive backplate, and the third via connects the second active semiconductor layer and the anode metal layer; Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the fourth via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

6. A method for fabricating a driving backplate, wherein the driving backplate is used to drive the light emission of a pixel layer, characterized in that, The fabrication method includes simultaneously forming multiple driving units on a substrate to form a driving backplate; In the step of forming the drive unit, at least one of the steps of forming the drive unit includes: A first active semiconductor layer is formed on one side of the substrate; A first channel region is formed in the first active semiconductor layer; A first gate layer is formed on the side of the first active semiconductor layer away from the substrate; A VDD line layer is formed on the side of the first gate layer away from the substrate; A DATA line layer and a second gate layer are formed on the side of the VDD line layer away from the substrate, wherein the DATA line layer and the second gate layer have the same depth in the thickness direction of the driving backplane. A second active semiconductor layer is formed on the side of the DATA line layer away from the substrate; A second channel region is formed in the second active semiconductor layer; An anode metal layer is formed on the side of the second active semiconductor layer away from the substrate; Wherein, the orthographic projection of the first active semiconductor layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap, and the extension direction of the first channel region is parallel to the extension direction of the second channel region.

7. The preparation method according to claim 6, characterized in that, The preparation method further includes: A first insulating layer is formed between the substrate and the first active semiconductor layer; A second insulating layer is formed between the second active semiconductor layer and the VDD line layer; A third insulating layer is formed between the VDD line layer and the DATA line layer; A fourth insulating layer is formed between the DATA line layer and the second active semiconductor layer; A fifth insulating layer is formed between the second active semiconductor layer and the anode metal layer.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: After the third insulating layer is formed A first via is formed that sequentially penetrates the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplane; the first via is used to connect the first active semiconductor layer and the DATA line layer; A second via is formed by sequentially penetrating the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplate. The second via is used to connect the first active semiconductor layer and the second gate layer. After the fifth insulating layer is formed, a third via is formed that passes through the fifth insulating layer along the thickness direction of the drive back plate. The third via is used to connect the second active semiconductor layer and the anode metal layer. Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

9. A display panel, characterized in that, This includes the drive backplate as described in any one of claims 1 to 5 or the drive backplate prepared by the method described in any one of claims 6 to 8.

10. A display device, characterized in that, This includes the drive backplate as described in any one of claims 1 to 5 or the drive backplate prepared by the method described in any one of claims 6 to 8.

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