Driving backplane and preparation method therefor, display panel, and display device

Abstract

The present invention relates to a driving backplane and a preparation method therefor, a display panel, and a display device. The driving backplane is used for driving the light emission of a pixel layer. The driving backplane comprises a plurality of driving units and a lead unit. The plurality of driving units are arranged in columns along a first direction and in rows along a second direction. The first direction is perpendicular to the second direction. The lead unit comprises DATA lines, VDD power lines, a VSS power line, and a SCAN signal line which are connected to the driving units. The extension direction of the DATA lines is parallel to the first direction. The extension direction of the VDD power lines, the extension direction of the VSS power line, and the extension direction of the SCAN signal line are parallel to the second direction. The driving backplane is only provided with the DATA lines in the first direction, and the VDD power lines are only arranged in the second direction, so that pixel layout space design optimization is achieved, and the display resolution of a display panel is improved. In addition, the VSS power line and the SCAN signal line which are used for providing a low-potential power supply are also arranged in the second direction, thereby further optimizing the pixel layout space design.

Description

Drive backplane and its manufacturing method, display panel, display device Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving backplate and its manufacturing method, a display panel, and a display device. Background Technology

[0002] Light-emitting devices, especially organic light-emitting diodes (OLEDs) as current-driven light-emitting devices, are increasingly being used in high-performance displays. Among them, active matrix organic light-emitting displays (AMOLEDs) have become widespread in mobile smart terminal applications.

[0003] In AMOLED, thin-film transistors (TFTs) are used to construct the pixel circuitry, providing the necessary current to the OLED device. Low-temperature polycrystalline silicon (LTPS) TFTs or oxide TFTs are commonly used. Regardless of the TFT technology employed, all emitting pixels require at least several basic driving power supplies and signal supply connections: power supply potential connection, light-emitting device cathode connection, scan signal connection (used to control pixel drive selection), and data signal connection (used to provide the voltage or current signal corresponding to the pixel brightness).

[0004] In traditional high-resolution screens, the pixel realization of high-resolution display devices is limited by unreasonable pixel driving circuit layout space design and lead design.

[0005] Summary of the Invention

[0006] The present invention provides a driving backplate and its manufacturing method, a display panel, and a display device to solve the problem that unreasonable pixel layout spatial arrangement and lead wire design in high-resolution screens limit the improvement of resolution and display effect.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] A driving backplane for driving the emission of a pixel layer, the driving backplane comprising:

[0009] Multiple driving units are arranged in a column along a first direction and in a row along a second direction, wherein the first direction is perpendicular to the second direction;

[0010] The lead unit includes a DATA data line, a VDD power line, a VSS power line, and a SCAN signal line connected to the drive unit. The DATA data line extends along the first direction, and the VDD power line, the VSS power line, and the SCAN signal line all extend along the second direction.

[0011] In one embodiment, the drive unit includes:

[0012] substrate;

[0013] The first active semiconductor layer is located on one side of the substrate;

[0014] The first gate layer is located on the side of the first active semiconductor layer away from the substrate;

[0015] The VDD line layer is located on the side of the first gate layer away from the substrate;

[0016] The DATA line layer and the second gate layer are both located on the side of the VDD line layer away from the substrate, and the DATA line layer and the second gate layer are on the same layer of the driving backplane;

[0017] The second active semiconductor layer is located on the side of the DATA line layer away from the substrate;

[0018] An anode metal layer is located on the side of the second active semiconductor layer away from the substrate;

[0019] The VDD line layers of the drive units located in the same row are electrically connected to form the VDD power line, and the DATA line layers of the drive units located in the same column are electrically connected to form the DATA data line.

[0020] In one embodiment, the orthographic projections of the DATA line layer on the substrate, the first active semiconductor layer on the substrate, the VDD line layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0021] In one embodiment, two driving units adjacent to each other in the first direction in the driving backplane are defined as a first driving unit and a second driving unit, and the second active semiconductor layer of the first driving unit and the second active semiconductor layer of the second driving unit are staggered in the thickness direction of the driving backplane.

[0022] In one embodiment, the drive unit further includes:

[0023] A first insulating layer is located between the substrate and the first gate layer;

[0024] The second insulating layer is located between the first gate layer and the VDD line layer;

[0025] The third insulating layer is located between the VDD line layer and the DATA line layer;

[0026] A fourth insulating layer is located between the DATA line layer and the second active semiconductor layer;

[0027] The fifth insulating layer is located between the second active semiconductor layer and the anode metal layer;

[0028] The first via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The first via connects the DATA line layer and the first active semiconductor layer.

[0029] The second via is formed by sequentially passing through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive back plate. The second via connects the second gate layer and the first active semiconductor layer.

[0030] The third via is formed by sequentially passing through the fourth insulating layer and the third insulating layer along the thickness direction of the drive backplane. The third via connects the VDD line layer and the second active semiconductor layer.

[0031] The fourth via extends through the fifth insulating layer along the thickness direction of the drive backplate, and the third via connects the second active semiconductor layer and the anode metal layer;

[0032] Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the fourth via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0033] A method for fabricating a driving backplate, the driving backplate being used to drive the emission of a pixel layer, the fabrication method comprising forming a driving unit and forming a driving array:

[0034] Forming a driving unit:

[0035] A first active semiconductor layer is formed on one side of the substrate;

[0036] A first gate layer is formed on the side of the first active semiconductor layer away from the substrate;

[0037] A VDD line layer is formed on the side of the first gate layer away from the substrate;

[0038] A DATA line layer and a second gate layer are formed on the side of the VDD line layer away from the substrate, and the DATA line layer and the second gate layer are on the same layer of the driving backplane.

[0039] A second active semiconductor layer is formed on the side of the DATA line layer away from the substrate;

[0040] An anode metal layer is formed on the side of the second active semiconductor layer away from the substrate;

[0041] Forming a driving array:

[0042] In the step of forming a drive unit, multiple drive units are formed simultaneously and the multiple drive units are arranged in a column along a first direction and in a row along a second direction, wherein the first direction is perpendicular to the second direction;

[0043] In this configuration, the VDD line layers of multiple drive units in the same row are electrically connected to form a VDD power line, and the DATA line layers of multiple drive units in the same column are electrically connected to form a DATA data line. The extension direction of the DATA data line is parallel to a first direction, and the extension direction of the VDD power line is parallel to a second direction. The first direction is perpendicular to the second direction.

[0044] In one embodiment, the preparation method further includes:

[0045] A first insulating layer is formed between the substrate and the first gate layer;

[0046] A second insulating layer is formed between the first gate layer and the VDD line layer;

[0047] A third insulating layer is formed between the VDD line layer and the DATA line layer;

[0048] A fourth insulating layer is formed between the DATA line layer and the second active semiconductor layer;

[0049] A fifth insulating layer is formed between the second active semiconductor layer and the anode metal layer.

[0050] In one embodiment, the preparation method further includes:

[0051] After the third insulating layer is formed

[0052] A first via is formed that sequentially penetrates the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplane; the first via is used to connect the first active semiconductor layer and the DATA line layer;

[0053] A second via is formed by sequentially penetrating the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the drive backplate. The second via is used to connect the first active semiconductor layer and the second gate layer.

[0054] After the fourth insulating layer is formed, a third via is formed that passes through the fourth insulating layer and the third insulating layer sequentially along the thickness direction of the drive backplane. The third via is used to connect the VDD line layer and the second active semiconductor layer.

[0055] After the fifth insulating layer is formed, a third via is formed that passes through the fifth insulating layer along the thickness direction of the drive back plate. The third via is used to connect the second active semiconductor layer and the anode metal layer.

[0056] Wherein, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the fourth via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0057] A display panel, characterized in that it includes the driving backplate described above or the driving backplate prepared by the above method.

[0058] A display device, characterized in that it includes the driving backplate described above or the driving backplate prepared by the above method.

[0059] As can be seen from the above technical solutions, the embodiments of the present invention have at least the following advantages and positive effects:

[0060] This application optimizes the layout and wiring arrangement of the driver backplane, ensuring that only DATA lines are placed in the first direction and VDD power lines are placed only in the second direction. This optimizes the pixel layout design space and improves the display panel's resolution. Furthermore, the VSS power line and SCAN signal line, used to provide low-potential power, are also placed in the second direction, further optimizing the pixel layout space design.

[0061] Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0063] Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention;

[0064] Figure 2 is a schematic diagram of the drive backplate shown in Figure 1;

[0065] Figure 3 is a 2T1C driving circuit diagram according to an embodiment of the present invention;

[0066] Figure 4 is a cross-sectional view of the drive backplate shown in Figure 2 along the thickness direction.

[0067] Figure 5 is a cross-sectional view of two adjacent drive units in the same column according to another embodiment of the present invention;

[0068] Figure 6 is a flowchart of the preparation method of the driving backplate according to an embodiment of the present invention;

[0069] Figure 7 is a partial flowchart of the preparation method shown in Figure 6;

[0070] Figures 8 to 10 are schematic diagrams of the structure formed during the fabrication process of the drive backplate according to an embodiment of the present invention.

[0071] The annotations in the attached figures are explained as follows:

[0072] 1. Display panel;

[0073] 10. Driver backplane; 20. Pixel layer; 30. Driver chip;

[0074] 110, Driving unit; 110a, First driving unit; 110b, Second driving unit; 111, Substrate; 112, First active semiconductor layer; 113, First gate layer; 114, VDD line layer; 115, DATA line layer; 116, Second gate layer; 117, Second active semiconductor layer; 118, Anode metal layer; 121, DATA data line; 122, VDD power line; 130, Insulating layer; 131, First insulating layer; 132, Second insulating layer; 133, Third insulating layer; 134, Fourth insulating layer; 135, Fifth insulating layer; 141, First via; 142, Second via; 143, Third via; 210, Pixel unit. Detailed Implementation

[0075] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the descriptions and illustrations herein are for illustrative purposes only and not intended to limit the present invention.

[0076] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0077] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0078] Referring to Figures 1 and 2, in a first aspect, the present invention provides a driving backplate 10 disposed on a display panel 1. The display panel 1 includes the driving backplate 10, a pixel layer 20, and a driving chip 30. The pixel layer 20 is used for emitting light, and the driving backplate 10 is used to drive the pixel layer 20 to emit light. The driving backplate 10 includes a plurality of driving units 110, which are arranged in a column along a first direction and in a row along a second direction, the first direction being perpendicular to the second direction. The pixel layer 20 includes a plurality of pixel units 210. The resolution of the display panel 1 is determined by the number of pixel units 210 per unit area; the more pixel units 210 per unit area, the higher the resolution of the display panel 1. The number of pixel units 210 is also affected by the number of driving units 110 in the driving backplate 10.

[0079] Specifically, the drive backplane 10 also includes a lead unit, which includes a DATA line 121, a VDD power line 122, a VSS power line, and a SCAN signal line connected to the drive unit 110. The DATA line 121 extends along a first direction, while the VDD power line 122, the VSS power line, and the SCAN signal line all extend along a second direction.

[0080] It should be noted that in this application, "first direction" refers to the direction perpendicular to the extension direction of the driver chip 30, and "second direction" refers to the direction perpendicular to the "first direction". For example, in Figure 1, the first direction refers to the vertical direction and the second direction refers to the horizontal direction. In other embodiments, the first direction may refer to the horizontal direction and the second direction may refer to the vertical direction. The specific direction is affected by the setting position of the driver chip 30.

[0081] Regardless of the driving circuit used, the emission of light from a pixel unit 210 requires at least a power supply and signal supply connections: a power supply connection, a cathode connection for the light-emitting device, a scan signal connection, and a data signal connection. The scan signal connection controls the driving and selection of the pixel unit, while the data signal connection provides the voltage or current required for pixel brightness. In existing manufacturing processes, the cathode of the light-emitting device is generally formed last, with all or part of the pixel units 210 sharing a cathode connection. Furthermore, these connections are separated from other light-emitting device electrodes by light-emitting devices, and there is no spatial competition with other connection electrode layers in the layout. However, the other three types of electrical connection signals must be connected to each pixel unit 210, and these three types of electrical connection signal lines create spatial competition in the layout, affecting the improvement of pixel resolution. For high-resolution screens, the pixel area is small, and the horizontal dimension of the pixel unit 210 is 1 / 3 or 1 / 2 of its vertical dimension (determined by the pixel arrangement direction), thus making vertical wiring space more limited. When the resolution increases to a certain level, the horizontal dimension cannot meet the wiring space requirements, limiting the realization of high-resolution devices.

[0082] To address this issue, this application designs the wiring layout of the drive circuit so that only the DATA line 121 is arranged in the first direction (i.e., the vertical direction in Figure 1), and the VDD power line 122 is arranged only along the second direction (the horizontal direction in Figure 1), thereby optimizing the pixel layout design space and providing the display resolution of the display panel 1. Furthermore, the VSS power line and the SCAN signal line used to provide low-potential power are also arranged in the second direction.

[0083] Referring to Figures 3 and 4, Figure 3 illustrates the drive backplane 1010 of the 2T1C type drive circuit. It should be noted that 2T1C refers to two transistors and one capacitor. The drive circuit shown in Figure 3 is a P-type 2T1C circuit. In other embodiments, an N-type 2T1C drive circuit can also be used, or more transistors and capacitors can be added. The specific layout can be set as needed. As long as the layout design and wiring design scheme of this embodiment are included, they should be within the protection scope of this application.

[0084] Figure 4 is a cross-sectional view of the driving unit 110 shown in Figure 2 along its thickness direction. The driving unit 110 includes a substrate 111, a first active semiconductor layer 112, a first gate layer 113, a DATA line layer 115, a second gate layer 116, a second active semiconductor layer 117, and an anode metal layer 118 arranged sequentially along its thickness direction. The DATA line layer 115 and the second gate layer 116 are located on the same layer of the driving unit 110. The VDD line layers 114 of the driving units 110 located in the same row are electrically connected to form a VDD power line 122, and the DATA line layers 115 of the driving units 110 located in the same column are electrically connected to form a DATA data line 121.

[0085] The substrate 111 is made of glass or carbon-based material, and includes a DATA line layer 115, a first gate layer 113, a VDD line layer 114, a second gate layer 116, and an anode metal layer 118. These layers can be made of metals such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of these metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The layers can be single-layer or multi-layer composite structures, such as Ti / Al / Ti.

[0086] Specifically, the orthographic projections of the DATA line layer 115, the first active semiconductor layer 112, the VDD line layer 114, and the second active semiconductor layer 117 on the substrate 111 at least partially overlap. That is, in the driving backplane 10, at least two of the following structures of the driving unit 110—the DATA line layer 115, the first active semiconductor layer 112, the VDD line layer 114, and the second active semiconductor layer 117—are partially stacked to reduce the orthographic projection area of ​​the driving unit 110 on the substrate 111, allowing more driving units 110 to be accommodated per unit area of ​​the display area.

[0087] In the driving unit 110, an insulating layer 130 is provided between every two adjacent layers. Specifically, a first insulating layer 131 is provided between the substrate 111 and the first gate layer 113; a second insulating layer 132 is provided between the first gate layer 113 and the VDD line layer 114; a third insulating layer 133 is provided between the VDD line layer 114 and the DATA line layer 115; a fourth insulating layer 134 is provided between the DATA line layer 115 and the second active semiconductor layer 117; and a fifth insulating layer 135 is provided between the second active semiconductor layer 117 and the anode metal layer 118. The first insulating layer 131, the second insulating layer 132, the third insulating layer 133, and the fourth insulating layer 134 are all composed of inorganic materials, specifically silicon dioxide, etc. The fifth insulating layer 135 is an organic insulating layer.

[0088] The driving unit 110 is further provided with a first via 141, a second via 142, a third via 143, and a fourth via. The first via 141 passes through the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 sequentially along the thickness direction of the driving backplate 10, and connects the DATA line layer 115 and the first active semiconductor layer 112. The second via 142 passes through the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 sequentially along the thickness direction of the driving backplate 10, and connects the second gate layer 116 and the first active semiconductor layer 112. The third via 143 passes through the fourth insulating layer 134 and the third insulating layer 133 sequentially along the thickness direction of the driving backplate 10, and connects the VDD line layer 114 and the second active semiconductor layer 117. The fourth via extends through the fifth insulating layer 135 along the thickness direction of the drive backplate 10, and the fourth via connects the second active semiconductor layer 117 and the anode metal layer 118.

[0089] The orthographic projections of the first via 141, the second via 142, the third via 143, the fourth via, the first active semiconductor layer 112, and the second active semiconductor layer 117 on the substrate 111 at least partially overlap. In other words, at least one of the first via 141, the second via 142, the third via 143, and the fourth via is stacked with either the first active semiconductor layer 112 or the second active semiconductor layer 117, saving layout space.

[0090] Referring to Figure 5, in one embodiment, two adjacent driving units 110 in the driving backplate 10 in the first direction are defined as a first driving unit 110a and a second driving unit 110b, respectively. The second active semiconductor layer 117 of the first driving unit 110a and the second active semiconductor layer 117 of the second driving unit 110b are staggered in the thickness direction of the driving backplate 10. It can be understood that the smaller the distance between adjacent driving units 110, the more driving units 110 can be accommodated in the display area, the more pixel units 210 can be controlled, and the higher the display resolution. However, due to limitations in processing precision, there is a processing limit to the distance between driving units 110. In this embodiment, the layer structures of the first driving unit 110a and the second driving unit 110b are staggered in the thickness direction of the driving backplate 1010. Taking the second active semiconductor layer 117 as an example, assuming that the shortest distance between the two second active semiconductor layers 117 in two adjacent driving units 110 under the current processing limit is L1 (L1 is not limited to a specific value), since the two second active semiconductor layers 117 are staggered in the thickness direction of the driving backplate 10, the distance L2 between the orthographic projection of the second active semiconductor layer 117 of the first driving unit 110a onto the pixel layer 20 and the orthographic projection of the second active semiconductor layer 117 of the second driving unit 110b onto the pixel layer 20 is obtained, where L2 < L1. By staggering the adjacent driving units 110 in the thickness direction of the driving backplate 10, more driving units 110 can be accommodated in the same size display area under the same processing precision.

[0091] Referring to Figure 6, this application also provides a method for fabricating a driving backplate 10, which is used to drive the light emission of the pixel layer 20. The fabrication method includes forming a driving unit and a stroke driving array.

[0092] The process of forming a drive unit includes the following steps:

[0093] Step S110: Form a first active semiconductor layer on one side of the substrate.

[0094] Step S120: A first gate layer is formed on the side of the first active semiconductor layer away from the substrate.

[0095] Step S130: Form a VDD line layer on the side of the first gate layer away from the substrate.

[0096] Step S140: A DATA line layer and a second gate layer are formed on the side of the VDD line layer away from the substrate. The DATA line layer and the second gate layer are on the same layer of the driving backplane.

[0097] Step S150: Form a second active semiconductor layer on the side of the DATA line layer away from the substrate.

[0098] Step S160: An anode metal layer is formed on the side of the second active semiconductor layer away from the substrate.

[0099] Forming the driving array includes the following steps:

[0100] In the step of forming a drive unit, multiple drive units are formed simultaneously and arranged in a column along a first direction and in a row along a second direction, wherein the first direction is perpendicular to the second direction.

[0101] In this configuration, the VDD line layers of multiple drive units in the same row are electrically connected to form a VDD power line, and the DATA line layers of multiple drive units in the same column are electrically connected to form a DATA data line. The extension direction of the DATA data line is parallel to the first direction, the VDD power line is parallel to the second direction, and the first direction is perpendicular to the second direction.

[0102] Referring to Figure 7, specifically, the preparation method further includes the step of forming an insulating layer, specifically:

[0103] Step S210: Form a first insulating layer between the substrate and the first gate layer.

[0104] Step S220: A second insulating layer is formed between the first gate layer and the VDD line layer.

[0105] Step S230: Form a third insulating layer between the VDD line layer and the second active semiconductor layer.

[0106] Step S240: A fourth insulating layer is formed between the DATA line layer and the second active semiconductor layer.

[0107] Step S250: A fifth insulating layer is formed between the second active semiconductor layer and the anode metal layer.

[0108] Insulating layers are placed between different layers of the drive unit to prevent short circuits caused by contact between metal layers.

[0109] Furthermore, the preparation method also includes a step of forming vias, specifically:

[0110] Step S235: After forming the third insulating layer, a first via is formed that sequentially passes through the third insulating layer, the second insulating layer and the first insulating layer along the thickness direction of the drive backplane. The first via is used to connect the first active semiconductor layer and the DATA line layer.

[0111] Step S236: Form a second via through which the third insulating layer, the second insulating layer and the first insulating layer are sequentially passed in the thickness direction of the driving backplate. The second via is used to connect the first active semiconductor layer and the second gate layer.

[0112] Step S245: After forming the fourth insulating layer, a third via is formed that passes through the fourth insulating layer and the third insulating layer sequentially along the thickness direction of the drive backplane. The third via is used to connect the VDD line layer and the second active semiconductor layer.

[0113] Step S255: After forming the fifth insulating layer, a fourth via is formed that penetrates the fifth insulating layer along the thickness direction of the drive backplate. The fourth via is used to connect the second active semiconductor layer and the anode metal layer.

[0114] Among them, the orthographic projections of the first via on the substrate, the second via on the substrate, the third via on the substrate, the fourth via on the substrate, the first active semiconductor layer on the substrate, and the second active semiconductor layer on the substrate at least partially overlap.

[0115] The following describes the fabrication method of the drive backplane 10 by way of example, with reference to a specific process flow. It should be noted that any fabrication process in the prior art can be used when forming the structure of the drive unit. In the context of "patterning" throughout this application, when the material of "patterning" is inorganic or metallic, "patterning" includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. When the material of "patterning" is organic, "patterning" includes processes such as mask exposure and development. In addition, this application can also use existing fabrication processes such as evaporation, deposition, coating, and plating.

[0116] Referring to Figures 4, 8, 9, and 10, Figure 4 is a cross-sectional view of the driving unit along the thickness direction, and Figures 8 to 10 are schematic diagrams of the orthographic projection of the driving unit obtained in each step of the fabrication process onto the substrate 111. The specific fabrication process is as follows:

[0117] A first active semiconductor layer 112 is formed on one side of the substrate 111, and a channel region is patterned thereon. The driving unit is shown in Figure 8a.

[0118] A first insulating layer 131 is formed on the side of the first active semiconductor layer 112 away from the substrate 111.

[0119] A metal layer is formed on the side of the first insulating layer 131 away from the substrate 111, and after patterning, a first gate layer 113 is formed. At this time, the driving unit is shown in Figure 8b.

[0120] A second insulating layer 132 is formed on the side of the first gate layer 113 away from the substrate 111.

[0121] A VDD line layer 114 is formed on the side of the second insulating layer 132 away from the substrate 111, and the driving unit is shown in Figure 8c.

[0122] A third insulating layer 133 is formed on the side of the VDD line layer 114 away from the substrate 111.

[0123] A first via 141 is patterned to sequentially penetrate the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 along the thickness direction of the drive backplane 10. The first via 141 is used to connect the first active semiconductor layer 112 and the DATA line layer 115. A second via 142 is patterned to sequentially penetrate the third insulating layer 133, the second insulating layer 132, and the first insulating layer 131 along the thickness direction of the drive backplane 10. The second via 142 is used to connect the first active semiconductor layer 112 and the second gate layer 116. The drive unit is shown in Figure 9a.

[0124] A metal layer is formed on the side of the third insulating layer 133 away from the substrate 111, and a DATA line layer 115 and a second gate layer 116 are patterned therein, wherein a storage capacitor is formed in the overlapping area of ​​the second gate layer 116 and the VDD line layer 114. The driving unit is shown in Figure 9b at this time.

[0125] A fourth insulating layer 134 is formed on the side of the DATA line layer 115 and the second gate layer 116 away from the substrate 111.

[0126] A third via 143 is formed by sequentially passing through the fourth insulating layer 134 and the third insulating layer 133 along the thickness direction of the drive backplate 10. The third via 143 is used to connect the VDD circuit layer and the second active semiconductor layer 117. At this time, the drive unit is shown in Figure 9c.

[0127] A second active semiconductor layer 117 is formed on the side of the fourth insulating layer 134 away from the substrate 111, and a channel region is patterned thereon. The driving unit is shown in Figure 10a.

[0128] A fifth insulating layer 135 is formed on the side of the second active semiconductor layer 117 away from the substrate 111.

[0129] A fourth via 144 is patterned to pass through the fifth insulating layer 135. The fourth via 144 is used to connect the second active semiconductor layer 117 and the anode metal layer 118. At this time, the driving unit is shown in Figure 10b.

[0130] A metal layer is formed on the side of the fifth insulating layer 135 away from the substrate 111, and an anode metal layer 118 is patterned. The anode metal layer 118 is electrically connected to the second active semiconductor layer 117 through the fourth via 114. At this time, the driving unit is shown in Figure 10c.

[0131] Referring to FIG1, in a second aspect, this application provides a display panel 1, which includes the aforementioned driving backplate 10 or a driving backplate 10 prepared by the aforementioned method, and other components of the display panel 1 can be any existing components.

[0132] In a third aspect, this application provides a display device, which includes the aforementioned driving backplate 10 or a driving backplate 10 formed by the aforementioned manufacturing direction, and other components of the display device can be any existing components.

[0133] Although the invention has been described with reference to several typical embodiments, it should be understood that the terminology used is illustrative and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A drive backplane for driving light emission of a pixel layer, characterized by, The driving backboard comprises: a plurality of driving units arranged in columns along a first direction and arranged in rows along a second direction, the first direction being perpendicular to the second direction; a lead unit comprising a DATA data line, a VDD power line, a VSS power line and a SCAN signal line connected with the driving units, the DATA data line extending along the first direction, the VDD power line, the VSS power line and the SCAN signal line all extending along the second direction.

2. The drive backplane of claim 1, wherein, The driving unit comprises: a substrate; a first active semiconductor layer located on one side of the substrate; a first gate layer located on a side of the first active semiconductor layer away from the substrate; a VDD line layer located on a side of the first gate layer away from the substrate; a DATA line layer and a second gate layer both located on a side of the VDD line layer away from the substrate, the DATA line layer and the second gate layer being on the same layer of the driving backboard; a second active semiconductor layer located on a side of the DATA line layer away from the substrate; an anode metal layer located on a side of the second active semiconductor layer away from the substrate; wherein the VDD line layers of the driving units in the same row are electrically connected and form the VDD power line, and the DATA line layers of the driving units in the same column are electrically connected and form the DATA data line.

3. The drive backplane of claim 2, wherein, The orthographic projection of the DATA line layer on the substrate, the orthographic projection of the first active semiconductor layer on the substrate, the orthographic projection of the VDD line layer on the substrate and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap.

4. The drive backplane of claim 2, wherein, Two driving units adjacent in the first direction in the driving backboard are defined as a first driving unit and a second driving unit respectively, and the second active semiconductor layer of the first driving unit and the second active semiconductor layer of the second driving unit are arranged in a staggered manner in the thickness direction of the driving backboard.

5. The drive backplane of claim 2, wherein, The driving unit further comprises: a first insulating layer located between the substrate and the first gate layer; a second insulating layer located between the first gate layer and the VDD line layer; a third insulating layer located between the VDD line layer and the DATA line layer; a fourth insulating layer located between the DATA line layer and the second active semiconductor layer; a fifth insulating layer located between the second active semiconductor layer and the anode metal layer; a first via hole sequentially penetrating the third insulating layer, the second insulating layer and the first insulating layer in the thickness direction of the driving backboard, the first via hole connecting the DATA line layer and the first active semiconductor layer; a second via hole sequentially penetrating the third insulating layer, the second insulating layer and the first insulating layer in the thickness direction of the driving backboard, the second via hole connecting the second gate layer and the first active semiconductor layer; a third via hole sequentially penetrating the fourth insulating layer and the third insulating layer in the thickness direction of the driving backboard, the third via hole connecting the VDD line layer and the second active semiconductor layer; A fourth via hole is formed through the fifth insulating layer along the thickness direction of the driving backplane, and the third via hole is connected with the second active semiconductor layer and the anode metal layer; The orthographic projection of the first via hole on the substrate, the orthographic projection of the second via hole on the substrate, the orthographic projection of the third via hole on the substrate, the orthographic projection of the fourth via hole on the substrate, the orthographic projection of the first active semiconductor layer on the substrate, and the orthographic projection of the second active semiconductor layer on the substrate at least partially overlap.

6. A method for manufacturing a drive backplane for driving light emission of a pixel layer, characterized by, The preparation method comprises forming a driving unit and forming a driving array: forming a driving unit: forming a first active semiconductor layer on one side of a substrate; forming a first gate layer on the side of the first active semiconductor layer away from the substrate; forming a VDD line layer on the side of the first gate layer away from the substrate; forming a DATA line layer and a second gate layer on the side of the VDD line layer away from the substrate, the DATA line layer and the second gate layer being on the same layer of the driving backplane; forming a second active semiconductor layer on the side of the DATA line layer away from the substrate; forming an anode metal layer on the side of the second active semiconductor layer away from the substrate; forming a driving array: in the step of forming a driving unit, a plurality of driving units are formed simultaneously and arranged into columns along a first direction and into rows along a second direction, the first direction being perpendicular to the second direction; wherein the VDD line layers of a plurality of driving units in the same row are electrically connected and form a VDD power line, the DATA line layers of a plurality of driving units in the same column are electrically connected and form a DATA data line, the extension direction of the DATA data line is parallel to the first direction, the extension direction of the VDD power line is parallel to the second direction, and the first direction is perpendicular to the second direction.

7. The production method according to claim 6, wherein The preparation method further comprises: forming a first insulating layer between the substrate and the first gate layer; forming a second insulating layer between the first gate layer and the VDD line layer; forming a third insulating layer between the VDD line layer and the DATA line layer; forming a fourth insulating layer between the DATA line layer and the second active semiconductor layer; forming a fifth insulating layer between the second active semiconductor layer and the anode metal layer.

8. The preparation method according to claim 7, characterized in that, The preparation method further comprises: after forming the third insulating layer, forming a first via hole through the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the driving backplane, the first via hole being used to connect the first active semiconductor layer and the DATA line layer; forming a second via hole through the third insulating layer, the second insulating layer, and the first insulating layer along the thickness direction of the driving backplane, the second via hole being used to connect the first active semiconductor layer and the second gate layer; After forming the fourth insulating layer, a third via hole is formed along the thickness direction of the driving backplane, sequentially penetrating the fourth insulating layer and the third insulating layer, and the third via hole is used for connecting the VDD wiring layer and the second active semiconductor layer; After forming the fifth insulating layer, a third via hole is formed along the thickness direction of the driving backplane, penetrating the fifth insulating layer, and the third via hole is used for connecting the second active semiconductor layer and the anode metal layer; The orthographic projection of the first via hole on the substrate, the orthographic projection of the second via hole on the substrate, the orthographic projection of the third via hole on the substrate, the orthographic projection of the fourth via hole on the substrate, the orthographic projection of the first active semiconductor layer on the substrate, and the orthographic projection of the second active semiconductor layer on the substrate at least partially coincide.

9. A display panel, characterized by, The driving backplane comprises the driving backplane according to any one of claims 1 to 5 or is prepared by the preparation method according to any one of claims 6 to 8.

10. A display device, characterized by comprising: The driving backplate comprises the driving backplate according to any one of claims 1 to 5 or is prepared by the preparation method according to any one of claims 6 to 8.

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