Preparation method for patterned silicon oxide mask, patterning method for topcon battery, and topcon battery

Abstract

A preparation method for a patterned silicon oxide mask, a patterning method for a TOPCon battery, and a TOPCon battery. The preparation method comprises the following step: forming a patterned silicon oxide mask on the surface of a silicon substrate by means of an electrochemical oxidation method, wherein in the electrochemical oxidation method, a pattern electrode is used as a cathode and the silicon substrate is used as an anode, and there is an electrolyte between the cathode and the anode.

Description

Fabrication method of patterned silicon oxide mask, patterning method of TOPCon cell, TOPCon cell

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410691930.X, filed on May 30, 2024, entitled “Method for Patterning the Front Poly Layer of a Bifacial TOPCon Battery and a Bifacial TOPCon Battery”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of photovoltaic cell or semiconductor device or semiconductor integrated circuit manufacturing, and more specifically, to a method for preparing a patterned silicon oxide mask, a patterning method for TOPCon cells, and TOPCon cells. Background Technology

[0004] In the existing semiconductor device manufacturing field (including crystalline silicon photovoltaic cells, semiconductor power devices, and semiconductor integrated circuits), patterning is a core and critical process step. For crystalline silicon photovoltaic cells, screen printing is currently the most common process, while laser direct etching and photomask exposure are under development. For semiconductor power devices and semiconductor integrated circuits, photoresist exposure is the primary method, with nanoimprint lithography and other techniques still under development. In crystalline silicon photovoltaic cells, patterning cost is a major bottleneck restricting technological development. Currently, screen printing is widely used, but it often generates environmentally sensitive waste and is not environmentally friendly. Although laser direct etching, laser transfer printing, and photomask exposure have been developed in recent years, they also have certain drawbacks.

[0005] For example, the laser direct lithography technology, which is developing in the industry, has low production capacity and high cost, and the high-energy laser inevitably damages the silicon substrate, leading to product performance degradation. In addition, the use of photolithography processes adapted from the semiconductor industry results in excessively high costs due to the application of photoresist, while organic photoresist creates significant environmental and cost pressures during the process, which is not conducive to sustainable development.

[0006] Therefore, there is an urgent need to develop a gate patterning method to replace the existing screen printing and laser direct etching techniques for generating poly gate lines. This method would not only reduce costs but also avoid damaging the silicon substrate and causing product performance degradation.

[0007] Public content

[0008] This disclosure provides a method for fabricating a patterned silicon oxide mask, a method for patterning a TOPCon cell, and a TOPCon cell, to at least alleviate one technical problem existing in the prior art.

[0009] In order to achieve at least one of the above-mentioned objectives of this disclosure, the following technical solution is adopted:

[0010] In a first aspect, this disclosure provides a method for preparing a patterned silicon oxide mask, the method comprising the following steps:

[0011] A patterned silicon oxide mask is formed on the surface of a silicon substrate by electrochemical oxidation.

[0012] In the electrochemical oxidation method, the patterned electrode serves as the cathode, the silicon substrate serves as the anode, and an electrolyte is present between the cathode and the anode.

[0013] Secondly, this disclosure provides a graphical method for representing a TOPCon battery, the graphical method comprising the following steps:

[0014] A poly layer is deposited on the front side of the silicon substrate.

[0015] A patterned silicon oxide mask is fabricated by selectively oxidizing the surface of the poly layer to form a silicon oxide gate pattern using the method described in the first aspect.

[0016] The poly layer on the silicon substrate surface that has not formed an etching mask is removed by chemical etching to obtain the gate pattern of the front poly layer.

[0017] Thirdly, this disclosure provides a TOPCon battery, which is prepared by the patterning method of the TOPCon battery as described in the second aspect.

[0018] Compared with the prior art, the beneficial effects of this disclosure include:

[0019] (1) This disclosure utilizes the physical principle that anodizing can directly generate silicon oxide films on silicon substrates to directly produce patterned silicon oxide hard masks, which can be used in the patterning steps of various crystalline silicon photovoltaic cells or in the patterning steps of various semiconductor chip processes. The process is simple, fast, environmentally friendly, and low-cost, and is superior to existing technologies in all aspects.

[0020] (2) This disclosure achieves the patterning purpose by directly generating a patterned silicon oxide mask layer on the silicon substrate of the product. The generated silicon oxide mask layer can be used as a barrier layer for subsequent etching processes or as a dielectric insulating layer in the structure. Similarly, this method can be used on various semiconductor power devices and semiconductor integrated circuits to generate local silicon oxide patterns or local silicon material ablation patterns, generating hard masks that can replace the original photolithography process.

[0021] (3) The TOPCon patterning method provided in this disclosure utilizes an electrochemical oxidation method to directly generate a patterned silicon oxide hard mask on the poly layer of a silicon substrate, and then generates poly gate lines through alkaline etching. Compared with existing screen printing and laser direct etching technologies for generating poly gate lines, the gate line patterning method of this application not only eliminates the need for indirect auxiliary materials such as screen printing inks and photoresists, significantly reducing production costs, but also avoids generating environmentally sensitive waste, thus exhibiting superior environmental friendliness.

[0022] (4) The bifacial TOPCon battery provided in this disclosure has a front poly layer grid structure mainly prepared by the above-mentioned grid patterning method. The preparation of the front poly layer grid of this bifacial TOPCon battery does not require the use of indirect auxiliary materials such as screen printing ink and photoresist, significantly reducing production costs and avoiding the generation of environmentally sensitive waste. Attached Figure Description

[0023] Figure 1 is a schematic diagram of a patterned silicon oxide mask formed on the surface of a silicon substrate by electrochemical oxidation, as provided in this disclosure.

[0024] Among them, 100 is the patterned electrode, 200 is the electrolyte, 300 is the silicon substrate, and 400 is the patterned silicon oxide mask.

[0025] Figure 2 is a schematic diagram of the structure of the patterned electrode provided in this disclosure.

[0026] In this diagram, 101 represents the oxidized region of the graphic, and 102 represents the non-oxidized region of the graphic.

[0027] Figure 3 is a structural diagram of a silicon substrate with a patterned silicon oxide mask on its surface provided in this disclosure.

[0028] Among them, 300 is the silicon substrate and 400 is the patterned silicon oxide mask.

[0029] Figure 4 is a schematic diagram of the process flow for obtaining intermediate battery cells before step (E) electrochemical oxidation treatment provided in this disclosure.

[0030] Figure 5 is a schematic diagram of step (E) of the present disclosure, which involves the electrochemical oxidation method to generate a patterned silicon oxide layer.

[0031] Figure 6 is a schematic diagram of the front poly layer gate pattern obtained after chemical etching in step (F) of this disclosure.

[0032] Figure 7 is a physical image of the silicon substrate wafer to be processed provided in Example 1.

[0033] Figure 8 is a physical image of the patterned electrode provided in Example 1.

[0034] Figure 9 is a physical image of a patterned silicon oxide mask formed on the surface of a silicon substrate by electrochemical oxidation, as provided in Example 1.

[0035] Figure 10 is a physical image of the silicon substrate with a patterned silicon oxide mask on its surface provided in Example 1. Detailed Implementation

[0036] The embodiments of this disclosure will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of this disclosure. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer shall apply.

[0037] In a first aspect, this disclosure provides a method for preparing a patterned silicon oxide mask, the method comprising the following steps:

[0038] A patterned silicon oxide mask 400 is formed on the surface of a silicon substrate by electrochemical oxidation.

[0039] As shown in Figure 1, in the electrochemical oxidation method, the patterned electrode 100 serves as the cathode, the silicon substrate 300 serves as the anode, and an electrolyte 200 is provided between the cathode and the anode.

[0040] The purpose of this disclosure is to provide a low-cost and environmentally friendly method for forming patterned silicon oxide masks on a silicon substrate. (The silicon substrate can be a monocrystalline silicon wafer, a polycrystalline silicon wafer, or a silicon film layer grown on a substrate, such as a polysilicon layer or an epitaxial silicon layer). The fabrication method described in this disclosure can serve as a fundamental process in the fabrication processes of crystalline silicon photovoltaic cells, semiconductor power devices, or semiconductor integrated circuits, thereby partially replacing various existing patterning processes. This method can directly generate patterned silicon oxide hard masks or perform patterned oxidation and ablation of localized silicon materials.

[0041] More specifically, the method described in this disclosure uses pre-patterned electrodes and a suitable electrolyte to contact the silicon substrate to be processed, and then applies an electric current. The patterned electrode acts as the cathode, the silicon substrate as the anode, and an electrolyte of suitable composition exists between the anode and cathode to selectively anodize the silicon substrate, thereby locally oxidizing the silicon material on the silicon substrate and ultimately directly generating a silicon oxide structure corresponding to the pre-patterned electrode. This silicon oxide structure can be used as a structural part of the manufactured product, or it can be chemically etched in subsequent processes to achieve selective etching and generate the desired structure for the product.

[0042] In an optional embodiment of this disclosure, the method for preparing the patterned silicon oxide mask includes the following steps:

[0043] The patterned electrode is brought close to the silicon substrate, with the patterned side of the patterned electrode facing the side of the silicon substrate to be patterned.

[0044] An electrolyte is filled between the patterned electrodes and the silicon substrate to form a circuit;

[0045] By energizing the circuit, a patterned silicon oxide mask is formed on the surface of the silicon substrate.

[0046] In an optional embodiment of this disclosure, as shown in FIG2, the patterned electrode includes a patterned oxidized region 101 and a patterned non-oxidized region 102.

[0047] The oxidized areas of the pattern are made of conductive materials, while the non-oxidized areas are made of insulating materials.

[0048] In optional embodiments of this disclosure, the conductive material of the patterned electrode material can be made of any optional conductive inert material, such as inert metals like titanium, gold, or platinum; or composite functional materials such as graphite, conductive rubber, or conductive plastic.

[0049] In optional embodiments of this disclosure, the insulating material of the patterned electrode material may be manufactured using optional acid and alkali resistant insulating materials, such as plastics, ceramics, insulating varnishes, etc.

[0050] In an optional embodiment of this disclosure, as can be seen from the combination of Figures 1 to 3, the position where the silicon oxide mask 400 is formed on the surface of the silicon substrate 300 corresponds to the patterned oxide region 101 in the patterned electrode.

[0051] In an optional embodiment of this disclosure, the distance between the patterned electrode and the silicon substrate is less than the minimum linewidth of the pattern formed on the surface of the silicon substrate.

[0052] It is important to note that during the process of bringing the patterned electrode close to the silicon substrate, a gap must be maintained to allow the electrolyte to continue flowing between the positive and negative electrodes. The size of the patterned electrode and its conductive pattern correspond to the area of ​​the desired silicon substrate and the desired pattern to be processed. The gap between the patterned electrode and the silicon substrate is positively correlated with the feature size of the processed pattern and should generally be smaller than the feature size of the processed pattern. For example, if the minimum linewidth of the pattern to be processed is 100 μm, then the gap between the electrode and the silicon substrate should be less than 100 μm.

[0053] In an optional embodiment of this disclosure, the electrolyte flows between the silicon substrate and the patterned electrodes via a circulation device.

[0054] It is important to note that in this disclosure, the surface of the silicon substrate to be processed is brought into full contact with the electrolyte. A liquid circulation mechanism, such as a circulation pump, can be used to circulate the electrolyte on the surface of the silicon substrate, so as to remove air bubbles generated on the surface of the silicon substrate when energized. In addition, the electrolyte circulation flow rate can be adjusted according to the processing area of ​​the silicon substrate. Generally, the larger the area of ​​the silicon substrate to be processed, the larger the required flow rate is, so as to remove the generated air bubbles in time.

[0055] In an optional embodiment of this disclosure, the electrolyte comprises an electrolyte solution.

[0056] In optional embodiments of this disclosure, the electrolyte includes any one or a combination of at least two of sulfuric acid, oxalic acid, or sodium hydroxide.

[0057] It should be noted that the electrolyte can be selected based on the working environment of the electrodes, etc., as long as it can achieve the "anodic oxidation" function. The selected electrolyte should not cause corrosion or passivation or other adverse effects on the electrodes or the materials contained in the product to be processed. Generally, dilute sulfuric acid, oxalic acid, sodium hydroxide, etc., can be used as electrolytes. The electrolyte may contain one or more additives to meet process requirements or further optimize the process window.

[0058] In an optional embodiment of this disclosure, the circuit is energized by means of an external DC power supply.

[0059] In this disclosure, an external DC power supply can be used to energize the circuit described above, ensuring that the patterned electrode acts as the cathode and the silicon substrate as the anode, to perform an anodic oxidation reaction on the silicon substrate. As the reaction proceeds, the silicon oxide mask on the silicon substrate gradually thickens. The process termination point can be determined based on the set process time or feedback from current and voltage to end the process.

[0060] In optional embodiments of this disclosure, the electrochemical oxidation method includes: constant current method or constant voltage method.

[0061] In an optional embodiment of this disclosure, the constant current method includes: initially setting a constant current value, such as 0.1 to 2 mA / cm² silicon wafer area (the specific current intensity needs to be calculated based on the patterned gate line density ratio of the specific product); during the initial stage of processing, the current remains unchanged, and the voltage gradually increases; when the voltage increases to a certain multiple of the initial value, such as 2 to 10 times, the process ends (the specific initial voltage value and the increase multiple depend on the structure of the semi-finished product to be processed and the thickness of the desired oxide layer, and are given after actual testing).

[0062] In an optional embodiment of this disclosure, the constant voltage method includes: initially setting a voltage value, such as 0.5 to 5V. During the processing, the voltage remains constant while the current gradually decreases. When the current decreases to a fraction of the initial value, such as 1 / 3 to 1 / 10, the process is terminated (the specific initial current value and the rate of decrease depend on the structure of the semi-finished product to be processed and the desired thickness of the oxide layer, and are given after actual testing).

[0063] In an optional embodiment of this disclosure, after the patterned silicon oxide mask is formed, the method further includes: cleaning the silicon substrate to remove residual electrolyte.

[0064] Secondly, this disclosure provides a graphical method for representing a TOPCon battery, the graphical method comprising the following steps:

[0065] A poly layer is deposited on the front side of the silicon substrate;

[0066] A patterned silicon oxide mask is fabricated by selectively oxidizing the surface of the poly layer to form a silicon oxide gate pattern using the method described in the first aspect.

[0067] The poly layer on the silicon substrate surface that has not formed an etching mask is removed by chemical etching to obtain the gate line pattern of the front poly layer.

[0068] In this disclosure, after the front-side poly deposition is completed, the present method is used to selectively oxidize the front-side poly to form a silicon oxide gate line pattern as an etching mask. Then, alkaline etching is performed to remove excess exposed poly layer, leaving a poly layer protected by the silicon oxide mask, thus realizing the fabrication of poly gate lines. This eliminates the need for existing laser direct etching or photoresist exposure processes.

[0069] In an optional embodiment of this disclosure, the silicon substrate is a silicon substrate for which a patterned tunneling oxide layer has been formed.

[0070] In an optional embodiment of this disclosure, when a poly layer is deposited on the front side of a silicon substrate on which a patterned tunneling oxide layer has been formed, the tunneling conductive portion of the patterned tunneling oxide layer must correspond to the gate line position.

[0071] In an optional embodiment of this disclosure, the patterned tunneling oxide layer is a silicon oxide layer.

[0072] In optional embodiments of this disclosure, the thickness of the patterned tunneling oxide layer is 0.5 to 2.0 nm, for example, it can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, etc.

[0073] In an optional embodiment of this disclosure, the remainder of the silicon substrate forming the patterned tunneling oxide layer is a non-conductive material layer, such as a phosphor glass layer and / or a borosilicate glass oxide layer.

[0074] In optional embodiments of this disclosure, the thickness of the non-conductive material layer is 10 to 200 nm, for example, it can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, etc.

[0075] In an optional embodiment of this disclosure, when the surface of the poly layer is selectively oxidized to form a silicon oxide gate pattern, the poly layer naturally forms a patterned conductive region due to the presence of the patterned tunneling conductive structure of the preceding layer. Therefore, it is no longer necessary to pre-fabricate a patterned cathode to grow the patterned oxide layer, and a planar cathode can be used instead.

[0076] In optional embodiments of this disclosure, the thickness of the poly layer is 50-150 nm, for example, it can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0077] In an optional embodiment of this disclosure, the step of cleaning the silicon substrate is included prior to selective oxidation.

[0078] In an optional embodiment of this disclosure, the following steps are further included before depositing a poly layer on the front side of the silicon substrate:

[0079] (A) Texturing the silicon substrate on both sides;

[0080] (B) Boron-expanded BSG layer is obtained by front-side boron expansion;

[0081] (C) The boron-expanded BSG layer is locally patterned and grooved. After removing the BSG layer in the part where the patterned grid lines need to be formed, the grid line pattern is obtained.

[0082] (D) Deposit a tunnel oxide layer on the grooved silicon substrate.

[0083] In an optional embodiment of this disclosure, the graphical method specifically includes the following steps:

[0084] (A) Texturing the silicon substrate on both sides;

[0085] (B) Boron-expanded BSG layer is obtained by front-side boron expansion;

[0086] (C) The boron-expanded BSG layer is locally patterned and grooved. After removing the BSG layer in the part where the patterned grid lines need to be formed, the grid line pattern is obtained.

[0087] (D) Deposit a tunnel oxide layer and a poly layer on the grooved silicon substrate to obtain an intermediate solar cell;

[0088] (E) A silicon oxide gate pattern is formed on the surface of the poly layer by selective oxidation using the patterned silicon oxide mask fabrication method described in the first aspect;

[0089] (F) The poly layer on the surface of the silicon substrate that has not formed an etching mask is removed by chemical etching to obtain the gate pattern of the front poly layer.

[0090] This disclosure provides a method for patterning grid lines on the front poly layer of a bifacial TOPCon solar cell. This method utilizes electrochemical oxidation to directly generate a patterned silicon oxide hard mask on the poly layer of a silicon substrate, followed by alkaline etching to generate poly grid lines. Compared to existing screen printing and laser etching techniques for generating poly grid lines, this method eliminates the need for indirect auxiliary materials such as screen printing inks and photoresists, significantly reducing production costs. Furthermore, it does not generate environmentally sensitive waste, demonstrating superior environmental friendliness.

[0091] To more clearly illustrate the grid line graphical method of this disclosure, the applicant has provided a graphical explanation, as shown in Figures 4 to 6.

[0092] Figure 4 is a schematic diagram of the process flow for obtaining intermediate battery cells before the electrochemical oxidation process in step (E) of this disclosure.

[0093] Figure 5 is a schematic diagram of the electrochemical oxidation method for generating a patterned silicon oxide layer in step (E) of this disclosure.

[0094] Figure 6 is a schematic diagram of the front poly layer gate pattern obtained after chemical etching in step (F) of this disclosure.

[0095] It should be noted that the method for local patterning grooving in step (C) above can be grooving, photoresist, or screen printing to form the grooving pattern, all of which are applicable to the processing method disclosed in this invention in subsequent processes; at the same time, the grooving here is single-sided grooving, and the grooving pattern corresponds to the shape of the patterned poly grid line.

[0096] In an optional embodiment of this disclosure, the groove width of the local patterned groove in step (C) is 5 to 20 μm, for example, it can be 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc.

[0097] In an optional embodiment of this disclosure, the thickness of the tunneling oxide layer in step (D) is 0.5 to 2 nm, for example, it can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc.

[0098] Thirdly, this disclosure provides a TOPCon battery, which is prepared by the patterning method of the TOPCon battery as described in the second aspect.

[0099] The bifacial TOPCon solar cell disclosed herein has its front-side poly layer grid line structure primarily fabricated using the aforementioned grid line patterning method. The fabrication process of this bifacial TOPCon solar cell eliminates the need for indirect auxiliary materials such as screen printing inks and photoresists, significantly reducing production costs and preventing the generation of environmentally sensitive waste.

[0100] The embodiments of this disclosure will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of this disclosure. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer shall apply.

[0101] To aid in a clearer understanding of the contents of this disclosure, specific embodiments are described in detail below. However, these embodiments are merely exemplary and do not constitute any limitation on the scope of this disclosure.

[0102] Example 1

[0103] This disclosure provides a method for preparing a patterned silicon oxide mask, the method comprising the following steps:

[0104] S1. Prepare the silicon substrate to be patterned (as shown in Figure 7) and the patterned titanium electrode (as shown in Figure 8);

[0105] S2. Immerse the patterned titanium electrode in the electrolyte of dilute sulfuric acid, and then suspend the silicon substrate above the titanium electrode with a gap of 1 mm, ensuring that only the lower surface of the silicon substrate is in contact with the electrolyte of dilute sulfuric acid, so that the electrolyte fills the space between the patterned electrode and the silicon substrate to form a circuit.

[0106] S3. By placing a copper plate on the side of the silicon substrate away from the electrolyte, the circuit is energized (as shown in Figure 9) with a current of 1A and an oxidation time of 10min. After oxidation, the silicon substrate is cleaned to remove residual electrolyte, and a patterned silicon oxide mask with an average thickness of 80nm is formed on the surface of the silicon substrate (as shown in Figure 10).

[0107] Application Example 1

[0108] A method for fabricating a bifacial TOPCon solar cell, the method comprising:

[0109] S1. Select a single-crystal silicon wafer with a resistivity of 1 ohm·cm and a thickness of 170 μm;

[0110] Double-sided texturing is performed on the front and back sides of the silicon substrate. First, the damaged layer on the surface of the silicon wafer is removed in a mixed solution of KOH and H2O2, and then texturing is performed in NaOH solution to form a pyramid textured surface on the silicon wafer. The size of the pyramid textured surface is 1-5μm, and the reflectivity of both the front and back sides should be less than 8%.

[0111] S2. Boron expansion is performed on the silicon wafer, with a boron expansion junction depth of approximately 0.5 μm.

[0112] S3. Use laser etching to create localized patterned grooves on the front side of the silicon wafer. After removing the BSG layer in the area where the patterned gate lines need to be formed, the gate line pattern is obtained.

[0113] The width of the locally patterned slot is 12 μm;

[0114] S4. A wet etching method is used to selectively etch the oxide layer on the silicon substrate surface, removing the entire back oxide layer and any residual oxide layer at the laser-processed gate lines. The back surface is then alkaline polished to achieve a reflectivity of over 40%. This back surface reflectivity setting is used to improve internal reflection, increase light utilization, reduce the contact resistance between the gate lines and the silicon substrate, and improve the fill factor. The alkaline solution is a 5% NaOH solution at 65°C.

[0115] S5. A tunnel oxide layer is prepared on both sides of the silicon wafer using a thermal oxidation process. The thickness of the tunnel oxide layer is 1.3 nm.

[0116] S6. Phosphorus-doped / boron-doped amorphous silicon layers are prepared on both sides of a silicon wafer using PECVD process. The thickness of the amorphous silicon layer is 100 nm.

[0117] S7. Anneal the silicon wafer to completely convert the amorphous silicon layer into a POLY layer. The annealing temperature is approximately 900℃.

[0118] S8. Using the electrochemical oxidation method described in this application, the POLY layer on the front side of the silicon wafer is locally oxidized to obtain a patterned oxide layer with an oxidation thickness of 80 nm.

[0119] S9. Remove the POLY layer from the non-gateline pattern area (without oxide layer) on the front side of the silicon substrate using a chain cleaning method; the cleaning alkaline solution used is NaOH solution with a concentration of 5% and a temperature of 65℃; at the same time, drip water onto the back side of the silicon substrate to form a water film to protect the back side of the silicon substrate and prevent it from being corroded.

[0120] S10. Continue etching the BSG layer under the POLY layer in the non-gateline pattern area (without oxide layer) on the front side of the silicon wafer on the chain cleaning machine to expose the texturized silicon surface; the etching solution is HF solution with a concentration of 20%.

[0121] S11. An aluminum oxide film with a thickness of 6nm is deposited on the front side of the silicon substrate using an ALD device;

[0122] S12. A silicon nitride film with a thickness of 80nm is deposited on both sides of a silicon substrate using a PECVD device.

[0123] S13. Silver paste is screen-printed on both sides of the silicon substrate and sintered to obtain a bifacial TOPCon cell.

[0124] Application Example 2

[0125] Except for the 5μm groove width in step S3, this application example is the same as Example 1.

[0126] Application Example 3

[0127] Except for the 20μm groove width in the local graphic grooving in step S3, this application example is the same as application example 1.

[0128] Application Example 4

[0129] Except for step S5, where the thickness of the tunneling oxide layer is 0.5 nm, this application example is the same as application example 1.

[0130] Application Example 5

[0131] Except for step S5, where the thickness of the tunneling oxide layer is 2 nm, this application example is the same as application example 1.

[0132] Application Example 6

[0133] Except for the fact that the oxide thickness of the POLY layer in step S8 is 50 nm, this application example is the same as application example 1.

[0134] Application Example 7

[0135] Except for the fact that the oxide thickness of the POLY layer in step S8 is 150 nm, this application example is the same as application example 1.

[0136] Comparative Application Example 1

[0137] Bifacial TOPCon cells with front-side poly layer grid lines are typically fabricated using screen printing technology.

[0138] The specific plan is as follows:

[0139] In Application Example 1, step S8 of the process is modified as follows: A masking adhesive is printed using screen printing at the locations where the poly grid lines need to be retained. This masking adhesive is typically a rubber or resin-based material mixed with fillers such as talc, and is a free-flowing colloid dispersed by volatile solvents. After printing, it is dried and set at high temperature, serving as a mask to block chemical corrosion.

[0140] In Application Example 1, step S9 is changed to: after printing the masking adhesive, the POLY layer on the non-gateline patterned area (without masking adhesive layer) of the silicon substrate is removed by a chain cleaning method. Then, the masking adhesive printed on the silicon wafer is removed using a resist remover solution.

[0141] The process remains unchanged before and after.

[0142] Compared to Application Example 1, the disadvantages are as follows: the masking adhesive is a complex organic compound, and the evaporation of organic solvents in step S8 will cause air pollution, requiring complex treatment of the exhaust gas. The masking adhesive needs to be completely removed using a desmearing solution in step S9, and the discharged waste liquid is a complex and harmful waste liquid containing a large amount of COD, which also puts pressure on the environment and requires high-cost environmental protection treatment processes for harmless treatment.

[0143] Comparative Application Example 2

[0144] Bifacial TOPCon solar cells with front-side poly layer grid lines are typically fabricated using laser direct etching technology.

[0145] The specific plan is as follows:

[0146] In Application Example 1, step S8 of the process is changed to: using a large spot laser direct writing etching machine, the part of the poly layer that needs to be removed is laser etched, and the required poly gate lines are retained.

[0147] In Application Example 1, step S9 is changed to: using wet equipment to clean the dust and residue remaining from the laser processing, fully exposing the underlying BSG layer.

[0148] The process remains unchanged before and after.

[0149] Compared to Application Example 1, the disadvantages are: the silicon wafer area required for laser processing accounts for more than 98% of the total product area, and expensive picosecond laser processing equipment is needed, requiring a large fixed investment and resulting in low processing economics. Furthermore, the substrate silicon damage caused by high-power laser processing will lead to a certain degree of product performance degradation.

[0150] Experimental Example 1

[0151] The bifacial TOPCon cells prepared in Application Examples 1 to 7 and Comparative Application Examples 1 to 2 of this application were subjected to performance tests, and the results of their electrical performance tests are shown in Table 1 below.

[0152] Table 1

[0153] As shown in Table 1 above, the bifacial TOPCon battery fabricated using the grid line patterning method for the front poly layer of the bifacial TOPCon battery in this application maintains the same level of battery conversion efficiency as bifacial TOPCon batteries fabricated using existing screen printing and laser direct etching methods for obtaining the poly layer grid lines. Furthermore, the fabrication process of the front poly layer grid lines in the bifacial TOPCon battery of this application eliminates the need for indirect auxiliary materials such as screen printing inks and photoresists, significantly reducing production costs and eliminating the generation of environmentally sensitive waste. Compared to existing technologies, this method offers both economic efficiency and environmental friendliness.

[0154] This disclosure also provides the following notes:

[0155] 1. A method for patterning the grid lines of the front poly layer of a double-sided TOPCon battery, wherein the grid line patterning method includes:

[0156] (A) Texturing the silicon substrate on both sides;

[0157] (B) Boron-expanded BSG layer is obtained by front-side boron expansion;

[0158] (C) The boron-expanded BSG layer is locally patterned and grooved. After removing the BSG layer in the part where the patterned grid lines need to be formed, the grid line pattern is obtained.

[0159] (D) Deposit a tunnel oxide layer and a poly layer on the grooved silicon substrate to obtain an intermediate solar cell;

[0160] (E) A silicon oxide hard mask is generated at the corresponding positions of the trenching and tunneling oxidation of the intermediate battery cell using an electrochemical oxidation method, wherein:

[0161] In the electrochemical oxidation method, the electrolyte serves as the cathode, the intermediate battery cell serves as the anode, and the electrolyte circulates between the cathode and anode.

[0162] (F) The battery cell after electrochemical oxidation is chemically etched to remove the non-oxidized poly layer and obtain the grid pattern of the front poly layer.

[0163] 2. The grid patterning method according to claim 1, wherein the slot width of the local patterned slot in step (C) is 5 to 20 μm.

[0164] 3. The gate patterning method according to claim 1, wherein the thickness of the tunneling oxide layer in step (D) is 0.5 to 2 nm.

[0165] 4. The gate patterning method according to claim 1, wherein the thickness of the poly layer in step (D) is 50-150 nm.

[0166] 5. The grid patterning method according to claim 1, wherein the electrochemical oxidation method includes: constant current method or constant voltage method.

[0167] 6. The grid line patterning method according to claim 5, wherein the electrolyte of the electrochemical oxidation method is mainly prepared from dilute sulfuric acid, oxalic acid or sodium hydroxide.

[0168] 7. The grid patterning method according to claim 1, wherein the method further includes a step of cleaning the intermediate battery cell before the electrochemical oxidation treatment in step (E).

[0169] 8. The grid patterning method according to claim 1, wherein the method further includes a step of cleaning the battery cell after the electrochemical oxidation treatment in step (E) to remove residual electrolyte.

[0170] 9. The grid patterning method according to claim 1, wherein the chemical etching solution in step (F) is a sodium hydroxide or potassium hydroxide solution with a concentration of 5%-10%.

[0171] 10. A bifacial TOPCon battery, wherein the front poly layer grid structure of the bifacial TOPCon battery is mainly prepared by the grid patterning method described in any one of Appendices 1 to 9.

[0172] Although this disclosure has been illustrated and described with reference to specific embodiments, it should be understood that many other changes and modifications can be made without departing from the spirit and scope of this disclosure. Therefore, it is intended that all such changes and modifications falling within the scope of this disclosure be included in the appended claims.

Claims

1. A method for preparing a patterned silicon oxide mask, characterized in that, include: A patterned silicon oxide mask is formed on the surface of a silicon substrate by electrochemical oxidation. In the electrochemical oxidation method, the patterned electrode serves as the cathode, the silicon substrate serves as the anode, and an electrolyte is present between the cathode and the anode.

2. The preparation method according to claim 1, characterized in that, The electrochemical oxidation method includes: The patterned electrode is brought close to the silicon substrate, with the patterned side of the patterned electrode facing the side of the silicon substrate to be patterned. An electrolyte is filled between the patterned electrodes and the silicon substrate to form a circuit; By energizing the circuit, a patterned silicon oxide mask is formed on the surface of the silicon substrate.

3. The preparation method according to claim 1 or 2, characterized in that, The patterned electrode includes a patterned oxidized region and a patterned non-oxidized region; The oxidized areas of the pattern are made of conductive materials, while the non-oxidized areas are made of insulating materials.

4. The preparation method according to claim 3, characterized in that, The silicon oxide mask is formed on the surface of the silicon substrate at a location corresponding to the patterned oxide region in the patterned electrode.

5. The preparation method according to claim 1 or 2, characterized in that, The distance between the patterned electrode and the silicon substrate is less than the minimum linewidth of the pattern formed on the silicon substrate surface.

6. The preparation method according to claim 1 or 2, characterized in that, The electrolyte flows between the silicon substrate and the patterned electrodes via a circulation device.

7. The preparation method according to claim 1 or 2, characterized in that, The electrolyte includes an electrolyte; The electrolyte includes any one or a combination of at least two of sulfuric acid, oxalic acid, or sodium hydroxide.

8. The preparation method according to claim 1 or 2, characterized in that, The circuit is energized by means of an external DC power supply.

9. The preparation method according to claim 1 or 2, characterized in that, After the patterned silicon oxide mask is formed, the process further includes cleaning the silicon substrate to remove residual electrolyte.

10. A graphical method for representing a TOPCon battery, characterized in that, include: A poly layer is deposited on the front side of the silicon substrate; The silicon oxide gate line pattern is formed on the surface of the poly layer by selective oxidation using the preparation method described in any one of claims 1 to 9; The poly layer on the silicon substrate surface that has not formed an etching mask is removed by chemical etching to obtain the gate line pattern of the front poly layer.

11. The graphical method according to claim 10, characterized in that, The thickness of the poly layer is 50–150 nm.

12. The graphical method according to claim 10, characterized in that, Prior to selective oxidation, this includes a step of cleaning the silicon substrate.

13. The graphical method according to claim 10, characterized in that, The following steps are included before depositing the poly layer on the front side of the silicon substrate: (A) Texturing the silicon substrate on both sides; (B) Boron-expanded BSG layer is obtained by front-side boron expansion; (C) The boron-expanded BSG layer is locally patterned and grooved. After removing the BSG layer in the part where the patterned grid lines need to be formed, the grid line pattern is obtained. (D) Deposit a tunnel oxide layer on the grooved silicon substrate.

14. The graphical method according to claim 11, characterized in that, The width of the locally patterned slot in step (C) is 5–20 μm.

15. The graphical method according to claim 11, characterized in that, The thickness of the tunneling oxide layer in step (D) is 0.5–2 nm.

16. A TOPCon battery, characterized in that, The TOPCon battery is prepared by the patterning method as described in any one of claims 10 to 15.

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