Packaging structure, semiconductor structure, and electronic device

Abstract

A packaging structure, a semiconductor structure, and an electronic device. The packaging structure comprises: a substrate; a first pin array, which is arranged on the substrate and comprises a plurality of first data pins; and a second pin array, which is arranged on the substrate and comprises a plurality of second data pins. A blank area is provided between the first pin array and the second pin array, the blank area extends from the center of the substrate to the edge of the substrate, the end of the blank area is located on the outer side of the first pin array, at least one first data pin and / or at least one second data pin is adjacent to the blank area, and the minimum size of the blank area is larger than the diameter of the first data pin. The size of the packaging structure is small.

Description

Packaging structures, semiconductor structures and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202410675094.6, filed on May 27, 2024, entitled "Packaging Structure, Semiconductor Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a packaging structure, semiconductor structure, and electronic device. Background Technology

[0003] With the advancement of technology, end users expect their devices to be smaller, faster, more energy-efficient, and have higher performance. The miniaturization and multi-functionality of electronic terminal products have become a major trend in industrial development.

[0004] In related technologies, existing packaging structures are too large to be applied to miniaturized electronic devices.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a packaging structure is provided, comprising:

[0007] Base;

[0008] A first pin array is disposed on the substrate, and the first pin array includes a plurality of first data pins;

[0009] A second pin array is disposed on the substrate, and the second pin array includes a plurality of second data pins;

[0010] A blank area is provided between the first pin array and the second pin array. The blank area extends from the center of the substrate to the edge of the substrate. The end of the blank area is located outside the first pin array. At least one first data pin and / or at least one second data pin is adjacent to the blank area. The minimum size of the blank area is greater than the diameter of the first data pin.

[0011] In some embodiments, in the first pin array, the number of first data pins in the Kth row is greater than the number of first data pins in the Lth row; wherein the Kth row is adjacent to the blank area, and the Lth row is adjacent to the Kth row.

[0012] In some embodiments, in the second pin array, the number of second data pins in the Mth row is greater than the number of second data pins in the Nth row; wherein the Mth row is adjacent to the blank area, and the Nth row is adjacent to the Mth row.

[0013] In some embodiments, the first data pin in row K is set opposite to or offset from the second data pin in row M, and the first data pin in row L is set opposite to the second data pin in row N.

[0014] In some embodiments, in the Nth row, at least one of the second data pins is adjacent to the blank area.

[0015] In some embodiments, in the Kth row, a first power supply pin is provided between adjacent first data pins; in the Mth row, a second power supply pin is provided between adjacent second data pins; wherein the first power supply pin is used to transmit a first voltage, the second power supply pin is used to transmit a second voltage, and the first voltage is higher than the second voltage.

[0016] In some embodiments, in the first pin array, up to three first power supply pins are arranged adjacent to each other in the column direction; in the second pin array, up to two first power supply pins are arranged adjacent to each other in the row direction.

[0017] In some embodiments, the first data pin is used to transmit higher-order data byte signals, and the second data pin is used to transmit lower-order data byte signals; or, the first data pin is used to transmit lower-order data byte signals, and the second data pin is used to transmit higher-order data byte signals.

[0018] In some embodiments, the first pin array further includes:

[0019] The first read strobe pin is spaced apart from the first data pin.

[0020] The first write clock pin is spaced apart from the first data pin.

[0021] The first power supply pin and the second power supply pin are provided between the first read strobe pin and the first write clock pin.

[0022] In some embodiments, the first write clock pin is adjacent to the blank area.

[0023] In some embodiments, the second pin array further includes:

[0024] The second read strobe pin is spaced apart from the second data pin.

[0025] The second write clock pin is spaced apart from the second data pin.

[0026] The second read strobe pin and the second write clock pin are staggered, and at least one of the second read strobe pins is adjacent to at least one of the second write clock pins.

[0027] In some embodiments, the second read strobe pin is adjacent to the first power supply pin, and the second write clock pin is adjacent to the second power supply pin.

[0028] In some embodiments, the substrate is provided with:

[0029] The third pin array includes multiple control pins;

[0030] At least one of the control pins is adjacent to the blank area.

[0031] In some embodiments, the control pin includes a plurality of command address pins, wherein at most two of the command address pins are arranged adjacent to each other; at least one of the command address pins is adjacent to the blank area.

[0032] In some embodiments, the second power supply pin in the first pin array is adjacent to the command address pin in the third pin array; the first power supply pin in the second pin array is adjacent to the control pin in the third pin array.

[0033] In some embodiments, the command address pin and the first write clock pin are located on opposite sides of the blank area.

[0034] According to a second aspect of the present disclosure, a semiconductor structure is provided, including: the above-described packaging structure and a chip disposed on the packaging structure.

[0035] According to a third aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0036] A circuit board having a first chip disposed thereon, a blank area on the circuit board, and metal lines disposed on the surface of the blank area;

[0037] The above-described packaging structure is disposed on the circuit board, and the blank area in the packaging structure corresponds to the blank area;

[0038] The second chip is disposed on the package structure;

[0039] The first chip is electrically connected to the second chip via the metal wire.

[0040] In summary, the embodiments of this disclosure provide a packaging structure, a semiconductor structure, and an electronic device. The packaging structure includes a substrate and a first pin array and a second pin array. By providing a blank area between the first and second pin arrays—that is, by not providing pins between the first and second pin arrays—the first and second pin arrays are separated. Therefore, the number of pins on the substrate is reduced, and the pin spacing can be decreased, thereby reducing the area of ​​the substrate and, consequently, the area of ​​the packaging structure. This allows the packaging structure to be applied to miniaturized electronic products. Attached Figure Description

[0041] Figure 1 is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment;

[0042] Figure 2 is a top view of Figure 1 according to an exemplary embodiment;

[0043] Figure 3 is a rear view of Figure 1 according to an exemplary embodiment;

[0044] Figure 4 is a cross-sectional view of Figure 3 along the AA direction according to an exemplary embodiment;

[0045] Figure 5 is a schematic diagram illustrating a packaging structure according to an exemplary embodiment;

[0046] Figure 6 is a schematic diagram of pins according to an exemplary embodiment;

[0047] Figure 7 is a schematic diagram of a blank area according to an exemplary embodiment;

[0048] Figure 8 is a schematic diagram illustrating the pin spacing according to an exemplary embodiment;

[0049] Figure 9 is another schematic diagram of pins according to an exemplary embodiment;

[0050] Figure 10 is another schematic diagram of pins according to an exemplary embodiment;

[0051] Figure 11 is an overall structural diagram of the substrate according to an exemplary embodiment;

[0052] Figure 12 is a schematic diagram of a pin architecture according to an exemplary embodiment;

[0053] Figure 13 is another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0054] Figure 14 is a schematic diagram of an electronic device according to an exemplary embodiment;

[0055] Figure 15 is a top view of Figure 14 according to an exemplary embodiment;

[0056] Figure 16 is a comparison diagram of plastic strain of a packaging substrate according to an exemplary embodiment;

[0057] Figure 17 is a comparison chart of the test performance of a packaging substrate according to an exemplary embodiment. Detailed Implementation

[0058] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0059] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0060] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0061] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0062] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0063] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0064] As shown in Figure 1, this disclosure provides a semiconductor structure 10, which includes a packaging substrate 11 and memory chips 12. Multiple memory chips 12 are disposed on the packaging substrate 11, for example, two, four, eight, or more memory chips 12 may be disposed. These memory chips 12 are stacked, for example, the two memory chips 12 in Figure 1 are stacked, with the upper memory chip 12 offset above the lower memory chip 12. Each memory chip 12 may include multiple memory cells connected to word lines and bit lines. For example, each of the multiple memory cells may be or correspond to a dynamic random access memory (DRAM) cell, and the memory chip 12 may be, for example, low-power double data rate (LPDDR) memory, such as fifth-generation low-power double-rate memory (LPDDR5 / 5X).

[0065] As shown in Figure 1, the memory chip 12 is connected to the packaging substrate 11 via gold wires 13 to achieve signal transmission. Each memory chip 12 corresponds to a signal channel; for example, the lower memory chip 12 corresponds to the first signal channel 14 (Channel A, CHA), and the upper memory chip 12 corresponds to the second signal channel 15 (Channel B, CHB). Both the first signal channel 14 and the second signal channel 15 have independent data signals, chip select signals, and clock enable signals, thus making them relatively independent. When this semiconductor structure 10 is applied, the memory controller can send data signals to the memory chip 12 via the data bus. The data signals are transmitted to the lower memory chip 12 via the first signal channel 14 and the gold wires 13, and the data signals are transmitted to the upper memory chip 12 via the second signal channel 15 and the gold wires 13.

[0066] As shown in Figures 1 and 2, Figure 2 is a simplified top view of Figure 1. A solder pad 16 is provided on the front side of the packaging substrate 11. The solder pad 16 is disposed, for example, on the edge of the packaging substrate 11. Gold wires 13 connect the solder pad 16 and the memory chip 12, thereby realizing signal transmission. In some embodiments, the same solder pad 16 can also be connected to multiple memory chips 12, i.e., multiple memory chips 12 are connected through multiple gold wires 13, thereby realizing a signal channel connected to multiple memory chips 12.

[0067] As shown in Figures 3 and 4, Figure 3 shows a schematic diagram of the back side of the packaging substrate 11, and Figure 4 shows a cross-sectional view of Figure 3 along the AA direction. Multiple pins 111 are disposed on the back side of the packaging substrate 11, and these pins 111 can be arranged in an array. The pins 111 can be solder balls or bumps. These pins 11 can transmit different signals, such as data quality (DQ) signals, chip select (CS) signals, etc. The pins 111 are connected to the pads 16 through internal traces 112 in the packaging substrate 11, and then the pads 16 are connected to the memory chip 12 through gold wires 13, thereby transmitting the signals to the memory chip 12. In some embodiments, due to the large number of pins 111 (e.g., 315 pins) and the large pitch between the pins 111, the overall package size of the semiconductor structure 10 is large, making it unsuitable for miniaturized electronic products.

[0068] As shown in Figure 5, this embodiment of the present disclosure proposes a packaging structure 20, which can be the aforementioned packaging substrate 11. The packaging structure 20 has a relatively small number of pins, reducing the spacing between pins, thereby reducing the size of the packaging structure 20 and enabling its application in miniaturized electronic products. This embodiment of the present disclosure also re-arranges the pins, resulting in good performance for the packaging structure 20, enabling it to provide good signal transmission for the chip and ensuring its normal operation.

[0069] As shown in Figure 5, this embodiment of the present disclosure proposes a packaging structure 20, which includes a substrate 21, a first pin array 30, a second pin array 40, and a third pin array 60. The first pin array 30, the second pin array 40, and the third pin array 60 are located on the substrate 21, for example, they can be disposed on the back side of the substrate 21. A blank region 50 is provided between the first pin array 30 and the second pin array 40. No pins are provided in the blank region 50, that is, the first pin array 30 and the second pin array 40 are separated by the blank region 50. The blank region 50 extends from the center of the substrate 21 to the edge of the substrate 21, and the end of the blank region 50 is outside the first pin array 30. That is, in the row direction, the length of the blank region 50 is greater than the length of the first pin array 30. At the same time, in the row direction, the length of the blank region 50 is greater than the length of the second pin array 40. A plurality of first signal pins 31 are provided in the first pin array 30, and a plurality of second signal pins 41 are provided in the second pin array 40. The first signal pins 31 and the second pin array 41 are respectively adjacent to the blank region 50. Therefore, when the package structure 20 is mounted on the PCB, the blank area 50 will form a corresponding blank area on the PCB. Thus, the first signal pin 31 and the second pin array 41 are adjacent to the blank area, so wiring can be carried out in the blank area, so that the wiring is connected to the first signal pin 31 and the second pin array 41, thereby enabling signal transmission.

[0070] As shown in Figure 5, in this embodiment of the present disclosure, the length of the blank area 50 is greater than the length of the first pin array 30 in the row direction. In the column direction, the minimum size of the blank area 50 is greater than the diameter of the first signal pin 31, and the minimum size of the blank area 50 is greater than the pitch between two adjacent first signal pins 31. Therefore, the blank area 50 has a large area, thus forming a large blank area on the PCB. Multiple traces are designed in this blank area, and the spacing between these traces is also increased, thereby improving crosstalk between signals.

[0071] As shown in Figure 5, in this embodiment of the present disclosure, at least one first signal pin 31 in the first pin array 30 is adjacent to the blank area 50, and at least one second signal pin 41 in the second pin array 40 is adjacent to the blank area 50. The first signal pin 31 and the second signal pin 41 can be adjacent to the blank area 50 simultaneously. Of course, either the first signal pin 31 or the second signal pin 41 can be adjacent to the blank area 50.

[0072] As shown in Figures 4 and 5, in this embodiment of the present disclosure, a pad 16 is provided on the front side of the substrate 21, and an internal trace 112 is provided in the substrate 21. The internal trace 112 is connected to the pad 16, and the internal trace 112 is also connected to the first signal pin 31, the second signal pin 41, or other pins, thereby realizing signal transmission.

[0073] Figure 6 shows a rear view of substrate 21. A first pin array 30 is located at the upper left of substrate 21, a second pin array 40 is located below substrate 21, and a third pin array 60 is located below substrate 21. A blank area 50 exists between the first pin array 30 and the second pin array 40, in which no pins are placed, thus separating the first pin array 30 and the second pin array 40. Viewed in the row direction (horizontal direction), the first pin array 30 has 8 columns of pins. Viewed in the column direction (vertical direction), the first pin array 30 has 5 rows of pins. The first pin array 30 can include a maximum of 40 pins, but to improve the pin routing in the third pin array 60, some pins are reduced in the first pin array 30, for example, by 2 pins, thus the first pin array 30 includes 38 pins. In this embodiment, two pins are reduced in the column adjacent to the third pin array 60 in the first pin array 30 (the 8th column of the first pin array 30). Since the number of pins is reduced, the area of ​​the blank area 50 is increased, which means the area of ​​the wiring on the PCB is increased.

[0074] As shown in Figure 6, a plurality of first signal pins 31 are provided in the first pin array 30, and at least one pin can be provided between these first signal pins 31. For example, in the first column, a pin is provided between two first signal pins 31. In the second row, a pin is provided between two first signal pins 31. In this embodiment, the first signal pins 31 can be used to transmit high-bandwidth data signals (Data Quality, DQ). When transmitting DQ signals, the first signal pins 31 generate a magnetic field. If two first signal pins 31 are set consecutively, the generated magnetic fields will overlap between the two signal pins. The overlapping magnetic fields will induce electric current in the first signal pins 31, thereby generating signal crosstalk and degrading signal quality. As can be seen from Figure 6, a first signal pin 31 can be diagonally adjacent to another first signal pin 31, that is, in the horizontal and vertical directions, two first signal pins 31 are not set consecutively. This can increase the dissipation space of the magnetic field, reduce magnetic field overlap, and reduce signal crosstalk.

[0075] As shown in Figure 6, in this embodiment of the disclosure, the first pin array 30 is provided with eight first signal pins 31. The number of first signal pins 31 in the rows adjacent to the blank area 50 in the first pin array 30 is relatively large. Rows 1 to 5 are sequentially adjacent, and row 5 is adjacent to the blank area 50. Therefore, row 5 is defined as row K, and row 4, which is adjacent to row 5, is defined as row L. Thus, the number of first signal pins 31 in row K is greater than the number of first signal pins 31 in row L, which facilitates routing for more first signal pins 31. For example, row 5 has 3 first signal pins 31, row 4 has 1 first signal pin 31, row 3 has 2 first signal pins 31, and row 2 has 2 first signal pins 31. Since row 5 has the largest number of first signal pins 31, meaning more first signal pins 31 are adjacent to the blank area 50, it facilitates routing for more first signal pins 31. In this embodiment, the positions of the first signal pins 31 are rearranged so that the positions of these first signal pins 31 are relatively concentrated and closer to the edge of the substrate 21, thereby reducing signal loss.

[0076] As shown in Figure 6, in this embodiment, the second pin array 40 is disposed on one side of the blank area 50, that is, the second pin array 40 and the first signal pin 30 are located on opposite sides of the blank area 50. From the row direction, the second pin array 40 includes 13 columns of pins; from the column direction, the second pin array 40 includes 4 rows of pins. The second pin array 40 includes a maximum of 52 pins. Since the number of pins in the second pin array 40 is greater than the number of pins in the first pin array 30, and the length of the second pin array 40 in the row direction is greater than the length of the first pin array 40 in the row direction, some pins are reduced in the rows adjacent to the blank area 50 in the second pin array 40 to improve the pin routing problem. In this embodiment, the pins near the left edge of the substrate 21 in the 8th row are reduced, that is, some pins adjacent to the blank area 50 are reduced, thereby forming a larger blank area 50. This allows the blank area 50 to extend into the second pin array 40. The increased area of ​​the blank area 50 facilitates the routing of the second signal pin 41 in the second pin array 40. Meanwhile, in this embodiment, the pins at the positions of the 1st column and the 10th row are also removed, thereby indirectly increasing the area of ​​the blank area 50, which also helps with the wiring of the second signal pin 41.

[0077] As shown in Figure 6, in this embodiment of the present disclosure, the second pin array 40 includes a plurality of second signal pins 41. The arrangement of the second signal pins 41 can refer to the arrangement of the first signal pins 31, and the arrangement rules of the first signal pins 31 can be applied to the arrangement rules of the second signal pins 41. In this embodiment of the present disclosure, the second signal pins 41 are used to transmit high-bandwidth signal data, and the second signal pins 41 are used to transmit high-bandwidth data signals (Data Quality, DQ). The second pin array 40 includes eight second signal pins 41, and the number of second signal pins 41 in the rows adjacent to the blank area 40 is relatively large. These second signal pins 41 are respectively arranged in rows 8 to 11, and rows 8 to 11 are sequentially adjacent. Row 8 is adjacent to the blank area 50. There are 3 second signal pins 41 in row 8, 1 second signal pin 41 in row 9, 2 second signal pins 41 in row 10, and 2 second signal pins 41 in row 11. The number of second signal pins 41 in row 8 is greater than the number of second signal pins 41 in row 9, thus facilitating the routing of a larger number of second signal pins 41. In this embodiment, row 8 is defined as row M and row 9 as row N, therefore the number of second signal pins 41 in row M is greater than the number of second signal pins 41 in row N. Simultaneously, since the blank area 50 extends into the second pin array 40, at least one second signal pin 41 in row 9 (row N) can be adjacent to the blank area 50, further facilitating the routing of that second signal pin 41. Of course, by arranging the second signal pins 41 in the second pin array 40, more second signal pins 41 can be placed in row N, and more second signal pins 41 can be adjacent to the blank area 50. It should be noted that although the second signal pins 41 in row 9 are adjacent to the blank area 50, there are still pins from row 8 between other pins in row 9 and the blank area 50; therefore, in this embodiment, row 9 is not defined as adjacent to the blank area 50.

[0078] As shown in FIG6, in this embodiment of the present disclosure, these second signal pins 41 are relatively concentrated, for example, distributed in columns 2 to 7. That is, in the row direction, the distance from the left edge of the substrate 21 to the second signal pin 41 (the second signal pin 41 in the 7th column) does not exceed the length of the blank area 50, so the wiring of the second signal pin 41 can be shortened.

[0079] As shown in Figure 6, in this embodiment of the present disclosure, the first signal pin 31 is used to transmit the DQ signal, and the second signal pin 41 is used to transmit the DQ signal. Therefore, some of the first signal pins 31 and some of the second signal pins 41 can be symmetrical about the blank area 50. For example, the first signal pins 31 in the 5th row (columns 3 and 5) and the second signal pins 41 in the 8th row (columns 3 and 5) are symmetrical, that is, they are arranged opposite each other. Therefore, the wiring of the first signal pins 31 and the second signal pins 41 can be symmetrical, and the wiring process is relatively simple. Of course, the first signal pins 31 in the 5th row (e.g., the Kth row) (column 1) and the second signal pins in the 8th row (e.g., the Mth row) (column 7) are staggered about the blank area 50. Because they are staggered, the spacing between the wiring can be larger during wiring to prevent the wiring distance from being too close, which would cause signal crosstalk. Of course, the first signal pin 31 (column 2) in row 4 (e.g., row L) and the second signal pin 41 (column 2) in row 9 (e.g., row N) are set relative to each other. It should be noted that M, N, K, and L are all positive integers greater than or equal to 1.

[0080] As shown in Figure 6, the first signal pin 31 and the second signal pin 41 belong, for example, to the first signal channel 14 (shown in Figure 1). Therefore, the first signal channel 14 can include 16 signal pins, for example, a total of 16 signal pins from DQ0_A to DQ15_A, where A represents the first signal channel. In this embodiment, 8 signal pins from DQ0_A to DQ7_A are used to transmit low-order data byte signals (byte0). 8 signal pins from DQ8_A to DQ15_A are used to transmit high-order data byte signals (byte1). When the package substrate 20 is mounted on a circuit board, the signals of the package substrate 20 need to match the signals of the control chip (CPU). Since the signal pins on the CPU are fixed, to prevent metal wiring from crossing on the circuit board, the first signal pin 31 is used to transmit high-order data byte signals, and the second signal pin 41 is used to transmit low-order data byte signals. This allows the package structure 20 to better match the CPU and ensures normal signal transmission. In some embodiments, the first signal pin 31 can also be used to transmit low-order data byte signals, and the second signal pin 41 can also be used to transmit high-order data byte signals.

[0081] As shown in Figure 6, the third pin array 60 is located at the upper right of the substrate 21. In the row direction, the third pin array 60 includes 5 columns of pins, and in the column direction, it includes 7 rows of pins, thus the third pin array can include 35 pins. In this embodiment, the pins in the 5th row and 13th column are removed, which facilitates the subsequent routing of control pins; therefore, the third pin array 60 includes 34 pins. The third pin array 60 includes multiple control pins, such as the command address pin 61 (Command / Address, CA) and the chip select pin 62 (Chip Select, CS). The command address pin 61 can receive a read address or a write address. The read address indicates which row and column of the memory array to read, and the write address indicates which row and column of the memory array to write to. The chip select pin 62 is used to transmit the chip select signal. The memory controller selects the corresponding chip (die) through the chip select signal, thereby independently transmitting data, address, or command to the selected chip.

[0082] As shown in Figure 6, the third pin array 60 includes seven command address pins 61, such as CA0_A to CA6_A, where A represents the first signal channel. In the row direction, two command address pins 61 can be arranged adjacently, meaning two command address pins 61 can be arranged consecutively. Since the command address pins 61 are used to transmit control signals, and the frequency of these control signals is low, two command address pins 61 can be arranged adjacently. To prevent crosstalk between control signals, at most two command address pins 61 are arranged adjacently in the row direction, and in the vertical direction, the command address pins 61 are spaced apart, thereby preventing four command address pins 61 from being arranged adjacently, which would cause significant signal crosstalk. In the column direction, at least one command address pin 61 is adjacent to the blank area 50, which facilitates routing of the command address pin 61. In some embodiments, if the pins in the 8th row of the first pin array 30 are removed, two command address pins 61 in the third pin array 60 will be adjacent to the blank area 50, which facilitates routing of the command address pins 61.

[0083] As shown in Figure 6, the third pin array 60 includes two chip select signal pins 62, such as CS1_A and CS0_A. CS0_A represents the first chip (Chip0) under the first signal channel, and CS1_A represents the second chip (Chip1) under the first signal channel. These two chip select signal pins 62 are arranged adjacent to each other in the row direction. One chip select signal pin 62 can be adjacent to a blank area 50, which facilitates routing of that chip select signal pin 62. In this embodiment, to facilitate routing of the chip select signal pin 62, the chip select signal pin 62 is spaced far from the command address pin 61. In some embodiments, the chip select signal pin 62 can also be arranged adjacent to the command address pin 61, thereby achieving better timing matching between the chip select signal and the command address signal.

[0084] As shown in Figure 7, this embodiment creates a blank area 50 by removing some pins and rearranging the positions of the first signal pins 31, thereby increasing the number of first signal pins 31 adjacent to the blank area 50 and improving the routing of the first signal pins 31. Since there are gaps between the pins, after removing some pins, the minimum size of the blank area 50 is greater than the diameter of the pins. For example, in Figure 7, in the row direction, the pins in the 8th column and 4th row are removed. At this time, the minimum size d1 of the blank area 50 is greater than the diameter of the pins, resulting in a larger area for the blank area 50. This corresponds to a larger routing area on the PCB, which is beneficial for pin routing. Similarly, in the row direction, the pins in the 8th column and 5th row are removed. In this case, the distance d2 between the pins in the 7th and 9th columns of the 5th row can also be defined as the minimum size of the blank area 50, and this distance d2 is also greater than the diameter of the pins. In the column direction, pins in rows 6-7 and columns 3-7 are removed. Therefore, the distance between the pins in rows 5 and 4 and the pins in rows 8 and 4 is d3. This distance d3 is greater than the distance d2. Similarly, the distance d4 is greater than the distance d3. In this embodiment, the blank area 50 extends from the center of the substrate 21 to the edge. For example, in the row direction, the blank area 50 extends from column 1 to column 8. At the same time, the end of the blank area 50 extends to the edge. That is, in the row direction, the length of the blank area 50 is greater than the length of the first pin array 30. Therefore, when routing, the blank area 50 will form a corresponding blank area on the PCB. The length of the blank area is greater than the length of the first pin array 30. Therefore, when routing in the blank area, there are no pins to block it, so routing can be performed on the surface of the PCB instead of inside the PCB, thus simplifying the routing process.

[0085] As shown in Figures 7 and 8, the width of the blank area 50 gradually decreases in the row direction, for example, from spacing d4 to spacing d3 and then to spacing d2 or d1. During routing, the shape of the blank area on the PCB is the same as that of the blank area 50. A large number of traces need to extend from the edge of the blank area into the blank area and then connect to the various pins. Therefore, the width at the end of the blank area 50 is relatively wide, and the width of the blank area on the PCB is also relatively wide, making the spacing of the traces at the edge of the blank area more suitable, which is beneficial to the routing process and reduces signal crosstalk. In the row direction, the spacing between adjacent pins (e.g., the first signal pin 31) is d5. In the column direction, the spacing between adjacent pins (e.g., the first signal pin 31) is d6. In the row direction, the minimum size d1 or d2 of the blank area 50 is greater than the spacing d5. In the column direction, the spacing d3 or d4 of the blank area 50 is greater than the spacing d6. Therefore, the spacing between adjacent pins cannot be defined as a blank area. That is, in this embodiment, the minimum size of the blank area 50 is greater than the spacing between adjacent pins. At the same time, the minimum size of the blank area 50 must also be greater than the diameter of the pin. In this embodiment, the pin diameter is, for example, 350 micrometers, the spacing d5 is, for example, 600 micrometers, and the spacing d6 is, for example, 500 micrometers. Due to the existence of the blank area 50, the number of pins on the substrate 21 is reduced, thus the pin spacing can be relatively reduced, and the size of the substrate 21 can be reduced. At the same time, due to the reduction in pin spacing, the wiring length is also reduced, thus reducing signal loss.

[0086] As shown in Figure 9, in some embodiments of this disclosure, both the first pin array 30 and the second pin array 40 are provided with power supply pins. The first pin array 30 and the second pin array 40 are provided with a first power supply pin 32 and a second power supply pin 33. The first power supply pin 32 and the first signal pin 31 are arranged adjacent to each other, and the second power supply pin 33 can also be arranged adjacent to the first signal pin 31. For example, in the 5th row (the Kth row), in the row direction, the pins in the 1st to 6th columns are respectively the first signal pin 31, the second power supply pin 33, the first signal pin 31, the first power supply pin 32, the first signal pin 31, and the second power supply pin 33. The first power supply pin 32, for example, transmits a first voltage, and the second voltage pin 33, for example, transmits a second voltage. The first voltage can be greater than the second voltage; the first voltage is, for example, 0.5V, and the second voltage is, for example, ground voltage (0V). The first power supply pin 32 can be distributed among the first signal pins 31, and the second power supply pin 33 can also be distributed among the first signal pins 31. Since the voltages of the first power supply pins 32 and 33 are relatively small, they can absorb the magnetic field generated by the first signal pins 31, thereby reducing crosstalk between the first signal pins 31. Similarly, in the second pin array 40, the first power supply pins 32 and 33 are also distributed among the second signal pins 41. The first power supply pins 32 and 33 can also absorb the magnetic field generated by the second signal pins, thereby reducing crosstalk between the second signal pins 41.

[0087] As shown in Figure 9, in this embodiment, the first power supply pins 32 can be arranged continuously. In the first pin array 30, three first power supply pins 32 are arranged continuously in the fourth column. Since this application first designs the position of the first signal pin 31, and then sets the first power supply pins 32 and second power supply pins 33 between the first signal pins 31, the first power supply pins 32 and second power supply pins 33 can be distributed among the first signal pins 31. At the same time, since the first power supply pins 32 are relatively close to the edge of the substrate 21 and the first power supply pins 32 are interconnected, setting three first power supply pins 32 continuously can increase the stability of the power supply. If more (four or more) first power supply pins 32 are arranged continuously, the size of the first pin array 30 will increase, resulting in an increase in the area of ​​the substrate 21, which is not conducive to improving the size of the substrate 21. Therefore, in the column direction, up to three first power supply pins 32 can be arranged adjacently in the first pin array 30. Of course, in the row direction, up to three first power supply pins 32 can be arranged adjacently in the first pin array 30. Of course, the first power supply pin 32 can also be distributed in the first pin array 30, that is, the first power supply pin 32 is arranged at intervals.

[0088] As shown in Figure 9, in the second pin array 40, the first power supply pin 32 and the second power supply pin 33 can be distributed among the second signal pins 41, thereby improving crosstalk between the second signal pins 41. Meanwhile, in the 8th row (Mth row), the pins in columns 3 to 8 are the first signal pin 41, the second power supply pin 33, the second signal pin 41, the second power supply pin 33, the second signal pin 41, and the second power supply pin 33. Since the second power supply pin 33 transmits ground voltage, it can better absorb the magnetic field of the second signal pin 41, thereby further reducing crosstalk between the second signal pins 41. Furthermore, the second pin array 40 is located at the lower part of the substrate 21, and the first voltage is transmitted from the upper part of the substrate 21 to the lower part, i.e., from the column direction. Therefore, the first voltage in the second pin array 40 is relatively stable, and two first power supply pins 32 can be arranged consecutively in the second pin array 40, instead of three or more consecutively arranged.

[0089] As shown in Figure 9, in row 5, first power supply pins 32 are arranged between first signal pins 31. In row 8, second power supply pins 33 are arranged between second signal pins 41. Since row 5 is closer to the upper part of substrate 21 and row 8 is located at the lower part of substrate 21, in order to ensure the stability of the first voltage, this embodiment of the present disclosure arranges three consecutively arranged first power supply pins 32 in the first pin array 30, thereby ensuring the stability of the first voltage. Therefore, in row 5, the first signal pins 31 can be isolated by the first power supply pins 32. In the second pin array 40, the first voltage is relatively stable. In order to further reduce the crosstalk of the second signal pins 41, the second signal pins 41 can be isolated by the second power supply pins 33 in row 8. At the same time, the second power supply pins 33 are also located in the third pin array 60, and the second power supply pins 33 are adjacent to the command address pin 61 and the chip select signal pin 62, thereby reducing the crosstalk between these signals.

[0090] As shown in Figure 10, the first pin array 30 also includes a first read strobe pin 34 and a first write clock pin 35. The first read strobe pin 34 can be associated with a first signal pin 31, and the first write clock pin 35 can be associated with the first signal pin 31. The first read strobe pin 34 and the first signal pin 31 are spaced apart and separated by a second power supply pin 33, thereby reducing signal crosstalk between them. The first write clock pin 35 and the first signal pin 31 are adjacent in a diagonal direction, meaning they are not adjacent in the row or column directions. Therefore, the spacing between the first signal pin 31 and the first write clock pin 35 is relatively large, reducing the magnetic field coupling between them and thus improving signal crosstalk. Meanwhile, the first read strobe pin 34 and the first write clock pin 35 are isolated by a first power supply pin 32 and a second power supply pin 33. That is, the first power supply pin 32 and the second power supply pin 33 are located at the first read strobe pin 34 and the first write clock pin 35, respectively. Therefore, the first power supply pin 32 and the second power supply pin 33 can absorb the magnetic fields generated by the first read strobe pin 34 and the first write clock pin 35, thereby reducing signal crosstalk between them. The first write clock pin 35 is also adjacent to the blank area 50, so the wiring of the first write clock pin 35 can be led out from the blank area 50, facilitating the wiring process.

[0091] As shown in Figure 10, a second read strobe pin 42 and a second write clock pin 43 are provided in the second pin array 40. A second power supply pin 33 is provided between the second read strobe pin 42 and the second signal pin 41 to improve signal crosstalk. Simultaneously, the second write clock pin 43 and the second signal pin 41 are positioned diagonally, which also improves signal crosstalk. The second read strobe pin 42 and the second write clock pin 43 are staggered, for example, the second read strobe pin 42 is located in column 9 / 10, and the second write clock pin 43 is located in column 8 / 9. Furthermore, the second read strobe pin 42 and the second write clock pin 43 are surrounded by the first power supply pin 32 and the second power supply pin 33, thus making the second read strobe pin 42 adjacent to the first power supply pin 32 and the second write clock pin 43 adjacent to the second power supply pin 33. The magnetic field generated by the second read strobe pin 42 and the second write clock pin 43 is absorbed by the first power supply pin 32 and the second power supply pin 33, thereby improving signal crosstalk between the second read strobe pin 42 and the second write clock pin 43.

[0092] As shown in Figure 10, the first read strobe pin 34 is used to transmit the first read strobe signal, and the first write clock pin 35 is used to transmit the first data clock signal. The second read strobe pin 42 is used to transmit the second read strobe signal, and the second write clock signal is used to transmit the second data clock signal. The first read strobe signal and the first data clock signal can be associated with higher-order data byte signals (DQ8-DQ15). The second read strobe signal and the second data clock signal can be associated with lower-order data byte signals (DQ0-DQ7). The first read strobe signal and the second read strobe signal can be differential signals (a pair of true signals and two's complement signals). The first read strobe pin 34 is represented, for example, by RDQS1_C_A and RDQS1_T_A, where A represents the first signal channel. The second read strobe pin 42 is represented, for example, by RDQS0_C_A and RDQS0_T_A. The first write clock pin 35 is represented, for example, by WCK1_C_A and WCK1_T_A, and the second write clock pin 43 is represented, for example, by WCK0_C_A and WCK0_T_A.

[0093] As shown in Figures 9 and 10, the 8th column of the first pin array 30 is adjacent to the third pin array 60, and a second power supply pin 33 is provided in the 8th column. The second power supply pin 33 isolates the first read strobe pin 34 from the command address pin 61. The second power supply pin 33 and the command address pin 61 are adjacent, thus improving crosstalk between their signals. Due to the presence of the blank area 50, the first write clock pin 35 is separated from the command address pin 61, meaning the first write clock pin 35 and the command address pin 61 are located on opposite sides of the blank area 50, thus improving crosstalk between their signals. The 8th row of the second pin array 40 is adjacent to the third pin array 60, and the second write clock pin 42 is separated from the chip select signal pin 62 by the first power supply pin 32, thus improving crosstalk between their signals. Simultaneously, the first power supply pin 32 can also ensure the stability of the first voltage in the second pin array 40.

[0094] As shown in Figure 10, the control signals in the third pin array 60 also include a clock signal pin 63, which is associated with the command address pin 61. The clock signal pin 63 can be a differential signal, for example, represented by CK_C_A and CK_T_A.

[0095] As shown in Figures 9-10, a first data mask inversion pin 36 is also provided in the first pin array 30. The first data mask inversion pin 36 is used to transmit the first data mask inversion signal associated with the higher-order data byte signal. The first data mask inversion pin 36 is surrounded by the first power supply pin 32 and the second power supply pin 33, thereby absorbing the magnetic field generated by the first data mask inversion pin 36 and reducing signal crosstalk between the first data mask inversion pin 36 and the first signal pin 31. The first data mask inversion pin 36 can be represented as DMI1_A. The first signal pin 31, the first read strobe pin 34, the first write clock pin 35, the first data mask inversion pin 36, the command address pin 61, the chip select signal pin 62, and the clock signal pin 63 are all coupled to the first signal channel. A second data mask inversion pin 44 is also provided in the second pin array 40. The second data mask inversion pin 44 is used to transmit the second data mask inversion signal associated with the lower-order data byte signal. The second data mask inversion pin 44 is surrounded by the first power supply pin 32 and the second power supply pin 33, thereby absorbing the magnetic field generated by the second data mask inversion pin 44 and reducing signal crosstalk between the second data mask inversion pin 44 and the second signal pin 41. The second data mask inversion pin 44 can be represented by DMI0_A. The second signal pin 41, the second read strobe pin 42, the second write clock pin 43, the second data mask inversion pin 44, the command address pin 61, the chip select signal pin 62, and the clock signal pin 63 are all coupled to the first signal channel, that is, the first pin array 30, the second pin array 40, and the third pin array 60 can be used to transmit signals for the first signal channel.

[0096] As shown in Figures 10 and 11, Figure 10 shows a schematic diagram of a partial pin array, and Figure 11 shows a schematic diagram of the entire pin array. Figure 10 shows a first pin array 30, a second pin array 40, and a third pin array 60. A fourth pin array 70, a fifth pin array 80, and a sixth pin array 90 are also provided on the substrate 21. The first pin array 30 and the fifth pin array 80 are essentially mirror images of the center row (row 12) of the substrate 21. The second pin array 40 and the fourth pin array 70 are essentially mirror images of the center row of the substrate 21. The third pin array 60 and the sixth pin array 90 are essentially mirror images of the center row of the substrate 21. A blank area 50 is provided between the first pin array 30 and the second pin array 40. A blank area 50 is provided between the second pin array 40 and the fourth pin array 70, and a blank area 50 is provided between the fifth pin array 80 and the fourth pin array 70. No pins are placed in these three blank areas 50, which facilitates subsequent routing. The fourth pin array 70, the fifth pin array 80, and the sixth pin array 90 can be used to transmit signals for the second signal channel.

[0097] It should be noted that the pins of the first pin array 30 are essentially mirror images of the pins in the fifth pin array 80. Therefore, the positions of the signal pins in the first pin array 30 are mirror images of the positions of the signal pins in the fifth pin array 80. In some embodiments, to facilitate subsequent routing, the positions of the signal pins in the first pin array 30 may not be mirror images of the positions of the signal pins in the fifth pin array 80.

[0098] As shown in Figures 11 and 12, Figure 12 illustrates the pin architecture. In this embodiment, there are 13 rows and 23 rows of pins on the substrate. Due to the presence of the blank area 50, the number of pins is reduced, thus allowing for a smaller pin spacing. In this embodiment, the number of pins is, for example, 245. Power supply pins may include VDD1, VDD2H, VDD2L, and VDDQ. The VDD1 pin receives VDD1 and powers the memory core. The VDD2H pin receives VDD2H and powers the memory core. The VDD2L pin receives VDD2L and also powers the memory core. The VDDQ pin receives VDDQ and powers the I / O buffer. In practical applications, the memory can have three sets of voltages: VDD1, VDD2, and VDDQ. VDD2 can include VDD2H and VDD2L. VDD1 and VDD2 represent the memory core operating voltages. VDD1 (1.8V) and VDD2 have different voltage values: VDD2H represents a higher voltage (1.05V), VDD2L (0.9V) represents a lower voltage, and VDDQ (0.5V) represents a high-quality voltage after noise filtering, offering strong anti-interference capabilities. The VSS pin represents the ground pin. There are 6 VDD1 pins, 26 VDD2H pins, 8 VDD2L pins, 22 VDDQ pins, and 93 VSS pins.

[0099] As shown in Figure 12, pins CA0 to CA6 can receive read or write addresses. The read address indicates which row and column of the memory array to read, and the write address indicates which row and column of the memory array to write. Pins DQ0 to DQ15 can receive write data and output read data. During a read operation, pins DQ0 to DQ15 output the data read from the memory cell, and during a write operation, pins DQ0 to DQ15 receive the data to be written to the memory cell.

[0100] As shown in Figure 12, WCK1_T, WCK1_C, WCK0_T, and WCK0_C represent the write clock, which is used to sample the write data received by pins DQ0 to DQ15. In practical applications, WCK1_T and WCK1_C are used to sample the write data received by pins DQ8 to DQ15, and WCK0_T and WCK0_C are used to sample the write data received by pins DQ0 to DQ7. WCK1_T, WCK1_C, WCK0_T, and WCK0_C can be operated at two or four times the frequency of CK_T / CK_C to improve the sampling rate. RDQS1_T, RDQS1_C, RDQS0_T, and RDQS0_C represent the read clock, also known as the read strobe signal, which is used to sample the read data output by pins DQ0 to DQ15. In practical applications, RDQS1_T and RDQS1_C are used to sample read data output from pins DQ8 to DQ15, and RDQS0_T and RDQS0_C are used to sample read data output from pins DQ0 to DQ7. DMI1 and DMI0 represent data mask signals (DM), which are used to mask write data received from pins DQ0 to DQ15 to determine which write data is written to the memory cells. In practical applications, DMI1 is used to mask write data received from pins DQ8 to DQ15, and DMI0 is used to mask write data received from pins DQ0 to DQ7. CK_T and CK_C represent command address clocks, which are used to sample read or write addresses. In practical applications, all command, address, and control input signals are sampled at the intersection of the rising edge of CK_T and the falling edge of CK_C. The ZQ pin receives ZQ, which represents the standard signal, a calibration signal used to calibrate the output drive strength. The RESET pin receives the RESET signal, which is used to reset the memory to its default state initially. The CS pin receives the CS signal, which is used to select the target chip (die). The DNU pin represents a mechanical ball and has no function. The RFU pin is a reserved pin. In Figure 12, A can represent the first signal channel, and B can represent the second signal channel. Alternatively, A can represent the second signal channel, and B can represent the first signal channel.

[0101] As shown in Figure 12, in some embodiments, the number and position of power supply pins (e.g., VSS pins) can be appropriately varied, for example, by appropriately increasing or decreasing the number of power supply pins. This changes the number of pins, allowing it to vary between 234 and 250, for example, 235, 236, 237, 238, 239, 241, 242, 243, 244, 245, 246, 247, 248, and 249 pins. It should be noted that the position and number of signal pins (e.g., DQ pins) and control pins (e.g., CA pins) remain unchanged.

[0102] As shown in Figure 13, this embodiment of the present disclosure also proposes another semiconductor structure 10, which includes a package structure 20 and a memory chip 12. The package structure 20 includes a substrate 21 and pins 111 located on the back of the substrate 21, that is, the package structure 20 can also be a package substrate. The structure of the package structure 20 can be referred to the above description, and the arrangement of the pins 111 can be referred to the above description. The memory chip 12 is located on the substrate 21, and the memory chip 12 is electrically connected to the pads (shown in Figure 2) of the substrate 21 through gold wires 13. The substrate 21 has internal traces (metal wires) that electrically connect the pins 111 and the pads, thereby electrically connecting them to the gold wires 13. In this embodiment of the present disclosure, the first signal channel 14 is electrically connected to two memory chips 12, and the second signal channel 15 is electrically connected to two memory chips 12.

[0103] As shown in Figure 14, this embodiment of the present disclosure also proposes an electronic device 100, which may include a circuit board 110, a first chip 120, and a semiconductor structure 10. The first chip 120 may be a control chip. The structure of the semiconductor structure 10 can be referred to the above description. The memory chip 12 in the semiconductor structure 10 may be a second chip. The first chip 120 may control the overall operation of the memory chip 12. For example, the first chip 120 may control the memory chip 12 to output data from the memory chip 12 or to store data in the memory chip 12. The first chip 120 may be a SOC chip. The memory chip 12 may include multiple memory cells. For example, the memory cells may be dynamic random access memory (DRAM) cells. The memory chip 12 may be Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), Wide I / O, High Bandwidth Memory (HBM). In this embodiment, the memory chip 12 is, for example, LPDDR5.

[0104] As shown in Figures 14 and 15, Figure 15 is a top view of Figure 14 on the circuit board 110. It should be noted that Figure 15 only shows the first pin array 30, the second pin array 40, and the third pin array 60, i.e., the pins under the first signal channel. Since the semiconductor structure 10 is fixed to the circuit board 110 via pins, each pin in the first pin array 30, the second pin array 40, and the third pin array 60 can be displayed on the circuit board 110. Simultaneously, a blank area 130 is formed between the first pin array 30 and the second pin array 40. The shape of this blank area 130 is the same as the shape of the blank area 50 in the package structure 10; that is, the blank area 50 in the package structure 10 corresponds to the blank area 130 on the circuit board 110. The structural description of the blank area 130 can be found in the structural description of the blank area 50. Furthermore, a metal line 140 (metal wiring) is provided on the surface of the circuit board 110. The metal line 140 is interconnected with the first chip 120 through the blank area 130, thereby enabling signal transmission between the first chip 120 and the memory chip 12. Because of the design of the blank area 130, which has no pins, the metal line 140 can be directly designed within it. The metal line 140 is short, resulting in low signal loss. If some pins were retained in the blank area 130, the metal line 140 would need to be avoided when designing it, leading to a longer metal line 140 and increased signal loss. Furthermore, designing the metal line 140 inside the circuit board 110 would make the routing process more complex.

[0105] As shown in Figure 15, the electronic device 100 may include one or more of the following: for example, a smartphone, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a home appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).

[0106] Figure 16 shows a comparison of the plastic strain of a packaging substrate in the prior art and a packaging substrate of the present invention. In Figure 16, the horizontal axis represents the number of temperature cycles, and the vertical axis displays the strain. It should be noted that the packaging substrate in the prior art has 315 pins, while the packaging substrate in this embodiment has 245 pins. In (a1) the figure shows 800µm, which represents the spacing of the packaging substrate in the X direction (row direction). In (a2) the figure shows 700µm, which represents the pin spacing of the packaging substrate in the Y direction (column direction). In (b1) the figure shows 600µm, which represents the spacing of the packaging substrate in the X direction (row direction). In (b2) the figure shows 500µm, which represents the pin spacing of the packaging substrate in the Y direction (column direction). In the X direction, the comparison shows that the strain curve in (a1) only stabilizes after a large number of temperature cycles (more than 8000), with the final strain difference Δε... p The value is 0.0236, while in Figure (b1), the strain curve tends to stabilize after dozens of temperature cycles, and the final strain difference Δε is 0.0236. p The value is 0.0128. Therefore, in the X direction, the strain of the leads of the prior art packaging substrate is greater than that of the leads of the packaging substrate in this embodiment. In the Y direction, the strain curve in Figure (a2) only stabilizes after hundreds of temperature cycles, and the final strain difference Δε p The value is 0.0185, while in Figure (b2), the strain curve tends to stabilize after several dozen temperature cycles, with the maximum strain difference Δε being 0.0185. p The value is 0.00711. Therefore, in the Y direction, the strain of the leads of the prior art packaging substrate is greater than that of the leads of the packaging substrate in this embodiment. Simultaneously, the strain difference of the leads in the X / Y directions of the prior art packaging substrate is significant, and the deformation of the leads in the X / Y directions is inconsistent, which is detrimental to subsequent soldering. In contrast, the strain difference of the leads in the X / Y directions of the packaging substrate in this embodiment is small, and the deformation of the leads in the X / Y directions is basically consistent, which is beneficial to subsequent soldering. This embodiment reduces the number of leads, designs blank areas, and reduces the lead spacing, resulting in a smaller overall size of the packaging substrate and a smaller stress expansion point for the leads. This leads to good plastic application performance, lower stress on the leads, and improved lead reliability.

[0107] As shown in Figure 17, Figure 17 illustrates the performance test diagrams of a prior art packaging substrate and a packaging substrate of this embodiment. (a) In the figure, curve L1 represents the write data test diagram of a prior art packaging substrate (315 pins), and curve L2 represents the write data test diagram of the packaging substrate of this disclosure (245 pins). Curves L1 and L2 represent the test diagrams of the two substrates at the same eye width and the same write rate (e.g., 7500 Mbps). As can be seen from Figure (a), the curves L1 and L2 are basically consistent, and the test performance of the packaging substrate of this disclosure can be basically consistent with the write performance of the prior art packaging substrate. (b) In the figure, curve L3 represents the read data test diagram of the packaging substrate of this embodiment, and curve L4 represents the read data test diagram of a prior art packaging substrate. Curves L3 and L4 represent the test diagrams of the two substrates at the same eye width and the same read rate (e.g., 7500 Mbps). As can be seen from Figure (a), the curves L3 and L4 show essentially the same change, indicating that the test performance of the packaging substrate of this disclosure is essentially consistent with the read performance of existing packaging substrates. The above tests demonstrate that this disclosure reduces the number of pins and rearranges the positions of signal pins, control pins, and power pins, thereby enabling the performance of the packaging substrate to remain consistent with that of existing packaging substrates. This facilitates the application of the packaging substrate in miniaturized electronic products.

[0108] In summary, the embodiments of this disclosure provide a packaging structure, a semiconductor structure, and an electronic device. The packaging structure includes a substrate and a first pin array and a second pin array. By providing a blank area between the first and second pin arrays—that is, by not providing pins between the first and second pin arrays—the first and second pin arrays are separated. Therefore, the number of pins on the substrate is reduced, and the pin spacing can be decreased, thereby reducing the area of ​​the substrate and, consequently, the area of ​​the packaging structure. This allows the packaging structure to be applied to miniaturized electronic products.

[0109] Meanwhile, the first data pin in the first pin array and / or the first data pin in the second pin array are adjacent to the blank area. Thus, when the package structure is applied to the circuit board, the blank area on the substrate will form a corresponding blank area on the circuit board. Therefore, the first data pin and / or the second data pin will also be adjacent to the blank area on the circuit board. Thus, metal lines can be directly formed on the surface of the circuit board. These metal lines will be electrically connected to the package structure and the control chip. Therefore, it is not necessary to form metal lines inside the circuit board.

[0110] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A package structure (20) characterized by, include: Base (21); A first pin array (30) is disposed on the substrate (20), the first pin array including a plurality of first data pins (31); A second pin array (40) is disposed on the substrate (20), the second pin array including a plurality of second data pins (41); A blank area (50) is provided between the first pin array (30) and the second pin array (40). The blank area (50) extends from the center of the substrate (20) to the edge of the substrate (20). The end of the blank area (50) is located outside the first pin array (30). At least one first data pin (31) and / or at least one second data pin (41) are adjacent to the blank area (50). The minimum size of the blank area (50) is greater than the diameter of the first data pin (31).

2. The package structure of claim 1, wherein, In the first pin array, the number of first data pins in the Kth row is greater than the number of first data pins in the Lth row; Wherein, row K is adjacent to the blank area, and row L is adjacent to row K.

3. The package structure of claim 1 or 2, wherein, In the second pin array, the number of second data pins in the Mth row is greater than the number of second data pins in the Nth row; Wherein, row M is adjacent to the blank area, and row N is adjacent to row M.

4. The package structure of claim 3, wherein, In row K, the first data pin is set opposite to or offset from the second data pin in row M, and in row L, the first data pin is set opposite to the second data pin in row N.

5. The package structure of claim 3, wherein, In the Nth row, at least one of the second data pins is adjacent to the blank area.

6. The package structure of claim 3, wherein, In row K, a first power supply pin is provided between adjacent first data pins; in row M, a second power supply pin is provided between adjacent second data pins. The first power pin is used to transmit a first voltage, and the second power pin is used to transmit a second voltage, wherein the first voltage is higher than the second voltage.

7. The package structure of claim 6, wherein, In the first pin array, up to three first power supply pins are arranged adjacent to each other in the column direction; in the second pin array, up to two first power supply pins are arranged adjacent to each other in the row direction.

8. The package structure of claim 1, wherein, The first data pin is used to transmit higher-order data byte signals, and the second data pin is used to transmit lower-order data byte signals; or, the first data pin is used to transmit lower-order data byte signals, and the second data pin is used to transmit higher-order data byte signals.

9. The package structure of any of claims 6-8, wherein, The first pin array further includes: The first read strobe pin is spaced apart from the first data pin. The first write clock pin is spaced apart from the first data pin. The first power supply pin and the second power supply pin are provided between the first read strobe pin and the first write clock pin.

10. The package structure of claim 9, wherein, The first write clock pin is adjacent to the blank area.

11. The package structure of any one of claims 6-8, wherein, The second pin array also includes: The second read strobe pin is spaced apart from the second data pin. The second write clock pin is spaced apart from the second data pin. The second read strobe pin and the second write clock pin are staggered, and at least one of the second read strobe pins is adjacent to at least one of the second write clock pins.

12. The package structure of claim 11, wherein, The second read strobe pin is adjacent to the first power supply pin, and the second write clock pin is adjacent to the second power supply pin.

13. The package structure of any one of claims 6-8, wherein, The substrate is provided with: The third pin array includes multiple control pins; At least one of the control pins is adjacent to the blank area.

14. The packaging structure according to claim 13, characterized in that, The control pins include multiple command address pins, wherein at most two of the command address pins are arranged adjacent to each other; at least one of the command address pins is adjacent to the blank area.

15. The packaging structure according to claim 14, characterized in that, The second power supply pin in the first pin array is adjacent to the command address pin in the third pin array; the first power supply pin in the second pin array is adjacent to the control pin in the third pin array.

16. The packaging structure according to claim 14, characterized in that, The command address pin and the first write clock pin are located on opposite sides of the blank area.

17. A semiconductor structure (10), characterized in that, include: The packaging structure (20) and the chip (12) disposed on the packaging structure as described in any one of claims 1-16.

18. An electronic device (100), characterized in that, include: A circuit board (110) is provided with a first chip (120), and a blank area (130) is provided on the surface of the blank area; The packaging structure (20) as described in any one of claims 1-16 is disposed on the circuit board, and the blank area in the packaging structure corresponds to the blank area; The second chip is disposed on the package structure (20); in, The first chip is electrically connected to the second chip via the metal wire.

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