Pixel unit and preparation method therefor, and photoelectric device based on multi-surface reflection and preparation method therefor

Abstract

The present invention relates to a pixel unit and a preparation method therefor, and a photoelectric device based on multi-surface reflection and a preparation method therefor. The pixel unit comprises a pixel body and a peripheral wall body, wherein the pixel body comprises a second semiconductor layer, an active layer and a first semiconductor layer, which are sequentially arranged in a first direction; the peripheral wall body is arranged on side walls of the pixel body, the peripheral wall body comprises a first wall body layer, and the first wall body layer is adhered to the side walls of the pixel body; and the first wall body layer is an insulator, and the first semiconductor layer and the second semiconductor layer are insulated from each other by means of the first wall body layer. Further disclosed in the present disclosure are a preparation method for a pixel unit, and a photoelectric device based on multi-surface reflection and a preparation method therefor. The present invention effectively improves the use reliability and optical intensity of an LED photoelectric device, thereby better meeting production and use requirements.

Description

Pixel unit, optoelectronic device based on multifaceted reflection and its fabrication method

[0001] Priority information: This application claims priority to Chinese Patent Application No. 2024106990206, filed on May 31, 2024, and Chinese Patent Application No. 2024106990117, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a pixel unit, a multi-faceted reflection-based optoelectronic device, and a method for its fabrication. Background Technology

[0003] As LED displays gradually move towards higher integration and higher resolution, pixel sizes are becoming increasingly smaller. Currently, when performing sidewall insulation passivation on existing pixel unit structures, a passivation layer is typically applied before patterning etching using a photolithography machine. However, when pixel sizes shrink to the micrometer or even sub-micrometer level, the minimum linewidth and overlay accuracy of the photolithography machine face greater challenges. Patterning failures and large overlay misalignments (misalignment between the lower and upper patterns in different areas of different wafers) are prone to occur during photolithography, leading to short circuits and leakage in different compound functional areas of the pixel unit. This, in turn, causes LED device performance degradation or failure, failing to meet processing and usage requirements. Furthermore, photolithography machines with higher overlay accuracy have higher purchase costs, further increasing production costs.

[0004] Current LED optoelectronic devices generally only have a single-sided reflector, typically located at the bottom of the pixel light-emitting unit. Since the LED emits light in all directions, this single-sided reflection method only utilizes bottom reflection. The emission angle of this type of single-sided reflector is generally above 110°, resulting in low light collection and utilization rates for the pixel unit. This is detrimental to improving overall optical efficiency and cannot meet application requirements. For example, in some projection applications, high collimation and a small emission angle of the light source are required to improve light source utilization and ensure the brightness of the LED optoelectronic device. However, this type of LED optoelectronic device cannot meet these requirements. Furthermore, the poor internal electrical isolation of the pixel unit in the aforementioned LED optoelectronic devices easily leads to short circuits and leakage, causing device failure and compromising the reliability of the LED optoelectronic device.

[0005] Therefore, given the aforementioned defects in LED optoelectronic devices, their reliability is affected, and they cannot adequately meet production and usage requirements. Summary of the Invention

[0006] Therefore, the main technical problem to be solved by the present invention is to improve the reliability of LED optoelectronic devices in the prior art.

[0007] To address the aforementioned technical problems, the present invention provides a pixel unit, comprising:

[0008] A pixel body, the pixel body comprising a second semiconductor layer, an active layer and a first semiconductor layer disposed sequentially along a first direction;

[0009] An outer edge wall is disposed on the side wall of the pixel body. The outer edge wall includes a first wall layer that is attached to the side wall of the pixel body. The first wall layer is an insulator, and the first semiconductor layer and the second semiconductor layer are insulated from each other through the first wall layer.

[0010] This invention also discloses a method for fabricating a pixel unit, comprising,

[0011] Step S1) A second semiconductor layer, an active layer, a first semiconductor layer, and an etch barrier layer are sequentially formed along the first direction;

[0012] Step S2) Using the etching barrier layer as a mask, the pixel body is etched by dry etching or wet etching to obtain the pixel body. The length of the pixel body along the second direction is the same as the length of the etching barrier layer, and the second direction is perpendicular to the first direction.

[0013] Step S3) Deposit a first wall layer on the outside of the pixel body, wherein the etch barrier layer is located between the pixel body and the first wall layer;

[0014] The first wall layer is etched using a dry etching method, and only the first wall layer located on the sidewall of the pixel body is retained after etching; the etching time is controlled to remove the etching barrier layer so that the first semiconductor layer can be exposed.

[0015] This invention also discloses a photoelectric device based on multi-faceted reflection, comprising,

[0016] A driving wafer, wherein the driving wafer includes an anode contact;

[0017] A pixel unit is disposed on the driving wafer and corresponds to the anode contact. The pixel unit includes a pixel body and an outer edge wall. The outer edge wall is disposed on the side wall of the pixel body. The outer edge wall includes a side insulating layer and a side reflective metal layer. The inner wall of the side insulating layer is attached to the side wall of the pixel body, and the outer wall of the side insulating layer is attached to the side reflective metal layer.

[0018] An N-type semiconductor layer is disposed on the side of the pixel body away from the driving wafer, and a P-type semiconductor layer is disposed on the side closer to the driving wafer. A transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer. The P-type semiconductor layer is electrically connected to a corresponding anode contact on the driving wafer through the transparent conductive film layer. A bottom reflective metal layer is formed between the transparent conductive film layer and the driving wafer. The N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated from each other by the side insulating layer, and the N-type semiconductor layers in all pixel units are connected by a common cathode.

[0019] This invention also discloses a method for fabricating an optoelectronic device based on multifaceted reflection, comprising,

[0020] Fabricate a driver wafer such that the driver wafer includes anode contacts;

[0021] A compound semiconductor is connected to the driving wafer, and the compound semiconductor is processed to form a pixel unit corresponding to the anode contact. The pixel unit includes a pixel body and an outer edge wall. The outer edge wall is disposed on the side wall of the pixel body and includes a side insulating layer and a side reflective metal layer. The inner wall of the side insulating layer is attached to the side wall of the pixel body, and the outer wall of the side insulating layer is attached to the side reflective metal layer. An N-type semiconductor layer is disposed on the side of the pixel body away from the driving wafer, and a P-type semiconductor layer is disposed on the side closer to the driving wafer. A transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer. The P-type semiconductor layer is electrically connected to the corresponding anode contact on the driving wafer through the transparent conductive film layer. A bottom reflective metal layer is formed between the transparent conductive film layer and the driving wafer.

[0022] In each pixel unit, the N-type semiconductor layer and the P-type semiconductor layer are insulated from each other by the side insulating layer;

[0023] All the N-type semiconductor layers in the pixel units are connected by a common cathode.

[0024] The technical solution of the present invention has the following advantages compared with the prior art:

[0025] The pixel unit and its fabrication method described in this invention can effectively prevent leakage failure of the pixel unit. Furthermore, when fabricating the outer edge wall at the sidewall of the pixel body, a dry etching method is used instead of a photolithography machine. This avoids the defects of patterning failure, large overlay misalignment, and high production cost caused by patterning etching using a photolithography machine in existing technologies, while also effectively ensuring fabrication accuracy. It also facilitates the customization of the outer edge wall structure to enhance optical and electrical functions, enabling optical or electrical control and improving ease of use. In the optoelectronic device based on multi-faceted reflection and its fabrication method, setting an outer edge wall at the sidewall of the pixel body can better ensure the reliability of the LED optoelectronic device. Simultaneously, it allows each pixel unit to achieve multi-faceted reflection ("side + bottom"), thereby achieving a multi-faceted reflection effect, improving light collection efficiency and utilization, and increasing the optical intensity and brightness performance of the LED optoelectronic device. Attached Figure Description

[0026] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0027] Figure 1 is a schematic diagram of the structure of one embodiment of the pixel unit of the present invention (including a second wall layer);

[0028] Figure 2 is a schematic diagram of another embodiment of the pixel unit of the present invention (including the second wall layer).

[0029] Figure 3 is a schematic diagram of one embodiment of the pixel unit of the present invention (having only the first wall layer).

[0030] Figure 4 is a schematic diagram of another embodiment of the pixel unit of the present invention (having only the first wall layer).

[0031] Figure 5 is a schematic diagram of one embodiment of the pixel unit of the present invention (including a metal barrier layer).

[0032] Figure 6 is a schematic diagram of the fabrication process of one embodiment of the pixel unit of the present invention (having only the first wall layer);

[0033] Figure 7 is a schematic diagram of the fabrication process of one embodiment of the pixel unit of the present invention (including the second wall layer);

[0034] Figure 8 is a schematic diagram of the fabrication process of another embodiment of the pixel unit of the present invention (including the second wall layer);

[0035] Figure 9 is a schematic diagram of the fabrication process of one embodiment of the pixel unit of the present invention (including a metal barrier layer);

[0036] Figure 10 is a schematic diagram of one embodiment of the optoelectronic device based on multi-faceted reflection of the present invention (common cathode omitted);

[0037] Figure 11 is a schematic diagram of another embodiment of the optoelectronic device based on multi-faceted reflection of the present invention (common cathode omitted);

[0038] Figure 12 is a schematic diagram of the driving wafer structure in this invention;

[0039] Figure 13 is a schematic diagram of one embodiment of the compound semiconductor in this invention;

[0040] Figure 14 is a schematic diagram of another embodiment of the compound semiconductor in this invention;

[0041] Figure 15 is a schematic diagram of the fabrication of optoelectronic devices using the compound semiconductor shown in Figure 13;

[0042] Figure 16 is a schematic diagram of the fabrication of optoelectronic devices using the compound semiconductor shown in Figure 14;

[0043] Figure 17 is a schematic diagram of one embodiment of the common cathode and microlens fabrication of the optoelectronic device of the present invention;

[0044] Figure 18 is a schematic diagram of another embodiment of the common cathode and microlens fabrication of the optoelectronic device of the present invention;

[0045] Figure 19 is a schematic diagram of a third embodiment of the common cathode and microlens fabrication of the optoelectronic device of the present invention;

[0046] Explanation of reference numerals in the accompanying drawings: 10, driving wafer; 101, anode contact; 20, pixel unit; 201, pixel body; 2011, N-type semiconductor layer; 2012, active layer; 2013, P-type semiconductor layer; 2014, first semiconductor layer; 2015, second semiconductor layer; 202, outer edge wall; 2021, side insulating layer; 20211, step portion; 2022, side reflective metal layer; 2023, side metal fence; 2024, first wall layer; 2025, second wall layer; 2026, metal barrier layer; 203, transparent conductive film layer; 204, bottom reflective metal layer; 205, bottom reflective dielectric layer; 206, first semiconductor layer; 207, second semiconductor layer; 30, bonding layer; 301, first bonding metal layer; 302, second bonding metal layer; 40, common cathode; 401, recess; 50. Compound semiconductor; 501. First substrate; 60. Metal mesh; 70. Microlens; 80. Supporting substrate; 801. First surface; 802. Second surface; 90. Etching barrier layer; Detailed Implementation

[0047] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure or its application or use.

[0048] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0049] Example 1

[0050] This embodiment provides a pixel unit and its fabrication method, which can avoid leakage failure of the pixel unit, improve the fabrication effect, increase production efficiency, and effectively reduce production costs.

[0051] The structure of the pixel unit in this embodiment will be further described below with reference to Figures 1-9.

[0052] Referring to Figure 1, this embodiment discloses a pixel unit, including a pixel body 201 and an outer edge wall 202;

[0053] As shown in Figure 1, the first direction is approximately the height direction of the pixel unit, and the second direction is perpendicular to the first direction.

[0054] The pixel body 201 includes a second semiconductor layer 2015, an active layer 2012 and a first semiconductor layer 2014 arranged sequentially along a first direction; wherein the active layer 2012 is used to emit light.

[0055] The outer edge wall 202 is disposed on the side wall of the pixel body 201. The outer edge wall 202 includes a first wall layer 2024. The first wall layer 2024 is attached to the side wall of the pixel body 201, and there is no gap between them. The first wall layer 2024 is an insulator. The first semiconductor layer 2014 and the second semiconductor layer 2015 are insulated from each other through the first wall layer 2024.

[0056] In some embodiments, the pixel body 201 is disposed on a support substrate 80, the support substrate 80 having a first surface 801 and a second surface 802 disposed opposite to each other along a first direction; the pixel body 201 is disposed on the first surface 801.

[0057] The aforementioned pixel unit, by providing an outer edge wall 202 on the sidewall of the pixel body 201 of the optical element, ensures that the first semiconductor layer 2014 and the second semiconductor layer 2015 are insulated from each other by the first wall layer 2024, which can effectively prevent short circuit leakage between the first semiconductor layer 2014 and the second semiconductor layer 2015. In addition, by providing the outer edge wall 202, the exposed opening of the first semiconductor layer 2014 is maximized, that is, the contact area of ​​the first semiconductor layer 2014 is maximized, which is more conducive to subsequent ohmic contact and thus better ensures the reliability of the pixel unit.

[0058] Furthermore, the aforementioned pixel units are primarily composed of compound semiconductor materials. Compound semiconductors typically refer to compounds formed from two or more elements. For example, these compound semiconductors are mainly epitaxial materials for light-emitting diodes, such as the InGaN ternary material system or the AlGaInP quaternary material system, whose emission wavelengths can cover the entire spectrum from ultraviolet, visible, and infrared.

[0059] In one embodiment, the first semiconductor layer 2014 is a P-type semiconductor and the second semiconductor layer 2015 is an N-type semiconductor; or the first semiconductor layer 2014 is an N-type semiconductor and the second semiconductor layer 2015 is a P-type semiconductor.

[0060] The supporting substrate 80 can be a substrate in a compound semiconductor, such as a substrate made of one or more of gallium nitride (GaN), silicon (Si), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), indium phosphide (InP), etc., or it can be a temporary or permanent substrate and its bonding structure that has undergone bonding transfer, such as a CMOS driver wafer and its bonding structure.

[0061] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layers of the compounds are more complex, or there is cross-use of materials, mainly including P-type semiconductor materials, N-type semiconductor materials, and an active layer (MQW quantum well) sandwiched between the two:

[0062] Table 1. Film Material Table for Each Compound

[0063] A P-type ohmic contact layer can also be formed on the surface of a P-type semiconductor. The materials used to form the P-type ohmic contact layer include single layers or stacks of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), or single layers or stacks of metals such as Ni, Cr, Au, Ag, Zn, Be, and Al (nickel, chromium, gold, silver, zinc, beryllium, and aluminum), or alloys, or stacks of transparent metal oxides and metals. Similarly, an N-type ohmic contact layer can also be formed on the surface of an N-type semiconductor. The materials used to form the N-type ohmic contact include single layers or stacks of transparent metal oxides such as ITO, IZO, and ZnO, or single layers or stacks of metals such as Ni (nickel), Cr (chromium), Ti (titanium), Au (gold), Ge (germanium), and Al (aluminum), or alloys, or stacks of transparent metal oxides and metals.

[0064] In one embodiment, as shown in Figures 1, 2, 3, and 5, the outer edge wall 202 is in direct contact with the support substrate 80 at one end near the support substrate 80. In this configuration, the outer edge wall 202 is in direct contact with the support substrate 80, and the second semiconductor layer 2015 is not exposed to the outside of the outer edge wall 202.

[0065] In one embodiment, as shown in Figure 1, the thickness L1 of the first wall layer 2024 is 50 nm to 1500 nm. This thickness range allows for the maximization of the dielectric layer thickness required for omnidirectional reflective structures with different wavelengths while achieving ideal insulating coverage.

[0066] In one embodiment, as shown in Figures 1 and 2, the outer wall 202 further includes a second wall layer 2025, which is in close contact with the outer wall of the first wall layer 2024.

[0067] As shown in Figure 1, the first wall layer 2024 near the supporting substrate 80 can adopt the following stepped portion 20211 structure:

[0068] A step portion 20211 is formed at one end of the first wall layer 2024 near the support substrate 80, and a second wall layer 2025 is located on the step portion 20211.

[0069] As shown in Figure 2, the end of the first wall layer 2024 near the support substrate 80 can also adopt a stepless structure.

[0070] In one embodiment, the second wall layer 2025 is either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, to enhance optical and electrical functions.

[0071] By setting a reflective layer in the second wall layer 2025, the effect of side reflection can be achieved, which is more conducive to the realization of all-round reflection, greatly improving the brightness of the pixel unit and the collimation of light, and obtaining better performance and a smaller divergence angle.

[0072] By providing a conductive layer in the second wall layer 2025, it is easier to make electrical connections between the pixel unit and other components.

[0073] Furthermore, the reflective layer can be deposited using highly reflective metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt);

[0074] The conductive layer can be deposited using highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0075] The second wall layer 2025 can also be a stack of transparent conductive layer and metal layer, such as a silver or titanium tungsten film layer superimposed on zinc oxide.

[0076] In one embodiment, as shown in FIG5, the outer wall 202 further includes a metal barrier layer 2026, and the second wall layer 2025 is located between the first wall layer 2024 and the metal barrier layer 2026.

[0077] The aforementioned metal barrier layer 2026 is mainly used to block the migration of metal ions on the periphery.

[0078] The metal barrier layer 2026 can be a single-layer structure or a multi-layer structure.

[0079] The aforementioned metal barrier layer 2026 can be a combination of a metal layer and a dielectric layer, or it can be a single metal layer or dielectric layer. For example, the metal layer can be made of Ag, Al, Cu or Ti, and the dielectric layer can be made of silicon nitride.

[0080] In one embodiment, as shown in FIG1, the length L2 of the pixel body 201 along the second direction is 0.35um to 50um, and the second direction is perpendicular to the first direction. This length range covers the size of the light-emitting unit for micro-display and micro-projection applications, and can minimize the pixel size while meeting the performance requirements of Micro LED.

[0081] In one embodiment, as shown in stage b of FIG6, the angle θ between the pixel body 201 and the support substrate 80 is approximately 90°, specifically 45° to 135°, for example 50°, 60°, 90°, 120°, etc.

[0082] Furthermore, the angle θ between the pixel body 201 and the supporting substrate 80 is 70° to 110°, for example, it can be 80°, 90°, 100°, etc. The above angle range can meet different light extraction requirements.

[0083] As shown in Figure 6, this embodiment also discloses a method for preparing a pixel unit, the method comprising,

[0084] Step S1) Referring to stage a in Figure 6, a second semiconductor layer 2015, an active layer 2012, a first semiconductor layer 2014 and an etch barrier layer 90 are sequentially formed on the first surface 801 of the support substrate 80 along the first direction.

[0085] In addition to forming a contact with the first semiconductor layer 2014, the etch barrier layer 90 is mainly used as a mask and etch termination layer for patterning etching and subsequent etching of the outer edge wall 202.

[0086] The etch barrier layer 90 can be a dielectric layer (such as silicon oxide, silicon nitride, etc.), a contact layer (such as), or a stack with the contact layer below and the dielectric layer above.

[0087] Masking layers include dielectric layers such as silicon oxide and silicon nitride, or contact layers (such as ITO or other metals), or stacked layers with contact layers below and dielectric layers above.

[0088] Step S2) Referring to stage b in Figure 6, the pixel body 201 is obtained by etching using dry etching or wet etching with the etching barrier layer 90 as a mask. The length of the pixel body 201 along the second direction is the same as the length of the etching barrier layer 90, and the second direction is perpendicular to the first direction.

[0089] The aforementioned dry etching methods can employ inductively coupled plasma etching (ICP) and reactive ion etching (RIE), while wet etching methods can employ potassium hydroxide (KOH) and hydrochloric acid (HCl).

[0090] Furthermore, the angle θ between the etched pixel body 201 and the supporting substrate 80 is about 90°, specifically it can be 45° to 135°, preferably 70° to 110°.

[0091] Furthermore, as shown in stage b of Figure 6, the total thickness H1 from the second semiconductor layer 2015 to the first semiconductor layer 2014 is 0.3um to 5um. It should be noted that this thickness includes the thickness of the first semiconductor layer 2014 and the second semiconductor layer 2015 themselves.

[0092] Step S3) Referring to stage c in Figure 6, a first wall layer 2024 is deposited on the outside of the pixel body 201. The etch barrier layer 90 is located between the pixel body 201 and the first wall layer 2024. That is, at this time, the first wall layer 2024 also covers the etch barrier layer 90.

[0093] The first wall layer 2024 is etched using a dry etching method. After etching, only the first wall layer 2024 located on the side wall of the pixel body is retained, as shown in stage d in Figure 6. The etching time is controlled to remove the etching barrier layer 90, thereby exposing the first semiconductor layer 2014 to facilitate the subsequent realization of ohmic contact.

[0094] In one embodiment, in step S3), when depositing the first wall layer 2024 on the outside of the pixel body 201, the deposition thickness of the first wall layer located on the top of the pixel body is defined as D1, and the deposition thickness of the first wall layer located on the side wall of the pixel body is defined as D2. Then D1≥D2, so that the thickness of the first wall layer on the side wall can be better preserved during subsequent etching.

[0095] The first wall layer 2024 may consist of a single layer or a multi-layer structure.

[0096] Furthermore, the first wall layer 2024 comprises at least two layers, with adjacent layers made of different materials.

[0097] For example, the first wall layer 2024 can be a stack of silicon oxide and aluminum oxide layers to utilize the refractive index difference between the two materials to construct a distributed Bragg reflector (DBR).

[0098] In one embodiment, the first wall layer 2024 comprises one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0099] The aforementioned pixel unit fabrication method eliminates the need for a photolithography machine when fabricating the outer edge wall 202 at the sidewall of the pixel body. Instead, it employs dry etching, thus avoiding the need for more advanced photolithography machines and eliminating the need for exposure processes. This avoids the defects caused by patterning failure, large overlay misalignment, and high production costs associated with patterning etching using photolithography machines in existing technologies. At the same time, it can effectively ensure fabrication accuracy, achieving in-situ or self-alignment type accuracy, and sub-micron accuracy is achieved using micron-level equipment and processes. Furthermore, it can ensure maximum exposure of the contact area of ​​the first semiconductor layer, and when needed, the outer edge wall structure can be customized to enhance optical and electrical functions, enabling optical or electrical control, and the structural form is also more flexible.

[0100] Example 2

[0101] Referring to Figure 4, the main difference between this embodiment and Embodiment 1 is that the end of the outer edge wall 202 near the support substrate 80 is separated from the support substrate 80 by the second semiconductor layer 2015 to expose the second semiconductor layer 2015. This method allows the second semiconductor to be directly exposed to the outside of the outer edge wall 202, making it easier to make electrical connections using the second semiconductor. For example, it can be used as a common cathode.

[0102] Example 3

[0103] Referring to Figure 7, the main difference between this embodiment and Embodiment 1 is that this embodiment also requires the preparation of the second wall layer 2025, which is prepared by integral etching. The specific preparation method is as follows:

[0104] First, complete the preparation in steps S1) and S2), then proceed to step S3). In step S3), referring to stage d in Figure 7, after depositing the first wall layer 2024 on the outside of the pixel body 201, the second wall layer 2025 also needs to be deposited. After all deposition is completed, the overall structure composed of the first wall layer 2024 and the second wall layer 2025 is etched using a dry etching method. After etching, only the first wall layer 2024 and the second wall layer 2025 located on the sidewall of the pixel body are retained, resulting in the structure shown in stage e in Figure 7. The etching time is controlled to remove the etching barrier layer 90, thereby exposing the first semiconductor layer 2014.

[0105] In the pixel unit obtained by the above preparation method, a step portion 20211 is formed at the end of the first wall layer 2024 near the supporting substrate, and the second wall layer 2025 is located on the step portion 20211.

[0106] The aforementioned second wall layer 2025 can be a single-layer or multi-layer structure.

[0107] The second wall layer 2025 can be either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, to enhance optical and electrical functions.

[0108] The reflective layer can be deposited using high-reflectivity metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt); the conductive layer can be deposited using high-conductivity metals such as aluminum (Al), copper (Cu), tungsten (W), or titanium (Ti).

[0109] By setting the second wall layer 2025 as a reflective layer, the effect of side reflection can be achieved, which is more conducive to the realization of all-round reflection, greatly improving the brightness of the pixel unit and the collimation of light, obtaining better performance and a smaller divergence angle. Furthermore, while forming all-round reflection, the exposure process for preparing each film layer can be omitted, eliminating the need for a photolithography machine, and featuring narrow overlay distance and high precision.

[0110] Example 4

[0111] Referring to Figure 8, the main difference between this embodiment and Embodiment 1 is that this embodiment also requires the preparation of a second wall layer 2025. Unlike Embodiment 2, the preparation is carried out using a layered etching method, and the specific preparation method is as follows:

[0112] First, complete the preparation of steps S1) and S2), then proceed to step S3). In step S3), after depositing the first wall layer 2024 on the outside of the pixel body 201, the first wall layer 2024 is etched using a dry etching method. After etching, only the first wall layer 2024 located on the sidewall of the pixel body is retained. Then, as shown in stage e of Figure 8, a second wall layer 2025 is deposited on the outside of the first wall layer 2024, so that the etch barrier layer 90, the pixel body 201, and the first wall layer 2024 are all located inside the second wall layer 2025. After deposition, the second wall layer 2025 is etched using a dry etching method. After etching, only the second wall layer 2025 located on the sidewall of the pixel body is retained, resulting in the structure shown in stage f of Figure 8. The etching time is controlled to remove the etch barrier layer 90, thereby exposing the first semiconductor layer 2014.

[0113] In the pixel unit obtained by the above preparation method, there is no step between the first wall layer 2024 and the second wall layer 2025.

[0114] The aforementioned second wall layer 2025 can be a single-layer or multi-layer structure.

[0115] The second wall layer 2025 can be either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, to enhance optical and electrical functions.

[0116] The reflective layer can be deposited using high-reflectivity metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt); the conductive layer can be deposited using high-conductivity metals such as aluminum (Al), copper (Cu), tungsten (W), or titanium (Ti).

[0117] Example 5

[0118] The main difference between this embodiment and embodiments three and four is that the pixel unit in this embodiment also needs to have a metal barrier layer 2026 prepared, and the specific preparation method is as follows:

[0119] One preparation method is as follows: As shown in Figure 9, after etching in Example 3, only the first wall layer 2024 and the second wall layer 2025 located on the sidewall of the pixel body are retained. Then, a metal barrier layer 2026 is deposited on the outside of the second wall layer 2025, so that the etching barrier layer 90, the pixel body 201, the first wall layer 2024 and the second wall layer 2025 are all located inside the metal barrier layer 2026. After the deposition is completed, the metal barrier layer 2026 is etched using a dry etching method. After etching, only the metal barrier layer 2026 located on the sidewall of the pixel body is retained. The etching time is controlled to remove the etching barrier layer 90 so that the first semiconductor layer 2014 can be exposed.

[0120] Another preparation method is as follows: After etching in Example 4, only the first wall layer 2024 and the second wall layer 2025 located on the sidewall of the pixel body 201 are retained. Then, a metal barrier layer 2026 is deposited on the outside of the second wall layer 2025, so that the etching barrier layer 90, the pixel body 201, the first wall layer 2024 and the second wall layer 2025 are all located inside the metal barrier layer 2026. After the deposition is completed, the metal barrier layer 2026 is etched by dry etching. After etching, only the metal barrier layer 2026 located on the sidewall of the pixel body is retained. The etching time is controlled to remove the etching barrier layer 90 so that the first semiconductor layer 2014 can be exposed.

[0121] The aforementioned metal barrier layer 2026 is mainly used to block the migration of metal ions on the periphery.

[0122] The metal barrier layer 2026 can be a single-layer structure or a multi-layer structure.

[0123] The aforementioned metal barrier layer 2026 can be a combination of a metal layer and a dielectric layer, or it can be a single metal layer or dielectric layer. For example, the metal layer can be made of Ag, Al, Cu, or Ti, and the dielectric layer can be made of silicon nitride.

[0124] The pixel unit fabrication method of the above embodiment does not require a photolithography machine when fabricating the outer edge wall at the sidewall of the pixel body. Instead, it uses a dry etching method, which avoids the defects of patterning failure, large overlay offset, and high production cost caused by using a photolithography machine for patterning etching in the prior art. At the same time, it can also effectively ensure the fabrication accuracy. In addition, the outer edge wall structure can be customized to enhance optical and electrical functions and realize optical or electrical control.

[0125] Example 6

[0126] This embodiment provides a photoelectric device based on multi-faceted reflection and its fabrication method, so that the LED photoelectric device has better optical intensity and effectively avoids leakage failure of pixel unit, thereby improving the reliability of LED photoelectric device.

[0127] The structure of the optoelectronic device based on multi-faceted reflection in this embodiment will be further described below with reference to Figures 10-19.

[0128] Referring to Figure 10, this embodiment discloses an optoelectronic device based on multi-faceted reflection, including a driving wafer 10 and a pixel unit 20. The driving wafer 10 is used for driving and controlling the light emission of the pixel unit 20.

[0129] The driving wafer 10 includes an anode contact 101 for anode connection with the pixel unit 20;

[0130] Pixel unit 20 is disposed on drive wafer 10 and corresponds to anode contact 101;

[0131] The pixel unit 20 includes a pixel body 201 and an outer edge wall 202. The outer edge wall 202 is disposed on the side wall of the pixel body 201. The outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022. The inner wall of the side insulating layer 2021 is attached to the side wall of the pixel body 201 so that there is no gap between them. The outer wall of the side insulating layer 2021 and the side reflective metal layer 2022 are attached to each other so that there is no gap between them.

[0132] The pixel body 201 has an N-type semiconductor layer 2011 on the side away from the driving wafer 10 and a P-type semiconductor layer 2013 on the side closer to the driving wafer 10.

[0133] A transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10; the P-type semiconductor layer 2013 is electrically connected to the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203.

[0134] A bottom reflective metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10 to achieve bottom reflection;

[0135] In each pixel unit 20, the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 are insulated from each other by a side insulating layer 2021, and the N-type semiconductor layers 2011 in all pixel units 20 are connected by a common cathode 40.

[0136] In this embodiment, the N-type semiconductor layer 2011 is equivalent to the second semiconductor layer 2015 in Embodiment 1, and the P-type semiconductor layer 2013 is equivalent to the first semiconductor layer 2014 in Embodiment 1; or, the N-type semiconductor layer 2011 is equivalent to the first semiconductor layer 2014 in Embodiment 1, and the P-type semiconductor layer 2013 is equivalent to the second semiconductor layer 2015 in Embodiment 1.

[0137] The side insulating layer 2021 is equivalent to the first wall layer 2024 in Embodiment 1, and the side reflective metal layer 2022 is equivalent to the second wall layer 2025 in Embodiment 1.

[0138] In the above structure, a side reflector is formed by the side insulating layer 2021 and the side reflective metal layer 2022, and a bottom reflector is formed by the transparent conductive film layer 203 and the bottom reflective metal layer 204, thus forming a multi-faceted reflection cavity. This allows the light emitted by the pixel unit 20 to be reflected not only from the bottom surface but also from the side surface, achieving a multi-faceted reflection effect. This improves the light collection rate and utilization rate, which is beneficial to the overall optical efficiency. It also greatly improves the brightness and collimation of the pixel unit 20, and further constrains the divergence angle while improving performance, thereby improving the overall optical intensity and brightness of the pixel unit 20.

[0139] Furthermore, the side insulating layer 2021 and the side reflective metal layer 2022 can be used to form an omni-directional reflector (ODR) mirror, while the transparent conductive film layer 203 and the bottom reflective metal layer 204 can also form an ODR mirror, so as to better reduce reflection loss and improve reflectivity, thereby better improving the light output brightness and intensity of the pixel unit 20.

[0140] In addition, the above-mentioned pixel unit 20 structure, by providing an outer edge wall 202 on the side wall of the pixel body 201, ensures that the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated from each other by the side insulating layer 2021, which can effectively prevent short circuit leakage between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013, thereby better ensuring the reliability of the pixel unit 20 structure.

[0141] In each pixel body 201, an active layer 2012 is generally provided between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 for emitting light; the driving wafer 10 can be a CMOS driving wafer.

[0142] In addition, the pixel unit and the anode contact can be in one-to-one correspondence, or multiple anode contacts can correspond to one pixel unit.

[0143] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 2 below. In some practical applications, the film layers of the compounds will be more complex, or there may be cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials, and the active layer (MQW quantum well) sandwiched between the two:

[0144] Table 2. Film Material Table for Each Compound

[0145] In one embodiment, a bonding layer 30 is further disposed between the bottom reflective metal layer 204 and the driving wafer 10. The bonding layer 30 is a conductive layer used to realize electrical conduction between the P-type semiconductor layer 2013 and the driving wafer 10. The bonding layer 30 includes a first bonding metal layer 301 and a second bonding metal layer 302. The bottom reflective metal layer 204 is electrically connected to the first bonding metal layer 301, and the second bonding metal layer 302 is electrically connected to the anode contact 101.

[0146] In this process, the P-type semiconductor layer 2013 and the bottom reflective metal layer 204 are directly in contact with the transparent conductive film layer 203 and electrically connected. At this time, the P-type semiconductor layer 2013 is electrically connected directly through the transparent conductive film layer 203, the bottom reflective metal layer 204 and the bonding layer 30 in sequence, without the need to set up an external conductive structure.

[0147] In one embodiment, the transparent conductive film layer 203 on the bottom surface is one or more of ITO (indium tin oxide) film, ZnO (zinc oxide) film, or IZO (indium zinc oxide) film.

[0148] Among them, the transparent conductive film layer 203 on the bottom surface can be directly used as the P-type ohmic contact layer of the P-type semiconductor layer 2013.

[0149] For example, a Si-based blue light-emitting indium gallium nitride (InGaN) compound is selected, and an ITO film is deposited on the surface of its P-type semiconductor layer through methods such as evaporation and sputtering. The ITO film thickness is 70 nm, and ohmic contacts are formed through high-temperature annealing, thus forming a P-type ohmic contact layer. The specific film thickness and contact formation conditions can be adjusted and varied according to requirements, and are not limited here.

[0150] In one embodiment, the thickness of the side insulating layer 2021 is greater than the thickness of the side reflective metal layer 2022, so as to better ensure the insulation effect of the side insulating layer.

[0151] For example, the side insulating layer 2021 uses a silicon dioxide layer with a thickness of 300 nm, and the side reflective metal layer 2022 uses an aluminum layer with a thickness of 100 nm.

[0152] In one embodiment, as shown in FIG10, a step portion 20211 is formed at one end of the side insulating layer 2021 near the transparent conductive film layer 203, and the side reflective metal is located on the step portion 20211.

[0153] In another embodiment, as shown in FIG11, the side insulating layer 2021 may not have a stepped portion 20211 at the end near the transparent conductive film layer 203.

[0154] In actual working conditions, the structure of stepped portion 20211 or stepless portion 20211 can be obtained according to the actual manufacturing process.

[0155] In one embodiment, as shown in Figures 17-19, a metal mesh 60 is provided between two adjacent pixel units 20. Each metal mesh 60 is electrically connected to the common cathode 40 to enhance the current spread of the common cathode 40, further enhance the light intensity and convergence of the emission angle, and better prevent pixel crosstalk.

[0156] The aforementioned metal mesh 60 can be achieved by patterned vapor deposition or patterned etching after coating, such as using aluminum metal as the metal mesh.

[0157] In one embodiment, as shown in Figures 17-19, a microlens 70 is also provided on each pixel unit 20. The lens can be hemispherical or semi-rugby-shaped, and the focal point of the lens can be the surface where the common cathode 40 is located or the surface where the metal mesh is located.

[0158] In some configurations, as shown in stage b of Figure 17, the metal mesh 60 is located below the common cathode 40, and the aforementioned metal mesh 60 is provided on both sides of each pixel unit 20.

[0159] In other embodiments, such as the structure shown in stage b of Figure 18, the metal mesh 60 may also be located above the common cathode 40, with a microlens 70 disposed between two adjacent metal meshes 60.

[0160] The height of each microlens 70 can be the same or different, and can be prepared according to actual needs.

[0161] In some methods, as shown in stage a of Figure 19, the common cathode 40 can also be a non-planar structure. The N-type semiconductor layer can be exposed by patterning etching, and then the common cathode 40 can be deposited by sputtering, evaporation or other methods. At this time, the end of the common cathode 40 that contacts the N-type semiconductor layer has a recess 401, and the common cathode 40 transitions from both sides of the pixel unit to the aforementioned recess 401 in the middle through rounded corners.

[0162] The aforementioned recess 401 can be trapezoidal in shape, wider at the top and narrower at the bottom, or it can be arc-shaped or other shapes. The recess 401 makes the relative height of the side reflective metal layer 2022 higher than the pixel body 201, thereby further improving the anti-crosstalk effect. For example, the upper end of the side reflective metal layer 2022 can be set to extend beyond the top of the pixel body 201. It is understood that by controlling the depth of the recess 401, the height of the side reflective metal layer 2022 relative to the pixel body 201 can be adjusted, thereby adjusting the anti-crosstalk effect.

[0163] Furthermore, as shown in stage c of Figure 19, the common cathode 40 is at least partially located inside the microlens 70, which also allows the outer edge wall 202 to be at least partially located inside the microlens 70.

[0164] As shown in Figure 15, this embodiment also discloses a method for fabricating an optoelectronic device based on multi-faceted reflection, including:

[0165] 1) As shown in Figure 12, a driving wafer 10 is first prepared, such that the driving wafer 10 includes an anode contact 101;

[0166] 2) The compound semiconductor and the driving wafer 10 are connected, and the compound semiconductor 50 is processed to form a pixel unit 20 corresponding to the anode contact 101; wherein, the structure of the compound semiconductor 50 is shown in FIG4.

[0167] The aforementioned pixel unit 20 includes a pixel body 201 and an outer edge wall 202. The outer edge wall 202 is disposed on the side wall of the pixel body 201. The outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022. The inner wall of the side insulating layer 2021 is attached to the side wall of the pixel body 201, and the outer wall of the side insulating layer 2021 is attached to the side reflective metal layer 2022.

[0168] An N-type semiconductor layer 2011 is disposed on the side of the pixel body 201 away from the driving wafer 10, and a P-type semiconductor layer 2013 is disposed on the side closer to the driving wafer 10; a transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10, and a bottom reflective metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10.

[0169] The P-type semiconductor layer 2013 is electrically connected to the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203, and the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated from each other by the side insulating layer 2021.

[0170] 3) Finally, all the N-type semiconductor layers 2011 in the pixel units 20 are connected through the common cathode 40.

[0171] In one embodiment, the compound semiconductor and the driving wafer 10 are bonded together by a bonding layer 30, which is a conductive layer and includes a first bonding metal layer 301 and a second bonding metal layer 302.

[0172] Before bonding, bonding metal needs to be deposited on the bottom reflective metal of the compound semiconductor 50 to form a first bonding metal layer 301, and bonding metal is also deposited on the driving wafer 10 to form a second bonding metal layer 302, so that the anode contact 101 and the second bonding metal layer 302 are electrically connected. Then the compound semiconductor 50 is inverted so that the first bonding metal layer 301 and the second bonding metal layer 302 are hot-pressed together to form a bonding layer 30.

[0173] The aforementioned bonding metal materials can be one or more of the following combinations: Ni+Sn, Au+Sn, Cu+Sn, Au+In, Au+Au, Al+Al, Cu+Cu, ITO+ITO, etc.

[0174] Compound semiconductors generally refer to compounds formed by two or more elements. These include crystalline inorganic compounds (such as group III-V and II-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in this application are mainly LED epitaxial materials, such as InGaN ternary material systems or AlGaInP quaternary material systems.

[0175] In one embodiment, as shown in FIG13, the compound semiconductor 50 includes a first substrate 501, and an N-type semiconductor layer 2011, a P-type semiconductor layer 2013, a transparent conductive film layer 203, a bottom reflective metal layer 204, and a first bonding metal layer 301 sequentially formed along a direction away from the first substrate 501. An active layer 2012 is disposed between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013. A second bonding metal layer 302 is disposed on the driving wafer 10, and the anode contact 101 is electrically connected to the second bonding metal layer 302.

[0176] The method of connecting the compound semiconductor and the driving wafer 10, and processing the compound semiconductor 50 to form a pixel unit 20 corresponding to the anode contact 101 includes,

[0177] Step W1), as shown in stage a of Figure 15, involves thermo-press bonding of the first bonding metal layer 301 of the compound semiconductor 50 and the second bonding metal layer 302 of the driving wafer 10 to achieve bonding connection.

[0178] Step W2), remove the first substrate 501 of the compound semiconductor 50;

[0179] The method for removing the first substrate varies depending on the substrate material. For example, laser lift-off can be used to remove the sapphire substrate, while HNA wet etching can be used to remove the silicon substrate. After removing the first substrate, the N-type semiconductor is exposed on the wafer surface, enabling pixelation fabrication. If necessary, an N-ohm contact layer can be fabricated on the N-type semiconductor. This ohm contact layer can be a transparent conductive layer or a metal layer, such as a single layer or stack of Au, Ge, or Al.

[0180] The first substrate can be gallium nitride (GaN), silicon (Si), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), indium phosphide (InP), etc.

[0181] Step W3) As shown in stage b of Figure 15, the compound semiconductor 50 is etched by the first etching method. During the etching, the transparent conductive film layer 203 is used as the etching stop layer, thereby obtaining multiple pixel bodies 201 corresponding to the anode contact 101.

[0182] The first etching method mentioned above can be photolithography, dry etching, or wet etching, etc.

[0183] Step W4) As shown in the cd stage of Figure 15, an outer edge wall 202 is formed at the side wall of each pixel body 201. The outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022. The side insulating layer 2021 is deposited on the side wall of the pixel body 201, and the side reflective metal layer 2022 is deposited on the outer wall of the side insulating layer 2021.

[0184] Step W5), as shown in stage e of Figure 15, involves etching away the bonding layer 30 between the outer edge walls 202 of two adjacent pixel bodies 201 and the material layer above the bonding layer 30, thereby forming electrical isolation between the pixel bodies 201.

[0185] Understandably, the so-called removal of "material layers above the bonding layer 30" refers to removing all material layers above the bonding layer 30 between the outer edge walls 202. For example, if the bonding layer 30 between the outer edge walls 202 also has a bottom metal reflective layer and a transparent conductive film layer 203, then they are removed together. If a bottom reflective medium layer 205 is also provided between the bottom metal reflective layer and the transparent conductive film layer 203, then all three in this area are removed together.

[0186] In step W5), the etching method can be IBE (Ion Beam Etching).

[0187] Finally, the common cathode 40 can be prepared as shown in stage f of Figure 15.

[0188] Furthermore, in step W4), when forming the outer edge wall 202 at the sidewall of each pixel body 201, either a whole-body etching method or a layered etching method can be used:

[0189] Referring to the cd stage in Figure 15, the overall etching method is as follows: a side insulating layer 2021 is deposited on the outside of the pixel body 201, and then a side reflective metal layer 2022 is deposited on the outside of the side insulating layer 2021. After all the deposition is completed, the overall structure composed of the side insulating layer 2021 and the side reflective metal layer 2022 is etched using a dry etching method. After etching, only the side insulating layer 2021 and the side reflective metal layer 2022 located on the side wall of the pixel body 201 are retained.

[0190] In the pixel unit 20 obtained by the overall etching method, a step portion 20211 is formed at one end of the side insulating layer 2021 near the transparent conductive film layer 203, and the side reflective metal is located on the step portion 20211.

[0191] Referring to stage cf in Figure 16, the layered etching method is as follows: After depositing a side insulating layer 2021 on the outside of the pixel body 201, the side insulating layer 2021 is first etched using a dry etching method. After etching, only the side insulating layer 2021 located on the side wall of the pixel body 201 is retained. Then, a side reflective metal layer 2022 is deposited on the outside of the side insulating layer 2021. After the deposition is completed, the side reflective metal layer 2022 is etched using a dry etching method. After etching, only the side reflective metal layer 2022 located on the side wall of the pixel body 201 is retained.

[0192] In the pixel unit 20 obtained by the layer etching method, a step portion will not be formed at the end of the side insulating layer 2021 near the transparent conductive film layer 203.

[0193] The above-mentioned method for fabricating the outer edge wall of the pixel unit does not require a photolithography machine during fabrication. Instead, it uses a dry etching method, which eliminates the need for more advanced photolithography machines and eliminates the need for exposure processes. This avoids the defects caused by patterning failure, large overlay offset, and high production cost in existing technologies that use photolithography machines for patterning etching. At the same time, it can effectively ensure the fabrication accuracy, achieving in-situ or self-alignment type accuracy, and realizing submicron accuracy using micron-level equipment and processes.

[0194] In one embodiment, the side insulating layer 2021 includes one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide, and niobium pentoxide.

[0195] In one embodiment, the bottom reflective metal layer 204 and the side reflective metal layer 2022 both include one or more of silver, aluminum, aluminum-copper alloy, aluminum-nickel alloy, gold, rhodium, and platinum.

[0196] In one embodiment, as shown in Figures 15-19, when all the N-type semiconductor layers 2011 in the pixel units 20 are connected by a common cathode 40, a common cathode 40 can be formed by depositing a transparent conductive film on the N-type semiconductor side of all pixel units 20 by sputtering, evaporation, or other methods. The film can be one or more of ITO (indium tin oxide), AZO (zinc aluminum oxide), ATO (tin antimony oxide), and FTO (tin dioxide doped with fluorine), or a combination thereof, or metal-doped ITO can be formed by depositing Al, Au, or Ag on the ITO surface and then annealing it to enhance the current transport capability of the common cathode 40 layer.

[0197] Specifically, as shown in stage a of Figure 17, the surface can be planarized and the N-type semiconductor layer exposed by CMP, and then common cathode deposition can be performed by sputtering, evaporation or other methods; or as shown in stage a of Figure 10, the N-type semiconductor layer can be exposed by patterning etching, and then common cathode deposition can be performed by sputtering, evaporation or other methods; or in the stage of patterning etching to expose the N-type semiconductor layer, the dielectric layer between the pixels can also be patterned and etched. The etching depth of the dielectric layer can be the same as the etching depth of the exposed N-type semiconductor layer, or it can be etched to a deeper depth. After etching, metal is filled in the etching trenches before the common cathode 40 is prepared.

[0198] In one embodiment, during fabrication, after connecting the N-type semiconductor layers 2011 in all pixel units 20 through a common cathode 40, a metal mesh 60 is also electrically connected to the common cathode 40.

[0199] Example 7

[0200] This embodiment provides an optoelectronic device based on multi-faceted reflection and its fabrication method. As shown in Figure 11, the main difference between this embodiment and Embodiment 7 is that a bottom surface reflective medium layer 205 is also provided between the transparent conductive film layer 203 and the bottom surface reflective metal layer 204. The bottom surface reflective medium layer 205 is a non-conductive layer, so as to enhance the bottom surface reflection effect through the bottom surface reflective medium layer 205.

[0201] Furthermore, the bottom reflective dielectric layer 205 includes one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide, and niobium pentoxide.

[0202] The above structure can be formed by the transparent conductive film layer 203, the bottom reflective medium layer 205 and the bottom reflective metal layer 204 together to form an ODR reflector, or by the bottom reflective medium layer 205 and the bottom reflective metal layer 204 together to form an ODR reflector.

[0203] In one embodiment, the refractive index of the bottom reflective medium layer 205 is less than that of the transparent conductive film layer 203 to enhance the ODR reflection effect.

[0204] In one embodiment, the pixel unit 20 further includes a side metal fence 2023, which is located outside the side reflective metal layer 2022. The transparent conductive film layer 203 and the bottom reflective metal layer 204 are electrically connected through the side metal fence 2023, thereby realizing the anodic connection between the P-type semiconductor layer 2013 and the bonding layer 30.

[0205] As shown in Figure 16, this embodiment also discloses a method for fabricating a multi-faceted reflective optoelectronic device. The main difference between this method and the method in Embodiment 1 is that the structure of the compound semiconductor 50 is shown in Figure 14. When the compound semiconductor and the driving wafer 10 are connected and the compound semiconductor 50 is processed to form a pixel unit 20 corresponding to the anode contact 101, in step S5), when the bonding layer 30 between the outer edge walls 202 of two adjacent pixel bodies 201 and the material layer above the bonding layer are etched away, a side metal fence 2023 also needs to be formed. The side metal fence 2023 is located outside the side reflective metal layer 2022, so that the transparent conductive film layer 203 and the bottom reflective metal layer 204 are electrically connected through the side metal fence 2023.

[0206] The aforementioned metal fence 2023 can be a fence formed by IBE etching, which allows the fence to be utilized without removal, thus simplifying the process and improving process stability, as well as improving product yield and reducing costs; the aforementioned metal fence can also be a fence formed by other methods.

[0207] The optoelectronic devices and their fabrication methods based on multi-faceted reflection described in Examples 6 and 7 introduce a side insulating layer and a side reflective metal layer to form a side reflector, and a bottom reflector is formed by a transparent conductive film layer and a bottom reflective metal layer, thereby forming a multi-faceted reflection cavity. This achieves a multi-faceted reflection effect, improves the light collection rate and utilization rate, and increases the brightness performance of the device. In addition, it can also effectively avoid leakage risks and crosstalk between pixels, and is also conducive to improving the pixel density of LED devices.

[0208] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0209] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A pixel cell, characterized by: The pixel body comprises a second semiconductor layer, an active layer and a first semiconductor layer arranged in sequence along a first direction. The outer edge wall is arranged on the side wall of the pixel body, and comprises a first wall layer which is in close contact with the side wall of the pixel body; the first wall layer is an insulator, and the first semiconductor layer and the second semiconductor layer are insulated from each other by the first wall layer. The support substrate has a first surface and a second surface arranged opposite along the first direction; the pixel body is arranged on the first surface.

2. The pixel cell of claim 1, wherein: The outer edge wall is in direct contact with the support substrate at one end close to the support substrate.

3. The pixel cell of claim 2, wherein: The outer edge wall is separated from the support substrate at one end close to the support substrate by the second semiconductor layer to expose the second semiconductor layer.

4. The pixel cell of claim 2, wherein: The thickness of the first wall layer is 50-1500 nm.

5. The pixel cell of claim 1, wherein: The outer edge wall further comprises a second wall layer which is in close contact with the outer wall of the first wall layer.

6. The pixel cell of claim 2, wherein: The first wall layer has a step portion at one end close to the support substrate, and the second wall layer is located on the step portion.

7. The pixel cell of claim 6, wherein: The second wall layer is one of a reflective layer or a conductive layer, or a composite layer composed of a reflective layer and a conductive layer.

8. The pixel cell of claim 6, wherein: The outer edge wall further comprises a metal barrier layer, and the second wall layer is located between the first wall layer and the metal barrier layer.

9. The pixel cell of claim 6, wherein: The length of the pixel body along a second direction is 0.35-50 um, and the second direction is perpendicular to the first direction.

10. The pixel cell of claim 2, wherein: The angle between the pixel body and the support substrate is 45-135°.

11. The pixel unit according to claim 2, characterized in that: The angle between the pixel body and the support substrate is 70-110°.

12. The pixel cell of claim 2, wherein: The pixel body comprises a second semiconductor layer, an active layer and a first semiconductor layer arranged in sequence along a first direction.

13. A method for fabricating a pixel unit, characterized in that: The pixel body is obtained by etching with the etching stop layer as a mask using a dry etching or wet etching method; the length of the pixel body along a second direction is the same as the length of the etching stop layer, and the second direction is perpendicular to the first direction. The first wall layer is deposited outside the pixel body, and the etching stop layer is located between the pixel body and the first wall layer. The first wall layer is etched using a dry etching method, and only the first wall layer located at the side wall of the pixel body is retained after etching. The etching time is controlled to remove the etching stop layer so that the first semiconductor layer is exposed. In step S1), the second semiconductor layer, the active layer, the first semiconductor layer and the etching stop layer are formed in sequence along the first direction on the first surface of the support substrate. In step S3), when the first wall layer is deposited outside the pixel body, the deposition thickness of the first wall layer at the top of the pixel body is defined as D1, and the deposition thickness of the first wall layer at the side wall of the pixel body is defined as D2, and D1≥D2.

14. The method of claim 13, wherein: ​ 15. The method of claim 13, wherein: ​ 16. The method of claim 13, wherein: In step S3), after the first wall layer is deposited outside the pixel body, a second wall layer is further deposited, and after the deposition is completed, the whole structure composed of the first wall layer and the second wall layer is etched as a whole by using a dry etching method, and only the first wall layer and the second wall layer located at the side wall of the pixel body are reserved after etching; and the etching time is controlled to remove the etching blocking layer so that the first semiconductor layer is exposed; Alternatively, after the first wall layer is deposited outside the pixel body, the first wall layer is etched by using a dry etching method, and only the first wall layer located at the side wall of the pixel body is reserved after etching, and then a second wall layer is deposited outside the first wall layer, and after the deposition is completed, the second wall layer is etched by using a dry etching method, and only the second wall layer located at the side wall of the pixel body is reserved after etching; and the etching time is controlled to remove the etching blocking layer so that the first semiconductor layer is exposed.

17. The method of claim 13, wherein: After etching, only the first wall layer and the second wall layer located at the side wall of the pixel body are reserved, and then a metal blocking layer is deposited outside the second wall layer, and after the deposition is completed, the metal blocking layer is etched by using a dry etching method, and only the metal blocking layer located at the side wall of the pixel body is reserved after etching; and the etching time is controlled to remove the etching blocking layer so that the first semiconductor layer is exposed.

18. The method of claim 13, wherein: The first wall layer comprises at least two layers, and the materials of the two adjacent layers are different.

19. The method of claim 13, wherein: The first wall layer comprises one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

20. A multi-faceted reflective based optoelectronic device, comprising: Comprise, A driving wafer, wherein an anode contact is included in the driving wafer; A pixel unit is arranged on the driving wafer and corresponds to the anode contact, and the pixel unit comprises a pixel body and an outer wall, the outer wall is arranged on the side wall of the pixel body, and the outer wall comprises a side insulating layer and a side reflective metal layer, the inner wall of the side insulating layer is fitted with the side wall of the pixel body, and the outer wall of the side insulating layer is fitted with the side reflective metal layer; The pixel body is provided with an N-type semiconductor layer away from the driving wafer, and is provided with a P-type semiconductor layer close to the driving wafer, a transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer, the P-type semiconductor layer is electrically connected with the corresponding anode contact on the driving wafer through the transparent conductive film layer, and a bottom reflective metal layer is formed between the transparent conductive film layer and the driving wafer; wherein the N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated by the side insulating layer, and the N-type semiconductor layers in all pixel units are connected by a common cathode.

21. The multi-faceted reflective-based optoelectronic device of claim 20, wherein: The bottom reflective metal layer and the driving wafer are further provided with a bonding layer, the bonding layer is a conductive layer, the bonding layer comprises a first bonding metal layer and a second bonding metal layer, the first bonding metal layer is electrically connected with the bottom reflective metal layer, and the second bonding metal layer is electrically connected with the anode contact.

22. The multi-faceted reflective-based optoelectronic device of claim 21, wherein: The P-type semiconductor layer and the bottom surface reflection metal layer are directly contacted with the transparent conductive film layer for electrical connection.

23. The multi-faceted reflective-based optoelectronic device of claim 21, wherein: A bottom surface reflection medium layer is further arranged between the transparent conductive film layer and the bottom surface reflection metal layer, and the bottom surface reflection medium layer is a non-conductive layer.

24. The multi-faceted reflective-based optoelectronic device of claim 23, wherein: The pixel unit further comprises a side surface metal fence, which is located outside the side surface reflection metal layer, and the transparent conductive film layer and the bottom surface reflection metal layer are electrically connected through the side surface metal fence.

25. The multi-faceted reflective-based optoelectronic device of claim 23, wherein: The refractive index of the bottom surface reflection medium layer is less than the refractive index of the transparent conductive film layer.

26. The multifaceted reflective optoelectronic device of claim 20, wherein: The transparent conductive film layer adopts one or more of ITO film layer, ZnO film layer and IZO film layer.

27. The multifaceted reflective optoelectronic device of claim 20, wherein: The side surface insulation layer is formed with a step portion near one end of the transparent conductive film layer, and the side surface reflection metal is located on the step portion.

28. The multifaceted reflective optoelectronic device of claim 20, wherein: A metal mesh is further arranged between two adjacent pixel units, and each metal mesh is electrically connected with the common cathode.

29. The multifaceted reflective optoelectronic device of claim 20, wherein: A microlens is further connected to each pixel unit.

30. A method of fabricating a multi-faceted reflective based optoelectronic device, the method comprising: The application relates to a pixel unit and a manufacturing method thereof. ​ The compound semiconductor and the driving wafer are connected, and the compound semiconductor is processed to form a pixel unit corresponding to the anode contact; the pixel unit comprises a pixel body and an outer wall body arranged on the side wall of the pixel body, the outer wall body comprises a side surface insulation layer and a side surface reflection metal layer, the inner wall of the side surface insulation layer is matched with the side wall of the pixel body, and the outer wall of the side surface insulation layer is matched with the side surface reflection metal layer; an N-type semiconductor layer is arranged on the side of the pixel body away from the driving wafer, and a P-type semiconductor layer is arranged on the side of the pixel body close to the driving wafer; a transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer; the P-type semiconductor layer is electrically connected with the corresponding anode contact on the driving wafer through the transparent conductive film layer; and a bottom surface reflection metal layer is formed between the transparent conductive film layer and the driving wafer. The N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated through the side surface insulation layer. The N-type semiconductor layers in all the pixel units are electrically connected through a common cathode. The compound semiconductor and the driving wafer are connected through a bonding layer, the bonding layer is a conductive layer, the bonding layer comprises a first bonding metal layer and a second bonding metal layer, the bottom surface reflection metal layer is electrically connected with the first bonding metal layer, and the anode contact is electrically connected with the second bonding metal layer.

31. The method of claim 30, wherein: The compound semiconductor comprises a first substrate, an N-type semiconductor layer, a P-type semiconductor layer, a transparent conductive film layer, a bottom surface reflection metal layer and a first bonding metal layer which are sequentially arranged away from the first substrate, and an active layer is arranged between the N-type semiconductor layer and the P-type semiconductor layer; a second bonding metal layer is arranged on the driving wafer, and the anode contact is electrically connected with the second bonding metal layer.

32. The method of claim 31, wherein: ​ A method for connecting a compound semiconductor and a driving wafer and processing the compound semiconductor to form pixel units corresponding to the anode contacts, comprising, Step W1), bonding and connecting a first bonding metal layer of the compound semiconductor and a second bonding metal layer of the driving wafer; Step W2), removing the first substrate of the compound semiconductor; Step W3), etching the compound semiconductor by a first etching method, and taking the transparent conductive film layer as an etching stop layer during etching, so as to obtain pixel bodies corresponding to the anode contacts; Step W4), forming an outer edge wall at the sidewall of each pixel body, the outer edge wall comprising a side insulating layer and a side reflective metal layer, the side insulating layer being deposited on the sidewall of the pixel body, and the side reflective metal layer being deposited on the outer wall of the side insulating layer; Step W5), etching and removing the bonding layer between the outer edge walls of two adjacent pixel bodies and all material layers above the bonding layer, so as to form electrical isolation between the pixel bodies.

33. The method of claim 32, wherein: The method for forming the outer edge wall at the sidewall of each pixel body in step W4) comprises, depositing a side insulating layer outside the pixel body, then depositing a side reflective metal layer outside the side insulating layer, and then performing overall etching on the overall structure of the side insulating layer and the side reflective metal layer by using a dry etching method, and only retaining the side insulating layer and the side reflective metal layer located at the sidewall of the pixel body after etching; or, after depositing the side insulating layer outside the pixel body, first etching the side insulating layer by using a dry etching method, then only retaining the side insulating layer located at the sidewall of the pixel body after etching, then depositing a side reflective metal layer outside the side insulating layer, and then etching the side reflective metal layer by using a dry etching method after deposition, and only retaining the side reflective metal layer located at the sidewall of the pixel body after etching.

34. The method of claim 32, wherein: A bottom reflective dielectric layer is further deposited between the transparent conductive film layer and the bottom reflective metal layer in the compound semiconductor, and the bottom reflective dielectric layer is a non-conductive layer; When the compound semiconductor and the driving wafer are connected and the compound semiconductor is processed to form pixel units corresponding to the anode contacts, a side metal fence needs to be formed in step W5) when etching and removing the bonding layer between the outer edge walls of two adjacent pixel bodies and the material layers above the bonding layer, the side metal fence is located outside the side reflective metal layer, and the transparent conductive film layer and the bottom reflective metal layer are electrically connected through the side metal fence.

35. The method of claim 34, wherein: The bottom reflective dielectric layer and the side insulating layer each comprise one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide and niobium pentoxide.

36. The method of claim 30, wherein: The bottom reflective metal layer and the side reflective metal layer each comprise one or more of silver, aluminum, aluminum-copper alloy, aluminum-nickel alloy, gold, rhodium and platinum.

37. The method of claim 30, wherein the method further comprises: After connecting the N-type semiconductor layers in all the pixel units through a common cathode, a metal mesh gate is electrically connected to the common cathode.

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