Shift register, scan driver circuit, and display device

Abstract

The present application provides a shift register, a scan driver circuit, and a display device. The shift register in the present application comprises an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; the input sub-circuit is configured to: in response to a first clock signal, control the potential of a first node by means of an input signal; the first control sub-circuit is configured to: in response to the input signal, control the potential of a second node by means of a first power supply signal; the second control sub-circuit is configured to: in response to the potential of the second node, control the potential of a third node by means of the first clock signal, or in response to the potential of the first node, control the potential of the third node by means of the first power supply signal; the output sub-circuit is configured to: in response to the potential of the first node, output a second power supply signal by means of a first signal output end, or in response to the potential of the third node, output a third power supply signal by means of the first signal output end; the output sub-circuit comprises at least one dual-gate transistor.

Description

Shift register, scan drive circuit and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a scan drive circuit, and a display device. Background Technology

[0002] The display panel includes multiple light-emitting devices, each driven by a corresponding pixel driving circuit. The scan driving circuit provides control signals to the pixel driving circuit. The scan driving circuit includes multiple cascaded shift registers, each often integrating multiple transistors. The characteristics of these transistors ultimately determine the performance of the scan driving circuit.

[0003] Currently, oxide semiconductor thin-film transistors (OSTs) are widely used in large-size display panels due to their good uniformity. However, OSTs have relatively low on-state current (Ion). To achieve the required larger on-state current (Ion) for OSTs, a large aspect ratio (W / L) is needed. Therefore, shift registers with a large number of OSTs are often not conducive to achieving narrow bezels in display panels. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a shift register, a scan drive circuit, and a display device.

[0005] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a shift register, including an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit;

[0006] The input sub-circuit is configured to control the potential of the first node using an input signal in response to a first clock signal;

[0007] The first control sub-circuit is configured to control the potential of the second node using a first power supply signal in response to the input signal;

[0008] The second control sub-circuit is configured to control the potential of the third node using the first clock signal in response to the potential of the second node; or to control the potential of the third node using the first power supply signal in response to the potential of the first node.

[0009] The output sub-circuit is configured to output a second power signal through a first signal output terminal in response to the potential of the first node, or to output a third power signal through the first signal output terminal in response to the potential of the third node; wherein the output sub-circuit includes at least one dual-gate transistor.

[0010] In some embodiments, the output sub-circuit includes two dual-gate transistors, referred to as the fourth transistor and the eleventh transistor, respectively;

[0011] The first electrode of the fourth transistor is electrically connected to the first signal output terminal, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the gate is electrically connected to the first node.

[0012] The first electrode of the eleventh transistor is electrically connected to the third power signal line that transmits the third power signal, the second electrode is electrically connected to the first signal output terminal, and the gate is electrically connected to the third node.

[0013] In some embodiments, the input sub-circuit includes at least one dual-gate transistor.

[0014] In some embodiments, the input sub-circuit includes a dual-gate transistor, referred to as the first transistor;

[0015] The first electrode of the first transistor is electrically connected to the signal input terminal that receives the input signal, the second electrode is electrically connected to the first node, and the gate is electrically connected to the first clock signal line that transmits the first clock signal.

[0016] In some embodiments, the output sub-circuit is further configured to output a fourth power signal through a second signal output terminal in response to the potential of the first node, or to output the first power signal through the second signal output terminal in response to the potential of the third node.

[0017] In some embodiments, the output sub-circuit further includes a third transistor and a tenth transistor;

[0018] The first electrode of the third transistor is electrically connected to the second signal output terminal, the second electrode is electrically connected to the fourth power signal line that transmits the fourth power signal, and the gate is electrically connected to the first node.

[0019] The first electrode of the tenth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the second signal output terminal, and the gate is electrically connected to the third potential.

[0020] In some embodiments, both the third transistor and the tenth transistor are dual-gate transistors.

[0021] In some embodiments, the output sub-circuit further includes a first capacitor and a second capacitor;

[0022] The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first signal output terminal, or the second plate is electrically connected to the second signal output terminal.

[0023] The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the third power signal line, or the second plate is electrically connected to the first power signal line that transmits the first power signal.

[0024] In some embodiments, the shift register includes a substrate and a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a fourth conductive layer, and a fifth conductive layer disposed sequentially along a direction away from the substrate.

[0025] One of the first plate and the second plate of the first capacitor is located in the first conductive layer, and the other is located in the second conductive layer;

[0026] One of the first and second plates of the second capacitor is located in the first conductive layer, and the other is located in the second conductive layer;

[0027] The gates of the fourth transistor and the eleventh transistor include a first gate electrode and a second gate electrode that are electrically connected, and the first gate electrode of the fourth transistor and the first gate electrode of the eleventh transistor are both located in the third conductive layer; the second gate electrode of the fourth transistor and the second gate electrode of the eleventh transistor are both located in the fourth conductive layer;

[0028] The active layer of the fourth transistor and the active layer of the eleventh transistor are both located in the semiconductor layer.

[0029] The first and second electrodes of the fourth transistor, as well as the first and second electrodes of the eleventh transistor, are all located in the fifth conductive layer.

[0030] In some embodiments, the orthographic projections of the first gate electrode and the second gate electrode of the fourth transistor on the substrate at least partially overlap; the first gate electrode of the fourth transistor includes a plurality of first extensions arranged side by side along a first direction, and the second gate electrode of the fourth transistor includes a plurality of second extensions arranged side by side along the first direction; the extension directions of the first extensions and the extension directions of the second extensions are both second directions, and the first direction and the second direction are intersected; one end of the plurality of first extensions is connected by a first connecting portion; one end of the plurality of second extensions is connected by a second connecting portion;

[0031] The first gate electrode and the second gate electrode of the eleventh transistor have at least partially overlapping orthogonal projections on the substrate; the first gate electrode of the eleventh transistor includes a plurality of third extensions arranged side by side along a first direction, and the second gate electrode of the eleventh transistor includes a plurality of fourth extensions arranged side by side along the first direction; the extension directions of the third extensions and the extension directions of the fourth extensions are both second directions; one end of the plurality of third extensions is connected by a third connecting portion; one end of the plurality of fourth extensions is connected by a fourth connecting portion.

[0032] In some embodiments, the active layers of the fourth transistor and the eleventh transistor are made of oxide semiconductor materials.

[0033] In some embodiments, the first control sub-circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0034] The first terminal of the fifth transistor is electrically connected to the second terminal of the sixth transistor and the second terminal of the seventh transistor, the second terminal is electrically connected to the first power signal line that transmits the first power signal, and the gate is electrically connected to the signal input terminal that transmits the input signal.

[0035] The first electrode of the sixth transistor is electrically connected to the second node, and the gate is electrically connected to the signal input terminal.

[0036] The first electrode of the seventh transistor is electrically connected to the second power signal line that transmits the second power signal, and the gate is electrically connected to the second node.

[0037] In some embodiments, the second control sub-circuit includes an eighth transistor, a third capacitor, and a ninth transistor;

[0038] The first electrode of the eighth transistor is electrically connected to the first clock signal line that transmits the first clock signal, the second electrode is electrically connected to the third node, and the gate is electrically connected to the second node.

[0039] The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first electrode of the eighth transistor.

[0040] The first electrode of the ninth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line that transmits the first power signal, and the gate is electrically connected to the first node.

[0041] In some embodiments, the shift register further includes a first isolation sub-circuit;

[0042] The first isolation sub-circuit is configured to isolate the first node and the input sub-circuit electrically connected to the first node, and to electrically connect the fourth node and the first node;

[0043] The input sub-circuit is electrically connected to the fourth node.

[0044] In some embodiments, the shift register further includes a second isolation sub-circuit; the second isolation sub-circuit isolates the third node and the input sub-circuit electrically connected to the third node;

[0045] The second isolation sub-circuit is configured to isolate the third node and the input sub-circuit electrically connected to the third node, and to electrically connect the third node and the fifth node;

[0046] The input sub-circuit is electrically connected to the fifth node.

[0047] In some embodiments, the shift register further includes a pull-up circuit; the pull-up circuit includes a fourth capacitor, a thirteenth transistor, and a fourteenth transistor;

[0048] The first electrode of the thirteenth transistor is electrically connected to the floating signal terminal, the second electrode is electrically connected to the second clock signal line, and the gate is electrically connected to the fourth node.

[0049] The first plate of the fourth capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the floating signal terminal.

[0050] The first electrode of the fourteenth transistor is electrically connected to the first clock signal line that transmits the first clock signal, the second electrode is electrically connected to the floating signal terminal, and the gate is electrically connected to the fifth node.

[0051] In some embodiments, the voltage of the first power signal is less than or equal to the voltage of the third power signal;

[0052] The voltage of the second power supply signal is less than or equal to the voltage of the fourth power supply signal.

[0053] Secondly, embodiments of this disclosure also provide a scan driving circuit, including N cascaded shift registers as described in any one of the first aspects.

[0054] In some embodiments, the output sub-circuit is further configured to output a fourth power signal through a second signal output terminal in response to the potential of the first node, or to output the first power signal through the second signal output terminal in response to the potential of the third node;

[0055] Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the second signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0056] Thirdly, embodiments of this disclosure also provide a display device, including the scanning drive circuit as described in the second aspect. Attached Figure Description

[0057] Figure 1 is a circuit diagram of a shift register under the first example provided in the embodiments of this disclosure;

[0058] Figure 2 is a schematic diagram of the output signal waveform of the first signal output terminal in two cases, a single-gate structure and a double-gate structure, provided in the embodiments of this disclosure;

[0059] Figure 3 is a circuit diagram of a shift register under the second example provided in the embodiments of this disclosure;

[0060] Figure 4 is a circuit diagram of a shift register under the third example provided in the embodiments of this disclosure;

[0061] Figure 5 is a circuit diagram of the shift register under the fourth example provided in the embodiments of this disclosure;

[0062] Figure 6 is a circuit diagram of a shift register under the fifth example provided in the embodiments of this disclosure;

[0063] Figure 7 is a circuit diagram of a shift register under the sixth example provided in the embodiments of this disclosure;

[0064] Figure 8 is a circuit diagram of a shift register under the seventh example provided in the embodiments of this disclosure;

[0065] Figure 9 is a timing diagram of an exemplary shift register provided in an embodiment of this disclosure;

[0066] Figure 10 is a timing diagram of another exemplary shift register provided in an embodiment of this disclosure;

[0067] Figure 11a is a layout of the first conductive layer in the shift register;

[0068] Figure 11b shows the layout of the second conductive layer in the shift register;

[0069] Figure 11c shows the layout of the third conductive layer in the shift register;

[0070] Figure 11d shows the layout of the semiconductor layer in the shift register;

[0071] Figure 11e shows the layout of the fourth conductive layer in the shift register;

[0072] Figure 11f shows the layout of the fifth conductive layer in the shift register;

[0073] Figures 12a to 12e show the film layer layouts during the sequential stacking process of Figures 11a to 11f, respectively.

[0074] Figure 13 is a schematic diagram of a scanning drive circuit provided in an embodiment of this disclosure. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0077] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0078] In related technologies, oxide semiconductor thin-film transistors (OSBMTs) are often used as a large number of transistors in the scanning drive circuit of a display panel to improve the uniformity and stability of the display effect. The conduction current Ion mentioned in this disclosure refers to the current magnitude of the transistor in the on-state. The magnitude of the conduction current Ion can be set by adjusting the width-to-length ratio W / L of the transistor. Within a reasonable range, the relationship between the two is that the larger the width-to-length ratio W / L, the larger the conduction current Ion; conversely, the smaller the width-to-length ratio W / L, the smaller the conduction current Ion. Here, the width-to-length ratio W / L refers to the ratio of the width to the length of the channel region of the active layer of the transistor. Due to their inherent characteristics, OSBMTs have relatively low conduction current Ion. To achieve a larger required conduction current Ion, OSBMTs with a larger width-to-length ratio W / L need to be designed. Therefore, scanning drive circuits with a large number of OSBMTs are often not conducive to achieving narrow bezels in display panels.

[0079] In view of this, the present disclosure provides a shift register, which essentially increases the on-state current Ion_1 of the output transistors by using dual-gate transistors in at least a portion of the output sub-circuit, compared to single-gate transistors. Since the increased on-state current Ion_1 is greater than the actual required on-state current Ion_0, the on-state current Ion_1 can be reduced by decreasing the width-to-length ratio W / L of the output transistors, so that the reduced on-state current Ion_2 meets the actual required on-state current Ion_0. Reducing the width-to-length ratio W / L of the output transistors is beneficial for achieving a narrow bezel.

[0080] Figure 1 is a circuit diagram of a shift register under the first example provided in the embodiments of this disclosure. As shown in Figure 1, the shift register includes an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3, and an output sub-circuit 4.

[0081] Input sub-circuit 1 is electrically connected to the signal input terminal Input, the first clock signal line, and the first node N1; input sub-circuit 1 can receive the input signal CR from the signal input terminal Input. <i-1>and receiving a first clock signal CK1 transmitted from a first clock signal line. Input sub-circuit 1 is configured to respond to the first clock signal CK1 by utilizing the input signal CR <i-1>Control the potential of the first node N1. The first clock signal CK1 is a periodic pulse signal.

[0082] The first control sub-circuit 2 is electrically connected to the signal input terminal Input and the first power signal line; the first control sub-circuit 2 can receive the input signal CR from the signal input terminal Input. <i-1>and receiving a first power signal VGL1 transmitted from a first power signal line. The first control sub-circuit 2 is configured to respond to the input signal CR <i-1>The potential of the second node N2 is controlled by the first power supply signal VGL1. The input signal CR... <i-1>It is the signal output from the previous stage shift register cascaded with the shift register. The first power supply signal VGL1 can be a low-level signal, such as -5V or -8V.

[0083] The second control sub-circuit 3 is electrically connected to the first node N1, the first power signal line, the second node N2, the first clock signal line, and the third node N3. The second control sub-circuit 3 can receive a potential from the first node N1 and a first power signal VGL1 transmitted from the first power signal line. Specifically, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first power signal VGL1 in response to the potential of the first node N1. Alternatively, the second control sub-circuit 3 can receive a potential from the second node N2 and a first clock signal CK1 transmitted from the first clock signal line. The second control sub-circuit 3 is configured to control the potential of the third node N3 using the first clock signal CK1 in response to the potential of the second node N2.

[0084] Output sub-circuit 4 is electrically connected to the first node N1, the second power signal line, the third node N3, and the third power signal line. Output sub-circuit 4 can receive the potential from the first node N1 and the second power signal VGH2 transmitted from the second power signal line. Specifically, output sub-circuit 4 is configured to output the second power signal VGH2 through the first signal output terminal Out1 in response to the potential of the first node N1. Alternatively, output sub-circuit 4 can receive the potential from the third node N3 and the third power signal VGL2 transmitted from the third power signal line. Output sub-circuit 4 is configured to output the third power signal VGL2 through the first signal output terminal Out1 in response to the potential of the third node N3. The first signal output terminal Out1 is used to provide an on or off signal to the gate of the transistor in the pixel driving circuit.

[0085] For example, the signals of the first node N1 and the third node N3 have the same timing but opposite potentials, thereby enabling the output sub-circuit 4 to output different power signals. The second power signal VGH2 can be a high-level signal, such as 5V or 8V. The third power signal VGL2 can be a low-level signal, such as -5V or -8V.

[0086] Optionally, the first power signal VGL1 and the third power signal VGL2 can be the same or different.

[0087] The output sub-circuit 4 includes at least one dual-gate transistor. A dual-gate transistor is a transistor that adopts a dual-gate structure, that is, the transistor includes a first gate electrode and a second gate electrode that are arranged opposite to each other and electrically connected.

[0088] Optionally, the orthogonal projections of the first gate electrode and the second gate electrode on the substrate completely overlap.

[0089] Optionally, the orthographic projection of one of the first gate electrode and the second gate electrode onto the substrate covers the orthographic projection of the other onto the substrate. For example, if the first gate electrode is closer to the substrate than the second gate electrode, the orthographic projection of the second gate electrode onto the substrate covers the orthographic projection of the first gate electrode onto the substrate.

[0090] For example, the output sub-circuit 4 includes a plurality of output transistors, at least some of which are dual-gate transistors. Compared to single-gate transistors, dual-gate transistors accelerate the output of the second power supply signal VGH2 or the third power supply signal VGL2 in the on state and reduce leakage current in the off state.

[0091] In embodiments of this disclosure, at least some of the output transistors are dual-gate transistors, which improve the on-state current Ion compared to single-gate transistors. In practical applications, the on-state current Ion of the dual-gate transistors can be reduced by decreasing the width-to-length ratio W / L to meet practical requirements, thereby reducing the size of the output sub-circuit 4 and achieving a narrow bezel.

[0092] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0093] It should be noted that the thin-film transistor can be either an N-type or a P-type thin-film transistor; specifically, an N-type thin-film transistor refers to one in which N-type ions are doped in the active layer, and a P-type thin-film transistor refers to one in which P-type ions are doped in the active layer. The operating level signal for an N-type thin-film transistor is a high-level signal; the operating level signal for a P-type thin-film transistor is a low-level signal. Furthermore, for ease of understanding, this disclosure uses an N-type thin-film transistor as an example in the following embodiments, but this disclosure is not limited to N-type thin-film transistors.

[0094] In some embodiments, as shown in FIG1, the output sub-circuit 4 includes two dual-gate transistors, denoted as the fourth transistor T4 and the eleventh transistor T11, respectively. The first gate of the fourth transistor T4 is electrically connected to the first signal output terminal Out1, the second gate is electrically connected to the second power signal line transmitting the second power signal VGH2, and the gate is electrically connected to the first node N1. The first gate of the eleventh transistor T11 is electrically connected to the third power signal line transmitting the third power signal VGL2, the second gate is electrically connected to the first signal output terminal Out1, and the gate is electrically connected to the third node N3.

[0095] Specifically, the potential of the first node N1 can control the on / off state of the fourth transistor T4. When the fourth transistor T4 responds to the potential of the first node N1 and is turned on, the second power supply signal VGH2 can be output through the first signal output terminal Out1. The potential of the third node N3 can control the on / off state of the eleventh transistor T11. When the eleventh transistor T11 responds to the potential of the third node N3 and is turned on, the third power supply signal VGL2 can be output through the first signal output terminal Out1.

[0096] In this embodiment, the fourth transistor T4 and the eleventh transistor T11 adopt a dual-gate structure, which increases the on-current Ion of the fourth transistor T4 and the eleventh transistor T11, respectively. In practical applications, the width-to-length ratio W / L of the fourth transistor T4 and the eleventh transistor T11 can be reduced to meet the actual requirements of the on-current Ion while achieving a narrow bezel.

[0097] Optionally, the active layers of the fourth transistor T4 and the eleventh transistor T11 can be made of oxide semiconductor materials. That is, the fourth transistor T4 and the eleventh transistor T11 are oxide semiconductor thin-film transistors. For example, oxide semiconductor materials can include, but are not limited to, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). In practical applications, the fourth transistor T4 and the eleventh transistor T11 are larger than other transistors (e.g., the second transistor T2, the twelfth transistor T12, the fifth transistor T5, etc.), occupying a larger area, which is a key factor affecting the bezel size.

[0098] Table 1 shows a comparison of the aspect ratio and on-state current Ion for transistors T4 and T11 when they employ single-gate and dual-gate structures, respectively. The test conditions for transistors T4 and T11 are Vgs = 5V and Vds = 12V.

[0099] Table 1

[0100] As can be seen from the comparative analysis in Table 1, when the width-to-length ratio W / L is the same, the on-state current Ion of the output transistor with a single-gate structure (the fourth transistor T4 or the eleventh transistor T11) is less than that of the output transistor with a dual-gate structure.

[0101] Figure 2 is a schematic diagram of the output signal waveforms of the first signal output terminal under two cases: single-gate structure and double-gate structure, provided in the embodiments of this disclosure. As shown in Figure 2, the fourth transistor T4 and the eleventh transistor T11 using the single-gate structure have the same width-to-length ratio W / L as the fourth transistor T4 and the eleventh transistor T11 using the double-gate structure, both being 300 / 6. The falling edge time Tf of the output waveform using the single-gate structure is 3.2 μm; the falling edge time Tf of the output waveform using the double-gate structure is 2.1 μm.

[0102] It should be noted that the fall time (Tf) is the duration of the signal transition from a high level to a low level during the turn-off of an oxide semiconductor thin-film transistor (OSB). Under the same width-to-length ratio (W / L), a longer fall time (Tf) indicates a smaller on-state current (Ion); conversely, a shorter fall time (Tf) indicates a larger on-state current (Ion). Generally, to achieve reasonable switching characteristics for OSB thin-film transistors, Tf ≤ 1μm. That is, based on the condition Tf ≤ 1μm, the actual on-state current (Ion_0) of the fourth transistor T4 and the eleventh transistor T11 (using a dual-gate structure) can be reasonably designed during application. Furthermore, the width-to-length ratio (W / L) of the fourth transistor T4 and the eleventh transistor T11 can be reduced accordingly, for example, from 300 / 6 to 200 / 6.

[0103] In some embodiments, the width-to-length ratio W / L of the fourth transistor T4 ranges from 100 / 6 to 500 / 6. The width-to-length ratio W / L of the eleventh transistor T11 ranges from 100 / 6 to 500 / 6.

[0104] In some embodiments, the input sub-circuit 1 includes at least one dual-gate transistor. The dual-gate transistor increases the on-state current Ion compared to a single-gate transistor. In practical applications, the on-state current Ion of the dual-gate transistor can be reduced to meet practical requirements by decreasing the width-to-length ratio W / L, thereby reducing the size of the input sub-circuit 1 and achieving a narrow bezel.

[0105] For example, the input sub-circuit 1 includes a first transistor T1, which is a dual-gate transistor, that is, the first transistor T1 adopts a dual-gate structure. Compared with a single-gate structure, the first transistor T1 accelerates the input signal CR when it is turned on. <i-1>The writing reduces leakage current in the off state.

[0106] In some embodiments, FIG3 is a circuit diagram of a shift register under a second example provided in the present disclosure, which differs from the shift register under the first example shown in FIG1 in that the first transistor T1 is a dual-gate transistor.

[0107] As shown in Figure 3, the input sub-circuit 1 includes a dual-gate transistor, denoted as the first transistor T1. The first gate of the first transistor T1 is electrically connected to receive the input signal CR. <i-1>The signal input terminal Input is electrically connected to the first node N1, and the gate is electrically connected to the first clock signal line that transmits the first clock signal CK1.

[0108] Specifically, the first clock signal CK1 transmitted by the first clock signal line can control the on / off state of the first transistor T1. When the first transistor T1 responds to the first clock signal CK1 and is turned on, it can control the input signal CR. <i-1>Write to the first node N1, thereby changing the potential of the first node N1.

[0109] In this embodiment, the first transistor T1 adopts a dual-gate structure, which increases the on-current Ion of the first transistor T1. In practical applications, by reducing the width-to-length ratio W / L of the first transistor T1, the actual requirement of the on-current Ion can be met, while the size of the input sub-circuit 1 can be reduced, which is beneficial for achieving a narrow bezel.

[0110] Optionally, the active layer of the first transistor T1 can be made of an oxide semiconductor material.

[0111] In some embodiments, FIG4 is a circuit diagram of a shift register under a third example provided in the present disclosure. The difference between the shift register and the shift register under the first example shown in FIG1 is that the cascade terminal of the shift register (i.e., the second signal output terminal Out2 described below) is set separately from the first signal output terminal Out1 described above.

[0112] As shown in Figure 4, compared to the first example, the output sub-circuit 4 is also electrically connected to the first power signal line and the fourth power signal line. The output sub-circuit 4 can receive the potential from the first node N1 and the fourth power signal VGH1 transmitted from the fourth power signal line; the output sub-circuit 4 can also receive the potential from the third node N3 and the first power signal VGL1 transmitted from the first power signal line. Specifically, the output sub-circuit 4 is further configured to output the fourth power signal VGH1 through the second signal output terminal Out2 in response to the potential of the first node N1. Alternatively, it can output the first power signal VGL1 through the second signal output terminal Out2 in response to the potential of the third node N3. The fourth power signal VGH1 can be a high-level signal, such as 5V or 8V.

[0113] Optionally, the second power signal VGH2 and the fourth power signal VGH1 can be the same or different.

[0114] In this embodiment, the cascade terminal of the shift register (i.e., the second signal output terminal Out2) is set separately from the first signal output terminal Out1, so that the output signals of the shift register corresponding to each row of pixel units in the whole screen are more uniform.

[0115] In some embodiments, as shown in FIG4, the output sub-circuit 4 further includes a third transistor T3 and a tenth transistor T10. The first electrode of the third transistor T3 is electrically connected to the second signal output terminal Out2, the second electrode is electrically connected to the fourth power signal line transmitting the fourth power signal VGH1, and the gate is electrically connected to the first node N1. The first electrode of the tenth transistor T10 is electrically connected to the first power signal line transmitting the first power signal VGL1, the second electrode is electrically connected to the second signal output terminal Out2, and the gate is electrically connected to the third potential.

[0116] Specifically, the potential of the first node N1 can control the on / off state of the third transistor T3. When the third transistor T3 responds to the potential of the first node N1 and is turned on, the fourth power supply signal VGH1 can be output through the second signal output terminal Out2. The potential of the third node N3 can control the on / off state of the tenth transistor T10. When the tenth transistor T10 responds to the potential of the third node N3 and is turned on, the first power supply signal VGL1 can be output through the second signal output terminal Out2.

[0117] The second signal output terminal, Out2, which is also the cascade terminal of the shift register, is used to transmit the input signal CR to the next stage shift register. <i-1>.

[0118] In some embodiments, both the third transistor T3 and the tenth transistor T10 are dual-gate transistors, meaning that both transistors employ a dual-gate structure, which improves the on-state current Ion compared to a single-gate structure. In practical applications, the width-to-length ratio W / L of the third transistor T3 and the tenth transistor T10 can be reduced to meet the actual requirements of the on-state current Ion while achieving a narrow bezel.

[0119] Optionally, the third transistor T3 and the tenth transistor T10 can be oxide semiconductor thin-film transistors.

[0120] Optionally, the active layers of the third transistor T3 and the tenth transistor T10 can be made of oxide semiconductor materials. For example, oxide semiconductor materials may include, but are not limited to, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), etc.

[0121] In some embodiments, as shown in Figures 1, 3, and 4, the output sub-circuit 4 further includes a first capacitor C1 and a second capacitor C2; the first plate of the first capacitor C1 is electrically connected to the first node N1, and the second plate is electrically connected to the first signal output terminal Out1, or the second plate is electrically connected to the second signal output terminal Out2; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate is electrically connected to the third power signal line, or the second plate is electrically connected to the first power signal line that transmits the first power signal VGL1.

[0122] As shown in Figures 1 and 3, the first capacitor C1 is mainly used to bootstrap the potential of the first node N1 to a higher potential, thereby ensuring the continuous conduction of the fourth transistor T4, and thus stabilizing the output of the second power supply signal VGH2. The second capacitor C2 is mainly used to bootstrap the potential of the third node N3 to a higher potential, thereby ensuring the continuous conduction of the eleventh transistor T11, and thus stabilizing the output of the third power supply signal VGL2.

[0123] As shown in Figure 4, the first capacitor C1 is mainly used to bootstrap the potential of the first node N1 to a higher potential, thereby ensuring the continuous conduction of the third transistor T3 and the fourth transistor T4, and thus stabilizing the output of the fourth power supply signal VGH1 and the second power supply signal VGH2. The second capacitor C2 is mainly used to bootstrap the potential of the third node N3 to a higher potential, thereby ensuring the continuous conduction of the fourth transistor T4 and the eleventh transistor T11, and thus stabilizing the output of the first power supply signal VGL1 and the third power supply signal VGL2.

[0124] In some embodiments, as shown in Figures 1, 3, and 4, the first control sub-circuit 2 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is electrically connected to the second node N2, the second terminal is electrically connected to the first power signal line transmitting the first power signal VGL1, and the gate is electrically connected to the input signal CR. <i-1>The signal input terminal Input.

[0125] Specifically, the input signal CR <i-1>The switching on and off of the fifth transistor T5 can be controlled, and the fifth transistor T5 responds to the input signal CR. <i-1>When the circuit is turned on, the first power signal VGL1 can be transmitted to the second node N2 to control the potential of the second node N2.

[0126] In some embodiments, FIG5 is a circuit diagram of a shift register under the fourth example provided in the present disclosure. The difference between the shift register under the third example shown in FIG4 and the shift register is that a leakage protection structure is added.

[0127] As shown in Figure 5, the first control sub-circuit 2 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first terminal of the fifth transistor T5 is electrically connected to the second terminals of the sixth transistor T6 and the seventh transistor T7. The second terminal of the fifth transistor T5 is electrically connected to the first power signal line transmitting the first power signal VGL1, and its gate is electrically connected to the input signal CR. <i-1>The signal input terminal Input; the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the gate is electrically connected to the signal input terminal Input; the first electrode of the seventh transistor T7 is electrically connected to the second power signal line transmitting the second power signal VGH2, and the gate is electrically connected to the second node N2.

[0128] Specifically, the input signal CR <i-1>The switching on and off of the fifth transistor T5 and the sixth transistor T6 can be controlled simultaneously, with the fifth transistor T5 and the sixth transistor T6 responding to the input signal CR. <i-1>When the transistor is turned on, the first power supply signal VGL1 can be transmitted to the second node N2 to change the potential of the second node N2. Simultaneously, the potential of the second node N2 can control the on / off state of the seventh transistor T7. When the seventh transistor T7 responds to the potential of the second node N2 and turns on, the second power supply signal VGH2 can be written to the sixth node N6. The sixth node N6 is the node between the first terminal of the fifth transistor T5 and the second terminal of the sixth transistor T6.

[0129] It should be noted that, as shown in Figure 4, taking an N-type thin-film transistor as an example, if the threshold voltage of the fifth transistor T5 is negative, the voltage of the high-potential second node N2 will be transmitted in reverse, causing the fifth transistor T5 to leak. After leakage, the potential of the second node N2 no longer remains high, causing the eighth transistor T8 to be cut off, which in turn prevents the eleventh transistor T11 (and the tenth transistor T10) from turning on.

[0130] In this embodiment, as shown in Figure 5, a leakage protection structure is set up. That is, based on the fifth transistor T5, a sixth transistor T6 and a seventh transistor T7 are added. When the potential of the second node N2N2 is high, the seventh transistor T7 is turned on, and the second power supply signal VGH2 is written to the sixth node N6, making the potential of the sixth node N6 high. At this time, the first and second terminals of the sixth transistor T6 are both high. Regardless of whether the threshold voltages of the fifth transistor T5 and the sixth transistor T6 are negative, the potential of the second node N2N2 always remains high, thereby suppressing reverse leakage and ensuring the stable conduction of the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11.

[0131] Optionally, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all oxide semiconductor thin-film transistors.

[0132] Optionally, the absolute value of the voltage of the second power signal VGH2 is less than the absolute value of the voltage of the first power signal VGL1.

[0133] In some embodiments, as shown in Figures 1, 3, 4, and 5, the second control sub-circuit 3 includes an eighth transistor T8, a third capacitor C3, and a ninth transistor T9. The first electrode of the eighth transistor T8 is electrically connected to the first clock signal line transmitting the first clock signal CK1, the second electrode is electrically connected to the third node N3, and the gate is electrically connected to the second node N2. The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate is electrically connected to the first electrode of the eighth transistor T8. The first electrode of the ninth transistor T9 is electrically connected to the third node N3, the second electrode is electrically connected to the first power signal line transmitting the first power signal VGL1, and the gate is electrically connected to the first node N1.

[0134] Specifically, the potential of the second node N2 can control the on / off state of the eighth transistor T8. When the eighth transistor T8 responds to the potential of the second node N2 and conducts, the first clock signal CK1 can be written into the third node N3, thereby changing the potential of the third node N3. Alternatively, the potential of the first node N1 can control the on / off state of the ninth transistor T9. When the ninth transistor T9 responds to the potential of the first node N1 and conducts, the first power supply signal VGL1 can be written into the third node N3, thereby changing the potential of the third node N3.

[0135] When the first clock signal CK1 is at a high potential, the third capacitor C3 is used to couple the potential of the second node N2 to a high potential, thereby ensuring the continuous conduction of the eighth transistor T8 and stabilizing the output of the first clock signal CK1.

[0136] Optionally, both the eighth transistor T8 and the ninth transistor T9 are oxide semiconductor thin-film transistors.

[0137] In some embodiments, FIG6 is a circuit diagram of a shift register under the fifth example provided in the present disclosure. The difference between the shift register under the fourth example shown in FIG5 and the shift register is that a first isolation sub-circuit 5 is added.

[0138] As shown in Figure 6, the shift register also includes a first isolation sub-circuit 5; the first isolation sub-circuit 5 is configured to isolate the first node N1 and the input sub-circuit 1 electrically connected to the first node N1, and electrically connect the fourth node N4 and the first node N1, thereby improving the stable output of the second power supply signal VGH2. The input sub-circuit 1 is electrically connected to the fourth node N4.

[0139] As shown in Figure 6, the input sub-circuit 1 is configured to respond to the first clock signal CK1, using the input signal CR <i-1>The potential of the first node N1 is controlled; the first control sub-circuit 2 is configured to respond to the input signal CR. <i-1>The first power signal VGL1 is used to control the potential of the second node N2; the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first clock signal CK1 in response to the potential of the second node N2; or to control the potential of the third node N3 using the first power signal VGL1 in response to the potential of the first node N1; the first isolation sub-circuit 5 is configured to write the potential of the first node N1 to the fourth node N4 in response to the fourth power signal VGH1; the output sub-circuit 4 is configured to output the second power signal VGH2 through the first signal output terminal Out1 in response to the potential of the fourth node N4, or to output the third power signal VGL2 through the first signal output terminal Out1 in response to the potential of the third node N3.

[0140] As shown in Figure 6, the first isolation sub-circuit 5 includes a second transistor T2. The first electrode of the second transistor T2 is electrically connected to the first node N1, the second electrode is electrically connected to the fourth node N4, and the gate is electrically connected to the fourth power signal line that transmits the fourth power signal VGH1. For example, the fourth power signal VGH1 is a high-level signal, such as 5V or 8V. Specifically, when the second transistor T2 responds to the fourth power signal VGH1 and turns on, it writes the potential of the first node N1 into the fourth node N4. The second transistor T2 is an N-type thin-film transistor, therefore, under the control of the fourth power signal VGH1, the second transistor T2 remains continuously turned on.

[0141] In some embodiments, FIG7 is a circuit diagram of a shift register under the sixth example provided in the present disclosure. The difference between the shift register under the fifth example shown in FIG6 and the shift register is that a second isolation sub-circuit 6 is added.

[0142] As shown in Figure 7, the shift register also includes a second isolation sub-circuit 6; the second isolation sub-circuit 6 isolates the third node N3 and the input sub-circuit 1 electrically connected to the third node N3; the second isolation sub-circuit 6 is configured to isolate the third node N3 and the input sub-circuit 1 electrically connected to the third node N3, and electrically connect the third node N3 and the fifth node N5; the input sub-circuit 1 is electrically connected to the fifth node N5.

[0143] As shown in Figure 7, the input sub-circuit 1 is configured to respond to the first clock signal CK1, using the input signal CR <i-1>The potential of the first node N1 is controlled; the first control sub-circuit 2 is configured to respond to the input signal CR. <i-1>The first power supply signal VGL1 is used to control the potential of the second node N2; the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first clock signal CK1 in response to the potential of the second node N2; or to control the potential of the third node N3 using the first power supply signal VGL1 in response to the potential of the first node N1; the first isolation sub-circuit 5 is configured to write the potential of the first node N1 into the fourth node N4; the second isolation sub-circuit 6 is configured to write the potential of the third node N3 into the fifth node N5; the output sub-circuit 4 is configured to output the second power supply signal VGH2 through the first signal output terminal Out1 in response to the potential of the fourth node N4, or to output the third power supply signal VGL2 through the first signal output terminal Out1 in response to the potential of the fifth node N5.

[0144] As shown in Figure 7, the second isolation sub-circuit 6 includes a twelfth transistor T12; the first electrode of the twelfth transistor T12 is electrically connected to the fifth node N5, the second electrode is electrically connected to the third node N3, and the gate is electrically connected to the first clock signal line that transmits the first clock signal CK1. Specifically, when the twelfth transistor T12 responds to the first clock signal CK1 and is turned on, it writes the potential of the third node N3 into the fifth node N5.

[0145] In this embodiment, by adding a second isolation sub-circuit 6, which is controlled by the first clock signal CK1, when the first clock signal CK1 is at a low potential, it prevents leakage from the fifth node N5 to the third node N3, ensuring the stable opening of the tenth transistor T10 and the eleventh transistor T11, thereby ensuring the stable output of the first power signal VGL1 and the third power signal VGL2.

[0146] In some embodiments, FIG8 is a circuit diagram of a shift register under the seventh example provided in the present disclosure. The difference between the shift register under the sixth example shown in FIG7 is that a pull-up circuit 7 is added.

[0147] As shown in Figure 8, the shift register also includes a pull-up circuit 7; the pull-up circuit 7 includes a thirteenth transistor T13 and a fourteenth transistor T14; the first electrode of the thirteenth transistor T13 is electrically connected to the floating signal terminal Out3, the second electrode is electrically connected to the second clock signal line of the second clock signal CK2, and the gate is electrically connected to the fourth node N4; the first plate of the fourth capacitor C4 is electrically connected to the fourth node N4, and the second plate is electrically connected to the floating signal terminal Out3; the first electrode of the fourteenth transistor T14 is electrically connected to the first clock signal line transmitting the first clock signal CK1, the second electrode is electrically connected to the floating signal terminal Out3, and the gate is electrically connected to the fifth node N5.

[0148] As shown in Figure 8, the potential of the fourth node N4 controls the on / off state of the thirteenth transistor T13. When the thirteenth transistor T13 responds to the potential of the fourth node N4 and is turned on, it transmits the second clock signal CK2 transmitted by the second clock signal line to the floating signal terminal Out3. The potential of the fifth node N5 controls the on / off state of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the potential of the fifth node N5 and is turned on, it transmits the first power supply signal VGL1 to the floating signal terminal Out3.

[0149] Here, the floating signal terminal Out3 is not connected to any structure and is in a floating state.

[0150] In this embodiment, the second clock signal CK2 transmitted by the second clock signal line is used as the bootstrap signal during the high potential period of the fifth node N5, so that the fifth node N5 can continuously bootstrap through the thirteenth transistor T13 and the fourth capacitor C4 during the high potential period, thereby maintaining the high potential of the fifth node N5, thereby keeping the third transistor T3 and the fourth transistor T4 continuously turned on, and thus maintaining the stable output of the fourth power supply signal VGH1 and the second power supply signal VGH2.

[0151] As shown in Figures 1 and 3, the shift register can adopt a 6T3C (i.e., 6 transistors and 3 capacitors) circuit structure; or, as shown in Figure 4, the shift register can also adopt an 8T3C (i.e., 8 transistors and 2 capacitors) circuit structure; or, as shown in Figure 5, the shift register can also adopt a 10T3C (i.e., 10 transistors and 3 capacitors) circuit structure; or, as shown in Figure 6, the shift register can also adopt an 11T3C (i.e., 11 transistors and 3 capacitors) circuit structure; or, as shown in Figure 7, the shift register can also adopt a 12T3C (i.e., 12 transistors and 3 capacitors) circuit structure; or, as shown in Figure 8, the shift register can also adopt a 14T3C (i.e., 12 transistors and 3 capacitors) circuit structure.

[0152] It should be noted that, in the embodiments of this disclosure, the internal circuit structure of the shift register, in addition to the 6T3C, 8T3C, 10T3C, 11T3C, 12T3C, and 14T3C listed above, can also be a structure with other numbers of transistors (the number of capacitors remains unchanged). Optionally, the shift register can also adopt a 7T3C circuit structure (i.e., 7 transistors and 3 capacitors), specifically including the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the first capacitor C1, the second capacitor C2, and the third capacitor C3 as described above. Optionally, the shift register can also adopt an 8T3C circuit structure (i.e., 8 transistors and 3 capacitors), specifically including the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the first capacitor C1, the second capacitor C2, and the third capacitor C3 as described above. Optionally, the shift register can also adopt a 10T3C (i.e., 10 transistors and 3 capacitors) circuit structure, specifically including the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, eighth transistor T8, ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, first capacitor C1, second capacitor C2, and third capacitor C3 as described above. Alternatively, the shift register can also adopt a 12T3C (i.e., 12 transistors and 3 capacitors) circuit structure, specifically including the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, eighth transistor T8, ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, first capacitor C1, second capacitor C2, and fourth capacitor C4 as described above. The functions and implementation principles of each transistor can be found in the detailed descriptions of the above embodiments; repeated parts will not be repeated.

[0153] It should be noted that, in the embodiments disclosed herein, except for the fourth transistor T4 and the eleventh transistor T11 which employ a dual-gate structure, the remaining transistors, such as the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14, can all be made into dual-gate structures. This improves signal writing in the on-state and leakage current in the off-state, while also reducing the aspect ratio (W / L) to achieve a narrow bezel. However, in practical applications, the fourth transistor T4 and the eleventh transistor T11 are larger than the other transistors, occupying a larger area, which is a key factor affecting the bezel size. The reduction in aspect ratio for the other transistors using a dual-gate structure is smaller or negligible, contributing little or no to achieving a narrow bezel. Furthermore, compared to a single-gate structure, the introduction of a gate electrode in a dual-gate structure makes it easier to form parasitic capacitances with other structures, affecting signal transmission stability. Therefore, this disclosure preferably uses a dual-gate structure for the larger fourth transistor T4 and eleventh transistor T11, while the remaining transistors use a single-gate structure. Alternatively, it is preferred that the moderately sized first transistor T1, and the larger fourth transistor T4 and eleventh transistor T11 use a dual-gate structure, while the remaining transistors use a single-gate structure. Alternatively, it is preferred that the moderately sized first transistor T1, third transistor T3, tenth transistor T10, and the larger fourth transistor T4 and eleventh transistor T11 use a dual-gate structure, while the remaining transistors use a single-gate structure. Alternatively, it is preferred that the moderately sized first transistor T1, third transistor T3, tenth transistor T10, eighth transistor T8, and the larger fourth transistor T4 and eleventh transistor T11 use a dual-gate structure, while the remaining transistors use a single-gate structure. For a visual assessment of the size, please refer to Figures 11c and 11e.

[0154] In some embodiments, the voltage of the first power signal VGL1 is less than or equal to the voltage of the third power signal VGL2; the voltage of the second power signal VGH2 is less than or equal to the voltage of the fourth power signal VGH1.

[0155] Optionally, the voltage of the first power signal VGL1 is less than the voltage of the fourth power signal VGH1; the voltage of the second power signal VGH2 is greater than the voltage of the third power signal VGL2. For example, the voltage of the first power signal VGL1 is -8V, the voltage of the third power signal VGL2 is -5V, the voltage of the second power signal VGH2 is 5V, and the voltage of the fourth power signal VGH1 is 8V.

[0156] This embodiment is configured in such a way that it ensures the uniformity of the high potential output at the first signal output terminal Out1 when the fourth transistor T4 is negatively biased, and that it is not affected by the leakage current of the fifth node N5 or the eleventh transistor T11.

[0157] This concludes the complete description of the circuit structure of the shift register in this disclosure.

[0158] The working principle of the shift register provided in the embodiments of this disclosure will be described in further detail below.

[0159] Figure 9 is a timing diagram of an exemplary shift register provided in an embodiment of this disclosure. As shown in Figure 9, the circuit structure in Figure 7 is used as an example for illustration. Its working stages specifically include a first stage t1, a second stage t2, and a third stage t3, wherein:

[0160] Phase 1 t1: Input signal CR <i-1>The first clock signal CK1 is high. At this time, the first transistor T1 is turned on, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first node N1 is written with the input signal CR. <i-1>In other words, a high-level signal is written to the second node N2, which is the first power signal VGL1, i.e., a low-level signal. At this time, the eighth transistor T8 is off, the ninth transistor T9 is on, and the third node N3 is written with the first power signal VGL1, i.e., a low-level signal. The fourth power signal VGH1 is a high-level signal, the second transistor T2 is continuously on, the high-level signal of the first node N1 is written to the fourth node N4, the third transistor T3 and the fourth transistor T4 are both on, the second power signal VGH2 is output through the first signal output terminal Out1, and the fourth power signal VGH1 is output through the second signal output terminal Out2. The twelfth transistor T12 is on, the low-level signal of the third node N3 is written to the fifth node N5, and the tenth transistor T10 and the eleventh transistor T11 are both off.

[0161] Second stage t2: Input signal CR <i-1>The first clock signal CK1 is low. At this time, the first transistor T1 is off, and both the fifth transistor T5 and the sixth transistor T6 are off. The fourth node N4 and the fifth node N5 maintain the same potential as in the previous stage; that is, the fourth node N4 remains high and the fifth node N5 remains low. The third transistor T3 and the fourth transistor T4 are both on. The second power supply signal VGH2 is output through the first signal output terminal Out1, and the fourth power supply signal VGH1 is output through the second signal output terminal Out2. The tenth transistor T10 and the eleventh transistor T11 are both off.

[0162] Phase 3 t3: Input signal CR <i-1>The signal is low, and the first clock signal CK1 is high. At this time, the first transistor T1 is turned on, and the fifth transistor T5 and the sixth transistor T6 are both turned off. The first node N1 is written with the input signal CR. <i-1>When the first clock signal CK1 is high, the second transistor T2 remains on, and the low-level signal from the first node N1 is written to the fourth node N4. Both the third and fourth transistors T3 and T4 are off. When the first clock signal CK1 is high, the third capacitor C3 couples the potential of the second node N2 to a high potential, causing the eighth transistor T8 to turn on and write the first clock signal CK1 to the third node N3. At this time, the third node N3 is high, the twelfth transistor T12 turns on, and the high-level signal from the third node N3 is written to the fifth node N5. Both the tenth and eleventh transistors T10 and T11 are on. The first power signal VGL1 is output through the second signal output terminal Out2, and the third power signal VGL2 is output through the first signal output terminal Out1.

[0163] For timing control of other circuit structures (Figures 1, 3 to 7), the timing control of the circuit in Figure 5 as shown in Figure 9 can also be used. Repeated parts will not be described again.

[0164] Figure 10 is a timing diagram of another exemplary shift register provided in an embodiment of this disclosure. As shown in Figure 10, the circuit structure in Figure 8 is used as an example for illustration. Its working stages specifically include the fourth stage t4, the fifth stage t5, and the sixth stage t6, wherein:

[0165] Fourth stage t4: Input signal CR <i-1>The first clock signal CK1 is high, and the second clock signal CK2 is low. At this time, the first transistor T1 is turned on, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first node N1 is written with the input signal CR. <i-1>That is, a high-level signal. The second node N2 is written with the first power signal VGL1, which is a low-level signal. At this time, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, and the third node N3 is written with the first power signal VGL1, which is a low-level signal. The fourth power signal VGH1 is a high-level signal, the second transistor T2 is continuously turned on, the high-level signal of the first node N1 is written to the fourth node N4, the thirteenth transistor T13, the third transistor T3, and the fourth transistor T4 are all turned on, the second clock signal CK2 is transmitted to the floating signal terminal Out3, the second power signal VGH2 is output through the first signal output terminal Out1, and the fourth power signal VGH1 is output through the second signal output terminal Out2. The twelfth transistor T12 is turned on, the low-level signal of the third node N3 is written to the fifth node N5, and the tenth transistor T10 and the eleventh transistor T11 are both turned off.

[0166] Fifth stage t5: Input signal CR <i-1>The first clock signal CK1 is low, and the second clock signal CK2 is high. At this time, the first transistor T1 is off, and the fifth transistor T5 and the sixth transistor T6 are also off. The fourth node N4 maintains the high potential of the previous node. At this time, the thirteenth transistor T13 is on. Because the second clock signal CK2 is high, the fourth node N4 bootstraps to a higher potential through the fourth capacitor C4. The third transistor T3 and the fourth transistor T4 remain on. The second power supply signal VGH2 is output through the first signal output terminal Out1, and the fourth power supply signal VGH1 is output through the second signal output terminal Out2. The fifth node N5 maintains the potential of the previous stage and remains at a low potential. The tenth transistor T10 and the eleventh transistor T11 are both off.

[0167] Stage 6 t6: Input signal CR <i-1>The first clock signal CK1 is high, and the second clock signal CK2 is low. At this time, the first transistor T1 is turned on, while the fifth transistor T5 and the sixth transistor T6 are both turned off. The first node N1 is written with the input signal CR. <i-1>When the first clock signal CK1 is high, the second transistor T2 remains on, and the low-level signal from the first node N1 is written to the fourth node N4. The thirteenth transistor T13, the third transistor T3, and the fourth transistor T4 are all off. When the first clock signal CK1 is high, the third capacitor C3 couples the potential of the second node N2 to a high potential, causing the eighth transistor T8 to turn on and write the first clock signal CK1 to the third node N3. At this time, the third node N3 is high, the twelfth transistor T12 turns on, and the high-level signal from the third node N3 is written to the fifth node N5. The fourteenth transistor T14, the tenth transistor T10, and the eleventh transistor T11 are all on. The first power signal VGL1 is transmitted to the floating signal terminal Out3, and the first power signal VGL1 is output through the second signal output terminal Out2. The third power signal VGL2 is output through the first signal output terminal Out1.

[0168] The above explains the working principle of the shift register. The following is a detailed description of the membrane structure of the shift register provided in the embodiments of this disclosure.

[0169] In some embodiments, FIG11a is a layout of the first conductive layer in the shift register, FIG11b is a layout of the second conductive layer in the shift register, FIG11c is a layout of the third conductive layer in the shift register, FIG11d is a layout of the semiconductor layer in the shift register, FIG11e is a layout of the fourth conductive layer in the shift register, and FIG11f is a layout of the fifth conductive layer in the shift register; FIG12a to FIG12e are film layer layouts during the sequential stacking process of FIG11a to FIG11f, respectively. As shown in FIG11a to FIG11f and FIG12a to FIG12e, the shift register includes a substrate and a first conductive layer 01, a second conductive layer 02, a third conductive layer 03, a semiconductor layer 04, a fourth conductive layer 05, and a fifth conductive layer 06 sequentially disposed along a direction away from the substrate.

[0170] For the output sub-circuit 4, one of the first plate C11 and the second plate C12 of the first capacitor C1 is located in the first conductive layer 01, and the other is located in the second conductive layer 02. For the second capacitor C2, one of the first plate C21 and the second plate C22 is located in the first conductive layer 01, and the other is located in the second conductive layer 02. For example, as shown in Figures 11a and 11b, the first electrode C11 of the first capacitor C1 is located in the second conductive layer 02, and the second electrode C12 is located in the first conductive layer 01; the first electrode C21 of the second capacitor C2 is located in the first conductive layer 01, and the second electrode C22 is located in the second conductive layer 02; the gates of the fourth transistor T4 and the eleventh transistor T11 include electrically connected first gate electrodes and second gate electrodes, and the first gate electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the third conductive layer 03; the second gate electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the fourth conductive layer 05; the active layers of the fourth transistor T4 and the eleventh transistor T11 are both located in the semiconductor layer 04; the first and second electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the fifth conductive layer 06.

[0171] For the output sub-circuit 4, the gates of the third transistor T3 and the tenth transistor T10 are both located in the fourth conductive layer 05; the active layers of the third transistor T3 and the tenth transistor T10 are both located in the semiconductor layer 04; and the first and second terminals of the third transistor T3 and the tenth transistor T10 are both located in the fifth conductive layer 06.

[0172] For input sub-circuit 1, the gate of the first transistor T1 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0173] For the first control sub-circuit 2, the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the fourth conductive layer 05; the active layers of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the semiconductor layer 04; and the first and second electrodes of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the fifth conductive layer 06.

[0174] For the second control sub-circuit 3, the gates of the eighth transistor T8 and the ninth transistor T9 are both located on the fourth conductive layer 05; the active layers of the eighth transistor T8 and the ninth transistor T9 are both located on the semiconductor layer 04; the first and second electrodes of the eighth transistor T8 and the ninth transistor T9 are both located on the fifth conductive layer 06. The first electrode C31 of the third capacitor C3 is located on the first conductive layer 01; the second electrode C32 of the third capacitor C3 is located on the second conductive layer 02.

[0175] For the first isolator circuit 5, the gate of the second transistor T2 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0176] For the second isolator circuit 6, the gate of the twelfth transistor T12 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0177] The first clock signal line, the first power signal line, the second power signal line, the third power signal line, and the fourth power signal line, along with the input signal CR electrically connected to the signal input terminal Input, are also included. <i-1>All leads are located in the fifth conductive layer 06.

[0178] In some embodiments, as shown in Figures 11c, 11e, 12b, 12d, and 12e, the orthogonal projections of the first gate electrode T41 and the second gate electrode T42 of the fourth transistor T4 on the substrate at least partially overlap; the first gate electrode T41 of the fourth transistor T4 includes a plurality of first extensions T411 arranged side by side along a first direction X, and the second gate electrode T42 of the fourth transistor T4 includes a plurality of second extensions T421 arranged side by side along the first direction X; the extension direction of the first extensions T411 and the extension direction of the second extensions T421 are both the second direction Y, and the first direction X and the second direction Y are intersected; one end of the plurality of first extensions T411 is connected by a first connecting portion T412; one end of the plurality of second extensions T421 is connected by a second connecting portion T422. The first gate electrode T111 and the second gate electrode T112 of the eleventh transistor T11 have at least partially overlapping orthogonal projections on the substrate; the first gate electrode T111 of the eleventh transistor T11 includes a plurality of third extensions T1111 arranged side by side along the first direction X, and the second gate electrode T112 of the eleventh transistor T11 includes a plurality of fourth extensions T1121 arranged side by side along the first direction X; the extension direction of the third extensions T1111 and the extension direction of the fourth extensions T1121 are both the second direction Y; one end of the plurality of third extensions T1111 is connected by a third connecting portion T1112; one end of the plurality of fourth extensions T1121 is connected by a fourth connecting portion T1122.

[0179] Optionally, the orthogonal projections of the first gate electrode T41 and the second gate electrode T42 of the fourth transistor T4 on the substrate completely overlap.

[0180] Optionally, as shown in FIG12d, the orthogonal projection of the second gate electrode T42 of the fourth transistor T4 on the substrate covers the orthogonal projection of the first gate electrode T41 of the fourth transistor T4 on the substrate.

[0181] Optionally, the first gate electrode T111 and the second gate electrode T112 of the eleventh transistor T11 have completely overlapping orthogonal projections on the substrate.

[0182] Optionally, as shown in FIG12d, the orthogonal projection of the second gate electrode T112 of the eleventh transistor T11 on the substrate covers the orthogonal projection of the first gate electrode T111 of the eleventh transistor T11 on the substrate.

[0183] Optionally, the distance from the first gate electrode of the fourth transistor T4 to the active layer is between 1000A and 2000A; the distance from the second gate electrode of the fourth transistor T4 to the active layer is between 500A and 3000A. Optionally, the distance from the first gate electrode of the eleventh transistor T11 to the active layer is between 1000A and 2000A; the distance from the second gate electrode of the eleventh transistor T11 to the active layer is between 500A and 3000A.

[0184] In some embodiments, the shift register includes a substrate and a first conductive layer 01, a second conductive layer 02, a third conductive layer 03, a semiconductor layer 04, a fourth conductive layer 05, and a fifth conductive layer 06 disposed sequentially in a direction away from the substrate.

[0185] For the output sub-circuit 4, one of the first plate C11 and the second plate C12 of the first capacitor C1 is located in the first conductive layer 01, and the other is located in the second conductive layer 02. For the second capacitor C2, one of the first plate C21 and the second plate C22 is located in the first conductive layer 01, and the other is located in the second conductive layer 02. For example, the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2 are both located in the first conductive layer 01; the second electrode of the first capacitor C1 and the second electrode of the second capacitor C2 are both located in the second conductive layer 02; the gates of the fourth transistor T4 and the eleventh transistor T11 include electrically connected first gate electrodes and second gate electrodes, and the first gate electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the third conductive layer 03; the second gate electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the fourth conductive layer 05; the active layer of the fourth transistor T4 and the active layer of the eleventh transistor T11 are both located in the semiconductor layer 04; the first and second electrodes of the fourth transistor T4 and the eleventh transistor T11 are both located in the fifth conductive layer 06.

[0186] For the output sub-circuit 4, the gates of the third transistor T3 and the tenth transistor T10 are both located in the fourth conductive layer 05; the active layers of the third transistor T3 and the tenth transistor T10 are both located in the semiconductor layer 04; and the first and second terminals of the third transistor T3 and the tenth transistor T10 are both located in the fifth conductive layer 06.

[0187] For input sub-circuit 1, the gate of the first transistor T1 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0188] For the first control sub-circuit 2, the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the fourth conductive layer 05; the active layers of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the semiconductor layer 04; and the first and second electrodes of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located on the fifth conductive layer 06.

[0189] For the second control sub-circuit 3, the gates of the eighth transistor T8 and the ninth transistor T9 are both located on the fourth conductive layer 05; the active layers of the eighth transistor T8 and the ninth transistor T9 are both located on the semiconductor layer 04; the first and second electrodes of the eighth transistor T8 and the ninth transistor T9 are both located on the fifth conductive layer 06. The first electrode of the third capacitor C3 is located on the first conductive layer 01; the second electrode of the third capacitor C3 is located on the second conductive layer 02.

[0190] For the first isolator circuit 5, the gate of the second transistor T2 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0191] For the second isolator circuit 6, the gate of the twelfth transistor T12 is located in the fourth conductive layer 05, the active layer is located in the semiconductor layer 04, and the first and second electrodes are both located in the fifth conductive layer 06.

[0192] For pull-up circuit 7, the gates of the thirteenth transistor T13 and the fourteenth transistor T14 are both located on the fourth conductive layer 05, the active layers of the thirteenth transistor T13 and the fourteenth transistor T14 are located on the semiconductor layer 04, and the first and second electrodes of the thirteenth transistor T13 and the fourteenth transistor T14 are both located on the fifth conductive layer 06.

[0193] The first clock signal line, the first power signal line, the second power signal line, the third power signal line, and the fourth power signal line, along with the input signal CR electrically connected to the signal input terminal Input, are also included. <i-1>All leads are located in the fifth conductive layer 06.

[0194] In addition, this disclosure also provides a scan driving circuit, specifically including N cascaded shift registers as described in any of the above embodiments.

[0195] In some embodiments, the output sub-circuit 4 is further configured to output the fourth power signal VGH1 through the second signal output terminal Out2 in response to the potential of the first node N1, or to output the first power signal VGL1 through the second signal output terminal Out2 in response to the potential of the third node N3.

[0196] Figure 13 is a schematic diagram of a scan driving circuit provided in an embodiment of this disclosure. As shown in Figure 13, in addition to the first-stage shift register, the signal input terminal Input of the (i+1)th-stage shift register...<i+1> Electrically connect the second signal output terminal Out2 of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0197] The scanning driving circuit provided in this embodiment is configured to provide an on or off signal to the gate of the transistor in each pixel driving circuit so that the pixel driving circuit controls the light-emitting device to emit light.

[0198] For example, the scan driving circuit provided in this embodiment can provide a light-emitting control signal to the gate of the light-emitting control transistor in the pixel driving circuit. Alternatively, the scan driving circuit provided in this embodiment can also provide a start signal to the gate of the switching transistor in the pixel driving circuit.

[0199] It should be noted that the light-emitting devices involved in the embodiments of this disclosure may include, but are not limited to, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or micro light-emitting diodes (Micro LEDs).

[0200] Optionally, the light-emitting device is an OLED device.

[0201] For a detailed explanation of the specific structure of a shift register, please refer to the detailed description of shift registers mentioned above. Repeated parts will not be repeated here.

[0202] In addition, this disclosure also provides a display device, which includes the display substrate of any of the above embodiments. This display device can be, for example, any product with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0203] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, comprising an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; The input sub-circuit is configured to control the potential of the first node using an input signal in response to a first clock signal; The first control sub-circuit is configured to control the potential of the second node using a first power supply signal in response to the input signal; The second control sub-circuit is configured to control the potential of the third node in response to the potential of the second node using the first clock signal; Alternatively, in response to the potential of the first node, the potential of the third node can be controlled using the first power signal; The output sub-circuit is configured to output a second power signal through a first signal output terminal in response to the potential of the first node, or to output a third power signal through the first signal output terminal in response to the potential of the third node; wherein the output sub-circuit includes at least one dual-gate transistor.

2. The shift register of claim 1, wherein, The output sub-circuit includes two dual-gate transistors, referred to as the fourth transistor and the eleventh transistor, respectively; The first electrode of the fourth transistor is electrically connected to the first signal output terminal, the second electrode is electrically connected to the second power signal line that transmits the second power signal, and the gate is electrically connected to the first node. The first electrode of the eleventh transistor is electrically connected to the third power signal line that transmits the third power signal, the second electrode is electrically connected to the first signal output terminal, and the gate is electrically connected to the third node.

3. The shift register of claim 1, wherein, The input sub-circuit includes at least one dual-gate transistor.

4. The shift register of claim 3, wherein, The input sub-circuit includes a dual-gate transistor, referred to as the first transistor; The first electrode of the first transistor is electrically connected to the signal input terminal that receives the input signal, the second electrode is electrically connected to the first node, and the gate is electrically connected to the first clock signal line that transmits the first clock signal.

5. The shift register of claim 2, wherein, The output sub-circuit is further configured to output a fourth power signal through a second signal output terminal in response to the potential of the first node, or to output the first power signal through the second signal output terminal in response to the potential of the third node.

6. The shift register of claim 5, wherein, The output sub-circuit also includes a third transistor and a tenth transistor; The first electrode of the third transistor is electrically connected to the second signal output terminal, the second electrode is electrically connected to the fourth power signal line that transmits the fourth power signal, and the gate is electrically connected to the first node. The first electrode of the tenth transistor is electrically connected to the first power signal line that transmits the first power signal, the second electrode is electrically connected to the second signal output terminal, and the gate is electrically connected to the third potential.

7. The shift register of claim 6, wherein, Both the third transistor and the tenth transistor are dual-gate transistors.

8. The shift register according to claim 2 or 6, wherein, The output sub-circuit also includes a first capacitor and a second capacitor. The first plate of the first capacitor is electrically connected to the first node, and the second plate is electrically connected to the first signal output terminal, or the second plate is electrically connected to the second signal output terminal. The first plate of the second capacitor is electrically connected to the third node, and the second plate is electrically connected to the third power signal line, or the second plate is electrically connected to the first power signal line that transmits the first power signal.

9. The shift register according to claim 8, wherein, The shift register includes a substrate and a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a fourth conductive layer and a fifth conductive layer arranged sequentially in a direction away from the substrate. One of the first plate and the second plate of the first capacitor is located in the first conductive layer, and the other is located in the second conductive layer; One of the first and second plates of the second capacitor is located in the first conductive layer, and the other is located in the second conductive layer; The gates of the fourth transistor and the eleventh transistor include a first gate electrode and a second gate electrode that are electrically connected, and the first gate electrode of the fourth transistor and the first gate electrode of the eleventh transistor are both located in the third conductive layer; the second gate electrode of the fourth transistor and the second gate electrode of the eleventh transistor are both located in the fourth conductive layer; The active layer of the fourth transistor and the active layer of the eleventh transistor are both located in the semiconductor layer. The first and second electrodes of the fourth transistor, as well as the first and second electrodes of the eleventh transistor, are all located in the fifth conductive layer.

10. The shift register according to claim 9, wherein, The first gate electrode and the second gate electrode of the fourth transistor have orthographic projections on the substrate that at least partially overlap; the first gate electrode of the fourth transistor includes a plurality of first extensions arranged side by side along a first direction, and the second gate electrode of the fourth transistor includes a plurality of second extensions arranged side by side along the first direction; the extension directions of the first extensions and the extension directions of the second extensions are both second directions, and the first direction and the second direction are intersected; one end of the plurality of first extensions is connected by a first connecting portion; one end of the plurality of second extensions is connected by a second connecting portion; The first gate electrode and the second gate electrode of the eleventh transistor have at least partially overlapping orthogonal projections on the substrate; the first gate electrode of the eleventh transistor includes a plurality of third extensions arranged side by side along a first direction, and the second gate electrode of the eleventh transistor includes a plurality of fourth extensions arranged side by side along the first direction; the extension directions of the third extensions and the extension directions of the fourth extensions are both second directions; one end of the plurality of third extensions is connected by a third connecting portion; one end of the plurality of fourth extensions is connected by a fourth connecting portion.

11. The shift register according to claim 9, wherein, The active layers of the fourth transistor and the eleventh transistor are made of oxide semiconductor materials.

12. The shift register according to claim 1, wherein, The first control sub-circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; The first terminal of the fifth transistor is electrically connected to the second terminal of the sixth transistor and the second terminal of the seventh transistor, the second terminal is electrically connected to the first power signal line that transmits the first power signal, and the gate is electrically connected to the signal input terminal that transmits the input signal. The first electrode of the sixth transistor is electrically connected to the second node, and the gate is electrically connected to the signal input terminal. The first electrode of the seventh transistor is electrically connected to the second power signal line that transmits the second power signal, and the gate is electrically connected to the second node.

13. The shift register according to claim 1, wherein, The second control sub-circuit includes an eighth transistor, a third capacitor, and a ninth transistor; The first electrode of the eighth transistor is electrically connected to the first clock signal line that transmits the first clock signal, the second electrode is electrically connected to the third node, and the gate is electrically connected to the second node. The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first electrode of the eighth transistor. The first electrode of the ninth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal line that transmits the first power signal, and the gate is electrically connected to the first node.

14. The shift register according to claim 1, wherein, The shift register also includes a first isolation sub-circuit; The first isolation sub-circuit is configured to isolate the first node and the input sub-circuit electrically connected to the first node, and to electrically connect the fourth node and the first node; The input sub-circuit is electrically connected to the fourth node.

15. The shift register according to claim 1 or 14, wherein, The shift register further includes a second isolation sub-circuit; the second isolation sub-circuit isolates the third node and the input sub-circuit electrically connected to the third node; The second isolation sub-circuit is configured to isolate the third node and the input sub-circuit electrically connected to the third node, and to electrically connect the third node and the fifth node; The input sub-circuit is electrically connected to the fifth node.

16. The shift register according to claim 15, wherein, The shift register further includes a pull-up circuit; the pull-up circuit includes a fourth capacitor, a thirteenth transistor, and a fourteenth transistor; The first electrode of the thirteenth transistor is electrically connected to the floating signal terminal, the second electrode is electrically connected to the second clock signal line, and the gate is electrically connected to the fourth node. The first plate of the fourth capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the floating signal terminal. The first electrode of the fourteenth transistor is electrically connected to the first clock signal line that transmits the first clock signal, the second electrode is electrically connected to the floating signal terminal, and the gate is electrically connected to the fifth node.

17. The shift register according to any one of claims 1 to 7, wherein, The voltage of the first power supply signal is less than or equal to the voltage of the third power supply signal; The voltage of the second power supply signal is less than or equal to the voltage of the fourth power supply signal.

18. A scan drive circuit comprising N cascaded shift registers as described in any one of claims 1 to 17.

19. The scanning drive circuit according to claim 18, wherein, The output sub-circuit is further configured to output a fourth power signal through a second signal output terminal in response to the potential of the first node, or to output the first power signal through the second signal output terminal in response to the potential of the third node. Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the second signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

20. A display device comprising the scanning drive circuit as described in claim 18 or 19.

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